1 #include <linux/init.h>
6 #include <asm/processor-cyrix.h>
7 #include <asm/processor-flags.h>
13 cyrix_get_arr(unsigned int reg, unsigned long *base,
14 unsigned long *size, mtrr_type * type)
17 unsigned char arr, ccr3, rcr, shift;
19 arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */
21 /* Save flags and disable interrupts */
22 local_irq_save(flags);
24 ccr3 = getCx86(CX86_CCR3);
25 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
26 ((unsigned char *) base)[3] = getCx86(arr);
27 ((unsigned char *) base)[2] = getCx86(arr + 1);
28 ((unsigned char *) base)[1] = getCx86(arr + 2);
29 rcr = getCx86(CX86_RCR_BASE + reg);
30 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
32 /* Enable interrupts if it was enabled previously */
33 local_irq_restore(flags);
34 shift = ((unsigned char *) base)[1] & 0x0f;
37 /* Power of two, at least 4K on ARR0-ARR6, 256K on ARR7
38 * Note: shift==0xf means 4G, this is unsupported.
41 *size = (reg < 7 ? 0x1UL : 0x40UL) << (shift - 1);
45 /* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */
49 *type = MTRR_TYPE_UNCACHABLE;
52 *type = MTRR_TYPE_WRBACK;
55 *type = MTRR_TYPE_WRCOMB;
59 *type = MTRR_TYPE_WRTHROUGH;
65 *type = MTRR_TYPE_UNCACHABLE;
68 *type = MTRR_TYPE_WRCOMB;
71 *type = MTRR_TYPE_WRBACK;
75 *type = MTRR_TYPE_WRTHROUGH;
82 cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
83 /* [SUMMARY] Get a free ARR.
84 <base> The starting (base) address of the region.
85 <size> The size (in bytes) of the region.
86 [RETURNS] The index of the region on success, else -1 on error.
91 unsigned long lbase, lsize;
93 switch (replace_reg) {
109 /* If we are to set up a region >32M then look at ARR7 immediately */
111 cyrix_get_arr(7, &lbase, &lsize, <ype);
114 /* Else try ARR0-ARR6 first */
116 for (i = 0; i < 7; i++) {
117 cyrix_get_arr(i, &lbase, &lsize, <ype);
118 if ((i == 3) && arr3_protected)
123 /* ARR0-ARR6 isn't free, try ARR7 but its size must be at least 256K */
124 cyrix_get_arr(i, &lbase, &lsize, <ype);
125 if ((lsize == 0) && (size >= 0x40))
134 static void prepare_set(void)
138 /* Save value of CR4 and clear Page Global Enable (bit 7) */
141 write_cr4(cr4 & ~X86_CR4_PGE);
144 /* Disable and flush caches. Note that wbinvd flushes the TLBs as
146 cr0 = read_cr0() | X86_CR0_CD;
151 /* Cyrix ARRs - everything else was excluded at the top */
152 ccr3 = getCx86(CX86_CCR3);
154 /* Cyrix ARRs - everything else was excluded at the top */
155 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
159 static void post_set(void)
161 /* Flush caches and TLBs */
164 /* Cyrix ARRs - everything else was excluded at the top */
165 setCx86(CX86_CCR3, ccr3);
168 write_cr0(read_cr0() & 0xbfffffff);
170 /* Restore value of CR4 */
175 static void cyrix_set_arr(unsigned int reg, unsigned long base,
176 unsigned long size, mtrr_type type)
178 unsigned char arr, arr_type, arr_size;
180 arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */
182 /* count down from 32M (ARR0-ARR6) or from 2G (ARR7) */
186 size &= 0x7fff; /* make sure arr_size <= 14 */
187 for (arr_size = 0; size; arr_size++, size >>= 1) ;
191 case MTRR_TYPE_UNCACHABLE:
194 case MTRR_TYPE_WRCOMB:
197 case MTRR_TYPE_WRTHROUGH:
206 case MTRR_TYPE_UNCACHABLE:
209 case MTRR_TYPE_WRCOMB:
212 case MTRR_TYPE_WRTHROUGH:
224 setCx86(arr, ((unsigned char *) &base)[3]);
225 setCx86(arr + 1, ((unsigned char *) &base)[2]);
226 setCx86(arr + 2, (((unsigned char *) &base)[1]) | arr_size);
227 setCx86(CX86_RCR_BASE + reg, arr_type);
238 static arr_state_t arr_state[8] = {
239 {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL},
240 {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}
243 static unsigned char ccr_state[7] = { 0, 0, 0, 0, 0, 0, 0 };
245 static void cyrix_set_all(void)
251 /* the CCRs are not contiguous */
252 for (i = 0; i < 4; i++)
253 setCx86(CX86_CCR0 + i, ccr_state[i]);
255 setCx86(CX86_CCR4 + i, ccr_state[i]);
256 for (i = 0; i < 8; i++)
257 cyrix_set_arr(i, arr_state[i].base,
258 arr_state[i].size, arr_state[i].type);
265 * On Cyrix 6x86(MX) and M II the ARR3 is special: it has connection
266 * with the SMM (System Management Mode) mode. So we need the following:
267 * Check whether SMI_LOCK (CCR3 bit 0) is set
268 * if it is set, write a warning message: ARR3 cannot be changed!
269 * (it cannot be changed until the next processor reset)
270 * if it is reset, then we can change it, set all the needed bits:
271 * - disable access to SMM memory through ARR3 range (CCR1 bit 7 reset)
272 * - disable access to SMM memory (CCR1 bit 2 reset)
273 * - disable SMM mode (CCR1 bit 1 reset)
274 * - disable write protection of ARR3 (CCR6 bit 1 reset)
275 * - (maybe) disable ARR3
276 * Just to be sure, we enable ARR usage by the processor (CCR5 bit 5 set)
281 struct set_mtrr_context ctxt;
282 unsigned char ccr[7];
283 int ccrc[7] = { 0, 0, 0, 0, 0, 0, 0 };
288 /* flush cache and enable MAPEN */
289 set_mtrr_prepare_save(&ctxt);
290 set_mtrr_cache_disable(&ctxt);
292 /* Save all CCRs locally */
293 ccr[0] = getCx86(CX86_CCR0);
294 ccr[1] = getCx86(CX86_CCR1);
295 ccr[2] = getCx86(CX86_CCR2);
297 ccr[4] = getCx86(CX86_CCR4);
298 ccr[5] = getCx86(CX86_CCR5);
299 ccr[6] = getCx86(CX86_CCR6);
305 /* Disable SMM mode (bit 1), access to SMM memory (bit 2) and
306 * access to SMM memory through ARR3 (bit 7).
323 ccrc[6] = 1; /* Disable write protection of ARR3 */
324 setCx86(CX86_CCR6, ccr[6]);
326 /* Disable ARR3. This is safe now that we disabled SMM. */
327 /* cyrix_set_arr_up (3, 0, 0, 0, FALSE); */
329 /* If we changed CCR1 in memory, change it in the processor, too. */
331 setCx86(CX86_CCR1, ccr[1]);
333 /* Enable ARR usage by the processor */
334 if (!(ccr[5] & 0x20)) {
337 setCx86(CX86_CCR5, ccr[5]);
340 for (i = 0; i < 7; i++)
341 ccr_state[i] = ccr[i];
342 for (i = 0; i < 8; i++)
344 &arr_state[i].base, &arr_state[i].size,
348 set_mtrr_done(&ctxt); /* flush cache and disable MAPEN */
351 printk(KERN_INFO "mtrr: ARR usage was not enabled, enabled manually\n");
353 printk(KERN_INFO "mtrr: ARR3 cannot be changed\n");
355 if ( ccrc[1] & 0x80) printk ("mtrr: SMM memory access through ARR3 disabled\n");
356 if ( ccrc[1] & 0x04) printk ("mtrr: SMM memory access disabled\n");
357 if ( ccrc[1] & 0x02) printk ("mtrr: SMM mode disabled\n");
360 printk(KERN_INFO "mtrr: ARR3 was write protected, unprotected\n");
364 static struct mtrr_ops cyrix_mtrr_ops = {
365 .vendor = X86_VENDOR_CYRIX,
366 // .init = cyrix_arr_init,
367 .set_all = cyrix_set_all,
368 .set = cyrix_set_arr,
369 .get = cyrix_get_arr,
370 .get_free_region = cyrix_get_free_region,
371 .validate_add_page = generic_validate_add_page,
372 .have_wrcomb = positive_have_wrcomb,
375 int __init cyrix_init_mtrr(void)
377 set_mtrr_ops(&cyrix_mtrr_ops);
381 //arch_initcall(cyrix_init_mtrr);