Merge branch 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
[linux-2.6] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6  * Based on 8260_io/fcc_enet.c
7  *
8  * Author: Andy Fleming
9  * Maintainer: Kumar Gala
10  *
11  * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
12  *
13  * This program is free software; you can redistribute  it and/or modify it
14  * under  the terms of  the GNU General  Public License as published by the
15  * Free Software Foundation;  either version 2 of the  License, or (at your
16  * option) any later version.
17  *
18  *  Gianfar:  AKA Lambda Draconis, "Dragon"
19  *  RA 11 31 24.2
20  *  Dec +69 19 52
21  *  V 3.84
22  *  B-V +1.62
23  *
24  *  Theory of operation
25  *  This driver is designed for the non-CPM ethernet controllers
26  *  on the 85xx and 83xx family of integrated processors
27  *
28  *  The driver is initialized through platform_device.  Structures which
29  *  define the configuration needed by the board are defined in a
30  *  board structure in arch/ppc/platforms (though I do not
31  *  discount the possibility that other architectures could one
32  *  day be supported.
33  *
34  *  The Gianfar Ethernet Controller uses a ring of buffer
35  *  descriptors.  The beginning is indicated by a register
36  *  pointing to the physical address of the start of the ring.
37  *  The end is determined by a "wrap" bit being set in the
38  *  last descriptor of the ring.
39  *
40  *  When a packet is received, the RXF bit in the
41  *  IEVENT register is set, triggering an interrupt when the
42  *  corresponding bit in the IMASK register is also set (if
43  *  interrupt coalescing is active, then the interrupt may not
44  *  happen immediately, but will wait until either a set number
45  *  of frames or amount of time have passed).  In NAPI, the
46  *  interrupt handler will signal there is work to be done, and
47  *  exit.  Without NAPI, the packet(s) will be handled
48  *  immediately.  Both methods will start at the last known empty
49  *  descriptor, and process every subsequent descriptor until there
50  *  are none left with data (NAPI will stop after a set number of
51  *  packets to give time to other tasks, but will eventually
52  *  process all the packets).  The data arrives inside a
53  *  pre-allocated skb, and so after the skb is passed up to the
54  *  stack, a new skb must be allocated, and the address field in
55  *  the buffer descriptor must be updated to indicate this new
56  *  skb.
57  *
58  *  When the kernel requests that a packet be transmitted, the
59  *  driver starts where it left off last time, and points the
60  *  descriptor at the buffer which was passed in.  The driver
61  *  then informs the DMA engine that there are packets ready to
62  *  be transmitted.  Once the controller is finished transmitting
63  *  the packet, an interrupt may be triggered (under the same
64  *  conditions as for reception, but depending on the TXF bit).
65  *  The driver then cleans up the buffer.
66  */
67
68 #include <linux/config.h>
69 #include <linux/kernel.h>
70 #include <linux/sched.h>
71 #include <linux/string.h>
72 #include <linux/errno.h>
73 #include <linux/unistd.h>
74 #include <linux/slab.h>
75 #include <linux/interrupt.h>
76 #include <linux/init.h>
77 #include <linux/delay.h>
78 #include <linux/netdevice.h>
79 #include <linux/etherdevice.h>
80 #include <linux/skbuff.h>
81 #include <linux/if_vlan.h>
82 #include <linux/spinlock.h>
83 #include <linux/mm.h>
84 #include <linux/platform_device.h>
85 #include <linux/ip.h>
86 #include <linux/tcp.h>
87 #include <linux/udp.h>
88
89 #include <asm/io.h>
90 #include <asm/irq.h>
91 #include <asm/uaccess.h>
92 #include <linux/module.h>
93 #include <linux/dma-mapping.h>
94 #include <linux/crc32.h>
95 #include <linux/mii.h>
96 #include <linux/phy.h>
97
98 #include "gianfar.h"
99 #include "gianfar_mii.h"
100
101 #define TX_TIMEOUT      (1*HZ)
102 #define SKB_ALLOC_TIMEOUT 1000000
103 #undef BRIEF_GFAR_ERRORS
104 #undef VERBOSE_GFAR_ERRORS
105
106 #ifdef CONFIG_GFAR_NAPI
107 #define RECEIVE(x) netif_receive_skb(x)
108 #else
109 #define RECEIVE(x) netif_rx(x)
110 #endif
111
112 const char gfar_driver_name[] = "Gianfar Ethernet";
113 const char gfar_driver_version[] = "1.2";
114
115 static int gfar_enet_open(struct net_device *dev);
116 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
117 static void gfar_timeout(struct net_device *dev);
118 static int gfar_close(struct net_device *dev);
119 struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
120 static struct net_device_stats *gfar_get_stats(struct net_device *dev);
121 static int gfar_set_mac_address(struct net_device *dev);
122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123 static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs);
124 static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs);
125 static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs);
126 static void adjust_link(struct net_device *dev);
127 static void init_registers(struct net_device *dev);
128 static int init_phy(struct net_device *dev);
129 static int gfar_probe(struct platform_device *pdev);
130 static int gfar_remove(struct platform_device *pdev);
131 static void free_skb_resources(struct gfar_private *priv);
132 static void gfar_set_multi(struct net_device *dev);
133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134 #ifdef CONFIG_GFAR_NAPI
135 static int gfar_poll(struct net_device *dev, int *budget);
136 #endif
137 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
138 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
139 static void gfar_vlan_rx_register(struct net_device *netdev,
140                                 struct vlan_group *grp);
141 static void gfar_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
142
143 extern struct ethtool_ops gfar_ethtool_ops;
144
145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
147 MODULE_LICENSE("GPL");
148
149 int gfar_uses_fcb(struct gfar_private *priv)
150 {
151         if (priv->vlan_enable || priv->rx_csum_enable)
152                 return 1;
153         else
154                 return 0;
155 }
156
157 /* Set up the ethernet device structure, private data,
158  * and anything else we need before we start */
159 static int gfar_probe(struct platform_device *pdev)
160 {
161         u32 tempval;
162         struct net_device *dev = NULL;
163         struct gfar_private *priv = NULL;
164         struct gianfar_platform_data *einfo;
165         struct resource *r;
166         int idx;
167         int err = 0;
168
169         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
170
171         if (NULL == einfo) {
172                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
173                        pdev->id);
174
175                 return -ENODEV;
176         }
177
178         /* Create an ethernet device instance */
179         dev = alloc_etherdev(sizeof (*priv));
180
181         if (NULL == dev)
182                 return -ENOMEM;
183
184         priv = netdev_priv(dev);
185
186         /* Set the info in the priv to the current info */
187         priv->einfo = einfo;
188
189         /* fill out IRQ fields */
190         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
191                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
192                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
193                 priv->interruptError = platform_get_irq_byname(pdev, "error");
194         } else {
195                 priv->interruptTransmit = platform_get_irq(pdev, 0);
196         }
197
198         /* get a pointer to the register memory */
199         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
200         priv->regs = (struct gfar *)
201                 ioremap(r->start, sizeof (struct gfar));
202
203         if (NULL == priv->regs) {
204                 err = -ENOMEM;
205                 goto regs_fail;
206         }
207
208         spin_lock_init(&priv->lock);
209
210         platform_set_drvdata(pdev, dev);
211
212         /* Stop the DMA engine now, in case it was running before */
213         /* (The firmware could have used it, and left it running). */
214         /* To do this, we write Graceful Receive Stop and Graceful */
215         /* Transmit Stop, and then wait until the corresponding bits */
216         /* in IEVENT indicate the stops have completed. */
217         tempval = gfar_read(&priv->regs->dmactrl);
218         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
219         gfar_write(&priv->regs->dmactrl, tempval);
220
221         tempval = gfar_read(&priv->regs->dmactrl);
222         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
223         gfar_write(&priv->regs->dmactrl, tempval);
224
225         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
226                 cpu_relax();
227
228         /* Reset MAC layer */
229         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
230
231         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
232         gfar_write(&priv->regs->maccfg1, tempval);
233
234         /* Initialize MACCFG2. */
235         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
236
237         /* Initialize ECNTRL */
238         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
239
240         /* Copy the station address into the dev structure, */
241         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
242
243         /* Set the dev->base_addr to the gfar reg region */
244         dev->base_addr = (unsigned long) (priv->regs);
245
246         SET_MODULE_OWNER(dev);
247         SET_NETDEV_DEV(dev, &pdev->dev);
248
249         /* Fill in the dev structure */
250         dev->open = gfar_enet_open;
251         dev->hard_start_xmit = gfar_start_xmit;
252         dev->tx_timeout = gfar_timeout;
253         dev->watchdog_timeo = TX_TIMEOUT;
254 #ifdef CONFIG_GFAR_NAPI
255         dev->poll = gfar_poll;
256         dev->weight = GFAR_DEV_WEIGHT;
257 #endif
258         dev->stop = gfar_close;
259         dev->get_stats = gfar_get_stats;
260         dev->change_mtu = gfar_change_mtu;
261         dev->mtu = 1500;
262         dev->set_multicast_list = gfar_set_multi;
263
264         dev->ethtool_ops = &gfar_ethtool_ops;
265
266         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
267                 priv->rx_csum_enable = 1;
268                 dev->features |= NETIF_F_IP_CSUM;
269         } else
270                 priv->rx_csum_enable = 0;
271
272         priv->vlgrp = NULL;
273
274         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
275                 dev->vlan_rx_register = gfar_vlan_rx_register;
276                 dev->vlan_rx_kill_vid = gfar_vlan_rx_kill_vid;
277
278                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
279
280                 priv->vlan_enable = 1;
281         }
282
283         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
284                 priv->extended_hash = 1;
285                 priv->hash_width = 9;
286
287                 priv->hash_regs[0] = &priv->regs->igaddr0;
288                 priv->hash_regs[1] = &priv->regs->igaddr1;
289                 priv->hash_regs[2] = &priv->regs->igaddr2;
290                 priv->hash_regs[3] = &priv->regs->igaddr3;
291                 priv->hash_regs[4] = &priv->regs->igaddr4;
292                 priv->hash_regs[5] = &priv->regs->igaddr5;
293                 priv->hash_regs[6] = &priv->regs->igaddr6;
294                 priv->hash_regs[7] = &priv->regs->igaddr7;
295                 priv->hash_regs[8] = &priv->regs->gaddr0;
296                 priv->hash_regs[9] = &priv->regs->gaddr1;
297                 priv->hash_regs[10] = &priv->regs->gaddr2;
298                 priv->hash_regs[11] = &priv->regs->gaddr3;
299                 priv->hash_regs[12] = &priv->regs->gaddr4;
300                 priv->hash_regs[13] = &priv->regs->gaddr5;
301                 priv->hash_regs[14] = &priv->regs->gaddr6;
302                 priv->hash_regs[15] = &priv->regs->gaddr7;
303
304         } else {
305                 priv->extended_hash = 0;
306                 priv->hash_width = 8;
307
308                 priv->hash_regs[0] = &priv->regs->gaddr0;
309                 priv->hash_regs[1] = &priv->regs->gaddr1;
310                 priv->hash_regs[2] = &priv->regs->gaddr2;
311                 priv->hash_regs[3] = &priv->regs->gaddr3;
312                 priv->hash_regs[4] = &priv->regs->gaddr4;
313                 priv->hash_regs[5] = &priv->regs->gaddr5;
314                 priv->hash_regs[6] = &priv->regs->gaddr6;
315                 priv->hash_regs[7] = &priv->regs->gaddr7;
316         }
317
318         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
319                 priv->padding = DEFAULT_PADDING;
320         else
321                 priv->padding = 0;
322
323         dev->hard_header_len += priv->padding;
324
325         if (dev->features & NETIF_F_IP_CSUM)
326                 dev->hard_header_len += GMAC_FCB_LEN;
327
328         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
329 #ifdef CONFIG_GFAR_BUFSTASH
330         priv->rx_stash_size = STASH_LENGTH;
331 #endif
332         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
333         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
334
335         priv->txcoalescing = DEFAULT_TX_COALESCE;
336         priv->txcount = DEFAULT_TXCOUNT;
337         priv->txtime = DEFAULT_TXTIME;
338         priv->rxcoalescing = DEFAULT_RX_COALESCE;
339         priv->rxcount = DEFAULT_RXCOUNT;
340         priv->rxtime = DEFAULT_RXTIME;
341
342         /* Enable most messages by default */
343         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
344
345         err = register_netdev(dev);
346
347         if (err) {
348                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
349                                 dev->name);
350                 goto register_fail;
351         }
352
353         /* Print out the device info */
354         printk(KERN_INFO DEVICE_NAME, dev->name);
355         for (idx = 0; idx < 6; idx++)
356                 printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
357         printk("\n");
358
359         /* Even more device info helps when determining which kernel */
360         /* provided which set of benchmarks.  Since this is global for all */
361         /* devices, we only print it once */
362 #ifdef CONFIG_GFAR_NAPI
363         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
364 #else
365         printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
366 #endif
367         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
368                dev->name, priv->rx_ring_size, priv->tx_ring_size);
369
370         return 0;
371
372 register_fail:
373         iounmap((void *) priv->regs);
374 regs_fail:
375         free_netdev(dev);
376         return err;
377 }
378
379 static int gfar_remove(struct platform_device *pdev)
380 {
381         struct net_device *dev = platform_get_drvdata(pdev);
382         struct gfar_private *priv = netdev_priv(dev);
383
384         platform_set_drvdata(pdev, NULL);
385
386         iounmap((void *) priv->regs);
387         free_netdev(dev);
388
389         return 0;
390 }
391
392
393 /* Initializes driver's PHY state, and attaches to the PHY.
394  * Returns 0 on success.
395  */
396 static int init_phy(struct net_device *dev)
397 {
398         struct gfar_private *priv = netdev_priv(dev);
399         uint gigabit_support =
400                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
401                 SUPPORTED_1000baseT_Full : 0;
402         struct phy_device *phydev;
403
404         priv->oldlink = 0;
405         priv->oldspeed = 0;
406         priv->oldduplex = -1;
407
408         phydev = phy_connect(dev, priv->einfo->bus_id, &adjust_link, 0);
409
410         if (IS_ERR(phydev)) {
411                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
412                 return PTR_ERR(phydev);
413         }
414
415         /* Remove any features not supported by the controller */
416         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
417         phydev->advertising = phydev->supported;
418
419         priv->phydev = phydev;
420
421         return 0;
422 }
423
424 static void init_registers(struct net_device *dev)
425 {
426         struct gfar_private *priv = netdev_priv(dev);
427
428         /* Clear IEVENT */
429         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
430
431         /* Initialize IMASK */
432         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
433
434         /* Init hash registers to zero */
435         gfar_write(&priv->regs->igaddr0, 0);
436         gfar_write(&priv->regs->igaddr1, 0);
437         gfar_write(&priv->regs->igaddr2, 0);
438         gfar_write(&priv->regs->igaddr3, 0);
439         gfar_write(&priv->regs->igaddr4, 0);
440         gfar_write(&priv->regs->igaddr5, 0);
441         gfar_write(&priv->regs->igaddr6, 0);
442         gfar_write(&priv->regs->igaddr7, 0);
443
444         gfar_write(&priv->regs->gaddr0, 0);
445         gfar_write(&priv->regs->gaddr1, 0);
446         gfar_write(&priv->regs->gaddr2, 0);
447         gfar_write(&priv->regs->gaddr3, 0);
448         gfar_write(&priv->regs->gaddr4, 0);
449         gfar_write(&priv->regs->gaddr5, 0);
450         gfar_write(&priv->regs->gaddr6, 0);
451         gfar_write(&priv->regs->gaddr7, 0);
452
453         /* Zero out the rmon mib registers if it has them */
454         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
455                 memset((void *) &(priv->regs->rmon), 0,
456                        sizeof (struct rmon_mib));
457
458                 /* Mask off the CAM interrupts */
459                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
460                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
461         }
462
463         /* Initialize the max receive buffer length */
464         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
465
466 #ifdef CONFIG_GFAR_BUFSTASH
467         /* If we are stashing buffers, we need to set the
468          * extraction length to the size of the buffer */
469         gfar_write(&priv->regs->attreli, priv->rx_stash_size << 16);
470 #endif
471
472         /* Initialize the Minimum Frame Length Register */
473         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
474
475         /* Setup Attributes so that snooping is on for rx */
476         gfar_write(&priv->regs->attr, ATTR_INIT_SETTINGS);
477         gfar_write(&priv->regs->attreli, ATTRELI_INIT_SETTINGS);
478
479         /* Assign the TBI an address which won't conflict with the PHYs */
480         gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
481 }
482
483
484 /* Halt the receive and transmit queues */
485 void gfar_halt(struct net_device *dev)
486 {
487         struct gfar_private *priv = netdev_priv(dev);
488         struct gfar *regs = priv->regs;
489         u32 tempval;
490
491         /* Mask all interrupts */
492         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
493
494         /* Clear all interrupts */
495         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
496
497         /* Stop the DMA, and wait for it to stop */
498         tempval = gfar_read(&priv->regs->dmactrl);
499         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
500             != (DMACTRL_GRS | DMACTRL_GTS)) {
501                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
502                 gfar_write(&priv->regs->dmactrl, tempval);
503
504                 while (!(gfar_read(&priv->regs->ievent) &
505                          (IEVENT_GRSC | IEVENT_GTSC)))
506                         cpu_relax();
507         }
508
509         /* Disable Rx and Tx */
510         tempval = gfar_read(&regs->maccfg1);
511         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
512         gfar_write(&regs->maccfg1, tempval);
513 }
514
515 void stop_gfar(struct net_device *dev)
516 {
517         struct gfar_private *priv = netdev_priv(dev);
518         struct gfar *regs = priv->regs;
519         unsigned long flags;
520
521         phy_stop(priv->phydev);
522
523         /* Lock it down */
524         spin_lock_irqsave(&priv->lock, flags);
525
526         gfar_halt(dev);
527
528         spin_unlock_irqrestore(&priv->lock, flags);
529
530         /* Free the IRQs */
531         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
532                 free_irq(priv->interruptError, dev);
533                 free_irq(priv->interruptTransmit, dev);
534                 free_irq(priv->interruptReceive, dev);
535         } else {
536                 free_irq(priv->interruptTransmit, dev);
537         }
538
539         free_skb_resources(priv);
540
541         dma_free_coherent(NULL,
542                         sizeof(struct txbd8)*priv->tx_ring_size
543                         + sizeof(struct rxbd8)*priv->rx_ring_size,
544                         priv->tx_bd_base,
545                         gfar_read(&regs->tbase0));
546 }
547
548 /* If there are any tx skbs or rx skbs still around, free them.
549  * Then free tx_skbuff and rx_skbuff */
550 static void free_skb_resources(struct gfar_private *priv)
551 {
552         struct rxbd8 *rxbdp;
553         struct txbd8 *txbdp;
554         int i;
555
556         /* Go through all the buffer descriptors and free their data buffers */
557         txbdp = priv->tx_bd_base;
558
559         for (i = 0; i < priv->tx_ring_size; i++) {
560
561                 if (priv->tx_skbuff[i]) {
562                         dma_unmap_single(NULL, txbdp->bufPtr,
563                                         txbdp->length,
564                                         DMA_TO_DEVICE);
565                         dev_kfree_skb_any(priv->tx_skbuff[i]);
566                         priv->tx_skbuff[i] = NULL;
567                 }
568         }
569
570         kfree(priv->tx_skbuff);
571
572         rxbdp = priv->rx_bd_base;
573
574         /* rx_skbuff is not guaranteed to be allocated, so only
575          * free it and its contents if it is allocated */
576         if(priv->rx_skbuff != NULL) {
577                 for (i = 0; i < priv->rx_ring_size; i++) {
578                         if (priv->rx_skbuff[i]) {
579                                 dma_unmap_single(NULL, rxbdp->bufPtr,
580                                                 priv->rx_buffer_size
581                                                 + RXBUF_ALIGNMENT,
582                                                 DMA_FROM_DEVICE);
583
584                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
585                                 priv->rx_skbuff[i] = NULL;
586                         }
587
588                         rxbdp->status = 0;
589                         rxbdp->length = 0;
590                         rxbdp->bufPtr = 0;
591
592                         rxbdp++;
593                 }
594
595                 kfree(priv->rx_skbuff);
596         }
597 }
598
599 void gfar_start(struct net_device *dev)
600 {
601         struct gfar_private *priv = netdev_priv(dev);
602         struct gfar *regs = priv->regs;
603         u32 tempval;
604
605         /* Enable Rx and Tx in MACCFG1 */
606         tempval = gfar_read(&regs->maccfg1);
607         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
608         gfar_write(&regs->maccfg1, tempval);
609
610         /* Initialize DMACTRL to have WWR and WOP */
611         tempval = gfar_read(&priv->regs->dmactrl);
612         tempval |= DMACTRL_INIT_SETTINGS;
613         gfar_write(&priv->regs->dmactrl, tempval);
614
615         /* Clear THLT, so that the DMA starts polling now */
616         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
617
618         /* Make sure we aren't stopped */
619         tempval = gfar_read(&priv->regs->dmactrl);
620         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
621         gfar_write(&priv->regs->dmactrl, tempval);
622
623         /* Unmask the interrupts we look for */
624         gfar_write(&regs->imask, IMASK_DEFAULT);
625 }
626
627 /* Bring the controller up and running */
628 int startup_gfar(struct net_device *dev)
629 {
630         struct txbd8 *txbdp;
631         struct rxbd8 *rxbdp;
632         dma_addr_t addr;
633         unsigned long vaddr;
634         int i;
635         struct gfar_private *priv = netdev_priv(dev);
636         struct gfar *regs = priv->regs;
637         int err = 0;
638         u32 rctrl = 0;
639
640         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
641
642         /* Allocate memory for the buffer descriptors */
643         vaddr = (unsigned long) dma_alloc_coherent(NULL,
644                         sizeof (struct txbd8) * priv->tx_ring_size +
645                         sizeof (struct rxbd8) * priv->rx_ring_size,
646                         &addr, GFP_KERNEL);
647
648         if (vaddr == 0) {
649                 if (netif_msg_ifup(priv))
650                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
651                                         dev->name);
652                 return -ENOMEM;
653         }
654
655         priv->tx_bd_base = (struct txbd8 *) vaddr;
656
657         /* enet DMA only understands physical addresses */
658         gfar_write(&regs->tbase0, addr);
659
660         /* Start the rx descriptor ring where the tx ring leaves off */
661         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
662         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
663         priv->rx_bd_base = (struct rxbd8 *) vaddr;
664         gfar_write(&regs->rbase0, addr);
665
666         /* Setup the skbuff rings */
667         priv->tx_skbuff =
668             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
669                                         priv->tx_ring_size, GFP_KERNEL);
670
671         if (NULL == priv->tx_skbuff) {
672                 if (netif_msg_ifup(priv))
673                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
674                                         dev->name);
675                 err = -ENOMEM;
676                 goto tx_skb_fail;
677         }
678
679         for (i = 0; i < priv->tx_ring_size; i++)
680                 priv->tx_skbuff[i] = NULL;
681
682         priv->rx_skbuff =
683             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
684                                         priv->rx_ring_size, GFP_KERNEL);
685
686         if (NULL == priv->rx_skbuff) {
687                 if (netif_msg_ifup(priv))
688                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
689                                         dev->name);
690                 err = -ENOMEM;
691                 goto rx_skb_fail;
692         }
693
694         for (i = 0; i < priv->rx_ring_size; i++)
695                 priv->rx_skbuff[i] = NULL;
696
697         /* Initialize some variables in our dev structure */
698         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
699         priv->cur_rx = priv->rx_bd_base;
700         priv->skb_curtx = priv->skb_dirtytx = 0;
701         priv->skb_currx = 0;
702
703         /* Initialize Transmit Descriptor Ring */
704         txbdp = priv->tx_bd_base;
705         for (i = 0; i < priv->tx_ring_size; i++) {
706                 txbdp->status = 0;
707                 txbdp->length = 0;
708                 txbdp->bufPtr = 0;
709                 txbdp++;
710         }
711
712         /* Set the last descriptor in the ring to indicate wrap */
713         txbdp--;
714         txbdp->status |= TXBD_WRAP;
715
716         rxbdp = priv->rx_bd_base;
717         for (i = 0; i < priv->rx_ring_size; i++) {
718                 struct sk_buff *skb = NULL;
719
720                 rxbdp->status = 0;
721
722                 skb = gfar_new_skb(dev, rxbdp);
723
724                 priv->rx_skbuff[i] = skb;
725
726                 rxbdp++;
727         }
728
729         /* Set the last descriptor in the ring to wrap */
730         rxbdp--;
731         rxbdp->status |= RXBD_WRAP;
732
733         /* If the device has multiple interrupts, register for
734          * them.  Otherwise, only register for the one */
735         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
736                 /* Install our interrupt handlers for Error,
737                  * Transmit, and Receive */
738                 if (request_irq(priv->interruptError, gfar_error,
739                                 0, "enet_error", dev) < 0) {
740                         if (netif_msg_intr(priv))
741                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
742                                         dev->name, priv->interruptError);
743
744                         err = -1;
745                         goto err_irq_fail;
746                 }
747
748                 if (request_irq(priv->interruptTransmit, gfar_transmit,
749                                 0, "enet_tx", dev) < 0) {
750                         if (netif_msg_intr(priv))
751                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
752                                         dev->name, priv->interruptTransmit);
753
754                         err = -1;
755
756                         goto tx_irq_fail;
757                 }
758
759                 if (request_irq(priv->interruptReceive, gfar_receive,
760                                 0, "enet_rx", dev) < 0) {
761                         if (netif_msg_intr(priv))
762                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
763                                                 dev->name, priv->interruptReceive);
764
765                         err = -1;
766                         goto rx_irq_fail;
767                 }
768         } else {
769                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
770                                 0, "gfar_interrupt", dev) < 0) {
771                         if (netif_msg_intr(priv))
772                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
773                                         dev->name, priv->interruptError);
774
775                         err = -1;
776                         goto err_irq_fail;
777                 }
778         }
779
780         phy_start(priv->phydev);
781
782         /* Configure the coalescing support */
783         if (priv->txcoalescing)
784                 gfar_write(&regs->txic,
785                            mk_ic_value(priv->txcount, priv->txtime));
786         else
787                 gfar_write(&regs->txic, 0);
788
789         if (priv->rxcoalescing)
790                 gfar_write(&regs->rxic,
791                            mk_ic_value(priv->rxcount, priv->rxtime));
792         else
793                 gfar_write(&regs->rxic, 0);
794
795         if (priv->rx_csum_enable)
796                 rctrl |= RCTRL_CHECKSUMMING;
797
798         if (priv->extended_hash)
799                 rctrl |= RCTRL_EXTHASH;
800
801         if (priv->vlan_enable)
802                 rctrl |= RCTRL_VLAN;
803
804         /* Init rctrl based on our settings */
805         gfar_write(&priv->regs->rctrl, rctrl);
806
807         if (dev->features & NETIF_F_IP_CSUM)
808                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
809
810         gfar_start(dev);
811
812         return 0;
813
814 rx_irq_fail:
815         free_irq(priv->interruptTransmit, dev);
816 tx_irq_fail:
817         free_irq(priv->interruptError, dev);
818 err_irq_fail:
819 rx_skb_fail:
820         free_skb_resources(priv);
821 tx_skb_fail:
822         dma_free_coherent(NULL,
823                         sizeof(struct txbd8)*priv->tx_ring_size
824                         + sizeof(struct rxbd8)*priv->rx_ring_size,
825                         priv->tx_bd_base,
826                         gfar_read(&regs->tbase0));
827
828         return err;
829 }
830
831 /* Called when something needs to use the ethernet device */
832 /* Returns 0 for success. */
833 static int gfar_enet_open(struct net_device *dev)
834 {
835         int err;
836
837         /* Initialize a bunch of registers */
838         init_registers(dev);
839
840         gfar_set_mac_address(dev);
841
842         err = init_phy(dev);
843
844         if(err)
845                 return err;
846
847         err = startup_gfar(dev);
848
849         netif_start_queue(dev);
850
851         return err;
852 }
853
854 static struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
855 {
856         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
857
858         memset(fcb, 0, GMAC_FCB_LEN);
859
860         /* Flag the bd so the controller looks for the FCB */
861         bdp->status |= TXBD_TOE;
862
863         return fcb;
864 }
865
866 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
867 {
868         int len;
869
870         /* If we're here, it's a IP packet with a TCP or UDP
871          * payload.  We set it to checksum, using a pseudo-header
872          * we provide
873          */
874         fcb->ip = 1;
875         fcb->tup = 1;
876         fcb->ctu = 1;
877         fcb->nph = 1;
878
879         /* Notify the controller what the protocol is */
880         if (skb->nh.iph->protocol == IPPROTO_UDP)
881                 fcb->udp = 1;
882
883         /* l3os is the distance between the start of the
884          * frame (skb->data) and the start of the IP hdr.
885          * l4os is the distance between the start of the
886          * l3 hdr and the l4 hdr */
887         fcb->l3os = (u16)(skb->nh.raw - skb->data - GMAC_FCB_LEN);
888         fcb->l4os = (u16)(skb->h.raw - skb->nh.raw);
889
890         len = skb->nh.iph->tot_len - fcb->l4os;
891
892         /* Provide the pseudoheader csum */
893         fcb->phcs = ~csum_tcpudp_magic(skb->nh.iph->saddr,
894                         skb->nh.iph->daddr, len,
895                         skb->nh.iph->protocol, 0);
896 }
897
898 void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
899 {
900         fcb->vln = 1;
901         fcb->vlctl = vlan_tx_tag_get(skb);
902 }
903
904 /* This is called by the kernel when a frame is ready for transmission. */
905 /* It is pointed to by the dev->hard_start_xmit function pointer */
906 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
907 {
908         struct gfar_private *priv = netdev_priv(dev);
909         struct txfcb *fcb = NULL;
910         struct txbd8 *txbdp;
911
912         /* Update transmit stats */
913         priv->stats.tx_bytes += skb->len;
914
915         /* Lock priv now */
916         spin_lock_irq(&priv->lock);
917
918         /* Point at the first free tx descriptor */
919         txbdp = priv->cur_tx;
920
921         /* Clear all but the WRAP status flags */
922         txbdp->status &= TXBD_WRAP;
923
924         /* Set up checksumming */
925         if ((dev->features & NETIF_F_IP_CSUM)
926                         && (CHECKSUM_HW == skb->ip_summed)) {
927                 fcb = gfar_add_fcb(skb, txbdp);
928                 gfar_tx_checksum(skb, fcb);
929         }
930
931         if (priv->vlan_enable &&
932                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
933                 if (NULL == fcb)
934                         fcb = gfar_add_fcb(skb, txbdp);
935
936                 gfar_tx_vlan(skb, fcb);
937         }
938
939         /* Set buffer length and pointer */
940         txbdp->length = skb->len;
941         txbdp->bufPtr = dma_map_single(NULL, skb->data,
942                         skb->len, DMA_TO_DEVICE);
943
944         /* Save the skb pointer so we can free it later */
945         priv->tx_skbuff[priv->skb_curtx] = skb;
946
947         /* Update the current skb pointer (wrapping if this was the last) */
948         priv->skb_curtx =
949             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
950
951         /* Flag the BD as interrupt-causing */
952         txbdp->status |= TXBD_INTERRUPT;
953
954         /* Flag the BD as ready to go, last in frame, and  */
955         /* in need of CRC */
956         txbdp->status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
957
958         dev->trans_start = jiffies;
959
960         /* If this was the last BD in the ring, the next one */
961         /* is at the beginning of the ring */
962         if (txbdp->status & TXBD_WRAP)
963                 txbdp = priv->tx_bd_base;
964         else
965                 txbdp++;
966
967         /* If the next BD still needs to be cleaned up, then the bds
968            are full.  We need to tell the kernel to stop sending us stuff. */
969         if (txbdp == priv->dirty_tx) {
970                 netif_stop_queue(dev);
971
972                 priv->stats.tx_fifo_errors++;
973         }
974
975         /* Update the current txbd to the next one */
976         priv->cur_tx = txbdp;
977
978         /* Tell the DMA to go go go */
979         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
980
981         /* Unlock priv */
982         spin_unlock_irq(&priv->lock);
983
984         return 0;
985 }
986
987 /* Stops the kernel queue, and halts the controller */
988 static int gfar_close(struct net_device *dev)
989 {
990         struct gfar_private *priv = netdev_priv(dev);
991         stop_gfar(dev);
992
993         /* Disconnect from the PHY */
994         phy_disconnect(priv->phydev);
995         priv->phydev = NULL;
996
997         netif_stop_queue(dev);
998
999         return 0;
1000 }
1001
1002 /* returns a net_device_stats structure pointer */
1003 static struct net_device_stats * gfar_get_stats(struct net_device *dev)
1004 {
1005         struct gfar_private *priv = netdev_priv(dev);
1006
1007         return &(priv->stats);
1008 }
1009
1010 /* Changes the mac address if the controller is not running. */
1011 int gfar_set_mac_address(struct net_device *dev)
1012 {
1013         struct gfar_private *priv = netdev_priv(dev);
1014         int i;
1015         char tmpbuf[MAC_ADDR_LEN];
1016         u32 tempval;
1017
1018         /* Now copy it into the mac registers backwards, cuz */
1019         /* little endian is silly */
1020         for (i = 0; i < MAC_ADDR_LEN; i++)
1021                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->dev_addr[i];
1022
1023         gfar_write(&priv->regs->macstnaddr1, *((u32 *) (tmpbuf)));
1024
1025         tempval = *((u32 *) (tmpbuf + 4));
1026
1027         gfar_write(&priv->regs->macstnaddr2, tempval);
1028
1029         return 0;
1030 }
1031
1032
1033 /* Enables and disables VLAN insertion/extraction */
1034 static void gfar_vlan_rx_register(struct net_device *dev,
1035                 struct vlan_group *grp)
1036 {
1037         struct gfar_private *priv = netdev_priv(dev);
1038         unsigned long flags;
1039         u32 tempval;
1040
1041         spin_lock_irqsave(&priv->lock, flags);
1042
1043         priv->vlgrp = grp;
1044
1045         if (grp) {
1046                 /* Enable VLAN tag insertion */
1047                 tempval = gfar_read(&priv->regs->tctrl);
1048                 tempval |= TCTRL_VLINS;
1049
1050                 gfar_write(&priv->regs->tctrl, tempval);
1051                 
1052                 /* Enable VLAN tag extraction */
1053                 tempval = gfar_read(&priv->regs->rctrl);
1054                 tempval |= RCTRL_VLEX;
1055                 gfar_write(&priv->regs->rctrl, tempval);
1056         } else {
1057                 /* Disable VLAN tag insertion */
1058                 tempval = gfar_read(&priv->regs->tctrl);
1059                 tempval &= ~TCTRL_VLINS;
1060                 gfar_write(&priv->regs->tctrl, tempval);
1061
1062                 /* Disable VLAN tag extraction */
1063                 tempval = gfar_read(&priv->regs->rctrl);
1064                 tempval &= ~RCTRL_VLEX;
1065                 gfar_write(&priv->regs->rctrl, tempval);
1066         }
1067
1068         spin_unlock_irqrestore(&priv->lock, flags);
1069 }
1070
1071
1072 static void gfar_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
1073 {
1074         struct gfar_private *priv = netdev_priv(dev);
1075         unsigned long flags;
1076
1077         spin_lock_irqsave(&priv->lock, flags);
1078
1079         if (priv->vlgrp)
1080                 priv->vlgrp->vlan_devices[vid] = NULL;
1081
1082         spin_unlock_irqrestore(&priv->lock, flags);
1083 }
1084
1085
1086 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1087 {
1088         int tempsize, tempval;
1089         struct gfar_private *priv = netdev_priv(dev);
1090         int oldsize = priv->rx_buffer_size;
1091         int frame_size = new_mtu + ETH_HLEN;
1092
1093         if (priv->vlan_enable)
1094                 frame_size += VLAN_ETH_HLEN;
1095
1096         if (gfar_uses_fcb(priv))
1097                 frame_size += GMAC_FCB_LEN;
1098
1099         frame_size += priv->padding;
1100
1101         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1102                 if (netif_msg_drv(priv))
1103                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1104                                         dev->name);
1105                 return -EINVAL;
1106         }
1107
1108         tempsize =
1109             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1110             INCREMENTAL_BUFFER_SIZE;
1111
1112         /* Only stop and start the controller if it isn't already
1113          * stopped */
1114         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1115                 stop_gfar(dev);
1116
1117         priv->rx_buffer_size = tempsize;
1118
1119         dev->mtu = new_mtu;
1120
1121         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1122         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1123
1124         /* If the mtu is larger than the max size for standard
1125          * ethernet frames (ie, a jumbo frame), then set maccfg2
1126          * to allow huge frames, and to check the length */
1127         tempval = gfar_read(&priv->regs->maccfg2);
1128
1129         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1130                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1131         else
1132                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1133
1134         gfar_write(&priv->regs->maccfg2, tempval);
1135
1136         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1137                 startup_gfar(dev);
1138
1139         return 0;
1140 }
1141
1142 /* gfar_timeout gets called when a packet has not been
1143  * transmitted after a set amount of time.
1144  * For now, assume that clearing out all the structures, and
1145  * starting over will fix the problem. */
1146 static void gfar_timeout(struct net_device *dev)
1147 {
1148         struct gfar_private *priv = netdev_priv(dev);
1149
1150         priv->stats.tx_errors++;
1151
1152         if (dev->flags & IFF_UP) {
1153                 stop_gfar(dev);
1154                 startup_gfar(dev);
1155         }
1156
1157         netif_schedule(dev);
1158 }
1159
1160 /* Interrupt Handler for Transmit complete */
1161 static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs)
1162 {
1163         struct net_device *dev = (struct net_device *) dev_id;
1164         struct gfar_private *priv = netdev_priv(dev);
1165         struct txbd8 *bdp;
1166
1167         /* Clear IEVENT */
1168         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1169
1170         /* Lock priv */
1171         spin_lock(&priv->lock);
1172         bdp = priv->dirty_tx;
1173         while ((bdp->status & TXBD_READY) == 0) {
1174                 /* If dirty_tx and cur_tx are the same, then either the */
1175                 /* ring is empty or full now (it could only be full in the beginning, */
1176                 /* obviously).  If it is empty, we are done. */
1177                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1178                         break;
1179
1180                 priv->stats.tx_packets++;
1181
1182                 /* Deferred means some collisions occurred during transmit, */
1183                 /* but we eventually sent the packet. */
1184                 if (bdp->status & TXBD_DEF)
1185                         priv->stats.collisions++;
1186
1187                 /* Free the sk buffer associated with this TxBD */
1188                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1189                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1190                 priv->skb_dirtytx =
1191                     (priv->skb_dirtytx +
1192                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1193
1194                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1195                 if (bdp->status & TXBD_WRAP)
1196                         bdp = priv->tx_bd_base;
1197                 else
1198                         bdp++;
1199
1200                 /* Move dirty_tx to be the next bd */
1201                 priv->dirty_tx = bdp;
1202
1203                 /* We freed a buffer, so now we can restart transmission */
1204                 if (netif_queue_stopped(dev))
1205                         netif_wake_queue(dev);
1206         } /* while ((bdp->status & TXBD_READY) == 0) */
1207
1208         /* If we are coalescing the interrupts, reset the timer */
1209         /* Otherwise, clear it */
1210         if (priv->txcoalescing)
1211                 gfar_write(&priv->regs->txic,
1212                            mk_ic_value(priv->txcount, priv->txtime));
1213         else
1214                 gfar_write(&priv->regs->txic, 0);
1215
1216         spin_unlock(&priv->lock);
1217
1218         return IRQ_HANDLED;
1219 }
1220
1221 struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1222 {
1223         struct gfar_private *priv = netdev_priv(dev);
1224         struct sk_buff *skb = NULL;
1225         unsigned int timeout = SKB_ALLOC_TIMEOUT;
1226
1227         /* We have to allocate the skb, so keep trying till we succeed */
1228         while ((!skb) && timeout--)
1229                 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1230
1231         if (NULL == skb)
1232                 return NULL;
1233
1234         /* We need the data buffer to be aligned properly.  We will reserve
1235          * as many bytes as needed to align the data properly
1236          */
1237         skb_reserve(skb,
1238                     RXBUF_ALIGNMENT -
1239                     (((unsigned) skb->data) & (RXBUF_ALIGNMENT - 1)));
1240
1241         skb->dev = dev;
1242
1243         bdp->bufPtr = dma_map_single(NULL, skb->data,
1244                         priv->rx_buffer_size + RXBUF_ALIGNMENT,
1245                         DMA_FROM_DEVICE);
1246
1247         bdp->length = 0;
1248
1249         /* Mark the buffer empty */
1250         bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1251
1252         return skb;
1253 }
1254
1255 static inline void count_errors(unsigned short status, struct gfar_private *priv)
1256 {
1257         struct net_device_stats *stats = &priv->stats;
1258         struct gfar_extra_stats *estats = &priv->extra_stats;
1259
1260         /* If the packet was truncated, none of the other errors
1261          * matter */
1262         if (status & RXBD_TRUNCATED) {
1263                 stats->rx_length_errors++;
1264
1265                 estats->rx_trunc++;
1266
1267                 return;
1268         }
1269         /* Count the errors, if there were any */
1270         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1271                 stats->rx_length_errors++;
1272
1273                 if (status & RXBD_LARGE)
1274                         estats->rx_large++;
1275                 else
1276                         estats->rx_short++;
1277         }
1278         if (status & RXBD_NONOCTET) {
1279                 stats->rx_frame_errors++;
1280                 estats->rx_nonoctet++;
1281         }
1282         if (status & RXBD_CRCERR) {
1283                 estats->rx_crcerr++;
1284                 stats->rx_crc_errors++;
1285         }
1286         if (status & RXBD_OVERRUN) {
1287                 estats->rx_overrun++;
1288                 stats->rx_crc_errors++;
1289         }
1290 }
1291
1292 irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs)
1293 {
1294         struct net_device *dev = (struct net_device *) dev_id;
1295         struct gfar_private *priv = netdev_priv(dev);
1296
1297 #ifdef CONFIG_GFAR_NAPI
1298         u32 tempval;
1299 #endif
1300
1301         /* Clear IEVENT, so rx interrupt isn't called again
1302          * because of this interrupt */
1303         gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1304
1305         /* support NAPI */
1306 #ifdef CONFIG_GFAR_NAPI
1307         if (netif_rx_schedule_prep(dev)) {
1308                 tempval = gfar_read(&priv->regs->imask);
1309                 tempval &= IMASK_RX_DISABLED;
1310                 gfar_write(&priv->regs->imask, tempval);
1311
1312                 __netif_rx_schedule(dev);
1313         } else {
1314                 if (netif_msg_rx_err(priv))
1315                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1316                                 dev->name, gfar_read(&priv->regs->ievent),
1317                                 gfar_read(&priv->regs->imask));
1318         }
1319 #else
1320
1321         spin_lock(&priv->lock);
1322         gfar_clean_rx_ring(dev, priv->rx_ring_size);
1323
1324         /* If we are coalescing interrupts, update the timer */
1325         /* Otherwise, clear it */
1326         if (priv->rxcoalescing)
1327                 gfar_write(&priv->regs->rxic,
1328                            mk_ic_value(priv->rxcount, priv->rxtime));
1329         else
1330                 gfar_write(&priv->regs->rxic, 0);
1331
1332         spin_unlock(&priv->lock);
1333 #endif
1334
1335         return IRQ_HANDLED;
1336 }
1337
1338 static inline int gfar_rx_vlan(struct sk_buff *skb,
1339                 struct vlan_group *vlgrp, unsigned short vlctl)
1340 {
1341 #ifdef CONFIG_GFAR_NAPI
1342         return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1343 #else
1344         return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1345 #endif
1346 }
1347
1348 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1349 {
1350         /* If valid headers were found, and valid sums
1351          * were verified, then we tell the kernel that no
1352          * checksumming is necessary.  Otherwise, it is */
1353         if (fcb->cip && !fcb->eip && fcb->ctu && !fcb->etu)
1354                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1355         else
1356                 skb->ip_summed = CHECKSUM_NONE;
1357 }
1358
1359
1360 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1361 {
1362         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1363
1364         /* Remove the FCB from the skb */
1365         skb_pull(skb, GMAC_FCB_LEN);
1366
1367         return fcb;
1368 }
1369
1370 /* gfar_process_frame() -- handle one incoming packet if skb
1371  * isn't NULL.  */
1372 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1373                 int length)
1374 {
1375         struct gfar_private *priv = netdev_priv(dev);
1376         struct rxfcb *fcb = NULL;
1377
1378         if (NULL == skb) {
1379                 if (netif_msg_rx_err(priv))
1380                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1381                 priv->stats.rx_dropped++;
1382                 priv->extra_stats.rx_skbmissing++;
1383         } else {
1384                 int ret;
1385
1386                 /* Prep the skb for the packet */
1387                 skb_put(skb, length);
1388
1389                 /* Grab the FCB if there is one */
1390                 if (gfar_uses_fcb(priv))
1391                         fcb = gfar_get_fcb(skb);
1392
1393                 /* Remove the padded bytes, if there are any */
1394                 if (priv->padding)
1395                         skb_pull(skb, priv->padding);
1396
1397                 if (priv->rx_csum_enable)
1398                         gfar_rx_checksum(skb, fcb);
1399
1400                 /* Tell the skb what kind of packet this is */
1401                 skb->protocol = eth_type_trans(skb, dev);
1402
1403                 /* Send the packet up the stack */
1404                 if (unlikely(priv->vlgrp && fcb->vln))
1405                         ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1406                 else
1407                         ret = RECEIVE(skb);
1408
1409                 if (NET_RX_DROP == ret)
1410                         priv->extra_stats.kernel_dropped++;
1411         }
1412
1413         return 0;
1414 }
1415
1416 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1417  *   until the budget/quota has been reached. Returns the number
1418  *   of frames handled
1419  */
1420 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1421 {
1422         struct rxbd8 *bdp;
1423         struct sk_buff *skb;
1424         u16 pkt_len;
1425         int howmany = 0;
1426         struct gfar_private *priv = netdev_priv(dev);
1427
1428         /* Get the first full descriptor */
1429         bdp = priv->cur_rx;
1430
1431         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1432                 skb = priv->rx_skbuff[priv->skb_currx];
1433
1434                 if (!(bdp->status &
1435                       (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1436                        | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1437                         /* Increment the number of packets */
1438                         priv->stats.rx_packets++;
1439                         howmany++;
1440
1441                         /* Remove the FCS from the packet length */
1442                         pkt_len = bdp->length - 4;
1443
1444                         gfar_process_frame(dev, skb, pkt_len);
1445
1446                         priv->stats.rx_bytes += pkt_len;
1447                 } else {
1448                         count_errors(bdp->status, priv);
1449
1450                         if (skb)
1451                                 dev_kfree_skb_any(skb);
1452
1453                         priv->rx_skbuff[priv->skb_currx] = NULL;
1454                 }
1455
1456                 dev->last_rx = jiffies;
1457
1458                 /* Clear the status flags for this buffer */
1459                 bdp->status &= ~RXBD_STATS;
1460
1461                 /* Add another skb for the future */
1462                 skb = gfar_new_skb(dev, bdp);
1463                 priv->rx_skbuff[priv->skb_currx] = skb;
1464
1465                 /* Update to the next pointer */
1466                 if (bdp->status & RXBD_WRAP)
1467                         bdp = priv->rx_bd_base;
1468                 else
1469                         bdp++;
1470
1471                 /* update to point at the next skb */
1472                 priv->skb_currx =
1473                     (priv->skb_currx +
1474                      1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1475
1476         }
1477
1478         /* Update the current rxbd pointer to be the next one */
1479         priv->cur_rx = bdp;
1480
1481         /* If no packets have arrived since the
1482          * last one we processed, clear the IEVENT RX and
1483          * BSY bits so that another interrupt won't be
1484          * generated when we set IMASK */
1485         if (bdp->status & RXBD_EMPTY)
1486                 gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1487
1488         return howmany;
1489 }
1490
1491 #ifdef CONFIG_GFAR_NAPI
1492 static int gfar_poll(struct net_device *dev, int *budget)
1493 {
1494         int howmany;
1495         struct gfar_private *priv = netdev_priv(dev);
1496         int rx_work_limit = *budget;
1497
1498         if (rx_work_limit > dev->quota)
1499                 rx_work_limit = dev->quota;
1500
1501         howmany = gfar_clean_rx_ring(dev, rx_work_limit);
1502
1503         dev->quota -= howmany;
1504         rx_work_limit -= howmany;
1505         *budget -= howmany;
1506
1507         if (rx_work_limit >= 0) {
1508                 netif_rx_complete(dev);
1509
1510                 /* Clear the halt bit in RSTAT */
1511                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1512
1513                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1514
1515                 /* If we are coalescing interrupts, update the timer */
1516                 /* Otherwise, clear it */
1517                 if (priv->rxcoalescing)
1518                         gfar_write(&priv->regs->rxic,
1519                                    mk_ic_value(priv->rxcount, priv->rxtime));
1520                 else
1521                         gfar_write(&priv->regs->rxic, 0);
1522         }
1523
1524         return (rx_work_limit < 0) ? 1 : 0;
1525 }
1526 #endif
1527
1528 /* The interrupt handler for devices with one interrupt */
1529 static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1530 {
1531         struct net_device *dev = dev_id;
1532         struct gfar_private *priv = netdev_priv(dev);
1533
1534         /* Save ievent for future reference */
1535         u32 events = gfar_read(&priv->regs->ievent);
1536
1537         /* Clear IEVENT */
1538         gfar_write(&priv->regs->ievent, events);
1539
1540         /* Check for reception */
1541         if ((events & IEVENT_RXF0) || (events & IEVENT_RXB0))
1542                 gfar_receive(irq, dev_id, regs);
1543
1544         /* Check for transmit completion */
1545         if ((events & IEVENT_TXF) || (events & IEVENT_TXB))
1546                 gfar_transmit(irq, dev_id, regs);
1547
1548         /* Update error statistics */
1549         if (events & IEVENT_TXE) {
1550                 priv->stats.tx_errors++;
1551
1552                 if (events & IEVENT_LC)
1553                         priv->stats.tx_window_errors++;
1554                 if (events & IEVENT_CRL)
1555                         priv->stats.tx_aborted_errors++;
1556                 if (events & IEVENT_XFUN) {
1557                         if (netif_msg_tx_err(priv))
1558                                 printk(KERN_WARNING "%s: tx underrun. dropped packet\n", dev->name);
1559                         priv->stats.tx_dropped++;
1560                         priv->extra_stats.tx_underrun++;
1561
1562                         /* Reactivate the Tx Queues */
1563                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1564                 }
1565         }
1566         if (events & IEVENT_BSY) {
1567                 priv->stats.rx_errors++;
1568                 priv->extra_stats.rx_bsy++;
1569
1570                 gfar_receive(irq, dev_id, regs);
1571
1572 #ifndef CONFIG_GFAR_NAPI
1573                 /* Clear the halt bit in RSTAT */
1574                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1575 #endif
1576
1577                 if (netif_msg_rx_err(priv))
1578                         printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1579                                         dev->name,
1580                                         gfar_read(&priv->regs->rstat));
1581         }
1582         if (events & IEVENT_BABR) {
1583                 priv->stats.rx_errors++;
1584                 priv->extra_stats.rx_babr++;
1585
1586                 if (netif_msg_rx_err(priv))
1587                         printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1588         }
1589         if (events & IEVENT_EBERR) {
1590                 priv->extra_stats.eberr++;
1591                 if (netif_msg_rx_err(priv))
1592                         printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1593         }
1594         if ((events & IEVENT_RXC) && (netif_msg_rx_err(priv)))
1595                         printk(KERN_DEBUG "%s: control frame\n", dev->name);
1596
1597         if (events & IEVENT_BABT) {
1598                 priv->extra_stats.tx_babt++;
1599                 if (netif_msg_rx_err(priv))
1600                         printk(KERN_DEBUG "%s: babt error\n", dev->name);
1601         }
1602
1603         return IRQ_HANDLED;
1604 }
1605
1606 /* Called every time the controller might need to be made
1607  * aware of new link state.  The PHY code conveys this
1608  * information through variables in the phydev structure, and this
1609  * function converts those variables into the appropriate
1610  * register values, and can bring down the device if needed.
1611  */
1612 static void adjust_link(struct net_device *dev)
1613 {
1614         struct gfar_private *priv = netdev_priv(dev);
1615         struct gfar *regs = priv->regs;
1616         unsigned long flags;
1617         struct phy_device *phydev = priv->phydev;
1618         int new_state = 0;
1619
1620         spin_lock_irqsave(&priv->lock, flags);
1621         if (phydev->link) {
1622                 u32 tempval = gfar_read(&regs->maccfg2);
1623
1624                 /* Now we make sure that we can be in full duplex mode.
1625                  * If not, we operate in half-duplex mode. */
1626                 if (phydev->duplex != priv->oldduplex) {
1627                         new_state = 1;
1628                         if (!(phydev->duplex))
1629                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1630                         else
1631                                 tempval |= MACCFG2_FULL_DUPLEX;
1632
1633                         priv->oldduplex = phydev->duplex;
1634                 }
1635
1636                 if (phydev->speed != priv->oldspeed) {
1637                         new_state = 1;
1638                         switch (phydev->speed) {
1639                         case 1000:
1640                                 tempval =
1641                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1642                                 break;
1643                         case 100:
1644                         case 10:
1645                                 tempval =
1646                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1647                                 break;
1648                         default:
1649                                 if (netif_msg_link(priv))
1650                                         printk(KERN_WARNING
1651                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1652                                                 dev->name, phydev->speed);
1653                                 break;
1654                         }
1655
1656                         priv->oldspeed = phydev->speed;
1657                 }
1658
1659                 gfar_write(&regs->maccfg2, tempval);
1660
1661                 if (!priv->oldlink) {
1662                         new_state = 1;
1663                         priv->oldlink = 1;
1664                         netif_schedule(dev);
1665                 }
1666         } else if (priv->oldlink) {
1667                 new_state = 1;
1668                 priv->oldlink = 0;
1669                 priv->oldspeed = 0;
1670                 priv->oldduplex = -1;
1671         }
1672
1673         if (new_state && netif_msg_link(priv))
1674                 phy_print_status(phydev);
1675
1676         spin_unlock_irqrestore(&priv->lock, flags);
1677 }
1678
1679 /* Update the hash table based on the current list of multicast
1680  * addresses we subscribe to.  Also, change the promiscuity of
1681  * the device based on the flags (this function is called
1682  * whenever dev->flags is changed */
1683 static void gfar_set_multi(struct net_device *dev)
1684 {
1685         struct dev_mc_list *mc_ptr;
1686         struct gfar_private *priv = netdev_priv(dev);
1687         struct gfar *regs = priv->regs;
1688         u32 tempval;
1689
1690         if(dev->flags & IFF_PROMISC) {
1691                 if (netif_msg_drv(priv))
1692                         printk(KERN_INFO "%s: Entering promiscuous mode.\n",
1693                                         dev->name);
1694                 /* Set RCTRL to PROM */
1695                 tempval = gfar_read(&regs->rctrl);
1696                 tempval |= RCTRL_PROM;
1697                 gfar_write(&regs->rctrl, tempval);
1698         } else {
1699                 /* Set RCTRL to not PROM */
1700                 tempval = gfar_read(&regs->rctrl);
1701                 tempval &= ~(RCTRL_PROM);
1702                 gfar_write(&regs->rctrl, tempval);
1703         }
1704         
1705         if(dev->flags & IFF_ALLMULTI) {
1706                 /* Set the hash to rx all multicast frames */
1707                 gfar_write(&regs->igaddr0, 0xffffffff);
1708                 gfar_write(&regs->igaddr1, 0xffffffff);
1709                 gfar_write(&regs->igaddr2, 0xffffffff);
1710                 gfar_write(&regs->igaddr3, 0xffffffff);
1711                 gfar_write(&regs->igaddr4, 0xffffffff);
1712                 gfar_write(&regs->igaddr5, 0xffffffff);
1713                 gfar_write(&regs->igaddr6, 0xffffffff);
1714                 gfar_write(&regs->igaddr7, 0xffffffff);
1715                 gfar_write(&regs->gaddr0, 0xffffffff);
1716                 gfar_write(&regs->gaddr1, 0xffffffff);
1717                 gfar_write(&regs->gaddr2, 0xffffffff);
1718                 gfar_write(&regs->gaddr3, 0xffffffff);
1719                 gfar_write(&regs->gaddr4, 0xffffffff);
1720                 gfar_write(&regs->gaddr5, 0xffffffff);
1721                 gfar_write(&regs->gaddr6, 0xffffffff);
1722                 gfar_write(&regs->gaddr7, 0xffffffff);
1723         } else {
1724                 /* zero out the hash */
1725                 gfar_write(&regs->igaddr0, 0x0);
1726                 gfar_write(&regs->igaddr1, 0x0);
1727                 gfar_write(&regs->igaddr2, 0x0);
1728                 gfar_write(&regs->igaddr3, 0x0);
1729                 gfar_write(&regs->igaddr4, 0x0);
1730                 gfar_write(&regs->igaddr5, 0x0);
1731                 gfar_write(&regs->igaddr6, 0x0);
1732                 gfar_write(&regs->igaddr7, 0x0);
1733                 gfar_write(&regs->gaddr0, 0x0);
1734                 gfar_write(&regs->gaddr1, 0x0);
1735                 gfar_write(&regs->gaddr2, 0x0);
1736                 gfar_write(&regs->gaddr3, 0x0);
1737                 gfar_write(&regs->gaddr4, 0x0);
1738                 gfar_write(&regs->gaddr5, 0x0);
1739                 gfar_write(&regs->gaddr6, 0x0);
1740                 gfar_write(&regs->gaddr7, 0x0);
1741
1742                 if(dev->mc_count == 0)
1743                         return;
1744
1745                 /* Parse the list, and set the appropriate bits */
1746                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1747                         gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1748                 }
1749         }
1750
1751         return;
1752 }
1753
1754 /* Set the appropriate hash bit for the given addr */
1755 /* The algorithm works like so:
1756  * 1) Take the Destination Address (ie the multicast address), and
1757  * do a CRC on it (little endian), and reverse the bits of the
1758  * result.
1759  * 2) Use the 8 most significant bits as a hash into a 256-entry
1760  * table.  The table is controlled through 8 32-bit registers:
1761  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1762  * gaddr7.  This means that the 3 most significant bits in the
1763  * hash index which gaddr register to use, and the 5 other bits
1764  * indicate which bit (assuming an IBM numbering scheme, which
1765  * for PowerPC (tm) is usually the case) in the register holds
1766  * the entry. */
1767 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1768 {
1769         u32 tempval;
1770         struct gfar_private *priv = netdev_priv(dev);
1771         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1772         int width = priv->hash_width;
1773         u8 whichbit = (result >> (32 - width)) & 0x1f;
1774         u8 whichreg = result >> (32 - width + 5);
1775         u32 value = (1 << (31-whichbit));
1776
1777         tempval = gfar_read(priv->hash_regs[whichreg]);
1778         tempval |= value;
1779         gfar_write(priv->hash_regs[whichreg], tempval);
1780
1781         return;
1782 }
1783
1784 /* GFAR error interrupt handler */
1785 static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs)
1786 {
1787         struct net_device *dev = dev_id;
1788         struct gfar_private *priv = netdev_priv(dev);
1789
1790         /* Save ievent for future reference */
1791         u32 events = gfar_read(&priv->regs->ievent);
1792
1793         /* Clear IEVENT */
1794         gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1795
1796         /* Hmm... */
1797         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1798                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1799                                 dev->name, events, gfar_read(&priv->regs->imask));
1800
1801         /* Update the error counters */
1802         if (events & IEVENT_TXE) {
1803                 priv->stats.tx_errors++;
1804
1805                 if (events & IEVENT_LC)
1806                         priv->stats.tx_window_errors++;
1807                 if (events & IEVENT_CRL)
1808                         priv->stats.tx_aborted_errors++;
1809                 if (events & IEVENT_XFUN) {
1810                         if (netif_msg_tx_err(priv))
1811                                 printk(KERN_DEBUG "%s: underrun.  packet dropped.\n",
1812                                                 dev->name);
1813                         priv->stats.tx_dropped++;
1814                         priv->extra_stats.tx_underrun++;
1815
1816                         /* Reactivate the Tx Queues */
1817                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1818                 }
1819                 if (netif_msg_tx_err(priv))
1820                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1821         }
1822         if (events & IEVENT_BSY) {
1823                 priv->stats.rx_errors++;
1824                 priv->extra_stats.rx_bsy++;
1825
1826                 gfar_receive(irq, dev_id, regs);
1827
1828 #ifndef CONFIG_GFAR_NAPI
1829                 /* Clear the halt bit in RSTAT */
1830                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1831 #endif
1832
1833                 if (netif_msg_rx_err(priv))
1834                         printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1835                                         dev->name,
1836                                         gfar_read(&priv->regs->rstat));
1837         }
1838         if (events & IEVENT_BABR) {
1839                 priv->stats.rx_errors++;
1840                 priv->extra_stats.rx_babr++;
1841
1842                 if (netif_msg_rx_err(priv))
1843                         printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1844         }
1845         if (events & IEVENT_EBERR) {
1846                 priv->extra_stats.eberr++;
1847                 if (netif_msg_rx_err(priv))
1848                         printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1849         }
1850         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1851                 if (netif_msg_rx_status(priv))
1852                         printk(KERN_DEBUG "%s: control frame\n", dev->name);
1853
1854         if (events & IEVENT_BABT) {
1855                 priv->extra_stats.tx_babt++;
1856                 if (netif_msg_tx_err(priv))
1857                         printk(KERN_DEBUG "%s: babt error\n", dev->name);
1858         }
1859         return IRQ_HANDLED;
1860 }
1861
1862 /* Structure for a device driver */
1863 static struct platform_driver gfar_driver = {
1864         .probe = gfar_probe,
1865         .remove = gfar_remove,
1866         .driver = {
1867                 .name = "fsl-gianfar",
1868         },
1869 };
1870
1871 static int __init gfar_init(void)
1872 {
1873         int err = gfar_mdio_init();
1874
1875         if (err)
1876                 return err;
1877
1878         err = platform_driver_register(&gfar_driver);
1879
1880         if (err)
1881                 gfar_mdio_exit();
1882         
1883         return err;
1884 }
1885
1886 static void __exit gfar_exit(void)
1887 {
1888         platform_driver_unregister(&gfar_driver);
1889         gfar_mdio_exit();
1890 }
1891
1892 module_init(gfar_init);
1893 module_exit(gfar_exit);
1894