2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
18 #include <linux/tty.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
29 #include <asm/pci-bridge.h>
31 #ifdef CONFIG_PMAC_BACKLIGHT
32 #include <asm/backlight.h>
40 #ifndef CONFIG_PCI /* sanity check */
41 #error This driver requires PCI support.
44 #undef CONFIG_FB_NVIDIA_DEBUG
45 #ifdef CONFIG_FB_NVIDIA_DEBUG
46 #define NVTRACE printk
48 #define NVTRACE if (0) printk
51 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
52 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
54 #ifdef CONFIG_FB_NVIDIA_DEBUG
55 #define assert(expr) \
57 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
58 #expr,__FILE__,__FUNCTION__,__LINE__); \
65 #define PFX "nvidiafb: "
67 /* HW cursor parameters */
70 static struct pci_device_id nvidiafb_pci_tbl[] = {
71 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
72 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
73 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
74 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
75 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
76 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
77 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN,
78 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
79 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
80 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
81 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
82 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
83 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
84 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
85 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
86 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
87 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
88 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
89 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
90 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
91 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
92 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
93 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
94 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
95 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
96 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
97 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
98 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
99 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
100 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
101 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
103 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
105 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
107 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
109 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
111 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
113 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
115 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
117 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
119 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
121 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
123 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
125 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
127 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
129 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
131 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
133 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
135 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
137 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
139 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
141 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
143 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
145 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
147 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
149 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
151 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
155 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
157 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
159 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
161 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
163 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
165 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
167 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
169 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
171 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
175 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
177 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
179 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
181 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
183 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
185 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
187 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
189 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
191 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
193 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
195 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
197 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
199 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
201 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
203 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
205 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
207 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
209 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
211 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
213 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
215 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
217 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
219 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
221 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
223 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
225 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
227 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
229 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
231 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
233 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
235 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
237 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
239 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
241 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
243 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
245 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
247 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
249 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
251 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
253 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
255 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
257 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
259 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
261 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
263 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
265 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
267 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
269 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800,
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
271 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
273 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
275 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000,
276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
277 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT,
278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
279 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600,
280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
281 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL,
282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
283 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540,
284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
285 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200,
286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
287 {PCI_VENDOR_ID_NVIDIA, 0x0252,
288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
289 {PCI_VENDOR_ID_NVIDIA, 0x0313,
290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
291 {PCI_VENDOR_ID_NVIDIA, 0x0316,
292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
293 {PCI_VENDOR_ID_NVIDIA, 0x0317,
294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
295 {PCI_VENDOR_ID_NVIDIA, 0x031D,
296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
297 {PCI_VENDOR_ID_NVIDIA, 0x031E,
298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
299 {PCI_VENDOR_ID_NVIDIA, 0x031F,
300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
301 {PCI_VENDOR_ID_NVIDIA, 0x0329,
302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
303 {PCI_VENDOR_ID_NVIDIA, 0x032F,
304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
305 {PCI_VENDOR_ID_NVIDIA, 0x0345,
306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
307 {PCI_VENDOR_ID_NVIDIA, 0x0349,
308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
309 {PCI_VENDOR_ID_NVIDIA, 0x034B,
310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
311 {PCI_VENDOR_ID_NVIDIA, 0x034F,
312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
313 {PCI_VENDOR_ID_NVIDIA, 0x00c0,
314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
315 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A,
316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
317 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A_LE,
318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
319 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800,
320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
321 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA,
322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
323 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_GO1400,
324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
325 {PCI_VENDOR_ID_NVIDIA, 0x00cd,
326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
327 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_1400,
328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
329 {PCI_VENDOR_ID_NVIDIA, 0x0142,
330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
331 {PCI_VENDOR_ID_NVIDIA, 0x0143,
332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
333 {PCI_VENDOR_ID_NVIDIA, 0x0144,
334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
335 {PCI_VENDOR_ID_NVIDIA, 0x0145,
336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
337 {PCI_VENDOR_ID_NVIDIA, 0x0146,
338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
339 {PCI_VENDOR_ID_NVIDIA, 0x0147,
340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
341 {PCI_VENDOR_ID_NVIDIA, 0x0148,
342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
343 {PCI_VENDOR_ID_NVIDIA, 0x0149,
344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
345 {PCI_VENDOR_ID_NVIDIA, 0x014b,
346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
347 {PCI_VENDOR_ID_NVIDIA, 0x14c,
348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
349 {PCI_VENDOR_ID_NVIDIA, 0x014d,
350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
351 {PCI_VENDOR_ID_NVIDIA, 0x0160,
352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
353 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE,
354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
355 {PCI_VENDOR_ID_NVIDIA, 0x0162,
356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
357 {PCI_VENDOR_ID_NVIDIA, 0x0163,
358 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
359 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200,
360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
361 {PCI_VENDOR_ID_NVIDIA, 0x0165,
362 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
363 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250,
364 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
365 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1,
366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
367 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1,
368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
369 {PCI_VENDOR_ID_NVIDIA, 0x0169,
370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
371 {PCI_VENDOR_ID_NVIDIA, 0x016b,
372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
373 {PCI_VENDOR_ID_NVIDIA, 0x016c,
374 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
375 {PCI_VENDOR_ID_NVIDIA, 0x016d,
376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
377 {PCI_VENDOR_ID_NVIDIA, 0x016e,
378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
379 {PCI_VENDOR_ID_NVIDIA, 0x0210,
380 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
381 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B,
382 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
383 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE,
384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
385 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT,
386 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
387 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT,
388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
389 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX,
390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
391 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800,
392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
393 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX,
394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
395 {PCI_VENDOR_ID_NVIDIA, 0x021d,
396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
397 {PCI_VENDOR_ID_NVIDIA, 0x021e,
398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
399 {PCI_VENDOR_ID_NVIDIA, 0x0220,
400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
401 {PCI_VENDOR_ID_NVIDIA, 0x0221,
402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
403 {PCI_VENDOR_ID_NVIDIA, 0x0222,
404 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
405 {PCI_VENDOR_ID_NVIDIA, 0x0228,
406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
407 {0,} /* terminate list */
410 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
412 /* command line data, set in nvidiafb_setup() */
413 static int flatpanel __devinitdata = -1; /* Autodetect later */
414 static int fpdither __devinitdata = -1;
415 static int forceCRTC __devinitdata = -1;
416 static int hwcur __devinitdata = 0;
417 static int noaccel __devinitdata = 0;
418 static int noscale __devinitdata = 0;
419 static int paneltweak __devinitdata = 0;
420 static int vram __devinitdata = 0;
422 static int nomtrr __devinitdata = 0;
425 static char *mode_option __devinitdata = NULL;
427 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
428 .type = FB_TYPE_PACKED_PIXELS,
433 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
443 .activate = FB_ACTIVATE_NOW,
453 .vmode = FB_VMODE_NONINTERLACED
459 #ifdef CONFIG_PMAC_BACKLIGHT
461 static int nvidia_backlight_levels[] = {
480 /* ------------------------------------------------------------------------- *
482 * Backlight operations
484 * ------------------------------------------------------------------------- */
486 static int nvidia_set_backlight_enable(int on, int level, void *data)
488 struct nvidia_par *par = (struct nvidia_par *)data;
489 u32 tmp_pcrt, tmp_pmc, fpcontrol;
491 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
492 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
493 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
495 if (on && (level > BACKLIGHT_OFF)) {
497 tmp_pmc |= (1 << 31); // backlight bit
498 tmp_pmc |= nvidia_backlight_levels[level - 1] << 16;
502 fpcontrol |= par->fpSyncs;
504 fpcontrol |= 0x20000022;
506 NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
507 NV_WR32(par->PMC, 0x10F0, tmp_pmc);
508 NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
513 static int nvidia_set_backlight_level(int level, void *data)
515 return nvidia_set_backlight_enable(1, level, data);
518 static struct backlight_controller nvidia_backlight_controller = {
519 nvidia_set_backlight_enable,
520 nvidia_set_backlight_level
523 #endif /* CONFIG_PMAC_BACKLIGHT */
525 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
526 u16 bg, u16 fg, u32 w, u32 h)
528 u32 *data = (u32 *) data8;
534 for (i = 0; i < h; i++) {
538 for (j = 0; j < w / 2; j++) {
540 #if defined (__BIG_ENDIAN)
541 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
543 tmp |= (b & (1 << 31)) ? fg : bg;
546 tmp = (b & 1) ? fg : bg;
548 tmp |= (b & 1) ? fg << 16 : bg << 16;
551 NV_WR32(&par->CURSOR[k++], 0, tmp);
553 k += (MAX_CURS - w) / 2;
557 static void nvidia_write_clut(struct nvidia_par *par,
558 u8 regnum, u8 red, u8 green, u8 blue)
560 NVWriteDacMask(par, 0xff);
561 NVWriteDacWriteAddr(par, regnum);
562 NVWriteDacData(par, red);
563 NVWriteDacData(par, green);
564 NVWriteDacData(par, blue);
567 static void nvidia_read_clut(struct nvidia_par *par,
568 u8 regnum, u8 * red, u8 * green, u8 * blue)
570 NVWriteDacMask(par, 0xff);
571 NVWriteDacReadAddr(par, regnum);
572 *red = NVReadDacData(par);
573 *green = NVReadDacData(par);
574 *blue = NVReadDacData(par);
577 static int nvidia_panel_tweak(struct nvidia_par *par,
578 struct _riva_hw_state *state)
582 if (par->paneltweak) {
583 tweak = par->paneltweak;
585 /* begin flat panel hacks */
586 /* This is unfortunate, but some chips need this register
587 tweaked or else you get artifacts where adjacent pixels are
588 swapped. There are no hard rules for what to set here so all
589 we can do is experiment and apply hacks. */
591 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
592 /* At least one NV34 laptop needs this workaround. */
596 if((par->Chipset & 0xfff0) == 0x0310) {
599 /* end flat panel hacks */
605 static void nvidia_save_vga(struct nvidia_par *par,
606 struct _riva_hw_state *state)
611 NVLockUnlock(par, 0);
613 NVUnloadStateExt(par, state);
615 state->misc_output = NVReadMiscOut(par);
617 for (i = 0; i < NUM_CRT_REGS; i++)
618 state->crtc[i] = NVReadCrtc(par, i);
620 for (i = 0; i < NUM_ATC_REGS; i++)
621 state->attr[i] = NVReadAttr(par, i);
623 for (i = 0; i < NUM_GRC_REGS; i++)
624 state->gra[i] = NVReadGr(par, i);
626 for (i = 0; i < NUM_SEQ_REGS; i++)
627 state->seq[i] = NVReadSeq(par, i);
633 static void nvidia_write_regs(struct nvidia_par *par)
635 struct _riva_hw_state *state = &par->ModeReg;
640 NVLoadStateExt(par, state);
642 NVWriteMiscOut(par, state->misc_output);
644 for (i = 1; i < NUM_SEQ_REGS; i++) {
646 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
648 NVWriteSeq(par, i, state->seq[i]);
651 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
652 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
654 for (i = 0; i < NUM_CRT_REGS; i++) {
661 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
663 NVWriteCrtc(par, i, state->crtc[i]);
667 for (i = 0; i < NUM_GRC_REGS; i++) {
669 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
671 NVWriteGr(par, i, state->gra[i]);
674 for (i = 0; i < NUM_ATC_REGS; i++) {
676 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
678 NVWriteAttr(par, i, state->attr[i]);
684 static void nvidia_vga_protect(struct nvidia_par *par, int on)
690 * Turn off screen and disable sequencer.
692 tmp = NVReadSeq(par, 0x01);
694 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
695 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
698 * Reenable sequencer, then turn on screen.
701 tmp = NVReadSeq(par, 0x01);
703 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
704 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
710 static int nvidia_calc_regs(struct fb_info *info)
712 struct nvidia_par *par = info->par;
713 struct _riva_hw_state *state = &par->ModeReg;
714 int i, depth = fb_get_color_depth(&info->var, &info->fix);
715 int h_display = info->var.xres / 8 - 1;
716 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
717 int h_end = (info->var.xres + info->var.right_margin +
718 info->var.hsync_len) / 8 - 1;
719 int h_total = (info->var.xres + info->var.right_margin +
720 info->var.hsync_len + info->var.left_margin) / 8 - 5;
721 int h_blank_s = h_display;
722 int h_blank_e = h_total + 4;
723 int v_display = info->var.yres - 1;
724 int v_start = info->var.yres + info->var.lower_margin - 1;
725 int v_end = (info->var.yres + info->var.lower_margin +
726 info->var.vsync_len) - 1;
727 int v_total = (info->var.yres + info->var.lower_margin +
728 info->var.vsync_len + info->var.upper_margin) - 2;
729 int v_blank_s = v_display;
730 int v_blank_e = v_total + 1;
733 * Set all CRTC values.
736 if (info->var.vmode & FB_VMODE_INTERLACED)
739 if (par->FlatPanel == 1) {
740 v_start = v_total - 3;
743 h_start = h_total - 5;
745 h_blank_e = h_total + 4;
748 state->crtc[0x0] = Set8Bits(h_total);
749 state->crtc[0x1] = Set8Bits(h_display);
750 state->crtc[0x2] = Set8Bits(h_blank_s);
751 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
753 state->crtc[0x4] = Set8Bits(h_start);
754 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
755 | SetBitField(h_end, 4: 0, 4:0);
756 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
757 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
758 | SetBitField(v_display, 8: 8, 1:1)
759 | SetBitField(v_start, 8: 8, 2:2)
760 | SetBitField(v_blank_s, 8: 8, 3:3)
762 | SetBitField(v_total, 9: 9, 5:5)
763 | SetBitField(v_display, 9: 9, 6:6)
764 | SetBitField(v_start, 9: 9, 7:7);
765 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
767 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
768 state->crtc[0x10] = Set8Bits(v_start);
769 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
770 state->crtc[0x12] = Set8Bits(v_display);
771 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
772 (info->var.bits_per_pixel / 8));
773 state->crtc[0x15] = Set8Bits(v_blank_s);
774 state->crtc[0x16] = Set8Bits(v_blank_e);
776 state->attr[0x10] = 0x01;
779 state->attr[0x11] = 0x00;
781 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
782 | SetBitField(v_blank_s, 10: 10, 3:3)
783 | SetBitField(v_start, 10: 10, 2:2)
784 | SetBitField(v_display, 10: 10, 1:1)
785 | SetBitField(v_total, 10: 10, 0:0);
787 state->horiz = SetBitField(h_total, 8: 8, 0:0)
788 | SetBitField(h_display, 8: 8, 1:1)
789 | SetBitField(h_blank_s, 8: 8, 2:2)
790 | SetBitField(h_start, 8: 8, 3:3);
792 state->extra = SetBitField(v_total, 11: 11, 0:0)
793 | SetBitField(v_display, 11: 11, 2:2)
794 | SetBitField(v_start, 11: 11, 4:4)
795 | SetBitField(v_blank_s, 11: 11, 6:6);
797 if (info->var.vmode & FB_VMODE_INTERLACED) {
798 h_total = (h_total >> 1) & ~1;
799 state->interlace = Set8Bits(h_total);
800 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
802 state->interlace = 0xff; /* interlace off */
806 * Calculate the extended registers.
814 if (par->Architecture >= NV_ARCH_10)
815 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
818 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
819 state->misc_output &= ~0x40;
821 state->misc_output |= 0x40;
822 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
823 state->misc_output &= ~0x80;
825 state->misc_output |= 0x80;
827 NVCalcStateExt(par, state, i, info->var.xres_virtual,
828 info->var.xres, info->var.yres_virtual,
829 1000000000 / info->var.pixclock, info->var.vmode);
831 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
832 if (par->FlatPanel == 1) {
833 state->pixel |= (1 << 7);
835 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
836 || (par->fpHeight <= info->var.yres)) {
837 state->scale |= (1 << 8);
840 if (!par->crtcSync_read) {
841 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
842 par->crtcSync_read = 1;
845 par->PanelTweak = nvidia_panel_tweak(par, state);
848 state->vpll = state->pll;
849 state->vpll2 = state->pll;
850 state->vpllB = state->pllB;
851 state->vpll2B = state->pllB;
853 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
854 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
856 if (par->CRTCnumber) {
857 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
858 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
859 state->crtcOwner = 3;
860 state->pllsel |= 0x20000800;
861 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
862 if (par->twoStagePLL)
863 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
864 } else if (par->twoHeads) {
865 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
866 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
867 state->crtcOwner = 0;
868 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
869 if (par->twoStagePLL)
870 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
873 state->cursorConfig = 0x00000100;
875 if (info->var.vmode & FB_VMODE_DOUBLE)
876 state->cursorConfig |= (1 << 4);
878 if (par->alphaCursor) {
879 if ((par->Chipset & 0x0ff0) != 0x0110)
880 state->cursorConfig |= 0x04011000;
882 state->cursorConfig |= 0x14011000;
883 state->general |= (1 << 29);
885 state->cursorConfig |= 0x02000000;
888 if ((par->Chipset & 0x0ff0) == 0x0110) {
889 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
892 state->dither |= 0x00010000;
894 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
902 state->displayV = info->var.xres;
907 static void nvidia_init_vga(struct fb_info *info)
909 struct nvidia_par *par = info->par;
910 struct _riva_hw_state *state = &par->ModeReg;
913 for (i = 0; i < 0x10; i++)
915 state->attr[0x10] = 0x41;
916 state->attr[0x11] = 0xff;
917 state->attr[0x12] = 0x0f;
918 state->attr[0x13] = 0x00;
919 state->attr[0x14] = 0x00;
921 memset(state->crtc, 0x00, NUM_CRT_REGS);
922 state->crtc[0x0a] = 0x20;
923 state->crtc[0x17] = 0xe3;
924 state->crtc[0x18] = 0xff;
925 state->crtc[0x28] = 0x40;
927 memset(state->gra, 0x00, NUM_GRC_REGS);
928 state->gra[0x05] = 0x40;
929 state->gra[0x06] = 0x05;
930 state->gra[0x07] = 0x0f;
931 state->gra[0x08] = 0xff;
933 state->seq[0x00] = 0x03;
934 state->seq[0x01] = 0x01;
935 state->seq[0x02] = 0x0f;
936 state->seq[0x03] = 0x00;
937 state->seq[0x04] = 0x0e;
939 state->misc_output = 0xeb;
942 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
944 struct nvidia_par *par = info->par;
945 u8 data[MAX_CURS * MAX_CURS / 8];
946 int i, set = cursor->set;
949 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
952 NVShowHideCursor(par, 0);
954 if (par->cursor_reset) {
956 par->cursor_reset = 0;
959 if (set & FB_CUR_SETSIZE)
960 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
962 if (set & FB_CUR_SETPOS) {
965 yy = cursor->image.dy - info->var.yoffset;
966 xx = cursor->image.dx - info->var.xoffset;
970 NV_WR32(par->PRAMDAC, 0x0000300, temp);
973 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
974 u32 bg_idx = cursor->image.bg_color;
975 u32 fg_idx = cursor->image.fg_color;
976 u32 s_pitch = (cursor->image.width + 7) >> 3;
977 u32 d_pitch = MAX_CURS / 8;
978 u8 *dat = (u8 *) cursor->image.data;
979 u8 *msk = (u8 *) cursor->mask;
982 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
985 switch (cursor->rop) {
987 for (i = 0; i < s_pitch * cursor->image.height; i++)
988 src[i] = dat[i] ^ msk[i];
992 for (i = 0; i < s_pitch * cursor->image.height; i++)
993 src[i] = dat[i] & msk[i];
997 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
998 cursor->image.height);
1000 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1001 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1002 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
1004 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1005 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1006 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
1008 NVLockUnlock(par, 0);
1010 nvidiafb_load_cursor_image(par, data, bg, fg,
1011 cursor->image.width,
1012 cursor->image.height);
1018 NVShowHideCursor(par, 1);
1023 static int nvidiafb_set_par(struct fb_info *info)
1025 struct nvidia_par *par = info->par;
1029 NVLockUnlock(par, 1);
1030 if (!par->FlatPanel || !par->twoHeads)
1033 if (par->FPDither < 0) {
1034 if ((par->Chipset & 0x0ff0) == 0x0110)
1035 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
1038 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
1039 printk(KERN_INFO PFX "Flat panel dithering %s\n",
1040 par->FPDither ? "enabled" : "disabled");
1043 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1044 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1046 nvidia_init_vga(info);
1047 nvidia_calc_regs(info);
1049 NVLockUnlock(par, 0);
1050 if (par->twoHeads) {
1051 VGA_WR08(par->PCIO, 0x03D4, 0x44);
1052 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
1053 NVLockUnlock(par, 0);
1056 nvidia_vga_protect(par, 1);
1058 nvidia_write_regs(par);
1060 #if defined (__BIG_ENDIAN)
1061 /* turn on LFB swapping */
1065 VGA_WR08(par->PCIO, 0x3d4, 0x46);
1066 tmp = VGA_RD08(par->PCIO, 0x3d5);
1068 VGA_WR08(par->PCIO, 0x3d5, tmp);
1072 info->fix.line_length = (info->var.xres_virtual *
1073 info->var.bits_per_pixel) >> 3;
1074 if (info->var.accel_flags) {
1075 info->fbops->fb_imageblit = nvidiafb_imageblit;
1076 info->fbops->fb_fillrect = nvidiafb_fillrect;
1077 info->fbops->fb_copyarea = nvidiafb_copyarea;
1078 info->fbops->fb_sync = nvidiafb_sync;
1079 info->pixmap.scan_align = 4;
1080 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1081 NVResetGraphics(info);
1083 info->fbops->fb_imageblit = cfb_imageblit;
1084 info->fbops->fb_fillrect = cfb_fillrect;
1085 info->fbops->fb_copyarea = cfb_copyarea;
1086 info->fbops->fb_sync = NULL;
1087 info->pixmap.scan_align = 1;
1088 info->flags |= FBINFO_HWACCEL_DISABLED;
1091 par->cursor_reset = 1;
1093 nvidia_vga_protect(par, 0);
1099 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1100 unsigned blue, unsigned transp,
1101 struct fb_info *info)
1103 struct nvidia_par *par = info->par;
1107 if (regno >= (1 << info->var.green.length))
1110 if (info->var.grayscale) {
1111 /* gray = 0.30*R + 0.59*G + 0.11*B */
1112 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1115 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1116 ((u32 *) info->pseudo_palette)[regno] =
1117 (regno << info->var.red.offset) |
1118 (regno << info->var.green.offset) |
1119 (regno << info->var.blue.offset);
1122 switch (info->var.bits_per_pixel) {
1124 /* "transparent" stuff is completely ignored. */
1125 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1128 if (info->var.green.length == 5) {
1129 for (i = 0; i < 8; i++) {
1130 nvidia_write_clut(par, regno * 8 + i, red >> 8,
1131 green >> 8, blue >> 8);
1137 for (i = 0; i < 8; i++) {
1138 nvidia_write_clut(par, regno * 8 + i,
1139 red >> 8, green >> 8,
1144 nvidia_read_clut(par, regno * 4, &r, &g, &b);
1146 for (i = 0; i < 4; i++)
1147 nvidia_write_clut(par, regno * 4 + i, r,
1152 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1163 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
1164 struct fb_info *info)
1166 struct nvidia_par *par = info->par;
1167 int memlen, vramlen, mode_valid = 0;
1172 var->transp.offset = 0;
1173 var->transp.length = 0;
1177 if (var->bits_per_pixel <= 8)
1178 var->bits_per_pixel = 8;
1179 else if (var->bits_per_pixel <= 16)
1180 var->bits_per_pixel = 16;
1182 var->bits_per_pixel = 32;
1184 switch (var->bits_per_pixel) {
1186 var->red.offset = 0;
1187 var->red.length = 8;
1188 var->green.offset = 0;
1189 var->green.length = 8;
1190 var->blue.offset = 0;
1191 var->blue.length = 8;
1192 var->transp.offset = 0;
1193 var->transp.length = 0;
1196 var->green.length = (var->green.length < 6) ? 5 : 6;
1197 var->red.length = 5;
1198 var->blue.length = 5;
1199 var->transp.length = 6 - var->green.length;
1200 var->blue.offset = 0;
1201 var->green.offset = 5;
1202 var->red.offset = 5 + var->green.length;
1203 var->transp.offset = (5 + var->red.offset) & 15;
1205 case 32: /* RGBA 8888 */
1206 var->red.offset = 16;
1207 var->red.length = 8;
1208 var->green.offset = 8;
1209 var->green.length = 8;
1210 var->blue.offset = 0;
1211 var->blue.length = 8;
1212 var->transp.length = 8;
1213 var->transp.offset = 24;
1217 var->red.msb_right = 0;
1218 var->green.msb_right = 0;
1219 var->blue.msb_right = 0;
1220 var->transp.msb_right = 0;
1222 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
1223 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1226 /* calculate modeline if supported by monitor */
1227 if (!mode_valid && info->monspecs.gtf) {
1228 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1233 struct fb_videomode *mode;
1235 mode = fb_find_best_mode(var, &info->modelist);
1237 fb_videomode_to_var(var, mode);
1242 if (!mode_valid && info->monspecs.modedb_len)
1245 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
1246 par->fpHeight < var->yres))
1249 if (var->yres_virtual < var->yres)
1250 var->yres_virtual = var->yres;
1252 if (var->xres_virtual < var->xres)
1253 var->xres_virtual = var->xres;
1255 var->xres_virtual = (var->xres_virtual + 63) & ~63;
1257 vramlen = info->screen_size;
1258 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
1259 memlen = pitch * var->yres_virtual;
1261 if (memlen > vramlen) {
1262 var->yres_virtual = vramlen / pitch;
1264 if (var->yres_virtual < var->yres) {
1265 var->yres_virtual = var->yres;
1266 var->xres_virtual = vramlen / var->yres_virtual;
1267 var->xres_virtual /= var->bits_per_pixel / 8;
1268 var->xres_virtual &= ~63;
1269 pitch = (var->xres_virtual *
1270 var->bits_per_pixel + 7) / 8;
1271 memlen = pitch * var->yres;
1273 if (var->xres_virtual < var->xres) {
1274 printk("nvidiafb: required video memory, "
1275 "%d bytes, for %dx%d-%d (virtual) "
1276 "is out of range\n",
1277 memlen, var->xres_virtual,
1278 var->yres_virtual, var->bits_per_pixel);
1284 if (var->accel_flags) {
1285 if (var->yres_virtual > 0x7fff)
1286 var->yres_virtual = 0x7fff;
1287 if (var->xres_virtual > 0x7fff)
1288 var->xres_virtual = 0x7fff;
1291 var->xres_virtual &= ~63;
1298 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
1299 struct fb_info *info)
1301 struct nvidia_par *par = info->par;
1304 total = var->yoffset * info->fix.line_length + var->xoffset;
1306 NVSetStartAddress(par, total);
1311 static int nvidiafb_blank(int blank, struct fb_info *info)
1313 struct nvidia_par *par = info->par;
1314 unsigned char tmp, vesa;
1316 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
1317 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
1325 case FB_BLANK_UNBLANK:
1326 case FB_BLANK_NORMAL:
1328 case FB_BLANK_VSYNC_SUSPEND:
1331 case FB_BLANK_HSYNC_SUSPEND:
1334 case FB_BLANK_POWERDOWN:
1339 NVWriteSeq(par, 0x01, tmp);
1340 NVWriteCrtc(par, 0x1a, vesa);
1342 #ifdef CONFIG_PMAC_BACKLIGHT
1343 if (par->FlatPanel && _machine == _MACH_Pmac) {
1344 set_backlight_enable(!blank);
1353 static struct fb_ops nvidia_fb_ops = {
1354 .owner = THIS_MODULE,
1355 .fb_check_var = nvidiafb_check_var,
1356 .fb_set_par = nvidiafb_set_par,
1357 .fb_setcolreg = nvidiafb_setcolreg,
1358 .fb_pan_display = nvidiafb_pan_display,
1359 .fb_blank = nvidiafb_blank,
1360 .fb_fillrect = nvidiafb_fillrect,
1361 .fb_copyarea = nvidiafb_copyarea,
1362 .fb_imageblit = nvidiafb_imageblit,
1363 .fb_cursor = nvidiafb_cursor,
1364 .fb_sync = nvidiafb_sync,
1367 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1369 struct fb_monspecs *specs = &info->monspecs;
1370 struct fb_videomode modedb;
1371 struct nvidia_par *par = info->par;
1375 info->flags = FBINFO_DEFAULT
1376 | FBINFO_HWACCEL_IMAGEBLIT
1377 | FBINFO_HWACCEL_FILLRECT
1378 | FBINFO_HWACCEL_COPYAREA
1379 | FBINFO_HWACCEL_YPAN;
1381 fb_videomode_to_modelist(info->monspecs.modedb,
1382 info->monspecs.modedb_len, &info->modelist);
1383 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1385 if (specs->modedb != NULL) {
1386 struct fb_videomode *modedb;
1388 modedb = fb_find_best_display(specs, &info->modelist);
1389 fb_videomode_to_var(&nvidiafb_default_var, modedb);
1390 nvidiafb_default_var.bits_per_pixel = 8;
1391 } else if (par->fpWidth && par->fpHeight) {
1395 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1396 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1397 specs->modedb_len, &modedb, 8);
1401 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1402 specs->modedb, specs->modedb_len, &modedb, 8);
1404 info->var = nvidiafb_default_var;
1405 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1406 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1407 info->pseudo_palette = par->pseudo_palette;
1408 fb_alloc_cmap(&info->cmap, 256, 0);
1409 fb_destroy_modedb(info->monspecs.modedb);
1410 info->monspecs.modedb = NULL;
1412 /* maximize virtual vertical length */
1413 lpitch = info->var.xres_virtual *
1414 ((info->var.bits_per_pixel + 7) >> 3);
1415 info->var.yres_virtual = info->screen_size / lpitch;
1417 info->pixmap.scan_align = 4;
1418 info->pixmap.buf_align = 4;
1419 info->pixmap.access_align = 32;
1420 info->pixmap.size = 8 * 1024;
1421 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1424 info->fbops->fb_cursor = NULL;
1426 info->var.accel_flags = (!noaccel);
1428 switch (par->Architecture) {
1430 info->fix.accel = FB_ACCEL_NV4;
1433 info->fix.accel = FB_ACCEL_NV_10;
1436 info->fix.accel = FB_ACCEL_NV_20;
1439 info->fix.accel = FB_ACCEL_NV_30;
1442 info->fix.accel = FB_ACCEL_NV_40;
1448 return nvidiafb_check_var(&info->var, info);
1451 static u32 __devinit nvidia_get_arch(struct pci_dev *pd)
1455 switch (pd->device & 0x0ff0) {
1456 case 0x0100: /* GeForce 256 */
1457 case 0x0110: /* GeForce2 MX */
1458 case 0x0150: /* GeForce2 */
1459 case 0x0170: /* GeForce4 MX */
1460 case 0x0180: /* GeForce4 MX (8x AGP) */
1461 case 0x01A0: /* nForce */
1462 case 0x01F0: /* nForce2 */
1465 case 0x0200: /* GeForce3 */
1466 case 0x0250: /* GeForce4 Ti */
1467 case 0x0280: /* GeForce4 Ti (8x AGP) */
1470 case 0x0300: /* GeForceFX 5800 */
1471 case 0x0310: /* GeForceFX 5600 */
1472 case 0x0320: /* GeForceFX 5200 */
1473 case 0x0330: /* GeForceFX 5900 */
1474 case 0x0340: /* GeForceFX 5700 */
1490 case 0x0020: /* TNT, TNT2 */
1493 default: /* unknown architecture */
1500 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1501 const struct pci_device_id *ent)
1503 struct nvidia_par *par;
1504 struct fb_info *info;
1511 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1516 par = (struct nvidia_par *)info->par;
1519 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1521 if (info->pixmap.addr == NULL)
1524 memset(info->pixmap.addr, 0, 8 * 1024);
1526 if (pci_enable_device(pd)) {
1527 printk(KERN_ERR PFX "cannot enable PCI device\n");
1528 goto err_out_enable;
1531 if (pci_request_regions(pd, "nvidiafb")) {
1532 printk(KERN_ERR PFX "cannot request PCI regions\n");
1533 goto err_out_request;
1536 par->Architecture = nvidia_get_arch(pd);
1538 par->Chipset = (pd->vendor << 16) | pd->device;
1539 printk(KERN_INFO PFX "nVidia device/chipset %X\n", par->Chipset);
1541 if (par->Architecture == 0) {
1542 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1543 goto err_out_free_base0;
1546 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1548 par->FlatPanel = flatpanel;
1550 printk(KERN_INFO PFX "flatpanel support enabled\n");
1551 par->FPDither = fpdither;
1553 par->CRTCnumber = forceCRTC;
1554 par->FpScale = (!noscale);
1555 par->paneltweak = paneltweak;
1557 /* enable IO and mem if not already done */
1558 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1559 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1560 pci_write_config_word(pd, PCI_COMMAND, cmd);
1562 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1563 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1564 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1566 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1569 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1570 goto err_out_free_base0;
1573 NVCommonSetup(info);
1575 par->FbAddress = nvidiafb_fix.smem_start;
1576 par->FbMapSize = par->RamAmountKBytes * 1024;
1577 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1578 par->FbMapSize = vram * 1024 * 1024;
1580 /* Limit amount of vram to 64 MB */
1581 if (par->FbMapSize > 64 * 1024 * 1024)
1582 par->FbMapSize = 64 * 1024 * 1024;
1584 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1585 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1587 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1588 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1589 info->screen_size = par->FbUsableSize;
1590 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1592 if (!info->screen_base) {
1593 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1594 goto err_out_free_base1;
1597 par->FbStart = info->screen_base;
1601 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1602 par->RamAmountKBytes * 1024,
1603 MTRR_TYPE_WRCOMB, 1);
1604 if (par->mtrr.vram < 0) {
1605 printk(KERN_ERR PFX "unable to setup MTRR\n");
1607 par->mtrr.vram_valid = 1;
1608 /* let there be speed */
1609 printk(KERN_INFO PFX "MTRR set to ON\n");
1612 #endif /* CONFIG_MTRR */
1614 info->fbops = &nvidia_fb_ops;
1615 info->fix = nvidiafb_fix;
1617 if (nvidia_set_fbinfo(info) < 0) {
1618 printk(KERN_ERR PFX "error setting initial video mode\n");
1619 goto err_out_iounmap_fb;
1622 nvidia_save_vga(par, &par->SavedReg);
1624 if (register_framebuffer(info) < 0) {
1625 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1626 goto err_out_iounmap_fb;
1629 pci_set_drvdata(pd, info);
1631 printk(KERN_INFO PFX
1632 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1634 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1635 #ifdef CONFIG_PMAC_BACKLIGHT
1636 if (par->FlatPanel && _machine == _MACH_Pmac)
1637 register_backlight_controller(&nvidia_backlight_controller,
1644 iounmap(info->screen_base);
1646 fb_destroy_modedb(info->monspecs.modedb);
1647 nvidia_delete_i2c_busses(par);
1650 pci_release_regions(pd);
1652 pci_disable_device(pd);
1654 kfree(info->pixmap.addr);
1656 framebuffer_release(info);
1661 static void __exit nvidiafb_remove(struct pci_dev *pd)
1663 struct fb_info *info = pci_get_drvdata(pd);
1664 struct nvidia_par *par = info->par;
1670 unregister_framebuffer(info);
1672 if (par->mtrr.vram_valid)
1673 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1674 info->fix.smem_len);
1675 #endif /* CONFIG_MTRR */
1677 iounmap(info->screen_base);
1678 fb_destroy_modedb(info->monspecs.modedb);
1679 nvidia_delete_i2c_busses(par);
1681 pci_release_regions(pd);
1682 pci_disable_device(pd);
1683 kfree(info->pixmap.addr);
1684 framebuffer_release(info);
1685 pci_set_drvdata(pd, NULL);
1689 /* ------------------------------------------------------------------------- *
1693 * ------------------------------------------------------------------------- */
1696 static int __devinit nvidiafb_setup(char *options)
1701 if (!options || !*options)
1704 while ((this_opt = strsep(&options, ",")) != NULL) {
1705 if (!strncmp(this_opt, "forceCRTC", 9)) {
1711 forceCRTC = *p - '0';
1712 if (forceCRTC < 0 || forceCRTC > 1)
1714 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1716 } else if (!strncmp(this_opt, "hwcur", 5)) {
1718 } else if (!strncmp(this_opt, "noaccel", 6)) {
1720 } else if (!strncmp(this_opt, "noscale", 7)) {
1722 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1723 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1724 } else if (!strncmp(this_opt, "vram:", 5)) {
1725 vram = simple_strtoul(this_opt+5, NULL, 0);
1727 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1730 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1731 fpdither = simple_strtol(this_opt+9, NULL, 0);
1733 mode_option = this_opt;
1738 #endif /* !MODULE */
1740 static struct pci_driver nvidiafb_driver = {
1742 .id_table = nvidiafb_pci_tbl,
1743 .probe = nvidiafb_probe,
1744 .remove = __exit_p(nvidiafb_remove),
1747 /* ------------------------------------------------------------------------- *
1751 * ------------------------------------------------------------------------- */
1753 static int __devinit nvidiafb_init(void)
1756 char *option = NULL;
1758 if (fb_get_options("nvidiafb", &option))
1760 nvidiafb_setup(option);
1762 return pci_register_driver(&nvidiafb_driver);
1765 module_init(nvidiafb_init);
1768 static void __exit nvidiafb_exit(void)
1770 pci_unregister_driver(&nvidiafb_driver);
1773 module_exit(nvidiafb_exit);
1775 module_param(flatpanel, int, 0);
1776 MODULE_PARM_DESC(flatpanel,
1777 "Enables experimental flat panel support for some chipsets. "
1778 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1779 module_param(fpdither, int, 0);
1780 MODULE_PARM_DESC(fpdither,
1781 "Enables dithering of flat panel for 6 bits panels. "
1782 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1783 module_param(hwcur, int, 0);
1784 MODULE_PARM_DESC(hwcur,
1785 "Enables hardware cursor implementation. (0 or 1=enabled) "
1787 module_param(noaccel, int, 0);
1788 MODULE_PARM_DESC(noaccel,
1789 "Disables hardware acceleration. (0 or 1=disable) "
1791 module_param(noscale, int, 0);
1792 MODULE_PARM_DESC(noscale,
1793 "Disables screen scaleing. (0 or 1=disable) "
1794 "(default=0, do scaling)");
1795 module_param(paneltweak, int, 0);
1796 MODULE_PARM_DESC(paneltweak,
1797 "Tweak display settings for flatpanels. "
1798 "(default=0, no tweaks)");
1799 module_param(forceCRTC, int, 0);
1800 MODULE_PARM_DESC(forceCRTC,
1801 "Forces usage of a particular CRTC in case autodetection "
1802 "fails. (0 or 1) (default=autodetect)");
1803 module_param(vram, int, 0);
1804 MODULE_PARM_DESC(vram,
1805 "amount of framebuffer memory to remap in MiB"
1806 "(default=0 - remap entire memory)");
1808 module_param(nomtrr, bool, 0);
1809 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1813 MODULE_AUTHOR("Antonino Daplas");
1814 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1815 MODULE_LICENSE("GPL");