Merge branch 'for_linus' of git://git.infradead.org/~dedekind/ubifs-2.6
[linux-2.6] / drivers / video / aty / radeonfb.h
1 #ifndef __RADEONFB_H__
2 #define __RADEONFB_H__
3
4 #ifdef CONFIG_FB_RADEON_DEBUG
5 #define DEBUG           1
6 #endif
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/delay.h>
12 #include <linux/pci.h>
13 #include <linux/fb.h>
14
15
16 #ifdef CONFIG_FB_RADEON_I2C
17 #include <linux/i2c.h>
18 #include <linux/i2c-algo-bit.h>
19 #endif
20
21 #include <asm/io.h>
22
23 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
24 #include <asm/prom.h>
25 #endif
26
27 #include <video/radeon.h>
28
29 /***************************************************************
30  * Most of the definitions here are adapted right from XFree86 *
31  ***************************************************************/
32
33
34 /*
35  * Chip families. Must fit in the low 16 bits of a long word
36  */
37 enum radeon_family {
38         CHIP_FAMILY_UNKNOW,
39         CHIP_FAMILY_LEGACY,
40         CHIP_FAMILY_RADEON,
41         CHIP_FAMILY_RV100,
42         CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
43         CHIP_FAMILY_RV200,
44         CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
45                                  RS250 (IGP 7000) */
46         CHIP_FAMILY_R200,
47         CHIP_FAMILY_RV250,
48         CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
49         CHIP_FAMILY_RV280,
50         CHIP_FAMILY_R300,
51         CHIP_FAMILY_R350,
52         CHIP_FAMILY_RV350,
53         CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
54         CHIP_FAMILY_R420,     /* R420/R423/M18 */
55         CHIP_FAMILY_RC410,
56         CHIP_FAMILY_RS480,
57         CHIP_FAMILY_LAST,
58 };
59
60 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
61                                  ((rinfo)->family == CHIP_FAMILY_RV200)  || \
62                                  ((rinfo)->family == CHIP_FAMILY_RS100)  || \
63                                  ((rinfo)->family == CHIP_FAMILY_RS200)  || \
64                                  ((rinfo)->family == CHIP_FAMILY_RV250)  || \
65                                  ((rinfo)->family == CHIP_FAMILY_RV280)  || \
66                                  ((rinfo)->family == CHIP_FAMILY_RS300))
67
68
69 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
70                                 ((rinfo)->family == CHIP_FAMILY_RV350) || \
71                                 ((rinfo)->family == CHIP_FAMILY_R350)  || \
72                                 ((rinfo)->family == CHIP_FAMILY_RV380) || \
73                                 ((rinfo)->family == CHIP_FAMILY_R420)  || \
74                                ((rinfo)->family == CHIP_FAMILY_RC410) || \
75                                ((rinfo)->family == CHIP_FAMILY_RS480))
76
77 /*
78  * Chip flags
79  */
80 enum radeon_chip_flags {
81         CHIP_FAMILY_MASK        = 0x0000ffffUL,
82         CHIP_FLAGS_MASK         = 0xffff0000UL,
83         CHIP_IS_MOBILITY        = 0x00010000UL,
84         CHIP_IS_IGP             = 0x00020000UL,
85         CHIP_HAS_CRTC2          = 0x00040000UL, 
86 };
87
88 /*
89  * Errata workarounds
90  */
91 enum radeon_errata {
92         CHIP_ERRATA_R300_CG             = 0x00000001,
93         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
94         CHIP_ERRATA_PLL_DELAY           = 0x00000004,
95 };
96
97
98 /*
99  * Monitor types
100  */
101 enum radeon_montype {
102         MT_NONE = 0,
103         MT_CRT,         /* CRT */
104         MT_LCD,         /* LCD */
105         MT_DFP,         /* DVI */
106         MT_CTV,         /* composite TV */
107         MT_STV          /* S-Video out */
108 };
109
110 /*
111  * DDC i2c ports
112  */
113 enum ddc_type {
114         ddc_none,
115         ddc_monid,
116         ddc_dvi,
117         ddc_vga,
118         ddc_crt2,
119 };
120
121 /*
122  * Connector types
123  */
124 enum conn_type {
125         conn_none,
126         conn_proprietary,
127         conn_crt,
128         conn_DVI_I,
129         conn_DVI_D,
130 };
131
132
133 /*
134  * PLL infos
135  */
136 struct pll_info {
137         int ppll_max;
138         int ppll_min;
139         int sclk, mclk;
140         int ref_div;
141         int ref_clk;
142 };
143
144
145 /*
146  * This structure contains the various registers manipulated by this
147  * driver for setting or restoring a mode. It's mostly copied from
148  * XFree's RADEONSaveRec structure. A few chip settings might still be
149  * tweaked without beeing reflected or saved in these registers though
150  */
151 struct radeon_regs {
152         /* Common registers */
153         u32             ovr_clr;
154         u32             ovr_wid_left_right;
155         u32             ovr_wid_top_bottom;
156         u32             ov0_scale_cntl;
157         u32             mpp_tb_config;
158         u32             mpp_gp_config;
159         u32             subpic_cntl;
160         u32             viph_control;
161         u32             i2c_cntl_1;
162         u32             gen_int_cntl;
163         u32             cap0_trig_cntl;
164         u32             cap1_trig_cntl;
165         u32             bus_cntl;
166         u32             surface_cntl;
167         u32             bios_5_scratch;
168
169         /* Other registers to save for VT switches or driver load/unload */
170         u32             dp_datatype;
171         u32             rbbm_soft_reset;
172         u32             clock_cntl_index;
173         u32             amcgpio_en_reg;
174         u32             amcgpio_mask;
175
176         /* Surface/tiling registers */
177         u32             surf_lower_bound[8];
178         u32             surf_upper_bound[8];
179         u32             surf_info[8];
180
181         /* CRTC registers */
182         u32             crtc_gen_cntl;
183         u32             crtc_ext_cntl;
184         u32             dac_cntl;
185         u32             crtc_h_total_disp;
186         u32             crtc_h_sync_strt_wid;
187         u32             crtc_v_total_disp;
188         u32             crtc_v_sync_strt_wid;
189         u32             crtc_offset;
190         u32             crtc_offset_cntl;
191         u32             crtc_pitch;
192         u32             disp_merge_cntl;
193         u32             grph_buffer_cntl;
194         u32             crtc_more_cntl;
195
196         /* CRTC2 registers */
197         u32             crtc2_gen_cntl;
198         u32             dac2_cntl;
199         u32             disp_output_cntl;
200         u32             disp_hw_debug;
201         u32             disp2_merge_cntl;
202         u32             grph2_buffer_cntl;
203         u32             crtc2_h_total_disp;
204         u32             crtc2_h_sync_strt_wid;
205         u32             crtc2_v_total_disp;
206         u32             crtc2_v_sync_strt_wid;
207         u32             crtc2_offset;
208         u32             crtc2_offset_cntl;
209         u32             crtc2_pitch;
210
211         /* Flat panel regs */
212         u32             fp_crtc_h_total_disp;
213         u32             fp_crtc_v_total_disp;
214         u32             fp_gen_cntl;
215         u32             fp2_gen_cntl;
216         u32             fp_h_sync_strt_wid;
217         u32             fp2_h_sync_strt_wid;
218         u32             fp_horz_stretch;
219         u32             fp_panel_cntl;
220         u32             fp_v_sync_strt_wid;
221         u32             fp2_v_sync_strt_wid;
222         u32             fp_vert_stretch;
223         u32             lvds_gen_cntl;
224         u32             lvds_pll_cntl;
225         u32             tmds_crc;
226         u32             tmds_transmitter_cntl;
227
228         /* Computed values for PLL */
229         u32             dot_clock_freq;
230         int             feedback_div;
231         int             post_div;       
232
233         /* PLL registers */
234         u32             ppll_div_3;
235         u32             ppll_ref_div;
236         u32             vclk_ecp_cntl;
237         u32             clk_cntl_index;
238
239         /* Computed values for PLL2 */
240         u32             dot_clock_freq_2;
241         int             feedback_div_2;
242         int             post_div_2;
243
244         /* PLL2 registers */
245         u32             p2pll_ref_div;
246         u32             p2pll_div_0;
247         u32             htotal_cntl2;
248
249         /* Palette */
250         int             palette_valid;
251 };
252
253 struct panel_info {
254         int xres, yres;
255         int valid;
256         int clock;
257         int hOver_plus, hSync_width, hblank;
258         int vOver_plus, vSync_width, vblank;
259         int hAct_high, vAct_high, interlaced;
260         int pwr_delay;
261         int use_bios_dividers;
262         int ref_divider;
263         int post_divider;
264         int fbk_divider;
265 };
266
267 struct radeonfb_info;
268
269 #ifdef CONFIG_FB_RADEON_I2C
270 struct radeon_i2c_chan {
271         struct radeonfb_info            *rinfo;
272         u32                             ddc_reg;
273         struct i2c_adapter              adapter;
274         struct i2c_algo_bit_data        algo;
275 };
276 #endif
277
278 enum radeon_pm_mode {
279         radeon_pm_none  = 0,            /* Nothing supported */
280         radeon_pm_d2    = 0x00000001,   /* Can do D2 state */
281         radeon_pm_off   = 0x00000002,   /* Can resume from D3 cold */
282 };
283
284 typedef void (*reinit_function_ptr)(struct radeonfb_info *rinfo);
285
286 struct radeonfb_info {
287         struct fb_info          *info;
288
289         struct radeon_regs      state;
290         struct radeon_regs      init_state;
291
292         char                    name[DEVICE_NAME_SIZE];
293
294         unsigned long           mmio_base_phys;
295         unsigned long           fb_base_phys;
296
297         void __iomem            *mmio_base;
298         void __iomem            *fb_base;
299
300         unsigned long           fb_local_base;
301
302         struct pci_dev          *pdev;
303 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
304         struct device_node      *of_node;
305 #endif
306
307         void __iomem            *bios_seg;
308         int                     fp_bios_start;
309
310         u32                     pseudo_palette[16];
311         struct { u8 red, green, blue, pad; }
312                                 palette[256];
313
314         int                     chipset;
315         u8                      family;
316         u8                      rev;
317         unsigned int            errata;
318         unsigned long           video_ram;
319         unsigned long           mapped_vram;
320         int                     vram_width;
321         int                     vram_ddr;
322
323         int                     pitch, bpp, depth;
324
325         int                     has_CRTC2;
326         int                     is_mobility;
327         int                     is_IGP;
328         int                     reversed_DAC;
329         int                     reversed_TMDS;
330         struct panel_info       panel_info;
331         int                     mon1_type;
332         u8                      *mon1_EDID;
333         struct fb_videomode     *mon1_modedb;
334         int                     mon1_dbsize;
335         int                     mon2_type;
336         u8                      *mon2_EDID;
337
338         u32                     dp_gui_master_cntl;
339
340         struct pll_info         pll;
341
342         int                     mtrr_hdl;
343
344         int                     pm_reg;
345         u32                     save_regs[100];
346         int                     asleep;
347         int                     lock_blank;
348         int                     dynclk;
349         int                     no_schedule;
350         enum radeon_pm_mode     pm_mode;
351         reinit_function_ptr     reinit_func;
352
353         /* Lock on register access */
354         spinlock_t              reg_lock;
355
356         /* Timer used for delayed LVDS operations */
357         struct timer_list       lvds_timer;
358         u32                     pending_lvds_gen_cntl;
359
360 #ifdef CONFIG_FB_RADEON_I2C
361         struct radeon_i2c_chan  i2c[4];
362 #endif
363
364         u32                     cfg_save[64];
365 };
366
367
368 #define PRIMARY_MONITOR(rinfo)  (rinfo->mon1_type)
369
370
371 /*
372  * IO macros
373  */
374
375 /* Note about this function: we have some rare cases where we must not schedule,
376  * this typically happen with our special "wake up early" hook which allows us to
377  * wake up the graphic chip (and thus get the console back) before everything else
378  * on some machines that support that mechanism. At this point, interrupts are off
379  * and scheduling is not permitted
380  */
381 static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
382 {
383         if (rinfo->no_schedule || oops_in_progress)
384                 mdelay(ms);
385         else
386                 msleep(ms);
387 }
388
389
390 #define INREG8(addr)            readb((rinfo->mmio_base)+addr)
391 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
392 #define INREG16(addr)           readw((rinfo->mmio_base)+addr)
393 #define OUTREG16(addr,val)      writew(val, (rinfo->mmio_base)+addr)
394 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
395 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
396
397 static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
398                        u32 val, u32 mask)
399 {
400         unsigned long flags;
401         unsigned int tmp;
402
403         spin_lock_irqsave(&rinfo->reg_lock, flags);
404         tmp = INREG(addr);
405         tmp &= (mask);
406         tmp |= (val);
407         OUTREG(addr, tmp);
408         spin_unlock_irqrestore(&rinfo->reg_lock, flags);
409 }
410
411 #define OUTREGP(addr,val,mask)  _OUTREGP(rinfo, addr, val,mask)
412
413 /*
414  * Note about PLL register accesses:
415  *
416  * I have removed the spinlock on them on purpose. The driver now
417  * expects that it will only manipulate the PLL registers in normal
418  * task environment, where radeon_msleep() will be called, protected
419  * by a semaphore (currently the console semaphore) so that no conflict
420  * will happen on the PLL register index.
421  *
422  * With the latest changes to the VT layer, this is guaranteed for all
423  * calls except the actual drawing/blits which aren't supposed to use
424  * the PLL registers anyway
425  *
426  * This is very important for the workarounds to work properly. The only
427  * possible exception to this rule is the call to unblank(), which may
428  * be done at irq time if an oops is in progress.
429  */
430 static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
431 {
432         if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
433                 return;
434
435         (void)INREG(CLOCK_CNTL_DATA);
436         (void)INREG(CRTC_GEN_CNTL);
437 }
438
439 static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
440 {
441         if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
442                 /* we can't deal with posted writes here ... */
443                 _radeon_msleep(rinfo, 5);
444         }
445         if (rinfo->errata & CHIP_ERRATA_R300_CG) {
446                 u32 save, tmp;
447                 save = INREG(CLOCK_CNTL_INDEX);
448                 tmp = save & ~(0x3f | PLL_WR_EN);
449                 OUTREG(CLOCK_CNTL_INDEX, tmp);
450                 tmp = INREG(CLOCK_CNTL_DATA);
451                 OUTREG(CLOCK_CNTL_INDEX, save);
452         }
453 }
454
455 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
456 {
457         u32 data;
458
459         OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
460         radeon_pll_errata_after_index(rinfo);
461         data = INREG(CLOCK_CNTL_DATA);
462         radeon_pll_errata_after_data(rinfo);
463         return data;
464 }
465
466 static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
467                             u32 val)
468 {
469
470         OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
471         radeon_pll_errata_after_index(rinfo);
472         OUTREG(CLOCK_CNTL_DATA, val);
473         radeon_pll_errata_after_data(rinfo);
474 }
475
476
477 static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
478                              u32 val, u32 mask)
479 {
480         unsigned int tmp;
481
482         tmp  = __INPLL(rinfo, index);
483         tmp &= (mask);
484         tmp |= (val);
485         __OUTPLL(rinfo, index, tmp);
486 }
487
488
489 #define INPLL(addr)                     __INPLL(rinfo, addr)
490 #define OUTPLL(index, val)              __OUTPLL(rinfo, index, val)
491 #define OUTPLLP(index, val, mask)       __OUTPLLP(rinfo, index, val, mask)
492
493
494 #define BIOS_IN8(v)     (readb(rinfo->bios_seg + (v)))
495 #define BIOS_IN16(v)    (readb(rinfo->bios_seg + (v)) | \
496                           (readb(rinfo->bios_seg + (v) + 1) << 8))
497 #define BIOS_IN32(v)    (readb(rinfo->bios_seg + (v)) | \
498                           (readb(rinfo->bios_seg + (v) + 1) << 8) | \
499                           (readb(rinfo->bios_seg + (v) + 2) << 16) | \
500                           (readb(rinfo->bios_seg + (v) + 3) << 24))
501
502 /*
503  * Inline utilities
504  */
505 static inline int round_div(int num, int den)
506 {
507         return (num + (den / 2)) / den;
508 }
509
510 static inline int var_to_depth(const struct fb_var_screeninfo *var)
511 {
512         if (var->bits_per_pixel != 16)
513                 return var->bits_per_pixel;
514         return (var->green.length == 5) ? 15 : 16;
515 }
516
517 static inline u32 radeon_get_dstbpp(u16 depth)
518 {
519         switch (depth) {
520         case 8:
521                 return DST_8BPP;
522         case 15:
523                 return DST_15BPP;
524         case 16:
525                 return DST_16BPP;
526         case 32:
527                 return DST_32BPP;
528         default:
529                 return 0;
530         }
531 }
532
533 /*
534  * 2D Engine helper routines
535  */
536 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
537 {
538         int i;
539
540         /* initiate flush */
541         OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
542                 ~RB2D_DC_FLUSH_ALL);
543
544         for (i=0; i < 2000000; i++) {
545                 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
546                         return;
547                 udelay(1);
548         }
549         printk(KERN_ERR "radeonfb: Flush Timeout !\n");
550 }
551
552
553 static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
554 {
555         int i;
556
557         for (i=0; i<2000000; i++) {
558                 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
559                         return;
560                 udelay(1);
561         }
562         printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
563 }
564
565
566 static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
567 {
568         int i;
569
570         /* ensure FIFO is empty before waiting for idle */
571         _radeon_fifo_wait (rinfo, 64);
572
573         for (i=0; i<2000000; i++) {
574                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
575                         radeon_engine_flush (rinfo);
576                         return;
577                 }
578                 udelay(1);
579         }
580         printk(KERN_ERR "radeonfb: Idle Timeout !\n");
581 }
582
583
584 #define radeon_engine_idle()            _radeon_engine_idle(rinfo)
585 #define radeon_fifo_wait(entries)       _radeon_fifo_wait(rinfo,entries)
586 #define radeon_msleep(ms)               _radeon_msleep(rinfo,ms)
587
588
589 /* I2C Functions */
590 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
591 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
592 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
593
594 /* PM Functions */
595 extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
596 extern int radeonfb_pci_resume(struct pci_dev *pdev);
597 extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep);
598 extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
599
600 /* Monitor probe functions */
601 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
602                                  const char *monitor_layout, int ignore_edid);
603 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
604 extern int radeon_match_mode(struct radeonfb_info *rinfo,
605                              struct fb_var_screeninfo *dest,
606                              const struct fb_var_screeninfo *src);
607
608 /* Accel functions */
609 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
610 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
611 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
612 extern int radeonfb_sync(struct fb_info *info);
613 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
614 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
615
616 /* Other functions */
617 extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
618 extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
619                                int reg_only);
620
621 /* Backlight functions */
622 #ifdef CONFIG_FB_RADEON_BACKLIGHT
623 extern void radeonfb_bl_init(struct radeonfb_info *rinfo);
624 extern void radeonfb_bl_exit(struct radeonfb_info *rinfo);
625 #else
626 static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
627 static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
628 #endif
629
630 #endif /* __RADEONFB_H__ */