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   1 /*
   2  *  linux/drivers/media/mmc/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/protocol.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/clk.h>
  28
  29 #include <asm/io.h>
  30 #include <asm/irq.h>
  31 #include <asm/scatterlist.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/gpio.h>
  36 #include <asm/arch/dma.h>
  37 #include <asm/arch/mux.h>
  38 #include <asm/arch/fpga.h>
  39 #include <asm/arch/tps65010.h>
  40
  41 #define OMAP_MMC_REG_CMD        0x00
  42 #define OMAP_MMC_REG_ARGL       0x04
  43 #define OMAP_MMC_REG_ARGH       0x08
  44 #define OMAP_MMC_REG_CON        0x0c
  45 #define OMAP_MMC_REG_STAT       0x10
  46 #define OMAP_MMC_REG_IE         0x14
  47 #define OMAP_MMC_REG_CTO        0x18
  48 #define OMAP_MMC_REG_DTO        0x1c
  49 #define OMAP_MMC_REG_DATA       0x20
  50 #define OMAP_MMC_REG_BLEN       0x24
  51 #define OMAP_MMC_REG_NBLK       0x28
  52 #define OMAP_MMC_REG_BUF        0x2c
  53 #define OMAP_MMC_REG_SDIO       0x34
  54 #define OMAP_MMC_REG_REV        0x3c
  55 #define OMAP_MMC_REG_RSP0       0x40
  56 #define OMAP_MMC_REG_RSP1       0x44
  57 #define OMAP_MMC_REG_RSP2       0x48
  58 #define OMAP_MMC_REG_RSP3       0x4c
  59 #define OMAP_MMC_REG_RSP4       0x50
  60 #define OMAP_MMC_REG_RSP5       0x54
  61 #define OMAP_MMC_REG_RSP6       0x58
  62 #define OMAP_MMC_REG_RSP7       0x5c
  63 #define OMAP_MMC_REG_IOSR       0x60
  64 #define OMAP_MMC_REG_SYSC       0x64
  65 #define OMAP_MMC_REG_SYSS       0x68
  66
  67 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  68 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  69 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  70 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  71 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  72 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  73 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  74 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  75 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  76 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  77 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  78 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  79 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  80
  81 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  82 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  83
  84 /*
  85  * Command types
  86  */
  87 #define OMAP_MMC_CMDTYPE_BC     0
  88 #define OMAP_MMC_CMDTYPE_BCR    1
  89 #define OMAP_MMC_CMDTYPE_AC     2
  90 #define OMAP_MMC_CMDTYPE_ADTC   3
  91
  92
  93 #define DRIVER_NAME "mmci-omap"
  94 #define RSP_TYPE(x)     ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
  95
  96 /* Specifies how often in millisecs to poll for card status changes
  97  * when the cover switch is open */
  98 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  99
 100 static int mmc_omap_enable_poll = 1;
 101
 102 struct mmc_omap_host {
 103         int                     initialized;
 104         int                     suspended;
 105         struct mmc_request *    mrq;
 106         struct mmc_command *    cmd;
 107         struct mmc_data *       data;
 108         struct mmc_host *       mmc;
 109         struct device *         dev;
 110         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 111         struct clk *            iclk;
 112         struct clk *            fclk;
 113         struct resource         *mem_res;
 114         void __iomem            *virt_base;
 115         unsigned int            phys_base;
 116         int                     irq;
 117         unsigned char           bus_mode;
 118         unsigned char           hw_bus_mode;
 119
 120         unsigned int            sg_len;
 121         int                     sg_idx;
 122         u16 *                   buffer;
 123         u32                     buffer_bytes_left;
 124         u32                     total_bytes_left;
 125
 126         unsigned                use_dma:1;
 127         unsigned                brs_received:1, dma_done:1;
 128         unsigned                dma_is_read:1;
 129         unsigned                dma_in_use:1;
 130         int                     dma_ch;
 131         spinlock_t              dma_lock;
 132         struct timer_list       dma_timer;
 133         unsigned                dma_len;
 134
 135         short                   power_pin;
 136         short                   wp_pin;
 137
 138         int                     switch_pin;
 139         struct work_struct      switch_work;
 140         struct timer_list       switch_timer;
 141         int                     switch_last_state;
 142 };
 143
 144 static inline int
 145 mmc_omap_cover_is_open(struct mmc_omap_host *host)
 146 {
 147         if (host->switch_pin < 0)
 148                 return 0;
 149         return omap_get_gpio_datain(host->switch_pin);
 150 }
 151
 152 static ssize_t
 153 mmc_omap_show_cover_switch(struct device *dev,
 154         struct device_attribute *attr, char *buf)
 155 {
 156         struct mmc_omap_host *host = dev_get_drvdata(dev);
 157
 158         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
 159                         "closed");
 160 }
 161
 162 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 163
 164 static ssize_t
 165 mmc_omap_show_enable_poll(struct device *dev,
 166         struct device_attribute *attr, char *buf)
 167 {
 168         return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
 169 }
 170
 171 static ssize_t
 172 mmc_omap_store_enable_poll(struct device *dev,
 173         struct device_attribute *attr, const char *buf,
 174         size_t size)
 175 {
 176         int enable_poll;
 177
 178         if (sscanf(buf, "%10d", &enable_poll) != 1)
 179                 return -EINVAL;
 180
 181         if (enable_poll != mmc_omap_enable_poll) {
 182                 struct mmc_omap_host *host = dev_get_drvdata(dev);
 183
 184                 mmc_omap_enable_poll = enable_poll;
 185                 if (enable_poll && host->switch_pin >= 0)
 186                         schedule_work(&host->switch_work);
 187         }
 188         return size;
 189 }
 190
 191 static DEVICE_ATTR(enable_poll, 0664,
 192                    mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
 193
 194 static void
 195 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 196 {
 197         u32 cmdreg;
 198         u32 resptype;
 199         u32 cmdtype;
 200
 201         host->cmd = cmd;
 202
 203         resptype = 0;
 204         cmdtype = 0;
 205
 206         /* Our hardware needs to know exact type */
 207         switch (RSP_TYPE(mmc_resp_type(cmd))) {
 208         case RSP_TYPE(MMC_RSP_R1):
 209                 /* resp 1, resp 1b */
 210                 resptype = 1;
 211                 break;
 212         case RSP_TYPE(MMC_RSP_R2):
 213                 resptype = 2;
 214                 break;
 215         case RSP_TYPE(MMC_RSP_R3):
 216                 resptype = 3;
 217                 break;
 218         default:
 219                 break;
 220         }
 221
 222         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 223                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 224         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 225                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 226         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 227                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 228         } else {
 229                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 230         }
 231
 232         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 233
 234         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 235                 cmdreg |= 1 << 6;
 236
 237         if (cmd->flags & MMC_RSP_BUSY)
 238                 cmdreg |= 1 << 11;
 239
 240         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 241                 cmdreg |= 1 << 15;
 242
 243         clk_enable(host->fclk);
 244
 245         OMAP_MMC_WRITE(host, CTO, 200);
 246         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 247         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 248         OMAP_MMC_WRITE(host, IE,
 249                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 250                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 251                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 252                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 253                        OMAP_MMC_STAT_END_OF_DATA);
 254         OMAP_MMC_WRITE(host, CMD, cmdreg);
 255 }
 256
 257 static void
 258 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 259 {
 260         if (host->dma_in_use) {
 261                 enum dma_data_direction dma_data_dir;
 262
 263                 BUG_ON(host->dma_ch < 0);
 264                 if (data->error != MMC_ERR_NONE)
 265                         omap_stop_dma(host->dma_ch);
 266                 /* Release DMA channel lazily */
 267                 mod_timer(&host->dma_timer, jiffies + HZ);
 268                 if (data->flags & MMC_DATA_WRITE)
 269                         dma_data_dir = DMA_TO_DEVICE;
 270                 else
 271                         dma_data_dir = DMA_FROM_DEVICE;
 272                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 273                              dma_data_dir);
 274         }
 275         host->data = NULL;
 276         host->sg_len = 0;
 277         clk_disable(host->fclk);
 278
 279         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 280          * dozens of requests until the card finishes writing data.
 281          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 282          */
 283
 284         if (!data->stop) {
 285                 host->mrq = NULL;
 286                 mmc_request_done(host->mmc, data->mrq);
 287                 return;
 288         }
 289
 290         mmc_omap_start_command(host, data->stop);
 291 }
 292
 293 static void
 294 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 295 {
 296         unsigned long flags;
 297         int done;
 298
 299         if (!host->dma_in_use) {
 300                 mmc_omap_xfer_done(host, data);
 301                 return;
 302         }
 303         done = 0;
 304         spin_lock_irqsave(&host->dma_lock, flags);
 305         if (host->dma_done)
 306                 done = 1;
 307         else
 308                 host->brs_received = 1;
 309         spin_unlock_irqrestore(&host->dma_lock, flags);
 310         if (done)
 311                 mmc_omap_xfer_done(host, data);
 312 }
 313
 314 static void
 315 mmc_omap_dma_timer(unsigned long data)
 316 {
 317         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 318
 319         BUG_ON(host->dma_ch < 0);
 320         omap_free_dma(host->dma_ch);
 321         host->dma_ch = -1;
 322 }
 323
 324 static void
 325 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 326 {
 327         unsigned long flags;
 328         int done;
 329
 330         done = 0;
 331         spin_lock_irqsave(&host->dma_lock, flags);
 332         if (host->brs_received)
 333                 done = 1;
 334         else
 335                 host->dma_done = 1;
 336         spin_unlock_irqrestore(&host->dma_lock, flags);
 337         if (done)
 338                 mmc_omap_xfer_done(host, data);
 339 }
 340
 341 static void
 342 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 343 {
 344         host->cmd = NULL;
 345
 346         if (cmd->flags & MMC_RSP_PRESENT) {
 347                 if (cmd->flags & MMC_RSP_136) {
 348                         /* response type 2 */
 349                         cmd->resp[3] =
 350                                 OMAP_MMC_READ(host, RSP0) |
 351                                 (OMAP_MMC_READ(host, RSP1) << 16);
 352                         cmd->resp[2] =
 353                                 OMAP_MMC_READ(host, RSP2) |
 354                                 (OMAP_MMC_READ(host, RSP3) << 16);
 355                         cmd->resp[1] =
 356                                 OMAP_MMC_READ(host, RSP4) |
 357                                 (OMAP_MMC_READ(host, RSP5) << 16);
 358                         cmd->resp[0] =
 359                                 OMAP_MMC_READ(host, RSP6) |
 360                                 (OMAP_MMC_READ(host, RSP7) << 16);
 361                 } else {
 362                         /* response types 1, 1b, 3, 4, 5, 6 */
 363                         cmd->resp[0] =
 364                                 OMAP_MMC_READ(host, RSP6) |
 365                                 (OMAP_MMC_READ(host, RSP7) << 16);
 366                 }
 367         }
 368
 369         if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
 370                 host->mrq = NULL;
 371                 clk_disable(host->fclk);
 372                 mmc_request_done(host->mmc, cmd->mrq);
 373         }
 374 }
 375
 376 /* PIO only */
 377 static void
 378 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 379 {
 380         struct scatterlist *sg;
 381
 382         sg = host->data->sg + host->sg_idx;
 383         host->buffer_bytes_left = sg->length;
 384         host->buffer = page_address(sg->page) + sg->offset;
 385         if (host->buffer_bytes_left > host->total_bytes_left)
 386                 host->buffer_bytes_left = host->total_bytes_left;
 387 }
 388
 389 /* PIO only */
 390 static void
 391 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 392 {
 393         int n;
 394
 395         if (host->buffer_bytes_left == 0) {
 396                 host->sg_idx++;
 397                 BUG_ON(host->sg_idx == host->sg_len);
 398                 mmc_omap_sg_to_buf(host);
 399         }
 400         n = 64;
 401         if (n > host->buffer_bytes_left)
 402                 n = host->buffer_bytes_left;
 403         host->buffer_bytes_left -= n;
 404         host->total_bytes_left -= n;
 405         host->data->bytes_xfered += n;
 406
 407         if (write) {
 408                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 409         } else {
 410                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 411         }
 412 }
 413
 414 static inline void mmc_omap_report_irq(u16 status)
 415 {
 416         static const char *mmc_omap_status_bits[] = {
 417                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 418                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 419         };
 420         int i, c = 0;
 421
 422         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 423                 if (status & (1 << i)) {
 424                         if (c)
 425                                 printk(" ");
 426                         printk("%s", mmc_omap_status_bits[i]);
 427                         c++;
 428                 }
 429 }
 430
 431 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 432 {
 433         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 434         u16 status;
 435         int end_command;
 436         int end_transfer;
 437         int transfer_error;
 438
 439         if (host->cmd == NULL && host->data == NULL) {
 440                 status = OMAP_MMC_READ(host, STAT);
 441                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 442                 if (status != 0) {
 443                         OMAP_MMC_WRITE(host, STAT, status);
 444                         OMAP_MMC_WRITE(host, IE, 0);
 445                 }
 446                 return IRQ_HANDLED;
 447         }
 448
 449         end_command = 0;
 450         end_transfer = 0;
 451         transfer_error = 0;
 452
 453         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 454                 OMAP_MMC_WRITE(host, STAT, status);
 455 #ifdef CONFIG_MMC_DEBUG
 456                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 457                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 458                 mmc_omap_report_irq(status);
 459                 printk("\n");
 460 #endif
 461                 if (host->total_bytes_left) {
 462                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 463                             (status & OMAP_MMC_STAT_END_OF_DATA))
 464                                 mmc_omap_xfer_data(host, 0);
 465                         if (status & OMAP_MMC_STAT_A_EMPTY)
 466                                 mmc_omap_xfer_data(host, 1);
 467                 }
 468
 469                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 470                         end_transfer = 1;
 471                 }
 472
 473                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 474                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 475                         if (host->data) {
 476                                 host->data->error |= MMC_ERR_TIMEOUT;
 477                                 transfer_error = 1;
 478                         }
 479                 }
 480
 481                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 482                         if (host->data) {
 483                                 host->data->error |= MMC_ERR_BADCRC;
 484                                 dev_dbg(mmc_dev(host->mmc),
 485                                          "data CRC error, bytes left %d\n",
 486                                         host->total_bytes_left);
 487                                 transfer_error = 1;
 488                         } else {
 489                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 490                         }
 491                 }
 492
 493                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 494                         /* Timeouts are routine with some commands */
 495                         if (host->cmd) {
 496                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 497                                                 host->cmd->opcode !=
 498                                                 MMC_SEND_OP_COND &&
 499                                                 host->cmd->opcode !=
 500                                                 MMC_APP_CMD &&
 501                                                 !mmc_omap_cover_is_open(host))
 502                                         dev_err(mmc_dev(host->mmc),
 503                                                 "command timeout, CMD %d\n",
 504                                                 host->cmd->opcode);
 505                                 host->cmd->error = MMC_ERR_TIMEOUT;
 506                                 end_command = 1;
 507                         }
 508                 }
 509
 510                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 511                         if (host->cmd) {
 512                                 dev_err(mmc_dev(host->mmc),
 513                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 514                                         host->cmd->opcode, host->cmd->arg);
 515                                 host->cmd->error = MMC_ERR_BADCRC;
 516                                 end_command = 1;
 517                         } else
 518                                 dev_err(mmc_dev(host->mmc),
 519                                         "command CRC error without cmd?\n");
 520                 }
 521
 522                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 523                         if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
 524                                 u32 response = OMAP_MMC_READ(host, RSP6)
 525                                         | (OMAP_MMC_READ(host, RSP7) << 16);
 526                                 /* STOP sometimes sets must-ignore bits */
 527                                 if (!(response & (R1_CC_ERROR
 528                                                                 | R1_ILLEGAL_COMMAND
 529                                                                 | R1_COM_CRC_ERROR))) {
 530                                         end_command = 1;
 531                                         continue;
 532                                 }
 533                         }
 534
 535                         dev_dbg(mmc_dev(host->mmc), "card status error (CMD%d)\n",
 536                                 host->cmd->opcode);
 537                         if (host->cmd) {
 538                                 host->cmd->error = MMC_ERR_FAILED;
 539                                 end_command = 1;
 540                         }
 541                         if (host->data) {
 542                                 host->data->error = MMC_ERR_FAILED;
 543                                 transfer_error = 1;
 544                         }
 545                 }
 546
 547                 /*
 548                  * NOTE: On 1610 the END_OF_CMD may come too early when
 549                  * starting a write
 550                  */
 551                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 552                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 553                         end_command = 1;
 554                 }
 555         }
 556
 557         if (end_command) {
 558                 mmc_omap_cmd_done(host, host->cmd);
 559         }
 560         if (transfer_error)
 561                 mmc_omap_xfer_done(host, host->data);
 562         else if (end_transfer)
 563                 mmc_omap_end_of_data(host, host->data);
 564
 565         return IRQ_HANDLED;
 566 }
 567
 568 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
 569 {
 570         struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
 571
 572         schedule_work(&host->switch_work);
 573
 574         return IRQ_HANDLED;
 575 }
 576
 577 static void mmc_omap_switch_timer(unsigned long arg)
 578 {
 579         struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
 580
 581         schedule_work(&host->switch_work);
 582 }
 583
 584 static void mmc_omap_switch_handler(struct work_struct *work)
 585 {
 586         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, switch_work);
 587         struct mmc_card *card;
 588         static int complained = 0;
 589         int cards = 0, cover_open;
 590
 591         if (host->switch_pin == -1)
 592                 return;
 593         cover_open = mmc_omap_cover_is_open(host);
 594         if (cover_open != host->switch_last_state) {
 595                 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
 596                 host->switch_last_state = cover_open;
 597         }
 598         mmc_detect_change(host->mmc, 0);
 599         list_for_each_entry(card, &host->mmc->cards, node) {
 600                 if (mmc_card_present(card))
 601                         cards++;
 602         }
 603         if (mmc_omap_cover_is_open(host)) {
 604                 if (!complained) {
 605                         dev_info(mmc_dev(host->mmc), "cover is open");
 606                         complained = 1;
 607                 }
 608                 if (mmc_omap_enable_poll)
 609                         mod_timer(&host->switch_timer, jiffies +
 610                                 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
 611         } else {
 612                 complained = 0;
 613         }
 614 }
 615
 616 /* Prepare to transfer the next segment of a scatterlist */
 617 static void
 618 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 619 {
 620         int dma_ch = host->dma_ch;
 621         unsigned long data_addr;
 622         u16 buf, frame;
 623         u32 count;
 624         struct scatterlist *sg = &data->sg[host->sg_idx];
 625         int src_port = 0;
 626         int dst_port = 0;
 627         int sync_dev = 0;
 628
 629         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 630         frame = data->blksz;
 631         count = sg_dma_len(sg);
 632
 633         if ((data->blocks == 1) && (count > data->blksz))
 634                 count = frame;
 635
 636         host->dma_len = count;
 637
 638         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 639          * Use 16 or 32 word frames when the blocksize is at least that large.
 640          * Blocksize is usually 512 bytes; but not for some SD reads.
 641          */
 642         if (cpu_is_omap15xx() && frame > 32)
 643                 frame = 32;
 644         else if (frame > 64)
 645                 frame = 64;
 646         count /= frame;
 647         frame >>= 1;
 648
 649         if (!(data->flags & MMC_DATA_WRITE)) {
 650                 buf = 0x800f | ((frame - 1) << 8);
 651
 652                 if (cpu_class_is_omap1()) {
 653                         src_port = OMAP_DMA_PORT_TIPB;
 654                         dst_port = OMAP_DMA_PORT_EMIFF;
 655                 }
 656                 if (cpu_is_omap24xx())
 657                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 658
 659                 omap_set_dma_src_params(dma_ch, src_port,
 660                                         OMAP_DMA_AMODE_CONSTANT,
 661                                         data_addr, 0, 0);
 662                 omap_set_dma_dest_params(dma_ch, dst_port,
 663                                          OMAP_DMA_AMODE_POST_INC,
 664                                          sg_dma_address(sg), 0, 0);
 665                 omap_set_dma_dest_data_pack(dma_ch, 1);
 666                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 667         } else {
 668                 buf = 0x0f80 | ((frame - 1) << 0);
 669
 670                 if (cpu_class_is_omap1()) {
 671                         src_port = OMAP_DMA_PORT_EMIFF;
 672                         dst_port = OMAP_DMA_PORT_TIPB;
 673                 }
 674                 if (cpu_is_omap24xx())
 675                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 676
 677                 omap_set_dma_dest_params(dma_ch, dst_port,
 678                                          OMAP_DMA_AMODE_CONSTANT,
 679                                          data_addr, 0, 0);
 680                 omap_set_dma_src_params(dma_ch, src_port,
 681                                         OMAP_DMA_AMODE_POST_INC,
 682                                         sg_dma_address(sg), 0, 0);
 683                 omap_set_dma_src_data_pack(dma_ch, 1);
 684                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 685         }
 686
 687         /* Max limit for DMA frame count is 0xffff */
 688         BUG_ON(count > 0xffff);
 689
 690         OMAP_MMC_WRITE(host, BUF, buf);
 691         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 692                                      frame, count, OMAP_DMA_SYNC_FRAME,
 693                                      sync_dev, 0);
 694 }
 695
 696 /* A scatterlist segment completed */
 697 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 698 {
 699         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 700         struct mmc_data *mmcdat = host->data;
 701
 702         if (unlikely(host->dma_ch < 0)) {
 703                 dev_err(mmc_dev(host->mmc),
 704                         "DMA callback while DMA not enabled\n");
 705                 return;
 706         }
 707         /* FIXME: We really should do something to _handle_ the errors */
 708         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 709                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 710                 return;
 711         }
 712         if (ch_status & OMAP_DMA_DROP_IRQ) {
 713                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 714                 return;
 715         }
 716         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 717                 return;
 718         }
 719         mmcdat->bytes_xfered += host->dma_len;
 720         host->sg_idx++;
 721         if (host->sg_idx < host->sg_len) {
 722                 mmc_omap_prepare_dma(host, host->data);
 723                 omap_start_dma(host->dma_ch);
 724         } else
 725                 mmc_omap_dma_done(host, host->data);
 726 }
 727
 728 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 729 {
 730         const char *dev_name;
 731         int sync_dev, dma_ch, is_read, r;
 732
 733         is_read = !(data->flags & MMC_DATA_WRITE);
 734         del_timer_sync(&host->dma_timer);
 735         if (host->dma_ch >= 0) {
 736                 if (is_read == host->dma_is_read)
 737                         return 0;
 738                 omap_free_dma(host->dma_ch);
 739                 host->dma_ch = -1;
 740         }
 741
 742         if (is_read) {
 743                 if (host->id == 1) {
 744                         sync_dev = OMAP_DMA_MMC_RX;
 745                         dev_name = "MMC1 read";
 746                 } else {
 747                         sync_dev = OMAP_DMA_MMC2_RX;
 748                         dev_name = "MMC2 read";
 749                 }
 750         } else {
 751                 if (host->id == 1) {
 752                         sync_dev = OMAP_DMA_MMC_TX;
 753                         dev_name = "MMC1 write";
 754                 } else {
 755                         sync_dev = OMAP_DMA_MMC2_TX;
 756                         dev_name = "MMC2 write";
 757                 }
 758         }
 759         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 760                              host, &dma_ch);
 761         if (r != 0) {
 762                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 763                 return r;
 764         }
 765         host->dma_ch = dma_ch;
 766         host->dma_is_read = is_read;
 767
 768         return 0;
 769 }
 770
 771 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 772 {
 773         u16 reg;
 774
 775         reg = OMAP_MMC_READ(host, SDIO);
 776         reg &= ~(1 << 5);
 777         OMAP_MMC_WRITE(host, SDIO, reg);
 778         /* Set maximum timeout */
 779         OMAP_MMC_WRITE(host, CTO, 0xff);
 780 }
 781
 782 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 783 {
 784         int timeout;
 785         u16 reg;
 786
 787         /* Convert ns to clock cycles by assuming 20MHz frequency
 788          * 1 cycle at 20MHz = 500 ns
 789          */
 790         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 791
 792         /* Check if we need to use timeout multiplier register */
 793         reg = OMAP_MMC_READ(host, SDIO);
 794         if (timeout > 0xffff) {
 795                 reg |= (1 << 5);
 796                 timeout /= 1024;
 797         } else
 798                 reg &= ~(1 << 5);
 799         OMAP_MMC_WRITE(host, SDIO, reg);
 800         OMAP_MMC_WRITE(host, DTO, timeout);
 801 }
 802
 803 static void
 804 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 805 {
 806         struct mmc_data *data = req->data;
 807         int i, use_dma, block_size;
 808         unsigned sg_len;
 809
 810         host->data = data;
 811         if (data == NULL) {
 812                 OMAP_MMC_WRITE(host, BLEN, 0);
 813                 OMAP_MMC_WRITE(host, NBLK, 0);
 814                 OMAP_MMC_WRITE(host, BUF, 0);
 815                 host->dma_in_use = 0;
 816                 set_cmd_timeout(host, req);
 817                 return;
 818         }
 819
 820         block_size = data->blksz;
 821
 822         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 823         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 824         set_data_timeout(host, req);
 825
 826         /* cope with calling layer confusion; it issues "single
 827          * block" writes using multi-block scatterlists.
 828          */
 829         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 830
 831         /* Only do DMA for entire blocks */
 832         use_dma = host->use_dma;
 833         if (use_dma) {
 834                 for (i = 0; i < sg_len; i++) {
 835                         if ((data->sg[i].length % block_size) != 0) {
 836                                 use_dma = 0;
 837                                 break;
 838                         }
 839                 }
 840         }
 841
 842         host->sg_idx = 0;
 843         if (use_dma) {
 844                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 845                         enum dma_data_direction dma_data_dir;
 846
 847                         if (data->flags & MMC_DATA_WRITE)
 848                                 dma_data_dir = DMA_TO_DEVICE;
 849                         else
 850                                 dma_data_dir = DMA_FROM_DEVICE;
 851
 852                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 853                                                 sg_len, dma_data_dir);
 854                         host->total_bytes_left = 0;
 855                         mmc_omap_prepare_dma(host, req->data);
 856                         host->brs_received = 0;
 857                         host->dma_done = 0;
 858                         host->dma_in_use = 1;
 859                 } else
 860                         use_dma = 0;
 861         }
 862
 863         /* Revert to PIO? */
 864         if (!use_dma) {
 865                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 866                 host->total_bytes_left = data->blocks * block_size;
 867                 host->sg_len = sg_len;
 868                 mmc_omap_sg_to_buf(host);
 869                 host->dma_in_use = 0;
 870         }
 871 }
 872
 873 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 874 {
 875         struct mmc_omap_host *host = mmc_priv(mmc);
 876
 877         WARN_ON(host->mrq != NULL);
 878
 879         host->mrq = req;
 880
 881         /* only touch fifo AFTER the controller readies it */
 882         mmc_omap_prepare_data(host, req);
 883         mmc_omap_start_command(host, req->cmd);
 884         if (host->dma_in_use)
 885                 omap_start_dma(host->dma_ch);
 886 }
 887
 888 static void innovator_fpga_socket_power(int on)
 889 {
 890 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 891         if (on) {
 892                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 893                      OMAP1510_FPGA_POWER);
 894         } else {
 895                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 896                      OMAP1510_FPGA_POWER);
 897         }
 898 #endif
 899 }
 900
 901 /*
 902  * Turn the socket power on/off. Innovator uses FPGA, most boards
 903  * probably use GPIO.
 904  */
 905 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 906 {
 907         if (on) {
 908                 if (machine_is_omap_innovator())
 909                         innovator_fpga_socket_power(1);
 910                 else if (machine_is_omap_h2())
 911                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 912                 else if (machine_is_omap_h3())
 913                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 914                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 915                 else if (cpu_is_omap24xx()) {
 916                         u16 reg = OMAP_MMC_READ(host, CON);
 917                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 918                 } else
 919                         if (host->power_pin >= 0)
 920                                 omap_set_gpio_dataout(host->power_pin, 1);
 921         } else {
 922                 if (machine_is_omap_innovator())
 923                         innovator_fpga_socket_power(0);
 924                 else if (machine_is_omap_h2())
 925                         tps65010_set_gpio_out_value(GPIO3, LOW);
 926                 else if (machine_is_omap_h3())
 927                         tps65010_set_gpio_out_value(GPIO4, LOW);
 928                 else if (cpu_is_omap24xx()) {
 929                         u16 reg = OMAP_MMC_READ(host, CON);
 930                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
 931                 } else
 932                         if (host->power_pin >= 0)
 933                                 omap_set_gpio_dataout(host->power_pin, 0);
 934         }
 935 }
 936
 937 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 938 {
 939         struct mmc_omap_host *host = mmc_priv(mmc);
 940         int dsor;
 941         int realclock, i;
 942
 943         realclock = ios->clock;
 944
 945         if (ios->clock == 0)
 946                 dsor = 0;
 947         else {
 948                 int func_clk_rate = clk_get_rate(host->fclk);
 949
 950                 dsor = func_clk_rate / realclock;
 951                 if (dsor < 1)
 952                         dsor = 1;
 953
 954                 if (func_clk_rate / dsor > realclock)
 955                         dsor++;
 956
 957                 if (dsor > 250)
 958                         dsor = 250;
 959                 dsor++;
 960
 961                 if (ios->bus_width == MMC_BUS_WIDTH_4)
 962                         dsor |= 1 << 15;
 963         }
 964
 965         switch (ios->power_mode) {
 966         case MMC_POWER_OFF:
 967                 mmc_omap_power(host, 0);
 968                 break;
 969         case MMC_POWER_UP:
 970         case MMC_POWER_ON:
 971                 mmc_omap_power(host, 1);
 972                 dsor |= 1 << 11;
 973                 break;
 974         }
 975
 976         host->bus_mode = ios->bus_mode;
 977         host->hw_bus_mode = host->bus_mode;
 978
 979         clk_enable(host->fclk);
 980
 981         /* On insanely high arm_per frequencies something sometimes
 982          * goes somehow out of sync, and the POW bit is not being set,
 983          * which results in the while loop below getting stuck.
 984          * Writing to the CON register twice seems to do the trick. */
 985         for (i = 0; i < 2; i++)
 986                 OMAP_MMC_WRITE(host, CON, dsor);
 987         if (ios->power_mode == MMC_POWER_UP) {
 988                 /* Send clock cycles, poll completion */
 989                 OMAP_MMC_WRITE(host, IE, 0);
 990                 OMAP_MMC_WRITE(host, STAT, 0xffff);
 991                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
 992                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
 993                 OMAP_MMC_WRITE(host, STAT, 1);
 994         }
 995         clk_disable(host->fclk);
 996 }
 997
 998 static int mmc_omap_get_ro(struct mmc_host *mmc)
 999 {
1000         struct mmc_omap_host *host = mmc_priv(mmc);
1001
1002         return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
1003 }
1004
1005 static const struct mmc_host_ops mmc_omap_ops = {
1006         .request        = mmc_omap_request,
1007         .set_ios        = mmc_omap_set_ios,
1008         .get_ro         = mmc_omap_get_ro,
1009 };
1010
1011 static int __init mmc_omap_probe(struct platform_device *pdev)
1012 {
1013         struct omap_mmc_conf *minfo = pdev->dev.platform_data;
1014         struct mmc_host *mmc;
1015         struct mmc_omap_host *host = NULL;
1016         struct resource *res;
1017         int ret = 0;
1018         int irq;
1019
1020         if (minfo == NULL) {
1021                 dev_err(&pdev->dev, "platform data missing\n");
1022                 return -ENXIO;
1023         }
1024
1025         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1026         irq = platform_get_irq(pdev, 0);
1027         if (res == NULL || irq < 0)
1028                 return -ENXIO;
1029
1030         res = request_mem_region(res->start, res->end - res->start + 1,
1031                                  pdev->name);
1032         if (res == NULL)
1033                 return -EBUSY;
1034
1035         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1036         if (mmc == NULL) {
1037                 ret = -ENOMEM;
1038                 goto err_free_mem_region;
1039         }
1040
1041         host = mmc_priv(mmc);
1042         host->mmc = mmc;
1043
1044         spin_lock_init(&host->dma_lock);
1045         init_timer(&host->dma_timer);
1046         host->dma_timer.function = mmc_omap_dma_timer;
1047         host->dma_timer.data = (unsigned long) host;
1048
1049         host->id = pdev->id;
1050         host->mem_res = res;
1051         host->irq = irq;
1052
1053         if (cpu_is_omap24xx()) {
1054                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1055                 if (IS_ERR(host->iclk))
1056                         goto err_free_mmc_host;
1057                 clk_enable(host->iclk);
1058         }
1059
1060         if (!cpu_is_omap24xx())
1061                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1062         else
1063                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1064
1065         if (IS_ERR(host->fclk)) {
1066                 ret = PTR_ERR(host->fclk);
1067                 goto err_free_iclk;
1068         }
1069
1070         /* REVISIT:
1071          * Also, use minfo->cover to decide how to manage
1072          * the card detect sensing.
1073          */
1074         host->power_pin = minfo->power_pin;
1075         host->switch_pin = minfo->switch_pin;
1076         host->wp_pin = minfo->wp_pin;
1077         host->use_dma = 1;
1078         host->dma_ch = -1;
1079
1080         host->irq = irq;
1081         host->phys_base = host->mem_res->start;
1082         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1083
1084         mmc->ops = &mmc_omap_ops;
1085         mmc->f_min = 400000;
1086         mmc->f_max = 24000000;
1087         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1088         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1089
1090         if (minfo->wire4)
1091                  mmc->caps |= MMC_CAP_4_BIT_DATA;
1092
1093         /* Use scatterlist DMA to reduce per-transfer costs.
1094          * NOTE max_seg_size assumption that small blocks aren't
1095          * normally used (except e.g. for reading SD registers).
1096          */
1097         mmc->max_phys_segs = 32;
1098         mmc->max_hw_segs = 32;
1099         mmc->max_sectors = 256; /* NBLK max 11-bits, OMAP also limited by DMA */
1100         mmc->max_seg_size = mmc->max_sectors * 512;
1101
1102         if (host->power_pin >= 0) {
1103                 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1104                         dev_err(mmc_dev(host->mmc),
1105                                 "Unable to get GPIO pin for MMC power\n");
1106                         goto err_free_fclk;
1107                 }
1108                 omap_set_gpio_direction(host->power_pin, 0);
1109         }
1110
1111         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1112         if (ret)
1113                 goto err_free_power_gpio;
1114
1115         host->dev = &pdev->dev;
1116         platform_set_drvdata(pdev, host);
1117
1118         if (host->switch_pin >= 0) {
1119                 INIT_WORK(&host->switch_work, mmc_omap_switch_handler);
1120                 init_timer(&host->switch_timer);
1121                 host->switch_timer.function = mmc_omap_switch_timer;
1122                 host->switch_timer.data = (unsigned long) host;
1123                 if (omap_request_gpio(host->switch_pin) != 0) {
1124                         dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1125                         host->switch_pin = -1;
1126                         goto no_switch;
1127                 }
1128
1129                 omap_set_gpio_direction(host->switch_pin, 1);
1130                 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1131                                   mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
1132                 if (ret) {
1133                         dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1134                         omap_free_gpio(host->switch_pin);
1135                         host->switch_pin = -1;
1136                         goto no_switch;
1137                 }
1138                 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1139                 if (ret == 0) {
1140                         ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1141                         if (ret != 0)
1142                                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1143                 }
1144                 if (ret) {
1145                         dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1146                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1147                         omap_free_gpio(host->switch_pin);
1148                         host->switch_pin = -1;
1149                         goto no_switch;
1150                 }
1151                 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1152                         schedule_work(&host->switch_work);
1153         }
1154
1155         mmc_add_host(mmc);
1156
1157         return 0;
1158
1159 no_switch:
1160         /* FIXME: Free other resources too. */
1161         if (host) {
1162                 if (host->iclk && !IS_ERR(host->iclk))
1163                         clk_put(host->iclk);
1164                 if (host->fclk && !IS_ERR(host->fclk))
1165                         clk_put(host->fclk);
1166                 mmc_free_host(host->mmc);
1167         }
1168 err_free_power_gpio:
1169         if (host->power_pin >= 0)
1170                 omap_free_gpio(host->power_pin);
1171 err_free_fclk:
1172         clk_put(host->fclk);
1173 err_free_iclk:
1174         if (host->iclk != NULL) {
1175                 clk_disable(host->iclk);
1176                 clk_put(host->iclk);
1177         }
1178 err_free_mmc_host:
1179         mmc_free_host(host->mmc);
1180 err_free_mem_region:
1181         release_mem_region(res->start, res->end - res->start + 1);
1182         return ret;
1183 }
1184
1185 static int mmc_omap_remove(struct platform_device *pdev)
1186 {
1187         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1188
1189         platform_set_drvdata(pdev, NULL);
1190
1191         BUG_ON(host == NULL);
1192
1193         mmc_remove_host(host->mmc);
1194         free_irq(host->irq, host);
1195
1196         if (host->power_pin >= 0)
1197                 omap_free_gpio(host->power_pin);
1198         if (host->switch_pin >= 0) {
1199                 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1200                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1201                 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1202                 omap_free_gpio(host->switch_pin);
1203                 host->switch_pin = -1;
1204                 del_timer_sync(&host->switch_timer);
1205                 flush_scheduled_work();
1206         }
1207         if (host->iclk && !IS_ERR(host->iclk))
1208                 clk_put(host->iclk);
1209         if (host->fclk && !IS_ERR(host->fclk))
1210                 clk_put(host->fclk);
1211
1212         release_mem_region(pdev->resource[0].start,
1213                            pdev->resource[0].end - pdev->resource[0].start + 1);
1214
1215         mmc_free_host(host->mmc);
1216
1217         return 0;
1218 }
1219
1220 #ifdef CONFIG_PM
1221 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1222 {
1223         int ret = 0;
1224         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1225
1226         if (host && host->suspended)
1227                 return 0;
1228
1229         if (host) {
1230                 ret = mmc_suspend_host(host->mmc, mesg);
1231                 if (ret == 0)
1232                         host->suspended = 1;
1233         }
1234         return ret;
1235 }
1236
1237 static int mmc_omap_resume(struct platform_device *pdev)
1238 {
1239         int ret = 0;
1240         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1241
1242         if (host && !host->suspended)
1243                 return 0;
1244
1245         if (host) {
1246                 ret = mmc_resume_host(host->mmc);
1247                 if (ret == 0)
1248                         host->suspended = 0;
1249         }
1250
1251         return ret;
1252 }
1253 #else
1254 #define mmc_omap_suspend        NULL
1255 #define mmc_omap_resume         NULL
1256 #endif
1257
1258 static struct platform_driver mmc_omap_driver = {
1259         .probe          = mmc_omap_probe,
1260         .remove         = mmc_omap_remove,
1261         .suspend        = mmc_omap_suspend,
1262         .resume         = mmc_omap_resume,
1263         .driver         = {
1264                 .name   = DRIVER_NAME,
1265         },
1266 };
1267
1268 static int __init mmc_omap_init(void)
1269 {
1270         return platform_driver_register(&mmc_omap_driver);
1271 }
1272
1273 static void __exit mmc_omap_exit(void)
1274 {
1275         platform_driver_unregister(&mmc_omap_driver);
1276 }
1277
1278 module_init(mmc_omap_init);
1279 module_exit(mmc_omap_exit);
1280
1281 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1282 MODULE_LICENSE("GPL");
1283 MODULE_ALIAS(DRIVER_NAME);
1284 MODULE_AUTHOR("Juha Yrjölä");