[MTD] [OneNAND] fix call to onenand_verify when writing subpages
[linux-2.6] / drivers / mtd / nand / bf5xx_nand.c
1 /* linux/drivers/mtd/nand/bf5xx_nand.c
2  *
3  * Copyright 2006-2007 Analog Devices Inc.
4  *      http://blackfin.uclinux.org/
5  *      Bryan Wu <bryan.wu@analog.com>
6  *
7  * Blackfin BF5xx on-chip NAND flash controler driver
8  *
9  * Derived from drivers/mtd/nand/s3c2410.c
10  * Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk>
11  *
12  * Derived from drivers/mtd/nand/cafe.c
13  * Copyright © 2006 Red Hat, Inc.
14  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
15  *
16  * Changelog:
17  *      12-Jun-2007  Bryan Wu:  Initial version
18  *      18-Jul-2007  Bryan Wu:
19  *              - ECC_HW and ECC_SW supported
20  *              - DMA supported in ECC_HW
21  *              - YAFFS tested as rootfs in both ECC_HW and ECC_SW
22  *
23  * TODO:
24  *      Enable JFFS2 over NAND as rootfs
25  *
26  * This program is free software; you can redistribute it and/or modify
27  * it under the terms of the GNU General Public License as published by
28  * the Free Software Foundation; either version 2 of the License, or
29  * (at your option) any later version.
30  *
31  * This program is distributed in the hope that it will be useful,
32  * but WITHOUT ANY WARRANTY; without even the implied warranty of
33  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
34  * GNU General Public License for more details.
35  *
36  * You should have received a copy of the GNU General Public License
37  * along with this program; if not, write to the Free Software
38  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
39 */
40
41 #include <linux/module.h>
42 #include <linux/types.h>
43 #include <linux/init.h>
44 #include <linux/kernel.h>
45 #include <linux/string.h>
46 #include <linux/ioport.h>
47 #include <linux/platform_device.h>
48 #include <linux/delay.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/err.h>
51 #include <linux/slab.h>
52 #include <linux/io.h>
53 #include <linux/bitops.h>
54
55 #include <linux/mtd/mtd.h>
56 #include <linux/mtd/nand.h>
57 #include <linux/mtd/nand_ecc.h>
58 #include <linux/mtd/partitions.h>
59
60 #include <asm/blackfin.h>
61 #include <asm/dma.h>
62 #include <asm/cacheflush.h>
63 #include <asm/nand.h>
64 #include <asm/portmux.h>
65
66 #define DRV_NAME        "bf5xx-nand"
67 #define DRV_VERSION     "1.2"
68 #define DRV_AUTHOR      "Bryan Wu <bryan.wu@analog.com>"
69 #define DRV_DESC        "BF5xx on-chip NAND FLash Controller Driver"
70
71 #ifdef CONFIG_MTD_NAND_BF5XX_HWECC
72 static int hardware_ecc = 1;
73 #else
74 static int hardware_ecc;
75 #endif
76
77 static unsigned short bfin_nfc_pin_req[] =
78         {P_NAND_CE,
79          P_NAND_RB,
80          P_NAND_D0,
81          P_NAND_D1,
82          P_NAND_D2,
83          P_NAND_D3,
84          P_NAND_D4,
85          P_NAND_D5,
86          P_NAND_D6,
87          P_NAND_D7,
88          P_NAND_WE,
89          P_NAND_RE,
90          P_NAND_CLE,
91          P_NAND_ALE,
92          0};
93
94 /*
95  * Data structures for bf5xx nand flash controller driver
96  */
97
98 /* bf5xx nand info */
99 struct bf5xx_nand_info {
100         /* mtd info */
101         struct nand_hw_control          controller;
102         struct mtd_info                 mtd;
103         struct nand_chip                chip;
104
105         /* platform info */
106         struct bf5xx_nand_platform      *platform;
107
108         /* device info */
109         struct device                   *device;
110
111         /* DMA stuff */
112         struct completion               dma_completion;
113 };
114
115 /*
116  * Conversion functions
117  */
118 static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd)
119 {
120         return container_of(mtd, struct bf5xx_nand_info, mtd);
121 }
122
123 static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev)
124 {
125         return platform_get_drvdata(pdev);
126 }
127
128 static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev)
129 {
130         return pdev->dev.platform_data;
131 }
132
133 /*
134  * struct nand_chip interface function pointers
135  */
136
137 /*
138  * bf5xx_nand_hwcontrol
139  *
140  * Issue command and address cycles to the chip
141  */
142 static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd,
143                                    unsigned int ctrl)
144 {
145         if (cmd == NAND_CMD_NONE)
146                 return;
147
148         while (bfin_read_NFC_STAT() & WB_FULL)
149                 cpu_relax();
150
151         if (ctrl & NAND_CLE)
152                 bfin_write_NFC_CMD(cmd);
153         else
154                 bfin_write_NFC_ADDR(cmd);
155         SSYNC();
156 }
157
158 /*
159  * bf5xx_nand_devready()
160  *
161  * returns 0 if the nand is busy, 1 if it is ready
162  */
163 static int bf5xx_nand_devready(struct mtd_info *mtd)
164 {
165         unsigned short val = bfin_read_NFC_IRQSTAT();
166
167         if ((val & NBUSYIRQ) == NBUSYIRQ)
168                 return 1;
169         else
170                 return 0;
171 }
172
173 /*
174  * ECC functions
175  * These allow the bf5xx to use the controller's ECC
176  * generator block to ECC the data as it passes through
177  */
178
179 /*
180  * ECC error correction function
181  */
182 static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat,
183                                         u_char *read_ecc, u_char *calc_ecc)
184 {
185         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
186         u32 syndrome[5];
187         u32 calced, stored;
188         int i;
189         unsigned short failing_bit, failing_byte;
190         u_char data;
191
192         calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
193         stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
194
195         syndrome[0] = (calced ^ stored);
196
197         /*
198          * syndrome 0: all zero
199          * No error in data
200          * No action
201          */
202         if (!syndrome[0] || !calced || !stored)
203                 return 0;
204
205         /*
206          * sysdrome 0: only one bit is one
207          * ECC data was incorrect
208          * No action
209          */
210         if (hweight32(syndrome[0]) == 1) {
211                 dev_err(info->device, "ECC data was incorrect!\n");
212                 return 1;
213         }
214
215         syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
216         syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
217         syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
218         syndrome[4] = syndrome[2] ^ syndrome[3];
219
220         for (i = 0; i < 5; i++)
221                 dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]);
222
223         dev_info(info->device,
224                 "calced[0x%08x], stored[0x%08x]\n",
225                 calced, stored);
226
227         /*
228          * sysdrome 0: exactly 11 bits are one, each parity
229          * and parity' pair is 1 & 0 or 0 & 1.
230          * 1-bit correctable error
231          * Correct the error
232          */
233         if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
234                 dev_info(info->device,
235                         "1-bit correctable error, correct it.\n");
236                 dev_info(info->device,
237                         "syndrome[1] 0x%08x\n", syndrome[1]);
238
239                 failing_bit = syndrome[1] & 0x7;
240                 failing_byte = syndrome[1] >> 0x3;
241                 data = *(dat + failing_byte);
242                 data = data ^ (0x1 << failing_bit);
243                 *(dat + failing_byte) = data;
244
245                 return 0;
246         }
247
248         /*
249          * sysdrome 0: random data
250          * More than 1-bit error, non-correctable error
251          * Discard data, mark bad block
252          */
253         dev_err(info->device,
254                 "More than 1-bit error, non-correctable error.\n");
255         dev_err(info->device,
256                 "Please discard data, mark bad block\n");
257
258         return 1;
259 }
260
261 static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat,
262                                         u_char *read_ecc, u_char *calc_ecc)
263 {
264         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
265         struct bf5xx_nand_platform *plat = info->platform;
266         unsigned short page_size = (plat->page_size ? 512 : 256);
267         int ret;
268
269         ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
270
271         /* If page size is 512, correct second 256 bytes */
272         if (page_size == 512) {
273                 dat += 256;
274                 read_ecc += 8;
275                 calc_ecc += 8;
276                 ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
277         }
278
279         return ret;
280 }
281
282 static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
283 {
284         return;
285 }
286
287 static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
288                 const u_char *dat, u_char *ecc_code)
289 {
290         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
291         struct bf5xx_nand_platform *plat = info->platform;
292         u16 page_size = (plat->page_size ? 512 : 256);
293         u16 ecc0, ecc1;
294         u32 code[2];
295         u8 *p;
296         int bytes = 3, i;
297
298         /* first 4 bytes ECC code for 256 page size */
299         ecc0 = bfin_read_NFC_ECC0();
300         ecc1 = bfin_read_NFC_ECC1();
301
302         code[0] = (ecc0 & 0x3FF) | ((ecc1 & 0x3FF) << 11);
303
304         dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]);
305
306         /* second 4 bytes ECC code for 512 page size */
307         if (page_size == 512) {
308                 ecc0 = bfin_read_NFC_ECC2();
309                 ecc1 = bfin_read_NFC_ECC3();
310                 code[1] = (ecc0 & 0x3FF) | ((ecc1 & 0x3FF) << 11);
311                 bytes = 6;
312                 dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]);
313         }
314
315         p = (u8 *)code;
316         for (i = 0; i < bytes; i++)
317                 ecc_code[i] = p[i];
318
319         return 0;
320 }
321
322 /*
323  * PIO mode for buffer writing and reading
324  */
325 static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
326 {
327         int i;
328         unsigned short val;
329
330         /*
331          * Data reads are requested by first writing to NFC_DATA_RD
332          * and then reading back from NFC_READ.
333          */
334         for (i = 0; i < len; i++) {
335                 while (bfin_read_NFC_STAT() & WB_FULL)
336                         cpu_relax();
337
338                 /* Contents do not matter */
339                 bfin_write_NFC_DATA_RD(0x0000);
340                 SSYNC();
341
342                 while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY)
343                         cpu_relax();
344
345                 buf[i] = bfin_read_NFC_READ();
346
347                 val = bfin_read_NFC_IRQSTAT();
348                 val |= RD_RDY;
349                 bfin_write_NFC_IRQSTAT(val);
350                 SSYNC();
351         }
352 }
353
354 static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd)
355 {
356         uint8_t val;
357
358         bf5xx_nand_read_buf(mtd, &val, 1);
359
360         return val;
361 }
362
363 static void bf5xx_nand_write_buf(struct mtd_info *mtd,
364                                 const uint8_t *buf, int len)
365 {
366         int i;
367
368         for (i = 0; i < len; i++) {
369                 while (bfin_read_NFC_STAT() & WB_FULL)
370                         cpu_relax();
371
372                 bfin_write_NFC_DATA_WR(buf[i]);
373                 SSYNC();
374         }
375 }
376
377 static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
378 {
379         int i;
380         u16 *p = (u16 *) buf;
381         len >>= 1;
382
383         /*
384          * Data reads are requested by first writing to NFC_DATA_RD
385          * and then reading back from NFC_READ.
386          */
387         bfin_write_NFC_DATA_RD(0x5555);
388
389         SSYNC();
390
391         for (i = 0; i < len; i++)
392                 p[i] = bfin_read_NFC_READ();
393 }
394
395 static void bf5xx_nand_write_buf16(struct mtd_info *mtd,
396                                 const uint8_t *buf, int len)
397 {
398         int i;
399         u16 *p = (u16 *) buf;
400         len >>= 1;
401
402         for (i = 0; i < len; i++)
403                 bfin_write_NFC_DATA_WR(p[i]);
404
405         SSYNC();
406 }
407
408 /*
409  * DMA functions for buffer writing and reading
410  */
411 static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id)
412 {
413         struct bf5xx_nand_info *info = dev_id;
414
415         clear_dma_irqstat(CH_NFC);
416         disable_dma(CH_NFC);
417         complete(&info->dma_completion);
418
419         return IRQ_HANDLED;
420 }
421
422 static int bf5xx_nand_dma_rw(struct mtd_info *mtd,
423                                 uint8_t *buf, int is_read)
424 {
425         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
426         struct bf5xx_nand_platform *plat = info->platform;
427         unsigned short page_size = (plat->page_size ? 512 : 256);
428         unsigned short val;
429
430         dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n",
431                         mtd, buf, is_read);
432
433         /*
434          * Before starting a dma transfer, be sure to invalidate/flush
435          * the cache over the address range of your DMA buffer to
436          * prevent cache coherency problems. Otherwise very subtle bugs
437          * can be introduced to your driver.
438          */
439         if (is_read)
440                 invalidate_dcache_range((unsigned int)buf,
441                                 (unsigned int)(buf + page_size));
442         else
443                 flush_dcache_range((unsigned int)buf,
444                                 (unsigned int)(buf + page_size));
445
446         /*
447          * This register must be written before each page is
448          * transferred to generate the correct ECC register
449          * values.
450          */
451         bfin_write_NFC_RST(0x1);
452         SSYNC();
453
454         disable_dma(CH_NFC);
455         clear_dma_irqstat(CH_NFC);
456
457         /* setup DMA register with Blackfin DMA API */
458         set_dma_config(CH_NFC, 0x0);
459         set_dma_start_addr(CH_NFC, (unsigned long) buf);
460         set_dma_x_count(CH_NFC, (page_size >> 2));
461         set_dma_x_modify(CH_NFC, 4);
462
463         /* setup write or read operation */
464         val = DI_EN | WDSIZE_32;
465         if (is_read)
466                 val |= WNR;
467         set_dma_config(CH_NFC, val);
468         enable_dma(CH_NFC);
469
470         /* Start PAGE read/write operation */
471         if (is_read)
472                 bfin_write_NFC_PGCTL(0x1);
473         else
474                 bfin_write_NFC_PGCTL(0x2);
475         wait_for_completion(&info->dma_completion);
476
477         return 0;
478 }
479
480 static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd,
481                                         uint8_t *buf, int len)
482 {
483         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
484         struct bf5xx_nand_platform *plat = info->platform;
485         unsigned short page_size = (plat->page_size ? 512 : 256);
486
487         dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len);
488
489         if (len == page_size)
490                 bf5xx_nand_dma_rw(mtd, buf, 1);
491         else
492                 bf5xx_nand_read_buf(mtd, buf, len);
493 }
494
495 static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
496                                 const uint8_t *buf, int len)
497 {
498         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
499         struct bf5xx_nand_platform *plat = info->platform;
500         unsigned short page_size = (plat->page_size ? 512 : 256);
501
502         dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len);
503
504         if (len == page_size)
505                 bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0);
506         else
507                 bf5xx_nand_write_buf(mtd, buf, len);
508 }
509
510 /*
511  * System initialization functions
512  */
513
514 static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info)
515 {
516         int ret;
517         unsigned short val;
518
519         /* Do not use dma */
520         if (!hardware_ecc)
521                 return 0;
522
523         init_completion(&info->dma_completion);
524
525 #ifdef CONFIG_BF54x
526         /* Setup DMAC1 channel mux for NFC which shared with SDH */
527         val = bfin_read_DMAC1_PERIMUX();
528         val &= 0xFFFE;
529         bfin_write_DMAC1_PERIMUX(val);
530         SSYNC();
531 #endif
532         /* Request NFC DMA channel */
533         ret = request_dma(CH_NFC, "BF5XX NFC driver");
534         if (ret < 0) {
535                 dev_err(info->device, " unable to get DMA channel\n");
536                 return ret;
537         }
538
539         set_dma_callback(CH_NFC, (void *) bf5xx_nand_dma_irq, (void *) info);
540
541         /* Turn off the DMA channel first */
542         disable_dma(CH_NFC);
543         return 0;
544 }
545
546 /*
547  * BF5XX NFC hardware initialization
548  *  - pin mux setup
549  *  - clear interrupt status
550  */
551 static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info)
552 {
553         int err = 0;
554         unsigned short val;
555         struct bf5xx_nand_platform *plat = info->platform;
556
557         /* setup NFC_CTL register */
558         dev_info(info->device,
559                 "page_size=%d, data_width=%d, wr_dly=%d, rd_dly=%d\n",
560                 (plat->page_size ? 512 : 256),
561                 (plat->data_width ? 16 : 8),
562                 plat->wr_dly, plat->rd_dly);
563
564         val = (plat->page_size << NFC_PG_SIZE_OFFSET) |
565                 (plat->data_width << NFC_NWIDTH_OFFSET) |
566                 (plat->rd_dly << NFC_RDDLY_OFFSET) |
567                 (plat->rd_dly << NFC_WRDLY_OFFSET);
568         dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val);
569
570         bfin_write_NFC_CTL(val);
571         SSYNC();
572
573         /* clear interrupt status */
574         bfin_write_NFC_IRQMASK(0x0);
575         SSYNC();
576         val = bfin_read_NFC_IRQSTAT();
577         bfin_write_NFC_IRQSTAT(val);
578         SSYNC();
579
580         if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) {
581                 printk(KERN_ERR DRV_NAME
582                 ": Requesting Peripherals failed\n");
583                 return -EFAULT;
584         }
585
586         /* DMA initialization  */
587         if (bf5xx_nand_dma_init(info))
588                 err = -ENXIO;
589
590         return err;
591 }
592
593 /*
594  * Device management interface
595  */
596 static int bf5xx_nand_add_partition(struct bf5xx_nand_info *info)
597 {
598         struct mtd_info *mtd = &info->mtd;
599
600 #ifdef CONFIG_MTD_PARTITIONS
601         struct mtd_partition *parts = info->platform->partitions;
602         int nr = info->platform->nr_partitions;
603
604         return add_mtd_partitions(mtd, parts, nr);
605 #else
606         return add_mtd_device(mtd);
607 #endif
608 }
609
610 static int bf5xx_nand_remove(struct platform_device *pdev)
611 {
612         struct bf5xx_nand_info *info = to_nand_info(pdev);
613         struct mtd_info *mtd = NULL;
614
615         platform_set_drvdata(pdev, NULL);
616
617         /* first thing we need to do is release all our mtds
618          * and their partitions, then go through freeing the
619          * resources used
620          */
621         mtd = &info->mtd;
622         if (mtd) {
623                 nand_release(mtd);
624                 kfree(mtd);
625         }
626
627         peripheral_free_list(bfin_nfc_pin_req);
628
629         /* free the common resources */
630         kfree(info);
631
632         return 0;
633 }
634
635 /*
636  * bf5xx_nand_probe
637  *
638  * called by device layer when it finds a device matching
639  * one our driver can handled. This code checks to see if
640  * it can allocate all necessary resources then calls the
641  * nand layer to look for devices
642  */
643 static int bf5xx_nand_probe(struct platform_device *pdev)
644 {
645         struct bf5xx_nand_platform *plat = to_nand_plat(pdev);
646         struct bf5xx_nand_info *info = NULL;
647         struct nand_chip *chip = NULL;
648         struct mtd_info *mtd = NULL;
649         int err = 0;
650
651         dev_dbg(&pdev->dev, "(%p)\n", pdev);
652
653         if (!plat) {
654                 dev_err(&pdev->dev, "no platform specific information\n");
655                 goto exit_error;
656         }
657
658         info = kzalloc(sizeof(*info), GFP_KERNEL);
659         if (info == NULL) {
660                 dev_err(&pdev->dev, "no memory for flash info\n");
661                 err = -ENOMEM;
662                 goto exit_error;
663         }
664
665         platform_set_drvdata(pdev, info);
666
667         spin_lock_init(&info->controller.lock);
668         init_waitqueue_head(&info->controller.wq);
669
670         info->device     = &pdev->dev;
671         info->platform   = plat;
672
673         /* initialise chip data struct */
674         chip = &info->chip;
675
676         if (plat->data_width)
677                 chip->options |= NAND_BUSWIDTH_16;
678
679         chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN;
680
681         chip->read_buf = (plat->data_width) ?
682                 bf5xx_nand_read_buf16 : bf5xx_nand_read_buf;
683         chip->write_buf = (plat->data_width) ?
684                 bf5xx_nand_write_buf16 : bf5xx_nand_write_buf;
685
686         chip->read_byte    = bf5xx_nand_read_byte;
687
688         chip->cmd_ctrl     = bf5xx_nand_hwcontrol;
689         chip->dev_ready    = bf5xx_nand_devready;
690
691         chip->priv         = &info->mtd;
692         chip->controller   = &info->controller;
693
694         chip->IO_ADDR_R    = (void __iomem *) NFC_READ;
695         chip->IO_ADDR_W    = (void __iomem *) NFC_DATA_WR;
696
697         chip->chip_delay   = 0;
698
699         /* initialise mtd info data struct */
700         mtd             = &info->mtd;
701         mtd->priv       = chip;
702         mtd->owner      = THIS_MODULE;
703
704         /* initialise the hardware */
705         err = bf5xx_nand_hw_init(info);
706         if (err != 0)
707                 goto exit_error;
708
709         /* setup hardware ECC data struct */
710         if (hardware_ecc) {
711                 if (plat->page_size == NFC_PG_SIZE_256) {
712                         chip->ecc.bytes = 3;
713                         chip->ecc.size = 256;
714                 } else if (plat->page_size == NFC_PG_SIZE_512) {
715                         chip->ecc.bytes = 6;
716                         chip->ecc.size = 512;
717                 }
718
719                 chip->read_buf      = bf5xx_nand_dma_read_buf;
720                 chip->write_buf     = bf5xx_nand_dma_write_buf;
721                 chip->ecc.calculate = bf5xx_nand_calculate_ecc;
722                 chip->ecc.correct   = bf5xx_nand_correct_data;
723                 chip->ecc.mode      = NAND_ECC_HW;
724                 chip->ecc.hwctl     = bf5xx_nand_enable_hwecc;
725         } else {
726                 chip->ecc.mode      = NAND_ECC_SOFT;
727         }
728
729         /* scan hardware nand chip and setup mtd info data struct */
730         if (nand_scan(mtd, 1)) {
731                 err = -ENXIO;
732                 goto exit_error;
733         }
734
735         /* add NAND partition */
736         bf5xx_nand_add_partition(info);
737
738         dev_dbg(&pdev->dev, "initialised ok\n");
739         return 0;
740
741 exit_error:
742         bf5xx_nand_remove(pdev);
743
744         if (err == 0)
745                 err = -EINVAL;
746         return err;
747 }
748
749 /* PM Support */
750 #ifdef CONFIG_PM
751
752 static int bf5xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
753 {
754         struct bf5xx_nand_info *info = platform_get_drvdata(dev);
755
756         return 0;
757 }
758
759 static int bf5xx_nand_resume(struct platform_device *dev)
760 {
761         struct bf5xx_nand_info *info = platform_get_drvdata(dev);
762
763         if (info)
764                 bf5xx_nand_hw_init(info);
765
766         return 0;
767 }
768
769 #else
770 #define bf5xx_nand_suspend NULL
771 #define bf5xx_nand_resume NULL
772 #endif
773
774 /* driver device registration */
775 static struct platform_driver bf5xx_nand_driver = {
776         .probe          = bf5xx_nand_probe,
777         .remove         = bf5xx_nand_remove,
778         .suspend        = bf5xx_nand_suspend,
779         .resume         = bf5xx_nand_resume,
780         .driver         = {
781                 .name   = DRV_NAME,
782                 .owner  = THIS_MODULE,
783         },
784 };
785
786 static int __init bf5xx_nand_init(void)
787 {
788         printk(KERN_INFO "%s, Version %s (c) 2007 Analog Devices, Inc.\n",
789                 DRV_DESC, DRV_VERSION);
790
791         return platform_driver_register(&bf5xx_nand_driver);
792 }
793
794 static void __exit bf5xx_nand_exit(void)
795 {
796         platform_driver_unregister(&bf5xx_nand_driver);
797 }
798
799 module_init(bf5xx_nand_init);
800 module_exit(bf5xx_nand_exit);
801
802 MODULE_LICENSE("GPL");
803 MODULE_AUTHOR(DRV_AUTHOR);
804 MODULE_DESCRIPTION(DRV_DESC);