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   1 /*
   2  *  Driver for the IDT RC32434 (Korina) on-chip ethernet controller.
   3  *
   4  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
   5  *  Copyright 2006 Felix Fietkau <nbd@openwrt.org>
   6  *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  *
  28  *  Writing to a DMA status register:
  29  *
  30  *  When writing to the status register, you should mask the bit you have
  31  *  been testing the status register with. Both Tx and Rx DMA registers
  32  *  should stick to this procedure.
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/kernel.h>
  37 #include <linux/moduleparam.h>
  38 #include <linux/sched.h>
  39 #include <linux/ctype.h>
  40 #include <linux/types.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/init.h>
  43 #include <linux/ioport.h>
  44 #include <linux/in.h>
  45 #include <linux/slab.h>
  46 #include <linux/string.h>
  47 #include <linux/delay.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/etherdevice.h>
  50 #include <linux/skbuff.h>
  51 #include <linux/errno.h>
  52 #include <linux/platform_device.h>
  53 #include <linux/mii.h>
  54 #include <linux/ethtool.h>
  55 #include <linux/crc32.h>
  56
  57 #include <asm/bootinfo.h>
  58 #include <asm/system.h>
  59 #include <asm/bitops.h>
  60 #include <asm/pgtable.h>
  61 #include <asm/segment.h>
  62 #include <asm/io.h>
  63 #include <asm/dma.h>
  64
  65 #include <asm/mach-rc32434/rb.h>
  66 #include <asm/mach-rc32434/rc32434.h>
  67 #include <asm/mach-rc32434/eth.h>
  68 #include <asm/mach-rc32434/dma_v.h>
  69
  70 #define DRV_NAME        "korina"
  71 #define DRV_VERSION     "0.10"
  72 #define DRV_RELDATE     "04Mar2008"
  73
  74 #define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
  75                                    ((dev)->dev_addr[1]))
  76 #define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
  77                                    ((dev)->dev_addr[3] << 16) | \
  78                                    ((dev)->dev_addr[4] << 8)  | \
  79                                    ((dev)->dev_addr[5]))
  80
  81 #define MII_CLOCK 1250000       /* no more than 2.5MHz */
  82
  83 /* the following must be powers of two */
  84 #define KORINA_NUM_RDS  64  /* number of receive descriptors */
  85 #define KORINA_NUM_TDS  64  /* number of transmit descriptors */
  86
  87 #define KORINA_RBSIZE   536 /* size of one resource buffer = Ether MTU */
  88 #define KORINA_RDS_MASK (KORINA_NUM_RDS - 1)
  89 #define KORINA_TDS_MASK (KORINA_NUM_TDS - 1)
  90 #define RD_RING_SIZE    (KORINA_NUM_RDS * sizeof(struct dma_desc))
  91 #define TD_RING_SIZE    (KORINA_NUM_TDS * sizeof(struct dma_desc))
  92
  93 #define TX_TIMEOUT      (6000 * HZ / 1000)
  94
  95 enum chain_status { desc_filled, desc_empty };
  96 #define IS_DMA_FINISHED(X)   (((X) & (DMA_DESC_FINI)) != 0)
  97 #define IS_DMA_DONE(X)   (((X) & (DMA_DESC_DONE)) != 0)
  98 #define RCVPKT_LENGTH(X)     (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT)
  99
 100 /* Information that need to be kept for each board. */
 101 struct korina_private {
 102         struct eth_regs *eth_regs;
 103         struct dma_reg *rx_dma_regs;
 104         struct dma_reg *tx_dma_regs;
 105         struct dma_desc *td_ring; /* transmit descriptor ring */
 106         struct dma_desc *rd_ring; /* receive descriptor ring  */
 107
 108         struct sk_buff *tx_skb[KORINA_NUM_TDS];
 109         struct sk_buff *rx_skb[KORINA_NUM_RDS];
 110
 111         int rx_next_done;
 112         int rx_chain_head;
 113         int rx_chain_tail;
 114         enum chain_status rx_chain_status;
 115
 116         int tx_next_done;
 117         int tx_chain_head;
 118         int tx_chain_tail;
 119         enum chain_status tx_chain_status;
 120         int tx_count;
 121         int tx_full;
 122
 123         int rx_irq;
 124         int tx_irq;
 125         int ovr_irq;
 126         int und_irq;
 127
 128         spinlock_t lock;        /* NIC xmit lock */
 129
 130         int dma_halt_cnt;
 131         int dma_run_cnt;
 132         struct napi_struct napi;
 133         struct mii_if_info mii_if;
 134         struct net_device *dev;
 135         int phy_addr;
 136 };
 137
 138 extern unsigned int idt_cpu_freq;
 139
 140 static inline void korina_start_dma(struct dma_reg *ch, u32 dma_addr)
 141 {
 142         writel(0, &ch->dmandptr);
 143         writel(dma_addr, &ch->dmadptr);
 144 }
 145
 146 static inline void korina_abort_dma(struct net_device *dev,
 147                                         struct dma_reg *ch)
 148 {
 149        if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
 150                writel(0x10, &ch->dmac);
 151
 152                while (!(readl(&ch->dmas) & DMA_STAT_HALT))
 153                        dev->trans_start = jiffies;
 154
 155                writel(0, &ch->dmas);
 156        }
 157
 158        writel(0, &ch->dmadptr);
 159        writel(0, &ch->dmandptr);
 160 }
 161
 162 static inline void korina_chain_dma(struct dma_reg *ch, u32 dma_addr)
 163 {
 164         writel(dma_addr, &ch->dmandptr);
 165 }
 166
 167 static void korina_abort_tx(struct net_device *dev)
 168 {
 169         struct korina_private *lp = netdev_priv(dev);
 170
 171         korina_abort_dma(dev, lp->tx_dma_regs);
 172 }
 173
 174 static void korina_abort_rx(struct net_device *dev)
 175 {
 176         struct korina_private *lp = netdev_priv(dev);
 177
 178         korina_abort_dma(dev, lp->rx_dma_regs);
 179 }
 180
 181 static void korina_start_rx(struct korina_private *lp,
 182                                         struct dma_desc *rd)
 183 {
 184         korina_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
 185 }
 186
 187 static void korina_chain_rx(struct korina_private *lp,
 188                                         struct dma_desc *rd)
 189 {
 190         korina_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
 191 }
 192
 193 /* transmit packet */
 194 static int korina_send_packet(struct sk_buff *skb, struct net_device *dev)
 195 {
 196         struct korina_private *lp = netdev_priv(dev);
 197         unsigned long flags;
 198         u32 length;
 199         u32 chain_index;
 200         struct dma_desc *td;
 201
 202         spin_lock_irqsave(&lp->lock, flags);
 203
 204         td = &lp->td_ring[lp->tx_chain_tail];
 205
 206         /* stop queue when full, drop pkts if queue already full */
 207         if (lp->tx_count >= (KORINA_NUM_TDS - 2)) {
 208                 lp->tx_full = 1;
 209
 210                 if (lp->tx_count == (KORINA_NUM_TDS - 2))
 211                         netif_stop_queue(dev);
 212                 else {
 213                         dev->stats.tx_dropped++;
 214                         dev_kfree_skb_any(skb);
 215                         spin_unlock_irqrestore(&lp->lock, flags);
 216
 217                         return NETDEV_TX_BUSY;
 218                 }
 219         }
 220
 221         lp->tx_count++;
 222
 223         lp->tx_skb[lp->tx_chain_tail] = skb;
 224
 225         length = skb->len;
 226         dma_cache_wback((u32)skb->data, skb->len);
 227
 228         /* Setup the transmit descriptor. */
 229         dma_cache_inv((u32) td, sizeof(*td));
 230         td->ca = CPHYSADDR(skb->data);
 231         chain_index = (lp->tx_chain_tail - 1) &
 232                         KORINA_TDS_MASK;
 233
 234         if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
 235                 if (lp->tx_chain_status == desc_empty) {
 236                         /* Update tail */
 237                         td->control = DMA_COUNT(length) |
 238                                         DMA_DESC_COF | DMA_DESC_IOF;
 239                         /* Move tail */
 240                         lp->tx_chain_tail = chain_index;
 241                         /* Write to NDPTR */
 242                         writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
 243                                         &lp->tx_dma_regs->dmandptr);
 244                         /* Move head to tail */
 245                         lp->tx_chain_head = lp->tx_chain_tail;
 246                 } else {
 247                         /* Update tail */
 248                         td->control = DMA_COUNT(length) |
 249                                         DMA_DESC_COF | DMA_DESC_IOF;
 250                         /* Link to prev */
 251                         lp->td_ring[chain_index].control &=
 252                                         ~DMA_DESC_COF;
 253                         /* Link to prev */
 254                         lp->td_ring[chain_index].link =  CPHYSADDR(td);
 255                         /* Move tail */
 256                         lp->tx_chain_tail = chain_index;
 257                         /* Write to NDPTR */
 258                         writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
 259                                         &(lp->tx_dma_regs->dmandptr));
 260                         /* Move head to tail */
 261                         lp->tx_chain_head = lp->tx_chain_tail;
 262                         lp->tx_chain_status = desc_empty;
 263                 }
 264         } else {
 265                 if (lp->tx_chain_status == desc_empty) {
 266                         /* Update tail */
 267                         td->control = DMA_COUNT(length) |
 268                                         DMA_DESC_COF | DMA_DESC_IOF;
 269                         /* Move tail */
 270                         lp->tx_chain_tail = chain_index;
 271                         lp->tx_chain_status = desc_filled;
 272                         netif_stop_queue(dev);
 273                 } else {
 274                         /* Update tail */
 275                         td->control = DMA_COUNT(length) |
 276                                         DMA_DESC_COF | DMA_DESC_IOF;
 277                         lp->td_ring[chain_index].control &=
 278                                         ~DMA_DESC_COF;
 279                         lp->td_ring[chain_index].link =  CPHYSADDR(td);
 280                         lp->tx_chain_tail = chain_index;
 281                 }
 282         }
 283         dma_cache_wback((u32) td, sizeof(*td));
 284
 285         dev->trans_start = jiffies;
 286         spin_unlock_irqrestore(&lp->lock, flags);
 287
 288         return NETDEV_TX_OK;
 289 }
 290
 291 static int mdio_read(struct net_device *dev, int mii_id, int reg)
 292 {
 293         struct korina_private *lp = netdev_priv(dev);
 294         int ret;
 295
 296         mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
 297
 298         writel(0, &lp->eth_regs->miimcfg);
 299         writel(0, &lp->eth_regs->miimcmd);
 300         writel(mii_id | reg, &lp->eth_regs->miimaddr);
 301         writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
 302
 303         ret = (int)(readl(&lp->eth_regs->miimrdd));
 304         return ret;
 305 }
 306
 307 static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
 308 {
 309         struct korina_private *lp = netdev_priv(dev);
 310
 311         mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
 312
 313         writel(0, &lp->eth_regs->miimcfg);
 314         writel(1, &lp->eth_regs->miimcmd);
 315         writel(mii_id | reg, &lp->eth_regs->miimaddr);
 316         writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
 317         writel(val, &lp->eth_regs->miimwtd);
 318 }
 319
 320 /* Ethernet Rx DMA interrupt */
 321 static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id)
 322 {
 323         struct net_device *dev = dev_id;
 324         struct korina_private *lp = netdev_priv(dev);
 325         u32 dmas, dmasm;
 326         irqreturn_t retval;
 327
 328         dmas = readl(&lp->rx_dma_regs->dmas);
 329         if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) {
 330                 netif_rx_schedule_prep(&lp->napi);
 331
 332                 dmasm = readl(&lp->rx_dma_regs->dmasm);
 333                 writel(dmasm | (DMA_STAT_DONE |
 334                                 DMA_STAT_HALT | DMA_STAT_ERR),
 335                                 &lp->rx_dma_regs->dmasm);
 336
 337                 if (dmas & DMA_STAT_ERR)
 338                         printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name);
 339
 340                 retval = IRQ_HANDLED;
 341         } else
 342                 retval = IRQ_NONE;
 343
 344         return retval;
 345 }
 346
 347 static int korina_rx(struct net_device *dev, int limit)
 348 {
 349         struct korina_private *lp = netdev_priv(dev);
 350         struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done];
 351         struct sk_buff *skb, *skb_new;
 352         u8 *pkt_buf;
 353         u32 devcs, pkt_len, dmas, rx_free_desc;
 354         int count;
 355
 356         dma_cache_inv((u32)rd, sizeof(*rd));
 357
 358         for (count = 0; count < limit; count++) {
 359
 360                 devcs = rd->devcs;
 361
 362                 /* Update statistics counters */
 363                 if (devcs & ETH_RX_CRC)
 364                         dev->stats.rx_crc_errors++;
 365                 if (devcs & ETH_RX_LOR)
 366                         dev->stats.rx_length_errors++;
 367                 if (devcs & ETH_RX_LE)
 368                         dev->stats.rx_length_errors++;
 369                 if (devcs & ETH_RX_OVR)
 370                         dev->stats.rx_over_errors++;
 371                 if (devcs & ETH_RX_CV)
 372                         dev->stats.rx_frame_errors++;
 373                 if (devcs & ETH_RX_CES)
 374                         dev->stats.rx_length_errors++;
 375                 if (devcs & ETH_RX_MP)
 376                         dev->stats.multicast++;
 377
 378                 if ((devcs & ETH_RX_LD) != ETH_RX_LD) {
 379                         /* check that this is a whole packet
 380                          * WARNING: DMA_FD bit incorrectly set
 381                          * in Rc32434 (errata ref #077) */
 382                         dev->stats.rx_errors++;
 383                         dev->stats.rx_dropped++;
 384                 }
 385
 386                 while ((rx_free_desc = KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
 387                         /* init the var. used for the later
 388                          * operations within the while loop */
 389                         skb_new = NULL;
 390                         pkt_len = RCVPKT_LENGTH(devcs);
 391                         skb = lp->rx_skb[lp->rx_next_done];
 392
 393                         if ((devcs & ETH_RX_ROK)) {
 394                                 /* must be the (first and) last
 395                                  * descriptor then */
 396                                 pkt_buf = (u8 *)lp->rx_skb[lp->rx_next_done]->data;
 397
 398                                 /* invalidate the cache */
 399                                 dma_cache_inv((unsigned long)pkt_buf, pkt_len - 4);
 400
 401                                 /* Malloc up new buffer. */
 402                                 skb_new = netdev_alloc_skb(dev, KORINA_RBSIZE + 2);
 403
 404                                 if (!skb_new)
 405                                         break;
 406                                 /* Do not count the CRC */
 407                                 skb_put(skb, pkt_len - 4);
 408                                 skb->protocol = eth_type_trans(skb, dev);
 409
 410                                 /* Pass the packet to upper layers */
 411                                 netif_receive_skb(skb);
 412                                 dev->stats.rx_packets++;
 413                                 dev->stats.rx_bytes += pkt_len;
 414
 415                                 /* Update the mcast stats */
 416                                 if (devcs & ETH_RX_MP)
 417                                         dev->stats.multicast++;
 418
 419                                 lp->rx_skb[lp->rx_next_done] = skb_new;
 420                         }
 421
 422                         rd->devcs = 0;
 423
 424                         /* Restore descriptor's curr_addr */
 425                         if (skb_new)
 426                                 rd->ca = CPHYSADDR(skb_new->data);
 427                         else
 428                                 rd->ca = CPHYSADDR(skb->data);
 429
 430                         rd->control = DMA_COUNT(KORINA_RBSIZE) |
 431                                 DMA_DESC_COD | DMA_DESC_IOD;
 432                         lp->rd_ring[(lp->rx_next_done - 1) &
 433                                 KORINA_RDS_MASK].control &=
 434                                 ~DMA_DESC_COD;
 435
 436                         lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK;
 437                         dma_cache_wback((u32)rd, sizeof(*rd));
 438                         rd = &lp->rd_ring[lp->rx_next_done];
 439                         writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas);
 440                 }
 441         }
 442
 443         dmas = readl(&lp->rx_dma_regs->dmas);
 444
 445         if (dmas & DMA_STAT_HALT) {
 446                 writel(~(DMA_STAT_HALT | DMA_STAT_ERR),
 447                                 &lp->rx_dma_regs->dmas);
 448
 449                 lp->dma_halt_cnt++;
 450                 rd->devcs = 0;
 451                 skb = lp->rx_skb[lp->rx_next_done];
 452                 rd->ca = CPHYSADDR(skb->data);
 453                 dma_cache_wback((u32)rd, sizeof(*rd));
 454                 korina_chain_rx(lp, rd);
 455         }
 456
 457         return count;
 458 }
 459
 460 static int korina_poll(struct napi_struct *napi, int budget)
 461 {
 462         struct korina_private *lp =
 463                 container_of(napi, struct korina_private, napi);
 464         struct net_device *dev = lp->dev;
 465         int work_done;
 466
 467         work_done = korina_rx(dev, budget);
 468         if (work_done < budget) {
 469                 netif_rx_complete(napi);
 470
 471                 writel(readl(&lp->rx_dma_regs->dmasm) &
 472                         ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
 473                         &lp->rx_dma_regs->dmasm);
 474         }
 475         return work_done;
 476 }
 477
 478 /*
 479  * Set or clear the multicast filter for this adaptor.
 480  */
 481 static void korina_multicast_list(struct net_device *dev)
 482 {
 483         struct korina_private *lp = netdev_priv(dev);
 484         unsigned long flags;
 485         struct dev_mc_list *dmi = dev->mc_list;
 486         u32 recognise = ETH_ARC_AB;     /* always accept broadcasts */
 487         int i;
 488
 489         /* Set promiscuous mode */
 490         if (dev->flags & IFF_PROMISC)
 491                 recognise |= ETH_ARC_PRO;
 492
 493         else if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 4))
 494                 /* All multicast and broadcast */
 495                 recognise |= ETH_ARC_AM;
 496
 497         /* Build the hash table */
 498         if (dev->mc_count > 4) {
 499                 u16 hash_table[4];
 500                 u32 crc;
 501
 502                 for (i = 0; i < 4; i++)
 503                         hash_table[i] = 0;
 504
 505                 for (i = 0; i < dev->mc_count; i++) {
 506                         char *addrs = dmi->dmi_addr;
 507
 508                         dmi = dmi->next;
 509
 510                         if (!(*addrs & 1))
 511                                 continue;
 512
 513                         crc = ether_crc_le(6, addrs);
 514                         crc >>= 26;
 515                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
 516                 }
 517                 /* Accept filtered multicast */
 518                 recognise |= ETH_ARC_AFM;
 519
 520                 /* Fill the MAC hash tables with their values */
 521                 writel((u32)(hash_table[1] << 16 | hash_table[0]),
 522                                         &lp->eth_regs->ethhash0);
 523                 writel((u32)(hash_table[3] << 16 | hash_table[2]),
 524                                         &lp->eth_regs->ethhash1);
 525         }
 526
 527         spin_lock_irqsave(&lp->lock, flags);
 528         writel(recognise, &lp->eth_regs->etharc);
 529         spin_unlock_irqrestore(&lp->lock, flags);
 530 }
 531
 532 static void korina_tx(struct net_device *dev)
 533 {
 534         struct korina_private *lp = netdev_priv(dev);
 535         struct dma_desc *td = &lp->td_ring[lp->tx_next_done];
 536         u32 devcs;
 537         u32 dmas;
 538
 539         spin_lock(&lp->lock);
 540
 541         /* Process all desc that are done */
 542         while (IS_DMA_FINISHED(td->control)) {
 543                 if (lp->tx_full == 1) {
 544                         netif_wake_queue(dev);
 545                         lp->tx_full = 0;
 546                 }
 547
 548                 devcs = lp->td_ring[lp->tx_next_done].devcs;
 549                 if ((devcs & (ETH_TX_FD | ETH_TX_LD)) !=
 550                                 (ETH_TX_FD | ETH_TX_LD)) {
 551                         dev->stats.tx_errors++;
 552                         dev->stats.tx_dropped++;
 553
 554                         /* Should never happen */
 555                         printk(KERN_ERR DRV_NAME "%s: split tx ignored\n",
 556                                                         dev->name);
 557                 } else if (devcs & ETH_TX_TOK) {
 558                         dev->stats.tx_packets++;
 559                         dev->stats.tx_bytes +=
 560                                         lp->tx_skb[lp->tx_next_done]->len;
 561                 } else {
 562                         dev->stats.tx_errors++;
 563                         dev->stats.tx_dropped++;
 564
 565                         /* Underflow */
 566                         if (devcs & ETH_TX_UND)
 567                                 dev->stats.tx_fifo_errors++;
 568
 569                         /* Oversized frame */
 570                         if (devcs & ETH_TX_OF)
 571                                 dev->stats.tx_aborted_errors++;
 572
 573                         /* Excessive deferrals */
 574                         if (devcs & ETH_TX_ED)
 575                                 dev->stats.tx_carrier_errors++;
 576
 577                         /* Collisions: medium busy */
 578                         if (devcs & ETH_TX_EC)
 579                                 dev->stats.collisions++;
 580
 581                         /* Late collision */
 582                         if (devcs & ETH_TX_LC)
 583                                 dev->stats.tx_window_errors++;
 584                 }
 585
 586                 /* We must always free the original skb */
 587                 if (lp->tx_skb[lp->tx_next_done]) {
 588                         dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
 589                         lp->tx_skb[lp->tx_next_done] = NULL;
 590                 }
 591
 592                 lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF;
 593                 lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD;
 594                 lp->td_ring[lp->tx_next_done].link = 0;
 595                 lp->td_ring[lp->tx_next_done].ca = 0;
 596                 lp->tx_count--;
 597
 598                 /* Go on to next transmission */
 599                 lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK;
 600                 td = &lp->td_ring[lp->tx_next_done];
 601
 602         }
 603
 604         /* Clear the DMA status register */
 605         dmas = readl(&lp->tx_dma_regs->dmas);
 606         writel(~dmas, &lp->tx_dma_regs->dmas);
 607
 608         writel(readl(&lp->tx_dma_regs->dmasm) &
 609                         ~(DMA_STAT_FINI | DMA_STAT_ERR),
 610                         &lp->tx_dma_regs->dmasm);
 611
 612         spin_unlock(&lp->lock);
 613 }
 614
 615 static irqreturn_t
 616 korina_tx_dma_interrupt(int irq, void *dev_id)
 617 {
 618         struct net_device *dev = dev_id;
 619         struct korina_private *lp = netdev_priv(dev);
 620         u32 dmas, dmasm;
 621         irqreturn_t retval;
 622
 623         dmas = readl(&lp->tx_dma_regs->dmas);
 624
 625         if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) {
 626                 korina_tx(dev);
 627
 628                 dmasm = readl(&lp->tx_dma_regs->dmasm);
 629                 writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR),
 630                                 &lp->tx_dma_regs->dmasm);
 631
 632                 if (lp->tx_chain_status == desc_filled &&
 633                         (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
 634                         writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
 635                                 &(lp->tx_dma_regs->dmandptr));
 636                         lp->tx_chain_status = desc_empty;
 637                         lp->tx_chain_head = lp->tx_chain_tail;
 638                         dev->trans_start = jiffies;
 639                 }
 640                 if (dmas & DMA_STAT_ERR)
 641                         printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name);
 642
 643                 retval = IRQ_HANDLED;
 644         } else
 645                 retval = IRQ_NONE;
 646
 647         return retval;
 648 }
 649
 650
 651 static void korina_check_media(struct net_device *dev, unsigned int init_media)
 652 {
 653         struct korina_private *lp = netdev_priv(dev);
 654
 655         mii_check_media(&lp->mii_if, 0, init_media);
 656
 657         if (lp->mii_if.full_duplex)
 658                 writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD,
 659                                                 &lp->eth_regs->ethmac2);
 660         else
 661                 writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD,
 662                                                 &lp->eth_regs->ethmac2);
 663 }
 664
 665 static void korina_set_carrier(struct mii_if_info *mii)
 666 {
 667         if (mii->force_media) {
 668                 /* autoneg is off: Link is always assumed to be up */
 669                 if (!netif_carrier_ok(mii->dev))
 670                         netif_carrier_on(mii->dev);
 671         } else  /* Let MMI library update carrier status */
 672                 korina_check_media(mii->dev, 0);
 673 }
 674
 675 static int korina_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 676 {
 677         struct korina_private *lp = netdev_priv(dev);
 678         struct mii_ioctl_data *data = if_mii(rq);
 679         int rc;
 680
 681         if (!netif_running(dev))
 682                 return -EINVAL;
 683         spin_lock_irq(&lp->lock);
 684         rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
 685         spin_unlock_irq(&lp->lock);
 686         korina_set_carrier(&lp->mii_if);
 687
 688         return rc;
 689 }
 690
 691 /* ethtool helpers */
 692 static void netdev_get_drvinfo(struct net_device *dev,
 693                         struct ethtool_drvinfo *info)
 694 {
 695         struct korina_private *lp = netdev_priv(dev);
 696
 697         strcpy(info->driver, DRV_NAME);
 698         strcpy(info->version, DRV_VERSION);
 699         strcpy(info->bus_info, lp->dev->name);
 700 }
 701
 702 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 703 {
 704         struct korina_private *lp = netdev_priv(dev);
 705         int rc;
 706
 707         spin_lock_irq(&lp->lock);
 708         rc = mii_ethtool_gset(&lp->mii_if, cmd);
 709         spin_unlock_irq(&lp->lock);
 710
 711         return rc;
 712 }
 713
 714 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 715 {
 716         struct korina_private *lp = netdev_priv(dev);
 717         int rc;
 718
 719         spin_lock_irq(&lp->lock);
 720         rc = mii_ethtool_sset(&lp->mii_if, cmd);
 721         spin_unlock_irq(&lp->lock);
 722         korina_set_carrier(&lp->mii_if);
 723
 724         return rc;
 725 }
 726
 727 static u32 netdev_get_link(struct net_device *dev)
 728 {
 729         struct korina_private *lp = netdev_priv(dev);
 730
 731         return mii_link_ok(&lp->mii_if);
 732 }
 733
 734 static struct ethtool_ops netdev_ethtool_ops = {
 735         .get_drvinfo            = netdev_get_drvinfo,
 736         .get_settings           = netdev_get_settings,
 737         .set_settings           = netdev_set_settings,
 738         .get_link               = netdev_get_link,
 739 };
 740
 741 static void korina_alloc_ring(struct net_device *dev)
 742 {
 743         struct korina_private *lp = netdev_priv(dev);
 744         int i;
 745
 746         /* Initialize the transmit descriptors */
 747         for (i = 0; i < KORINA_NUM_TDS; i++) {
 748                 lp->td_ring[i].control = DMA_DESC_IOF;
 749                 lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD;
 750                 lp->td_ring[i].ca = 0;
 751                 lp->td_ring[i].link = 0;
 752         }
 753         lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =
 754                         lp->tx_full = lp->tx_count = 0;
 755         lp->tx_chain_status = desc_empty;
 756
 757         /* Initialize the receive descriptors */
 758         for (i = 0; i < KORINA_NUM_RDS; i++) {
 759                 struct sk_buff *skb = lp->rx_skb[i];
 760
 761                 skb = dev_alloc_skb(KORINA_RBSIZE + 2);
 762                 if (!skb)
 763                         break;
 764                 skb_reserve(skb, 2);
 765                 lp->rx_skb[i] = skb;
 766                 lp->rd_ring[i].control = DMA_DESC_IOD |
 767                                 DMA_COUNT(KORINA_RBSIZE);
 768                 lp->rd_ring[i].devcs = 0;
 769                 lp->rd_ring[i].ca = CPHYSADDR(skb->data);
 770                 lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
 771         }
 772
 773         /* loop back */
 774         lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[0]);
 775         lp->rx_next_done  = 0;
 776
 777         lp->rd_ring[i].control |= DMA_DESC_COD;
 778         lp->rx_chain_head = 0;
 779         lp->rx_chain_tail = 0;
 780         lp->rx_chain_status = desc_empty;
 781 }
 782
 783 static void korina_free_ring(struct net_device *dev)
 784 {
 785         struct korina_private *lp = netdev_priv(dev);
 786         int i;
 787
 788         for (i = 0; i < KORINA_NUM_RDS; i++) {
 789                 lp->rd_ring[i].control = 0;
 790                 if (lp->rx_skb[i])
 791                         dev_kfree_skb_any(lp->rx_skb[i]);
 792                 lp->rx_skb[i] = NULL;
 793         }
 794
 795         for (i = 0; i < KORINA_NUM_TDS; i++) {
 796                 lp->td_ring[i].control = 0;
 797                 if (lp->tx_skb[i])
 798                         dev_kfree_skb_any(lp->tx_skb[i]);
 799                 lp->tx_skb[i] = NULL;
 800         }
 801 }
 802
 803 /*
 804  * Initialize the RC32434 ethernet controller.
 805  */
 806 static int korina_init(struct net_device *dev)
 807 {
 808         struct korina_private *lp = netdev_priv(dev);
 809
 810         /* Disable DMA */
 811         korina_abort_tx(dev);
 812         korina_abort_rx(dev);
 813
 814         /* reset ethernet logic */
 815         writel(0, &lp->eth_regs->ethintfc);
 816         while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP))
 817                 dev->trans_start = jiffies;
 818
 819         /* Enable Ethernet Interface */
 820         writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc);
 821
 822         /* Allocate rings */
 823         korina_alloc_ring(dev);
 824
 825         writel(0, &lp->rx_dma_regs->dmas);
 826         /* Start Rx DMA */
 827         korina_start_rx(lp, &lp->rd_ring[0]);
 828
 829         writel(readl(&lp->tx_dma_regs->dmasm) &
 830                         ~(DMA_STAT_FINI | DMA_STAT_ERR),
 831                         &lp->tx_dma_regs->dmasm);
 832         writel(readl(&lp->rx_dma_regs->dmasm) &
 833                         ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
 834                         &lp->rx_dma_regs->dmasm);
 835
 836         /* Accept only packets destined for this Ethernet device address */
 837         writel(ETH_ARC_AB, &lp->eth_regs->etharc);
 838
 839         /* Set all Ether station address registers to their initial values */
 840         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
 841         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
 842
 843         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
 844         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
 845
 846         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
 847         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
 848
 849         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
 850         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
 851
 852
 853         /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
 854         writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD,
 855                         &lp->eth_regs->ethmac2);
 856
 857         /* Back to back inter-packet-gap */
 858         writel(0x15, &lp->eth_regs->ethipgt);
 859         /* Non - Back to back inter-packet-gap */
 860         writel(0x12, &lp->eth_regs->ethipgr);
 861
 862         /* Management Clock Prescaler Divisor
 863          * Clock independent setting */
 864         writel(((idt_cpu_freq) / MII_CLOCK + 1) & ~1,
 865                        &lp->eth_regs->ethmcp);
 866
 867         /* don't transmit until fifo contains 48b */
 868         writel(48, &lp->eth_regs->ethfifott);
 869
 870         writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1);
 871
 872         napi_enable(&lp->napi);
 873         netif_start_queue(dev);
 874
 875         return 0;
 876 }
 877
 878 /*
 879  * Restart the RC32434 ethernet controller.
 880  * FIXME: check the return status where we call it
 881  */
 882 static int korina_restart(struct net_device *dev)
 883 {
 884         struct korina_private *lp = netdev_priv(dev);
 885         int ret;
 886
 887         /*
 888          * Disable interrupts
 889          */
 890         disable_irq(lp->rx_irq);
 891         disable_irq(lp->tx_irq);
 892         disable_irq(lp->ovr_irq);
 893         disable_irq(lp->und_irq);
 894
 895         writel(readl(&lp->tx_dma_regs->dmasm) |
 896                                 DMA_STAT_FINI | DMA_STAT_ERR,
 897                                 &lp->tx_dma_regs->dmasm);
 898         writel(readl(&lp->rx_dma_regs->dmasm) |
 899                                 DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR,
 900                                 &lp->rx_dma_regs->dmasm);
 901
 902         korina_free_ring(dev);
 903
 904         ret = korina_init(dev);
 905         if (ret < 0) {
 906                 printk(KERN_ERR DRV_NAME "%s: cannot restart device\n",
 907                                                                 dev->name);
 908                 return ret;
 909         }
 910         korina_multicast_list(dev);
 911
 912         enable_irq(lp->und_irq);
 913         enable_irq(lp->ovr_irq);
 914         enable_irq(lp->tx_irq);
 915         enable_irq(lp->rx_irq);
 916
 917         return ret;
 918 }
 919
 920 static void korina_clear_and_restart(struct net_device *dev, u32 value)
 921 {
 922         struct korina_private *lp = netdev_priv(dev);
 923
 924         netif_stop_queue(dev);
 925         writel(value, &lp->eth_regs->ethintfc);
 926         korina_restart(dev);
 927 }
 928
 929 /* Ethernet Tx Underflow interrupt */
 930 static irqreturn_t korina_und_interrupt(int irq, void *dev_id)
 931 {
 932         struct net_device *dev = dev_id;
 933         struct korina_private *lp = netdev_priv(dev);
 934         unsigned int und;
 935
 936         spin_lock(&lp->lock);
 937
 938         und = readl(&lp->eth_regs->ethintfc);
 939
 940         if (und & ETH_INT_FC_UND)
 941                 korina_clear_and_restart(dev, und & ~ETH_INT_FC_UND);
 942
 943         spin_unlock(&lp->lock);
 944
 945         return IRQ_HANDLED;
 946 }
 947
 948 static void korina_tx_timeout(struct net_device *dev)
 949 {
 950         struct korina_private *lp = netdev_priv(dev);
 951         unsigned long flags;
 952
 953         spin_lock_irqsave(&lp->lock, flags);
 954         korina_restart(dev);
 955         spin_unlock_irqrestore(&lp->lock, flags);
 956 }
 957
 958 /* Ethernet Rx Overflow interrupt */
 959 static irqreturn_t
 960 korina_ovr_interrupt(int irq, void *dev_id)
 961 {
 962         struct net_device *dev = dev_id;
 963         struct korina_private *lp = netdev_priv(dev);
 964         unsigned int ovr;
 965
 966         spin_lock(&lp->lock);
 967         ovr = readl(&lp->eth_regs->ethintfc);
 968
 969         if (ovr & ETH_INT_FC_OVR)
 970                 korina_clear_and_restart(dev, ovr & ~ETH_INT_FC_OVR);
 971
 972         spin_unlock(&lp->lock);
 973
 974         return IRQ_HANDLED;
 975 }
 976
 977 #ifdef CONFIG_NET_POLL_CONTROLLER
 978 static void korina_poll_controller(struct net_device *dev)
 979 {
 980         disable_irq(dev->irq);
 981         korina_tx_dma_interrupt(dev->irq, dev);
 982         enable_irq(dev->irq);
 983 }
 984 #endif
 985
 986 static int korina_open(struct net_device *dev)
 987 {
 988         struct korina_private *lp = netdev_priv(dev);
 989         int ret;
 990
 991         /* Initialize */
 992         ret = korina_init(dev);
 993         if (ret < 0) {
 994                 printk(KERN_ERR DRV_NAME "%s: cannot open device\n", dev->name);
 995                 goto out;
 996         }
 997
 998         /* Install the interrupt handler
 999          * that handles the Done Finished
1000          * Ovr and Und Events */
1001         ret = request_irq(lp->rx_irq, &korina_rx_dma_interrupt,
1002                 IRQF_SHARED | IRQF_DISABLED, "Korina ethernet Rx", dev);
1003         if (ret < 0) {
1004                 printk(KERN_ERR DRV_NAME "%s: unable to get Rx DMA IRQ %d\n",
1005                     dev->name, lp->rx_irq);
1006                 goto err_release;
1007         }
1008         ret = request_irq(lp->tx_irq, &korina_tx_dma_interrupt,
1009                 IRQF_SHARED | IRQF_DISABLED, "Korina ethernet Tx", dev);
1010         if (ret < 0) {
1011                 printk(KERN_ERR DRV_NAME "%s: unable to get Tx DMA IRQ %d\n",
1012                     dev->name, lp->tx_irq);
1013                 goto err_free_rx_irq;
1014         }
1015
1016         /* Install handler for overrun error. */
1017         ret = request_irq(lp->ovr_irq, &korina_ovr_interrupt,
1018                         IRQF_SHARED | IRQF_DISABLED, "Ethernet Overflow", dev);
1019         if (ret < 0) {
1020                 printk(KERN_ERR DRV_NAME"%s: unable to get OVR IRQ %d\n",
1021                     dev->name, lp->ovr_irq);
1022                 goto err_free_tx_irq;
1023         }
1024
1025         /* Install handler for underflow error. */
1026         ret = request_irq(lp->und_irq, &korina_und_interrupt,
1027                         IRQF_SHARED | IRQF_DISABLED, "Ethernet Underflow", dev);
1028         if (ret < 0) {
1029                 printk(KERN_ERR DRV_NAME "%s: unable to get UND IRQ %d\n",
1030                     dev->name, lp->und_irq);
1031                 goto err_free_ovr_irq;
1032         }
1033 out:
1034         return ret;
1035
1036 err_free_ovr_irq:
1037         free_irq(lp->ovr_irq, dev);
1038 err_free_tx_irq:
1039         free_irq(lp->tx_irq, dev);
1040 err_free_rx_irq:
1041         free_irq(lp->rx_irq, dev);
1042 err_release:
1043         korina_free_ring(dev);
1044         goto out;
1045 }
1046
1047 static int korina_close(struct net_device *dev)
1048 {
1049         struct korina_private *lp = netdev_priv(dev);
1050         u32 tmp;
1051
1052         /* Disable interrupts */
1053         disable_irq(lp->rx_irq);
1054         disable_irq(lp->tx_irq);
1055         disable_irq(lp->ovr_irq);
1056         disable_irq(lp->und_irq);
1057
1058         korina_abort_tx(dev);
1059         tmp = readl(&lp->tx_dma_regs->dmasm);
1060         tmp = tmp | DMA_STAT_FINI | DMA_STAT_ERR;
1061         writel(tmp, &lp->tx_dma_regs->dmasm);
1062
1063         korina_abort_rx(dev);
1064         tmp = readl(&lp->rx_dma_regs->dmasm);
1065         tmp = tmp | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR;
1066         writel(tmp, &lp->rx_dma_regs->dmasm);
1067
1068         korina_free_ring(dev);
1069
1070         free_irq(lp->rx_irq, dev);
1071         free_irq(lp->tx_irq, dev);
1072         free_irq(lp->ovr_irq, dev);
1073         free_irq(lp->und_irq, dev);
1074
1075         return 0;
1076 }
1077
1078 static int korina_probe(struct platform_device *pdev)
1079 {
1080         struct korina_device *bif = platform_get_drvdata(pdev);
1081         struct korina_private *lp;
1082         struct net_device *dev;
1083         struct resource *r;
1084         int rc;
1085
1086         dev = alloc_etherdev(sizeof(struct korina_private));
1087         if (!dev) {
1088                 printk(KERN_ERR DRV_NAME ": alloc_etherdev failed\n");
1089                 return -ENOMEM;
1090         }
1091         SET_NETDEV_DEV(dev, &pdev->dev);
1092         platform_set_drvdata(pdev, dev);
1093         lp = netdev_priv(dev);
1094
1095         bif->dev = dev;
1096         memcpy(dev->dev_addr, bif->mac, 6);
1097
1098         lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx");
1099         lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx");
1100         lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr");
1101         lp->und_irq = platform_get_irq_byname(pdev, "korina_und");
1102
1103         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs");
1104         dev->base_addr = r->start;
1105         lp->eth_regs = ioremap_nocache(r->start, r->end - r->start);
1106         if (!lp->eth_regs) {
1107                 printk(KERN_ERR DRV_NAME "cannot remap registers\n");
1108                 rc = -ENXIO;
1109                 goto probe_err_out;
1110         }
1111
1112         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx");
1113         lp->rx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
1114         if (!lp->rx_dma_regs) {
1115                 printk(KERN_ERR DRV_NAME "cannot remap Rx DMA registers\n");
1116                 rc = -ENXIO;
1117                 goto probe_err_dma_rx;
1118         }
1119
1120         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx");
1121         lp->tx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
1122         if (!lp->tx_dma_regs) {
1123                 printk(KERN_ERR DRV_NAME "cannot remap Tx DMA registers\n");
1124                 rc = -ENXIO;
1125                 goto probe_err_dma_tx;
1126         }
1127
1128         lp->td_ring = kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1129         if (!lp->td_ring) {
1130                 printk(KERN_ERR DRV_NAME "cannot allocate descriptors\n");
1131                 rc = -ENXIO;
1132                 goto probe_err_td_ring;
1133         }
1134
1135         dma_cache_inv((unsigned long)(lp->td_ring),
1136                         TD_RING_SIZE + RD_RING_SIZE);
1137
1138         /* now convert TD_RING pointer to KSEG1 */
1139         lp->td_ring = (struct dma_desc *)KSEG1ADDR(lp->td_ring);
1140         lp->rd_ring = &lp->td_ring[KORINA_NUM_TDS];
1141
1142         spin_lock_init(&lp->lock);
1143         /* just use the rx dma irq */
1144         dev->irq = lp->rx_irq;
1145         lp->dev = dev;
1146
1147         dev->open = korina_open;
1148         dev->stop = korina_close;
1149         dev->hard_start_xmit = korina_send_packet;
1150         dev->set_multicast_list = &korina_multicast_list;
1151         dev->ethtool_ops = &netdev_ethtool_ops;
1152         dev->tx_timeout = korina_tx_timeout;
1153         dev->watchdog_timeo = TX_TIMEOUT;
1154         dev->do_ioctl = &korina_ioctl;
1155 #ifdef CONFIG_NET_POLL_CONTROLLER
1156         dev->poll_controller = korina_poll_controller;
1157 #endif
1158         netif_napi_add(dev, &lp->napi, korina_poll, 64);
1159
1160         lp->phy_addr = (((lp->rx_irq == 0x2c? 1:0) << 8) | 0x05);
1161         lp->mii_if.dev = dev;
1162         lp->mii_if.mdio_read = mdio_read;
1163         lp->mii_if.mdio_write = mdio_write;
1164         lp->mii_if.phy_id = lp->phy_addr;
1165         lp->mii_if.phy_id_mask = 0x1f;
1166         lp->mii_if.reg_num_mask = 0x1f;
1167
1168         rc = register_netdev(dev);
1169         if (rc < 0) {
1170                 printk(KERN_ERR DRV_NAME
1171                         ": cannot register net device %d\n", rc);
1172                 goto probe_err_register;
1173         }
1174 out:
1175         return rc;
1176
1177 probe_err_register:
1178         kfree(lp->td_ring);
1179 probe_err_td_ring:
1180         iounmap(lp->tx_dma_regs);
1181 probe_err_dma_tx:
1182         iounmap(lp->rx_dma_regs);
1183 probe_err_dma_rx:
1184         iounmap(lp->eth_regs);
1185 probe_err_out:
1186         free_netdev(dev);
1187         goto out;
1188 }
1189
1190 static int korina_remove(struct platform_device *pdev)
1191 {
1192         struct korina_device *bif = platform_get_drvdata(pdev);
1193         struct korina_private *lp = netdev_priv(bif->dev);
1194
1195         iounmap(lp->eth_regs);
1196         iounmap(lp->rx_dma_regs);
1197         iounmap(lp->tx_dma_regs);
1198
1199         platform_set_drvdata(pdev, NULL);
1200         unregister_netdev(bif->dev);
1201         free_netdev(bif->dev);
1202
1203         return 0;
1204 }
1205
1206 static struct platform_driver korina_driver = {
1207         .driver.name = "korina",
1208         .probe = korina_probe,
1209         .remove = korina_remove,
1210 };
1211
1212 static int __init korina_init_module(void)
1213 {
1214         return platform_driver_register(&korina_driver);
1215 }
1216
1217 static void korina_cleanup_module(void)
1218 {
1219         return platform_driver_unregister(&korina_driver);
1220 }
1221
1222 module_init(korina_init_module);
1223 module_exit(korina_cleanup_module);
1224
1225 MODULE_AUTHOR("Philip Rischel <rischelp@idt.com>");
1226 MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
1227 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
1228 MODULE_DESCRIPTION("IDT RC32434 (Korina) Ethernet driver");
1229 MODULE_LICENSE("GPL");