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   1 /*
   2  * arch/sh/mm/consistent.c
   3  *
   4  * Copyright (C) 2004 - 2007  Paul Mundt
   5  *
   6  * Declared coherent memory functions based on arch/x86/kernel/pci-dma_32.c
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/mm.h>
  13 #include <linux/dma-mapping.h>
  14 #include <asm/cacheflush.h>
  15 #include <asm/addrspace.h>
  16 #include <asm/io.h>
  17
  18 struct dma_coherent_mem {
  19         void            *virt_base;
  20         u32             device_base;
  21         int             size;
  22         int             flags;
  23         unsigned long   *bitmap;
  24 };
  25
  26 void *dma_alloc_coherent(struct device *dev, size_t size,
  27                            dma_addr_t *dma_handle, gfp_t gfp)
  28 {
  29         void *ret, *ret_nocache;
  30         int order = get_order(size);
  31
  32         if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
  33                 return ret;
  34
  35         ret = (void *)__get_free_pages(gfp, order);
  36         if (!ret)
  37                 return NULL;
  38
  39         memset(ret, 0, size);
  40         /*
  41          * Pages from the page allocator may have data present in
  42          * cache. So flush the cache before using uncached memory.
  43          */
  44         dma_cache_sync(dev, ret, size, DMA_BIDIRECTIONAL);
  45
  46         ret_nocache = ioremap_nocache(virt_to_phys(ret), size);
  47         if (!ret_nocache) {
  48                 free_pages((unsigned long)ret, order);
  49                 return NULL;
  50         }
  51
  52         *dma_handle = virt_to_phys(ret);
  53         return ret_nocache;
  54 }
  55 EXPORT_SYMBOL(dma_alloc_coherent);
  56
  57 void dma_free_coherent(struct device *dev, size_t size,
  58                          void *vaddr, dma_addr_t dma_handle)
  59 {
  60         struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
  61         int order = get_order(size);
  62
  63         if (!dma_release_from_coherent(dev, order, vaddr)) {
  64                 WARN_ON(irqs_disabled());       /* for portability */
  65                 BUG_ON(mem && mem->flags & DMA_MEMORY_EXCLUSIVE);
  66                 free_pages((unsigned long)phys_to_virt(dma_handle), order);
  67                 iounmap(vaddr);
  68         }
  69 }
  70 EXPORT_SYMBOL(dma_free_coherent);
  71
  72 void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
  73                     enum dma_data_direction direction)
  74 {
  75 #ifdef CONFIG_CPU_SH5
  76         void *p1addr = vaddr;
  77 #else
  78         void *p1addr = (void*) P1SEGADDR((unsigned long)vaddr);
  79 #endif
  80
  81         switch (direction) {
  82         case DMA_FROM_DEVICE:           /* invalidate only */
  83                 __flush_invalidate_region(p1addr, size);
  84                 break;
  85         case DMA_TO_DEVICE:             /* writeback only */
  86                 __flush_wback_region(p1addr, size);
  87                 break;
  88         case DMA_BIDIRECTIONAL:         /* writeback and invalidate */
  89                 __flush_purge_region(p1addr, size);
  90                 break;
  91         default:
  92                 BUG();
  93         }
  94 }
  95 EXPORT_SYMBOL(dma_cache_sync);