2 * SGI UltraViolet TLB flush routines.
4 * (c) 2008 Cliff Wickman <cpw@sgi.com>, SGI.
6 * This code is released under the GNU General Public License version 2 or
9 #include <linux/mc146818rtc.h>
10 #include <linux/proc_fs.h>
11 #include <linux/kernel.h>
13 #include <asm/mmu_context.h>
14 #include <asm/uv/uv_mmrs.h>
15 #include <asm/uv/uv_hub.h>
16 #include <asm/uv/uv_bau.h>
17 #include <asm/genapic.h>
20 #include <asm/irq_vectors.h>
22 #include <mach_apic.h>
24 static struct bau_control **uv_bau_table_bases __read_mostly;
25 static int uv_bau_retry_limit __read_mostly;
27 /* position of pnode (which is nasid>>1): */
28 static int uv_nshift __read_mostly;
30 static unsigned long uv_mmask __read_mostly;
32 static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
33 static DEFINE_PER_CPU(struct bau_control, bau_control);
36 * Free a software acknowledge hardware resource by clearing its Pending
37 * bit. This will return a reply to the sender.
38 * If the message has timed out, a reply has already been sent by the
39 * hardware but the resource has not been released. In that case our
40 * clear of the Timeout bit (as well) will free the resource. No reply will
41 * be sent (the hardware will only do one reply per message).
43 static void uv_reply_to_message(int resource,
44 struct bau_payload_queue_entry *msg,
45 struct bau_msg_status *msp)
49 dw = (1 << (resource + UV_SW_ACK_NPENDING)) | (1 << resource);
51 msg->sw_ack_vector = 0;
53 msp->seen_by.bits = 0;
54 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw);
58 * Do all the things a cpu should do for a TLB shootdown message.
59 * Other cpu's may come here at the same time for this message.
61 static void uv_bau_process_message(struct bau_payload_queue_entry *msg,
62 int msg_slot, int sw_ack_slot)
64 unsigned long this_cpu_mask;
65 struct bau_msg_status *msp;
68 msp = __get_cpu_var(bau_control).msg_statuses + msg_slot;
69 cpu = uv_blade_processor_id();
71 uv_blade_nr_online_cpus(uv_node_to_blade_id(numa_node_id()));
72 this_cpu_mask = 1UL << cpu;
73 if (msp->seen_by.bits & this_cpu_mask)
75 atomic_or_long(&msp->seen_by.bits, this_cpu_mask);
77 if (msg->replied_to == 1)
80 if (msg->address == TLB_FLUSH_ALL) {
82 __get_cpu_var(ptcstats).alltlb++;
84 __flush_tlb_one(msg->address);
85 __get_cpu_var(ptcstats).onetlb++;
88 __get_cpu_var(ptcstats).requestee++;
90 atomic_inc_short(&msg->acknowledge_count);
91 if (msg->number_of_cpus == msg->acknowledge_count)
92 uv_reply_to_message(sw_ack_slot, msg, msp);
96 * Examine the payload queue on one distribution node to see
97 * which messages have not been seen, and which cpu(s) have not seen them.
99 * Returns the number of cpu's that have not responded.
101 static int uv_examine_destination(struct bau_control *bau_tablesp, int sender)
103 struct bau_payload_queue_entry *msg;
104 struct bau_msg_status *msp;
109 for (msg = bau_tablesp->va_queue_first, i = 0; i < DEST_Q_SIZE;
111 if ((msg->sending_cpu == sender) && (!msg->replied_to)) {
112 msp = bau_tablesp->msg_statuses + i;
114 "blade %d: address:%#lx %d of %d, not cpu(s): ",
115 i, msg->address, msg->acknowledge_count,
116 msg->number_of_cpus);
117 for (j = 0; j < msg->number_of_cpus; j++) {
118 if (!((1L << j) & msp->seen_by.bits)) {
130 * Examine the payload queue on all the distribution nodes to see
131 * which messages have not been seen, and which cpu(s) have not seen them.
133 * Returns the number of cpu's that have not responded.
135 static int uv_examine_destinations(struct bau_target_nodemask *distribution)
141 sender = smp_processor_id();
142 for (i = 0; i < sizeof(struct bau_target_nodemask) * BITSPERBYTE; i++) {
143 if (!bau_node_isset(i, distribution))
145 count += uv_examine_destination(uv_bau_table_bases[i], sender);
151 * wait for completion of a broadcast message
153 * return COMPLETE, RETRY or GIVEUP
155 static int uv_wait_completion(struct bau_desc *bau_desc,
156 unsigned long mmr_offset, int right_shift)
159 long destination_timeouts = 0;
160 long source_timeouts = 0;
161 unsigned long descriptor_status;
163 while ((descriptor_status = (((unsigned long)
164 uv_read_local_mmr(mmr_offset) >>
165 right_shift) & UV_ACT_STATUS_MASK)) !=
167 if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) {
169 if (source_timeouts > SOURCE_TIMEOUT_LIMIT)
171 __get_cpu_var(ptcstats).s_retry++;
175 * spin here looking for progress at the destinations
177 if (descriptor_status == DESC_STATUS_DESTINATION_TIMEOUT) {
178 destination_timeouts++;
179 if (destination_timeouts > DESTINATION_TIMEOUT_LIMIT) {
181 * returns number of cpus not responding
183 if (uv_examine_destinations
184 (&bau_desc->distribution) == 0) {
185 __get_cpu_var(ptcstats).d_retry++;
189 if (exams >= uv_bau_retry_limit) {
191 "uv_flush_tlb_others");
192 printk("giving up on cpu %d\n",
197 * delays can hang the simulator
200 destination_timeouts = 0;
204 return FLUSH_COMPLETE;
208 * uv_flush_send_and_wait
210 * Send a broadcast and wait for a broadcast message to complete.
212 * The cpumaskp mask contains the cpus the broadcast was sent to.
214 * Returns 1 if all remote flushing was done. The mask is zeroed.
215 * Returns 0 if some remote flushing remains to be done. The mask is left
218 int uv_flush_send_and_wait(int cpu, int this_blade, struct bau_desc *bau_desc,
221 int completion_status = 0;
226 unsigned long mmr_offset;
231 if (cpu < UV_CPUS_PER_ACT_STATUS) {
232 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
233 right_shift = cpu * UV_ACT_STATUS_SIZE;
235 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
237 ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE);
239 time1 = get_cycles();
242 index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) |
244 uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
245 completion_status = uv_wait_completion(bau_desc, mmr_offset,
247 } while (completion_status == FLUSH_RETRY);
248 time2 = get_cycles();
249 __get_cpu_var(ptcstats).sflush += (time2 - time1);
251 __get_cpu_var(ptcstats).retriesok++;
253 if (completion_status == FLUSH_GIVEUP) {
255 * Cause the caller to do an IPI-style TLB shootdown on
256 * the cpu's, all of which are still in the mask.
258 __get_cpu_var(ptcstats).ptc_i++;
263 * Success, so clear the remote cpu's from the mask so we don't
264 * use the IPI method of shootdown on them.
266 for_each_cpu_mask(bit, *cpumaskp) {
267 blade = uv_cpu_to_blade_id(bit);
268 if (blade == this_blade)
270 cpu_clear(bit, *cpumaskp);
272 if (!cpus_empty(*cpumaskp))
278 * uv_flush_tlb_others - globally purge translation cache of a virtual
279 * address or all TLB's
280 * @cpumaskp: mask of all cpu's in which the address is to be removed
281 * @mm: mm_struct containing virtual address range
282 * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
284 * This is the entry point for initiating any UV global TLB shootdown.
286 * Purges the translation caches of all specified processors of the given
287 * virtual address, or purges all TLB's on specified processors.
289 * The caller has derived the cpumaskp from the mm_struct and has subtracted
290 * the local cpu from the mask. This function is called only if there
291 * are bits set in the mask. (e.g. flush_tlb_page())
293 * The cpumaskp is converted into a nodemask of the nodes containing
296 * Returns 1 if all remote flushing was done.
297 * Returns 0 if some remote flushing remains to be done.
299 int uv_flush_tlb_others(cpumask_t *cpumaskp, struct mm_struct *mm,
308 struct bau_desc *bau_desc;
310 cpu = uv_blade_processor_id();
311 this_blade = uv_numa_blade_id();
312 bau_desc = __get_cpu_var(bau_control).descriptor_base;
313 bau_desc += UV_ITEMS_PER_DESCRIPTOR * cpu;
315 bau_nodes_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
318 for_each_cpu_mask(bit, *cpumaskp) {
319 blade = uv_cpu_to_blade_id(bit);
320 BUG_ON(blade > (UV_DISTRIBUTION_SIZE - 1));
321 if (blade == this_blade) {
325 bau_node_set(blade, &bau_desc->distribution);
330 * no off_node flushing; return status for local node
337 __get_cpu_var(ptcstats).requestor++;
338 __get_cpu_var(ptcstats).ntargeted += i;
340 bau_desc->payload.address = va;
341 bau_desc->payload.sending_cpu = smp_processor_id();
343 return uv_flush_send_and_wait(cpu, this_blade, bau_desc, cpumaskp);
347 * The BAU message interrupt comes here. (registered by set_intr_gate)
350 * We received a broadcast assist message.
352 * Interrupts may have been disabled; this interrupt could represent
353 * the receipt of several messages.
355 * All cores/threads on this node get this interrupt.
356 * The last one to see it does the s/w ack.
357 * (the resource will not be freed until noninterruptable cpus see this
358 * interrupt; hardware will timeout the s/w ack and reply ERROR)
360 void uv_bau_message_interrupt(struct pt_regs *regs)
362 struct bau_payload_queue_entry *va_queue_first;
363 struct bau_payload_queue_entry *va_queue_last;
364 struct bau_payload_queue_entry *msg;
365 struct pt_regs *old_regs = set_irq_regs(regs);
372 unsigned long local_pnode;
378 time1 = get_cycles();
380 local_pnode = uv_blade_to_pnode(uv_numa_blade_id());
382 va_queue_first = __get_cpu_var(bau_control).va_queue_first;
383 va_queue_last = __get_cpu_var(bau_control).va_queue_last;
385 msg = __get_cpu_var(bau_control).bau_msg_head;
386 while (msg->sw_ack_vector) {
388 fw = msg->sw_ack_vector;
389 msg_slot = msg - va_queue_first;
390 sw_ack_slot = ffs(fw) - 1;
392 uv_bau_process_message(msg, msg_slot, sw_ack_slot);
395 if (msg > va_queue_last)
396 msg = va_queue_first;
397 __get_cpu_var(bau_control).bau_msg_head = msg;
400 __get_cpu_var(ptcstats).nomsg++;
402 __get_cpu_var(ptcstats).multmsg++;
404 time2 = get_cycles();
405 __get_cpu_var(ptcstats).dflush += (time2 - time1);
408 set_irq_regs(old_regs);
411 static void uv_enable_timeouts(void)
418 unsigned long apicid;
421 for_each_online_node(i) {
422 blade = uv_node_to_blade_id(i);
423 if (blade == last_blade)
426 apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
427 pnode = uv_blade_to_pnode(blade);
428 cur_cpu += uv_blade_nr_possible_cpus(i);
432 static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset)
434 if (*offset < num_possible_cpus())
439 static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
442 if (*offset < num_possible_cpus())
447 static void uv_ptc_seq_stop(struct seq_file *file, void *data)
452 * Display the statistics thru /proc
453 * data points to the cpu number
455 static int uv_ptc_seq_show(struct seq_file *file, void *data)
457 struct ptc_stats *stat;
460 cpu = *(loff_t *)data;
464 "# cpu requestor requestee one all sretry dretry ptc_i ");
466 "sw_ack sflush dflush sok dnomsg dmult starget\n");
468 if (cpu < num_possible_cpus() && cpu_online(cpu)) {
469 stat = &per_cpu(ptcstats, cpu);
470 seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld ",
471 cpu, stat->requestor,
472 stat->requestee, stat->onetlb, stat->alltlb,
473 stat->s_retry, stat->d_retry, stat->ptc_i);
474 seq_printf(file, "%lx %ld %ld %ld %ld %ld %ld\n",
475 uv_read_global_mmr64(uv_blade_to_pnode
476 (uv_cpu_to_blade_id(cpu)),
477 UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE),
478 stat->sflush, stat->dflush,
479 stat->retriesok, stat->nomsg,
480 stat->multmsg, stat->ntargeted);
487 * 0: display meaning of the statistics
490 static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user,
491 size_t count, loff_t *data)
496 if (count == 0 || count > sizeof(optstr))
498 if (copy_from_user(optstr, user, count))
500 optstr[count - 1] = '\0';
501 if (strict_strtoul(optstr, 10, &newmode) < 0) {
502 printk(KERN_DEBUG "%s is invalid\n", optstr);
507 printk(KERN_DEBUG "# cpu: cpu number\n");
509 "requestor: times this cpu was the flush requestor\n");
511 "requestee: times this cpu was requested to flush its TLBs\n");
513 "one: times requested to flush a single address\n");
515 "all: times requested to flush all TLB's\n");
517 "sretry: number of retries of source-side timeouts\n");
519 "dretry: number of retries of destination-side timeouts\n");
521 "ptc_i: times UV fell through to IPI-style flushes\n");
523 "sw_ack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n");
525 "sflush_us: cycles spent in uv_flush_tlb_others()\n");
527 "dflush_us: cycles spent in handling flush requests\n");
528 printk(KERN_DEBUG "sok: successes on retry\n");
529 printk(KERN_DEBUG "dnomsg: interrupts with no message\n");
531 "dmult: interrupts with multiple messages\n");
532 printk(KERN_DEBUG "starget: nodes targeted\n");
534 uv_bau_retry_limit = newmode;
535 printk(KERN_DEBUG "timeout retry limit:%d\n",
542 static const struct seq_operations uv_ptc_seq_ops = {
543 .start = uv_ptc_seq_start,
544 .next = uv_ptc_seq_next,
545 .stop = uv_ptc_seq_stop,
546 .show = uv_ptc_seq_show
549 static int uv_ptc_proc_open(struct inode *inode, struct file *file)
551 return seq_open(file, &uv_ptc_seq_ops);
554 static const struct file_operations proc_uv_ptc_operations = {
555 .open = uv_ptc_proc_open,
557 .write = uv_ptc_proc_write,
559 .release = seq_release,
562 static int __init uv_ptc_init(void)
564 struct proc_dir_entry *proc_uv_ptc;
569 if (!proc_mkdir("sgi_uv", NULL))
572 proc_uv_ptc = create_proc_entry(UV_PTC_BASENAME, 0444, NULL);
574 printk(KERN_ERR "unable to create %s proc entry\n",
576 remove_proc_entry("sgi_uv", NULL);
579 proc_uv_ptc->proc_fops = &proc_uv_ptc_operations;
584 * begin the initialization of the per-blade control structures
586 static struct bau_control * __init uv_table_bases_init(int blade, int node)
590 struct bau_msg_status *msp;
591 struct bau_control *bau_tabp;
594 kmalloc_node(sizeof(struct bau_control), GFP_KERNEL, node);
597 bau_tabp->msg_statuses =
598 kmalloc_node(sizeof(struct bau_msg_status) *
599 DEST_Q_SIZE, GFP_KERNEL, node);
600 BUG_ON(!bau_tabp->msg_statuses);
602 for (i = 0, msp = bau_tabp->msg_statuses; i < DEST_Q_SIZE; i++, msp++)
603 bau_cpubits_clear(&msp->seen_by, (int)
604 uv_blade_nr_possible_cpus(blade));
607 kmalloc_node(sizeof(int) * DEST_NUM_RESOURCES, GFP_KERNEL, node);
608 BUG_ON(!bau_tabp->watching);
610 for (i = 0, ip = bau_tabp->watching; i < DEST_Q_SIZE; i++, ip++)
613 uv_bau_table_bases[blade] = bau_tabp;
619 * finish the initialization of the per-blade control structures
622 uv_table_bases_finish(int blade, int node, int cur_cpu,
623 struct bau_control *bau_tablesp,
624 struct bau_desc *adp)
626 struct bau_control *bcp;
629 for (i = cur_cpu; i < cur_cpu + uv_blade_nr_possible_cpus(blade); i++) {
630 bcp = (struct bau_control *)&per_cpu(bau_control, i);
632 bcp->bau_msg_head = bau_tablesp->va_queue_first;
633 bcp->va_queue_first = bau_tablesp->va_queue_first;
634 bcp->va_queue_last = bau_tablesp->va_queue_last;
635 bcp->watching = bau_tablesp->watching;
636 bcp->msg_statuses = bau_tablesp->msg_statuses;
637 bcp->descriptor_base = adp;
642 * initialize the sending side's sending buffers
644 static struct bau_desc * __init
645 uv_activation_descriptor_init(int node, int pnode)
651 unsigned long mmr_image;
652 struct bau_desc *adp;
653 struct bau_desc *ad2;
655 adp = (struct bau_desc *)
656 kmalloc_node(16384, GFP_KERNEL, node);
659 pa = __pa((unsigned long)adp);
663 mmr_image = uv_read_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE);
665 uv_write_global_mmr64(pnode, (unsigned long)
666 UVH_LB_BAU_SB_DESCRIPTOR_BASE,
667 (n << UV_DESC_BASE_PNODE_SHIFT | m));
670 for (i = 0, ad2 = adp; i < UV_ACTIVATION_DESCRIPTOR_SIZE; i++, ad2++) {
671 memset(ad2, 0, sizeof(struct bau_desc));
672 ad2->header.sw_ack_flag = 1;
673 ad2->header.base_dest_nodeid =
674 uv_blade_to_pnode(uv_cpu_to_blade_id(0));
675 ad2->header.command = UV_NET_ENDPOINT_INTD;
676 ad2->header.int_both = 1;
678 * all others need to be set to zero:
679 * fairness chaining multilevel count replied_to
686 * initialize the destination side's receiving buffers
688 static struct bau_payload_queue_entry * __init
689 uv_payload_queue_init(int node, int pnode, struct bau_control *bau_tablesp)
691 struct bau_payload_queue_entry *pqp;
694 pqp = (struct bau_payload_queue_entry *) kmalloc_node(
695 (DEST_Q_SIZE + 1) * sizeof(struct bau_payload_queue_entry),
699 cp = (char *)pqp + 31;
700 pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5);
701 bau_tablesp->va_queue_first = pqp;
702 uv_write_global_mmr64(pnode,
703 UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST,
704 ((unsigned long)pnode <<
705 UV_PAYLOADQ_PNODE_SHIFT) |
706 uv_physnodeaddr(pqp));
707 uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL,
708 uv_physnodeaddr(pqp));
709 bau_tablesp->va_queue_last = pqp + (DEST_Q_SIZE - 1);
710 uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST,
712 uv_physnodeaddr(bau_tablesp->va_queue_last));
713 memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE);
719 * Initialization of each UV blade's structures
721 static int __init uv_init_blade(int blade, int node, int cur_cpu)
725 unsigned long apicid;
726 struct bau_desc *adp;
727 struct bau_payload_queue_entry *pqp;
728 struct bau_control *bau_tablesp;
730 bau_tablesp = uv_table_bases_init(blade, node);
731 pnode = uv_blade_to_pnode(blade);
732 adp = uv_activation_descriptor_init(node, pnode);
733 pqp = uv_payload_queue_init(node, pnode, bau_tablesp);
734 uv_table_bases_finish(blade, node, cur_cpu, bau_tablesp, adp);
736 * the below initialization can't be in firmware because the
737 * messaging IRQ will be determined by the OS
739 apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
740 pa = uv_read_global_mmr64(pnode, UVH_BAU_DATA_CONFIG);
741 if ((pa & 0xff) != UV_BAU_MESSAGE) {
742 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG,
743 ((apicid << 32) | UV_BAU_MESSAGE));
749 * Initialization of BAU-related structures
751 static int __init uv_bau_init(void)
762 uv_bau_retry_limit = 1;
763 uv_nshift = uv_hub_info->n_val;
764 uv_mmask = (1UL << uv_hub_info->n_val) - 1;
767 for_each_online_node(node) {
768 blade = uv_node_to_blade_id(node);
769 if (blade == last_blade)
774 uv_bau_table_bases = (struct bau_control **)
775 kmalloc(nblades * sizeof(struct bau_control *), GFP_KERNEL);
776 BUG_ON(!uv_bau_table_bases);
779 for_each_online_node(node) {
780 blade = uv_node_to_blade_id(node);
781 if (blade == last_blade)
784 uv_init_blade(blade, node, cur_cpu);
785 cur_cpu += uv_blade_nr_possible_cpus(blade);
787 alloc_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1);
788 uv_enable_timeouts();
792 __initcall(uv_bau_init);
793 __initcall(uv_ptc_init);