sgiioc4: fix sgiioc4_ide_dma_check() to enable/disable DMA properly
[linux-2.6] / drivers / ide / pci / sgiioc4.c
1 /*
2  * Copyright (c) 2003-2006 Silicon Graphics, Inc.  All Rights Reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms of version 2 of the GNU General Public License
6  * as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it would be useful, but
9  * WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11  *
12  * You should have received a copy of the GNU General Public
13  * License along with this program; if not, write the Free Software
14  * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
15  *
16  * For further information regarding this notice, see:
17  *
18  * http://oss.sgi.com/projects/GenInfo/NoticeExplan
19  */
20
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/hdreg.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/timer.h>
29 #include <linux/mm.h>
30 #include <linux/ioport.h>
31 #include <linux/blkdev.h>
32 #include <linux/ioc4.h>
33 #include <asm/io.h>
34
35 #include <linux/ide.h>
36
37 /* IOC4 Specific Definitions */
38 #define IOC4_CMD_OFFSET         0x100
39 #define IOC4_CTRL_OFFSET        0x120
40 #define IOC4_DMA_OFFSET         0x140
41 #define IOC4_INTR_OFFSET        0x0
42
43 #define IOC4_TIMING             0x00
44 #define IOC4_DMA_PTR_L          0x01
45 #define IOC4_DMA_PTR_H          0x02
46 #define IOC4_DMA_ADDR_L         0x03
47 #define IOC4_DMA_ADDR_H         0x04
48 #define IOC4_BC_DEV             0x05
49 #define IOC4_BC_MEM             0x06
50 #define IOC4_DMA_CTRL           0x07
51 #define IOC4_DMA_END_ADDR       0x08
52
53 /* Bits in the IOC4 Control/Status Register */
54 #define IOC4_S_DMA_START        0x01
55 #define IOC4_S_DMA_STOP         0x02
56 #define IOC4_S_DMA_DIR          0x04
57 #define IOC4_S_DMA_ACTIVE       0x08
58 #define IOC4_S_DMA_ERROR        0x10
59 #define IOC4_ATA_MEMERR         0x02
60
61 /* Read/Write Directions */
62 #define IOC4_DMA_WRITE          0x04
63 #define IOC4_DMA_READ           0x00
64
65 /* Interrupt Register Offsets */
66 #define IOC4_INTR_REG           0x03
67 #define IOC4_INTR_SET           0x05
68 #define IOC4_INTR_CLEAR         0x07
69
70 #define IOC4_IDE_CACHELINE_SIZE 128
71 #define IOC4_CMD_CTL_BLK_SIZE   0x20
72 #define IOC4_SUPPORTED_FIRMWARE_REV 46
73
74 typedef struct {
75         u32 timing_reg0;
76         u32 timing_reg1;
77         u32 low_mem_ptr;
78         u32 high_mem_ptr;
79         u32 low_mem_addr;
80         u32 high_mem_addr;
81         u32 dev_byte_count;
82         u32 mem_byte_count;
83         u32 status;
84 } ioc4_dma_regs_t;
85
86 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
87 /* IOC4 has only 1 IDE channel */
88 #define IOC4_PRD_BYTES       16
89 #define IOC4_PRD_ENTRIES     (PAGE_SIZE /(4*IOC4_PRD_BYTES))
90
91
92 static void
93 sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
94                         unsigned long ctrl_port, unsigned long irq_port)
95 {
96         unsigned long reg = data_port;
97         int i;
98
99         /* Registers are word (32 bit) aligned */
100         for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
101                 hw->io_ports[i] = reg + i * 4;
102
103         if (ctrl_port)
104                 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
105
106         if (irq_port)
107                 hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
108 }
109
110 static void
111 sgiioc4_maskproc(ide_drive_t * drive, int mask)
112 {
113         writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
114                (void __iomem *)IDE_CONTROL_REG);
115 }
116
117
118 static int
119 sgiioc4_checkirq(ide_hwif_t * hwif)
120 {
121         unsigned long intr_addr =
122                 hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4;
123
124         if ((u8)readl((void __iomem *)intr_addr) & 0x03)
125                 return 1;
126
127         return 0;
128 }
129
130 static u8 sgiioc4_INB(unsigned long);
131
132 static int
133 sgiioc4_clearirq(ide_drive_t * drive)
134 {
135         u32 intr_reg;
136         ide_hwif_t *hwif = HWIF(drive);
137         unsigned long other_ir =
138             hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
139
140         /* Code to check for PCI error conditions */
141         intr_reg = readl((void __iomem *)other_ir);
142         if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
143                 /*
144                  * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect
145                  * of clearing the interrupt.  The first read should clear it
146                  * if it is set.  The second read should return a "clear" status
147                  * if it got cleared.  If not, then spin for a bit trying to
148                  * clear it.
149                  */
150                 u8 stat = sgiioc4_INB(IDE_STATUS_REG);
151                 int count = 0;
152                 stat = sgiioc4_INB(IDE_STATUS_REG);
153                 while ((stat & 0x80) && (count++ < 100)) {
154                         udelay(1);
155                         stat = sgiioc4_INB(IDE_STATUS_REG);
156                 }
157
158                 if (intr_reg & 0x02) {
159                         /* Error when transferring DMA data on PCI bus */
160                         u32 pci_err_addr_low, pci_err_addr_high,
161                             pci_stat_cmd_reg;
162
163                         pci_err_addr_low =
164                                 readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]);
165                         pci_err_addr_high =
166                                 readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4));
167                         pci_read_config_dword(hwif->pci_dev, PCI_COMMAND,
168                                               &pci_stat_cmd_reg);
169                         printk(KERN_ERR
170                                "%s(%s) : PCI Bus Error when doing DMA:"
171                                    " status-cmd reg is 0x%x\n",
172                                __FUNCTION__, drive->name, pci_stat_cmd_reg);
173                         printk(KERN_ERR
174                                "%s(%s) : PCI Error Address is 0x%x%x\n",
175                                __FUNCTION__, drive->name,
176                                pci_err_addr_high, pci_err_addr_low);
177                         /* Clear the PCI Error indicator */
178                         pci_write_config_dword(hwif->pci_dev, PCI_COMMAND,
179                                                0x00000146);
180                 }
181
182                 /* Clear the Interrupt, Error bits on the IOC4 */
183                 writel(0x03, (void __iomem *)other_ir);
184
185                 intr_reg = readl((void __iomem *)other_ir);
186         }
187
188         return intr_reg & 3;
189 }
190
191 static void sgiioc4_ide_dma_start(ide_drive_t * drive)
192 {
193         ide_hwif_t *hwif = HWIF(drive);
194         unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
195         unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
196         unsigned int temp_reg = reg | IOC4_S_DMA_START;
197
198         writel(temp_reg, (void __iomem *)ioc4_dma_addr);
199 }
200
201 static u32
202 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
203 {
204         unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
205         u32     ioc4_dma;
206         int     count;
207
208         count = 0;
209         ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
210         while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
211                 udelay(1);
212                 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
213         }
214         return ioc4_dma;
215 }
216
217 /* Stops the IOC4 DMA Engine */
218 static int
219 sgiioc4_ide_dma_end(ide_drive_t * drive)
220 {
221         u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
222         ide_hwif_t *hwif = HWIF(drive);
223         unsigned long dma_base = hwif->dma_base;
224         int dma_stat = 0;
225         unsigned long *ending_dma = ide_get_hwifdata(hwif);
226
227         writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
228
229         ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
230
231         if (ioc4_dma & IOC4_S_DMA_STOP) {
232                 printk(KERN_ERR
233                        "%s(%s): IOC4 DMA STOP bit is still 1 :"
234                        "ioc4_dma_reg 0x%x\n",
235                        __FUNCTION__, drive->name, ioc4_dma);
236                 dma_stat = 1;
237         }
238
239         /*
240          * The IOC4 will DMA 1's to the ending dma area to indicate that
241          * previous data DMA is complete.  This is necessary because of relaxed
242          * ordering between register reads and DMA writes on the Altix.
243          */
244         while ((cnt++ < 200) && (!valid)) {
245                 for (num = 0; num < 16; num++) {
246                         if (ending_dma[num]) {
247                                 valid = 1;
248                                 break;
249                         }
250                 }
251                 udelay(1);
252         }
253         if (!valid) {
254                 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__,
255                        drive->name);
256                 dma_stat = 1;
257         }
258
259         bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
260         bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
261
262         if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
263                 if (bc_dev > bc_mem + 8) {
264                         printk(KERN_ERR
265                                "%s(%s): WARNING!! byte_count_dev %d "
266                                "!= byte_count_mem %d\n",
267                                __FUNCTION__, drive->name, bc_dev, bc_mem);
268                 }
269         }
270
271         drive->waiting_for_dma = 0;
272         ide_destroy_dmatable(drive);
273
274         return dma_stat;
275 }
276
277 static int
278 sgiioc4_ide_dma_on(ide_drive_t * drive)
279 {
280         drive->using_dma = 1;
281
282         return HWIF(drive)->ide_dma_host_on(drive);
283 }
284
285 static int
286 sgiioc4_ide_dma_off_quietly(ide_drive_t * drive)
287 {
288         drive->using_dma = 0;
289
290         return HWIF(drive)->ide_dma_host_off(drive);
291 }
292
293 static int sgiioc4_ide_dma_check(ide_drive_t *drive)
294 {
295         /* FIXME: check for available DMA modes */
296         if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0) {
297                 printk(KERN_WARNING "%s: couldn't set MWDMA2 mode, "
298                                     "using PIO instead\n", drive->name);
299                 return sgiioc4_ide_dma_off_quietly(drive);
300         } else
301                 return sgiioc4_ide_dma_on(drive);
302 }
303
304 /* returns 1 if dma irq issued, 0 otherwise */
305 static int
306 sgiioc4_ide_dma_test_irq(ide_drive_t * drive)
307 {
308         return sgiioc4_checkirq(HWIF(drive));
309 }
310
311 static int
312 sgiioc4_ide_dma_host_on(ide_drive_t * drive)
313 {
314         if (drive->using_dma)
315                 return 0;
316
317         return 1;
318 }
319
320 static int
321 sgiioc4_ide_dma_host_off(ide_drive_t * drive)
322 {
323         sgiioc4_clearirq(drive);
324
325         return 0;
326 }
327
328 static int
329 sgiioc4_ide_dma_lostirq(ide_drive_t * drive)
330 {
331         HWIF(drive)->resetproc(drive);
332
333         return __ide_dma_lostirq(drive);
334 }
335
336 static void
337 sgiioc4_resetproc(ide_drive_t * drive)
338 {
339         sgiioc4_ide_dma_end(drive);
340         sgiioc4_clearirq(drive);
341 }
342
343 static u8
344 sgiioc4_INB(unsigned long port)
345 {
346         u8 reg = (u8) readb((void __iomem *) port);
347
348         if ((port & 0xFFF) == 0x11C) {  /* Status register of IOC4 */
349                 if (reg & 0x51) {       /* Not busy...check for interrupt */
350                         unsigned long other_ir = port - 0x110;
351                         unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
352
353                         /* Clear the Interrupt, Error bits on the IOC4 */
354                         if (intr_reg & 0x03) {
355                                 writel(0x03, (void __iomem *) other_ir);
356                                 intr_reg = (u32) readl((void __iomem *) other_ir);
357                         }
358                 }
359         }
360
361         return reg;
362 }
363
364 /* Creates a dma map for the scatter-gather list entries */
365 static void __devinit
366 ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base)
367 {
368         void __iomem *virt_dma_base;
369         int num_ports = sizeof (ioc4_dma_regs_t);
370         void *pad;
371
372         printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
373                dma_base, dma_base + num_ports - 1);
374
375         if (!request_mem_region(dma_base, num_ports, hwif->name)) {
376                 printk(KERN_ERR
377                        "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
378                        "ALREADY in use\n",
379                        __FUNCTION__, hwif->name, (void *) dma_base,
380                        (void *) dma_base + num_ports - 1);
381                 goto dma_alloc_failure;
382         }
383
384         virt_dma_base = ioremap(dma_base, num_ports);
385         if (virt_dma_base == NULL) {
386                 printk(KERN_ERR
387                        "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n",
388                        __FUNCTION__, hwif->name, dma_base, dma_base + num_ports - 1);
389                 goto dma_remap_failure;
390         }
391         hwif->dma_base = (unsigned long) virt_dma_base;
392
393         hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
394                                           IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
395                                           &hwif->dmatable_dma);
396
397         if (!hwif->dmatable_cpu)
398                 goto dma_pci_alloc_failure;
399
400         hwif->sg_max_nents = IOC4_PRD_ENTRIES;
401
402         pad = pci_alloc_consistent(hwif->pci_dev, IOC4_IDE_CACHELINE_SIZE,
403                                    (dma_addr_t *) &(hwif->dma_status));
404
405         if (pad) {
406                 ide_set_hwifdata(hwif, pad);
407                 return;
408         }
409
410         pci_free_consistent(hwif->pci_dev,
411                             IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
412                             hwif->dmatable_cpu, hwif->dmatable_dma);
413         printk(KERN_INFO
414                "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
415                __FUNCTION__, hwif->name);
416         printk(KERN_INFO
417                "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
418
419 dma_pci_alloc_failure:
420         iounmap(virt_dma_base);
421
422 dma_remap_failure:
423         release_mem_region(dma_base, num_ports);
424
425 dma_alloc_failure:
426         /* Disable DMA because we couldnot allocate any DMA maps */
427         hwif->autodma = 0;
428         hwif->atapi_dma = 0;
429 }
430
431 /* Initializes the IOC4 DMA Engine */
432 static void
433 sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
434 {
435         u32 ioc4_dma;
436         ide_hwif_t *hwif = HWIF(drive);
437         unsigned long dma_base = hwif->dma_base;
438         unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
439         u32 dma_addr, ending_dma_addr;
440
441         ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
442
443         if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
444                 printk(KERN_WARNING
445                         "%s(%s):Warning!! DMA from previous transfer was still active\n",
446                        __FUNCTION__, drive->name);
447                 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
448                 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
449
450                 if (ioc4_dma & IOC4_S_DMA_STOP)
451                         printk(KERN_ERR
452                                "%s(%s) : IOC4 Dma STOP bit is still 1\n",
453                                __FUNCTION__, drive->name);
454         }
455
456         ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
457         if (ioc4_dma & IOC4_S_DMA_ERROR) {
458                 printk(KERN_WARNING
459                        "%s(%s) : Warning!! - DMA Error during Previous"
460                        " transfer | status 0x%x\n",
461                        __FUNCTION__, drive->name, ioc4_dma);
462                 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
463                 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
464
465                 if (ioc4_dma & IOC4_S_DMA_STOP)
466                         printk(KERN_ERR
467                                "%s(%s) : IOC4 DMA STOP bit is still 1\n",
468                                __FUNCTION__, drive->name);
469         }
470
471         /* Address of the Scatter Gather List */
472         dma_addr = cpu_to_le32(hwif->dmatable_dma);
473         writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
474
475         /* Address of the Ending DMA */
476         memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
477         ending_dma_addr = cpu_to_le32(hwif->dma_status);
478         writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
479
480         writel(dma_direction, (void __iomem *)ioc4_dma_addr);
481         drive->waiting_for_dma = 1;
482 }
483
484 /* IOC4 Scatter Gather list Format                                       */
485 /* 128 Bit entries to support 64 bit addresses in the future             */
486 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format      */
487 /* --------------------------------------------------------------------- */
488 /* | Upper 32 bits - Zero           |           Lower 32 bits- address | */
489 /* --------------------------------------------------------------------- */
490 /* | Upper 32 bits - Zero           |EOL| 15 unused     | 16 Bit Length| */
491 /* --------------------------------------------------------------------- */
492 /* Creates the scatter gather list, DMA Table */
493 static unsigned int
494 sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
495 {
496         ide_hwif_t *hwif = HWIF(drive);
497         unsigned int *table = hwif->dmatable_cpu;
498         unsigned int count = 0, i = 1;
499         struct scatterlist *sg;
500
501         hwif->sg_nents = i = ide_build_sglist(drive, rq);
502
503         if (!i)
504                 return 0;       /* sglist of length Zero */
505
506         sg = hwif->sg_table;
507         while (i && sg_dma_len(sg)) {
508                 dma_addr_t cur_addr;
509                 int cur_len;
510                 cur_addr = sg_dma_address(sg);
511                 cur_len = sg_dma_len(sg);
512
513                 while (cur_len) {
514                         if (count++ >= IOC4_PRD_ENTRIES) {
515                                 printk(KERN_WARNING
516                                        "%s: DMA table too small\n",
517                                        drive->name);
518                                 goto use_pio_instead;
519                         } else {
520                                 u32 bcount =
521                                     0x10000 - (cur_addr & 0xffff);
522
523                                 if (bcount > cur_len)
524                                         bcount = cur_len;
525
526                                 /* put the addr, length in
527                                  * the IOC4 dma-table format */
528                                 *table = 0x0;
529                                 table++;
530                                 *table = cpu_to_be32(cur_addr);
531                                 table++;
532                                 *table = 0x0;
533                                 table++;
534
535                                 *table = cpu_to_be32(bcount);
536                                 table++;
537
538                                 cur_addr += bcount;
539                                 cur_len -= bcount;
540                         }
541                 }
542
543                 sg++;
544                 i--;
545         }
546
547         if (count) {
548                 table--;
549                 *table |= cpu_to_be32(0x80000000);
550                 return count;
551         }
552
553 use_pio_instead:
554         pci_unmap_sg(hwif->pci_dev, hwif->sg_table, hwif->sg_nents,
555                      hwif->sg_dma_direction);
556
557         return 0;               /* revert to PIO for this request */
558 }
559
560 static int sgiioc4_ide_dma_setup(ide_drive_t *drive)
561 {
562         struct request *rq = HWGROUP(drive)->rq;
563         unsigned int count = 0;
564         int ddir;
565
566         if (rq_data_dir(rq))
567                 ddir = PCI_DMA_TODEVICE;
568         else
569                 ddir = PCI_DMA_FROMDEVICE;
570
571         if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
572                 /* try PIO instead of DMA */
573                 ide_map_sg(drive, rq);
574                 return 1;
575         }
576
577         if (rq_data_dir(rq))
578                 /* Writes TO the IOC4 FROM Main Memory */
579                 ddir = IOC4_DMA_READ;
580         else
581                 /* Writes FROM the IOC4 TO Main Memory */
582                 ddir = IOC4_DMA_WRITE;
583
584         sgiioc4_configure_for_dma(ddir, drive);
585
586         return 0;
587 }
588
589 static void __devinit
590 ide_init_sgiioc4(ide_hwif_t * hwif)
591 {
592         hwif->mmio = 1;
593         hwif->autodma = 1;
594         hwif->atapi_dma = 1;
595         hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
596         hwif->mwdma_mask = 0x2; /* Multimode-2 DMA  */
597         hwif->swdma_mask = 0x2;
598         hwif->tuneproc = NULL;  /* Sets timing for PIO mode */
599         hwif->speedproc = NULL; /* Sets timing for DMA &/or PIO modes */
600         hwif->selectproc = NULL;/* Use the default routine to select drive */
601         hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */
602         hwif->pre_reset = NULL; /* No HBA specific pre_set needed */
603         hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine,
604                                                 clear interrupts */
605         hwif->intrproc = NULL;  /* Enable or Disable interrupt from drive */
606         hwif->maskproc = &sgiioc4_maskproc;     /* Mask on/off NIEN register */
607         hwif->quirkproc = NULL;
608         hwif->busproc = NULL;
609
610         hwif->dma_setup = &sgiioc4_ide_dma_setup;
611         hwif->dma_start = &sgiioc4_ide_dma_start;
612         hwif->ide_dma_end = &sgiioc4_ide_dma_end;
613         hwif->ide_dma_check = &sgiioc4_ide_dma_check;
614         hwif->ide_dma_on = &sgiioc4_ide_dma_on;
615         hwif->ide_dma_off_quietly = &sgiioc4_ide_dma_off_quietly;
616         hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq;
617         hwif->ide_dma_host_on = &sgiioc4_ide_dma_host_on;
618         hwif->ide_dma_host_off = &sgiioc4_ide_dma_host_off;
619         hwif->ide_dma_lostirq = &sgiioc4_ide_dma_lostirq;
620         hwif->ide_dma_timeout = &__ide_dma_timeout;
621
622         hwif->INB = &sgiioc4_INB;
623 }
624
625 static int __devinit
626 sgiioc4_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t * d)
627 {
628         unsigned long cmd_base, dma_base, irqport;
629         unsigned long bar0, cmd_phys_base, ctl;
630         void __iomem *virt_base;
631         ide_hwif_t *hwif;
632         int h;
633
634         /*
635          * Find an empty HWIF; if none available, return -ENOMEM.
636          */
637         for (h = 0; h < MAX_HWIFS; ++h) {
638                 hwif = &ide_hwifs[h];
639                 if (hwif->chipset == ide_unknown)
640                         break;
641         }
642         if (h == MAX_HWIFS) {
643                 printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", d->name);
644                 return -ENOMEM;
645         }
646
647         /*  Get the CmdBlk and CtrlBlk Base Registers */
648         bar0 = pci_resource_start(dev, 0);
649         virt_base = ioremap(bar0, pci_resource_len(dev, 0));
650         if (virt_base == NULL) {
651                 printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
652                         d->name, bar0);
653                 return -ENOMEM;
654         }
655         cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
656         ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
657         irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
658         dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
659
660         cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
661         if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
662             hwif->name)) {
663                 printk(KERN_ERR
664                         "%s : %s -- ERROR, Addresses "
665                         "0x%p to 0x%p ALREADY in use\n",
666                        __FUNCTION__, hwif->name, (void *) cmd_phys_base,
667                        (void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
668                 return -ENOMEM;
669         }
670
671         if (hwif->io_ports[IDE_DATA_OFFSET] != cmd_base) {
672                 /* Initialize the IO registers */
673                 sgiioc4_init_hwif_ports(&hwif->hw, cmd_base, ctl, irqport);
674                 memcpy(hwif->io_ports, hwif->hw.io_ports,
675                        sizeof (hwif->io_ports));
676                 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
677         }
678
679         hwif->irq = dev->irq;
680         hwif->chipset = ide_pci;
681         hwif->pci_dev = dev;
682         hwif->channel = 0;      /* Single Channel chip */
683         hwif->cds = (struct ide_pci_device_s *) d;
684         hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */
685
686         /* The IOC4 uses MMIO rather than Port IO. */
687         default_hwif_mmiops(hwif);
688
689         /* Initializing chipset IRQ Registers */
690         writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
691
692         ide_init_sgiioc4(hwif);
693
694         if (dma_base)
695                 ide_dma_sgiioc4(hwif, dma_base);
696         else
697                 printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
698                        hwif->name, d->name);
699
700         if (probe_hwif_init(hwif))
701                 return -EIO;
702
703         /* Create /proc/ide entries */
704         create_proc_ide_interfaces();
705
706         return 0;
707 }
708
709 static unsigned int __devinit
710 pci_init_sgiioc4(struct pci_dev *dev, ide_pci_device_t * d)
711 {
712         unsigned int class_rev;
713         int ret;
714
715         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
716         class_rev &= 0xff;
717         printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
718                         d->name, pci_name(dev), class_rev);
719         if (class_rev < IOC4_SUPPORTED_FIRMWARE_REV) {
720                 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
721                         "firmware is obsolete - please upgrade to revision"
722                         "46 or higher\n", d->name, pci_name(dev));
723                 ret = -EAGAIN;
724                 goto out;
725         }
726         ret = sgiioc4_ide_setup_pci_device(dev, d);
727 out:
728         return ret;
729 }
730
731 static ide_pci_device_t sgiioc4_chipset __devinitdata = {
732          /* Channel 0 */
733          .name = "SGIIOC4",
734          .init_hwif = ide_init_sgiioc4,
735          .init_dma = ide_dma_sgiioc4,
736          .channels = 1,
737          .autodma = AUTODMA,
738          /* SGI IOC4 doesn't have enablebits. */
739          .bootable = ON_BOARD,
740 };
741
742 int
743 ioc4_ide_attach_one(struct ioc4_driver_data *idd)
744 {
745         /* PCI-RT does not bring out IDE connection.
746          * Do not attach to this particular IOC4.
747          */
748         if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
749                 return 0;
750
751         return pci_init_sgiioc4(idd->idd_pdev, &sgiioc4_chipset);
752 }
753
754 static struct ioc4_submodule ioc4_ide_submodule = {
755         .is_name = "IOC4_ide",
756         .is_owner = THIS_MODULE,
757         .is_probe = ioc4_ide_attach_one,
758 /*      .is_remove = ioc4_ide_remove_one,       */
759 };
760
761 static int __init ioc4_ide_init(void)
762 {
763         return ioc4_register_submodule(&ioc4_ide_submodule);
764 }
765
766 late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
767
768 MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
769 MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
770 MODULE_LICENSE("GPL");