1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
17 /* Force re-assigning all resources (ignore firmware
20 PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001,
22 /* Re-assign all bus numbers */
23 PPC_PCI_REASSIGN_ALL_BUS = 0x00000002,
25 /* Do not try to assign, just use existing setup */
26 PPC_PCI_PROBE_ONLY = 0x00000004,
28 /* Don't bother with ISA alignment unless the bridge has
29 * ISA forwarding enabled
31 PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
33 /* Enable domain numbers in /proc */
34 PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010,
35 /* ... except for domain 0 */
36 PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020,
39 extern unsigned int ppc_pci_flags;
41 static inline void ppc_pci_set_flags(int flags)
43 ppc_pci_flags = flags;
46 static inline void ppc_pci_add_flags(int flags)
48 ppc_pci_flags |= flags;
51 static inline int ppc_pci_has_flag(int flag)
53 return (ppc_pci_flags & flag);
56 static inline void ppc_pci_set_flags(int flags) { }
57 static inline void ppc_pci_add_flags(int flags) { }
58 static inline int ppc_pci_has_flag(int flag)
66 * Structure of a PCI controller (host bridge)
68 struct pci_controller {
74 struct device_node *dn;
75 struct list_head list_node;
76 struct device *parent;
84 void __iomem *io_base_virt;
88 resource_size_t io_base_phys;
89 resource_size_t pci_io_size;
91 /* Some machines (PReP) have a non 1:1 mapping of
92 * the PCI memory space in the CPU bus space
94 resource_size_t pci_mem_offset;
96 /* Some machines have a special region to forward the ISA
97 * "memory" cycles such as VGA memory regions. Left to 0
100 resource_size_t isa_mem_phys;
101 resource_size_t isa_mem_size;
104 unsigned int __iomem *cfg_addr;
105 void __iomem *cfg_data;
109 * Used for variants of PCI indirect handling and possible quirks:
110 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
111 * EXT_REG - provides access to PCI-e extended registers
112 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
113 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
114 * to determine which bus number to match on when generating type0
116 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
117 * hanging if we don't have link and try to do config cycles to
118 * anything but the PHB. Only allow talking to the PHB if this is
120 * BIG_ENDIAN - cfg_addr is a big endian register
121 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
122 * the PLB4. Effectively disable MRM commands by setting this.
124 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
125 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
126 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
127 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
128 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
129 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
131 #endif /* !CONFIG_PPC64 */
132 /* Currently, we limit ourselves to 1 IO range and 3 mem
133 * ranges since the common pci_bus structure can't handle more
135 struct resource io_resource;
136 struct resource mem_resources[3];
137 int global_number; /* PCI domain number */
139 resource_size_t dma_window_base_cur;
140 resource_size_t dma_window_size;
146 #endif /* CONFIG_PPC64 */
151 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
156 static inline int isa_vaddr_is_ioport(void __iomem *address)
158 /* No specific ISA handling on ppc32 at this stage, it
159 * all goes through PCI
164 /* These are used for config access before all the PCI probing
166 extern int early_read_config_byte(struct pci_controller *hose, int bus,
167 int dev_fn, int where, u8 *val);
168 extern int early_read_config_word(struct pci_controller *hose, int bus,
169 int dev_fn, int where, u16 *val);
170 extern int early_read_config_dword(struct pci_controller *hose, int bus,
171 int dev_fn, int where, u32 *val);
172 extern int early_write_config_byte(struct pci_controller *hose, int bus,
173 int dev_fn, int where, u8 val);
174 extern int early_write_config_word(struct pci_controller *hose, int bus,
175 int dev_fn, int where, u16 val);
176 extern int early_write_config_dword(struct pci_controller *hose, int bus,
177 int dev_fn, int where, u32 val);
179 extern int early_find_capability(struct pci_controller *hose, int bus,
180 int dev_fn, int cap);
182 extern void setup_indirect_pci(struct pci_controller* hose,
183 resource_size_t cfg_addr,
184 resource_size_t cfg_data, u32 flags);
185 #else /* CONFIG_PPC64 */
188 * PCI stuff, for nodes representing PCI devices, pointed to
189 * by device_node->data.
194 int busno; /* pci bus number */
195 int devfn; /* pci device and function number */
197 struct pci_controller *phb; /* for pci devices */
198 struct iommu_table *iommu_table; /* for phb's or bridges */
199 struct device_node *node; /* back-pointer to the device_node */
201 int pci_ext_config_space; /* for pci devices */
204 struct pci_dev *pcidev; /* back-pointer to the pci device */
205 int class_code; /* pci device class */
206 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
208 int eeh_pe_config_addr; /* new-style partition endpoint address */
209 int eeh_check_count; /* # times driver ignored error */
210 int eeh_freeze_count; /* # times this device froze up. */
211 int eeh_false_positives; /* # times this device reported #ff's */
212 u32 config_space[16]; /* saved PCI config space */
216 /* Get the pointer to a device_node's pci_dn */
217 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
219 extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
220 extern void * update_dn_pci_info(struct device_node *dn, void *data);
222 /* Get a device_node from a pci_dev. This code must be fast except
223 * in the case where the sysdata is incorrect and needs to be fixed
224 * up (this will only happen once).
225 * In this case the sysdata will have been inherited from a PCI host
226 * bridge or a PCI-PCI bridge further up the tree, so it will point
227 * to a valid struct pci_dn, just not the one we want.
229 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
231 struct device_node *dn = dev->sysdata;
232 struct pci_dn *pdn = dn->data;
234 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
235 return dn; /* fast path. sysdata is good */
236 return fetch_dev_dn(dev);
239 static inline int pci_device_from_OF_node(struct device_node *np,
244 *bus = PCI_DN(np)->busno;
245 *devfn = PCI_DN(np)->devfn;
249 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
252 return pci_device_to_OF_node(bus->self);
254 return bus->sysdata; /* Must be root bus (PHB) */
257 /** Find the bus corresponding to the indicated device node */
258 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
260 /** Remove all of the PCI devices under this bus */
261 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
263 /** Discover new pci devices under this bus, and add them */
264 extern void pcibios_add_pci_devices(struct pci_bus *bus);
266 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
268 struct device_node *busdn = bus->sysdata;
270 BUG_ON(busdn == NULL);
271 return PCI_DN(busdn)->phb;
275 extern void isa_bridge_find_early(struct pci_controller *hose);
277 static inline int isa_vaddr_is_ioport(void __iomem *address)
279 /* Check if address hits the reserved legacy IO range */
280 unsigned long ea = (unsigned long)address;
281 return ea >= ISA_IO_BASE && ea < ISA_IO_END;
284 extern int pcibios_unmap_io_space(struct pci_bus *bus);
285 extern int pcibios_map_io_space(struct pci_bus *bus);
287 /* Return values for ppc_md.pci_probe_mode function */
288 #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
289 #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
290 #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
293 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
295 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
298 #endif /* CONFIG_PPC64 */
300 /* Get the PCI host controller for an OF device */
301 extern struct pci_controller *pci_find_hose_for_OF_device(
302 struct device_node* node);
304 /* Fill up host controller resources from the OF node */
305 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
306 struct device_node *dev, int primary);
308 /* Allocate & free a PCI host bridge structure */
309 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
310 extern void pcibios_free_controller(struct pci_controller *phb);
311 extern void pcibios_setup_phb_resources(struct pci_controller *hose);
314 extern unsigned long pci_address_to_pio(phys_addr_t address);
315 extern int pcibios_vaddr_is_ioport(void __iomem *address);
317 static inline unsigned long pci_address_to_pio(phys_addr_t address)
319 return (unsigned long)-1;
321 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
325 #endif /* CONFIG_PCI */
327 #endif /* __KERNEL__ */
328 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */