Merge git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-2.6] / drivers / serial / cpm_uart / cpm_uart_cpm1.c
1 /*
2  *  linux/drivers/serial/cpm_uart.c
3  *
4  *  Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
5  *
6  *  Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
7  *              Pantelis Antoniou (panto@intracom.gr) (CPM1)
8  *
9  *  Copyright (C) 2004 Freescale Semiconductor, Inc.
10  *            (C) 2004 Intracom, S.A.
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2 of the License, or
15  * (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
25  *
26  */
27
28 #include <linux/config.h>
29 #include <linux/module.h>
30 #include <linux/tty.h>
31 #include <linux/ioport.h>
32 #include <linux/init.h>
33 #include <linux/serial.h>
34 #include <linux/console.h>
35 #include <linux/sysrq.h>
36 #include <linux/device.h>
37 #include <linux/bootmem.h>
38 #include <linux/dma-mapping.h>
39
40 #include <asm/io.h>
41 #include <asm/irq.h>
42
43 #include <linux/serial_core.h>
44 #include <linux/kernel.h>
45
46 #include "cpm_uart.h"
47
48 /**************************************************************/
49
50 void cpm_line_cr_cmd(int line, int cmd)
51 {
52         ushort val;
53         volatile cpm8xx_t *cp = cpmp;
54
55         switch (line) {
56         case UART_SMC1:
57                 val = mk_cr_cmd(CPM_CR_CH_SMC1, cmd) | CPM_CR_FLG;
58                 break;
59         case UART_SMC2:
60                 val = mk_cr_cmd(CPM_CR_CH_SMC2, cmd) | CPM_CR_FLG;
61                 break;
62         case UART_SCC1:
63                 val = mk_cr_cmd(CPM_CR_CH_SCC1, cmd) | CPM_CR_FLG;
64                 break;
65         case UART_SCC2:
66                 val = mk_cr_cmd(CPM_CR_CH_SCC2, cmd) | CPM_CR_FLG;
67                 break;
68         case UART_SCC3:
69                 val = mk_cr_cmd(CPM_CR_CH_SCC3, cmd) | CPM_CR_FLG;
70                 break;
71         case UART_SCC4:
72                 val = mk_cr_cmd(CPM_CR_CH_SCC4, cmd) | CPM_CR_FLG;
73                 break;
74         default:
75                 return;
76
77         }
78         cp->cp_cpcr = val;
79         while (cp->cp_cpcr & CPM_CR_FLG) ;
80 }
81
82 void smc1_lineif(struct uart_cpm_port *pinfo)
83 {
84         pinfo->brg = 1;
85 }
86
87 void smc2_lineif(struct uart_cpm_port *pinfo)
88 {
89         pinfo->brg = 2;
90 }
91
92 void scc1_lineif(struct uart_cpm_port *pinfo)
93 {
94         /* XXX SCC1: insert port configuration here */
95         pinfo->brg = 1;
96 }
97
98 void scc2_lineif(struct uart_cpm_port *pinfo)
99 {
100         /* XXX SCC2: insert port configuration here */
101         pinfo->brg = 2;
102 }
103
104 void scc3_lineif(struct uart_cpm_port *pinfo)
105 {
106         /* XXX SCC3: insert port configuration here */
107         pinfo->brg = 3;
108 }
109
110 void scc4_lineif(struct uart_cpm_port *pinfo)
111 {
112         /* XXX SCC4: insert port configuration here */
113         pinfo->brg = 4;
114 }
115
116 /*
117  * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
118  * receive buffer descriptors from dual port ram, and a character
119  * buffer area from host mem. If we are allocating for the console we need
120  * to do it from bootmem
121  */
122 int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
123 {
124         int dpmemsz, memsz;
125         u8 *dp_mem;
126         uint dp_offset;
127         u8 *mem_addr;
128         dma_addr_t dma_addr = 0;
129
130         pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
131
132         dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
133         dp_offset = cpm_dpalloc(dpmemsz, 8);
134         if (IS_DPERR(dp_offset)) {
135                 printk(KERN_ERR
136                        "cpm_uart_cpm1.c: could not allocate buffer descriptors\n");
137                 return -ENOMEM;
138         }
139         dp_mem = cpm_dpram_addr(dp_offset);
140
141         memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
142             L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
143         if (is_con) {
144                 /* was hostalloc but changed cause it blows away the */
145                 /* large tlb mapping when pinning the kernel area    */
146                 mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8));
147                 dma_addr = (u32)mem_addr;
148         } else
149                 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
150                                               GFP_KERNEL);
151
152         if (mem_addr == NULL) {
153                 cpm_dpfree(dp_offset);
154                 printk(KERN_ERR
155                        "cpm_uart_cpm1.c: could not allocate coherent memory\n");
156                 return -ENOMEM;
157         }
158
159         pinfo->dp_addr = dp_offset;
160         pinfo->mem_addr = mem_addr;             /*  virtual address*/
161         pinfo->dma_addr = dma_addr;             /*  physical address*/
162         pinfo->mem_size = memsz;
163
164         pinfo->rx_buf = mem_addr;
165         pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
166                                                        * pinfo->rx_fifosize);
167
168         pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
169         pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
170
171         return 0;
172 }
173
174 void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
175 {
176         dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
177                                                pinfo->rx_fifosize) +
178                           L1_CACHE_ALIGN(pinfo->tx_nrfifos *
179                                          pinfo->tx_fifosize), pinfo->mem_addr,
180                           pinfo->dma_addr);
181
182         cpm_dpfree(pinfo->dp_addr);
183 }
184
185 /* Setup any dynamic params in the uart desc */
186 int cpm_uart_init_portdesc(void)
187 {
188         pr_debug("CPM uart[-]:init portdesc\n");
189
190         cpm_uart_nr = 0;
191 #ifdef CONFIG_SERIAL_CPM_SMC1
192         cpm_uart_ports[UART_SMC1].smcp = &cpmp->cp_smc[0];
193 /*
194  *  Is SMC1 being relocated?
195  */
196 # ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH
197         cpm_uart_ports[UART_SMC1].smcup =
198             (smc_uart_t *) & cpmp->cp_dparam[0x3C0];
199 # else
200         cpm_uart_ports[UART_SMC1].smcup =
201             (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC1];
202 # endif
203         cpm_uart_ports[UART_SMC1].port.mapbase =
204             (unsigned long)&cpmp->cp_smc[0];
205         cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
206         cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
207         cpm_uart_ports[UART_SMC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
208         cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
209 #endif
210
211 #ifdef CONFIG_SERIAL_CPM_SMC2
212         cpm_uart_ports[UART_SMC2].smcp = &cpmp->cp_smc[1];
213         cpm_uart_ports[UART_SMC2].smcup =
214             (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC2];
215         cpm_uart_ports[UART_SMC2].port.mapbase =
216             (unsigned long)&cpmp->cp_smc[1];
217         cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
218         cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
219         cpm_uart_ports[UART_SMC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
220         cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
221 #endif
222
223 #ifdef CONFIG_SERIAL_CPM_SCC1
224         cpm_uart_ports[UART_SCC1].sccp = &cpmp->cp_scc[0];
225         cpm_uart_ports[UART_SCC1].sccup =
226             (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC1];
227         cpm_uart_ports[UART_SCC1].port.mapbase =
228             (unsigned long)&cpmp->cp_scc[0];
229         cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
230             ~(UART_SCCM_TX | UART_SCCM_RX);
231         cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
232             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
233         cpm_uart_ports[UART_SCC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
234         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
235 #endif
236
237 #ifdef CONFIG_SERIAL_CPM_SCC2
238         cpm_uart_ports[UART_SCC2].sccp = &cpmp->cp_scc[1];
239         cpm_uart_ports[UART_SCC2].sccup =
240             (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC2];
241         cpm_uart_ports[UART_SCC2].port.mapbase =
242             (unsigned long)&cpmp->cp_scc[1];
243         cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
244             ~(UART_SCCM_TX | UART_SCCM_RX);
245         cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
246             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
247         cpm_uart_ports[UART_SCC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
248         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
249 #endif
250
251 #ifdef CONFIG_SERIAL_CPM_SCC3
252         cpm_uart_ports[UART_SCC3].sccp = &cpmp->cp_scc[2];
253         cpm_uart_ports[UART_SCC3].sccup =
254             (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC3];
255         cpm_uart_ports[UART_SCC3].port.mapbase =
256             (unsigned long)&cpmp->cp_scc[2];
257         cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
258             ~(UART_SCCM_TX | UART_SCCM_RX);
259         cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
260             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
261         cpm_uart_ports[UART_SCC3].port.uartclk = (((bd_t *) __res)->bi_intfreq);
262         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
263 #endif
264
265 #ifdef CONFIG_SERIAL_CPM_SCC4
266         cpm_uart_ports[UART_SCC4].sccp = &cpmp->cp_scc[3];
267         cpm_uart_ports[UART_SCC4].sccup =
268             (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC4];
269         cpm_uart_ports[UART_SCC4].port.mapbase =
270             (unsigned long)&cpmp->cp_scc[3];
271         cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
272             ~(UART_SCCM_TX | UART_SCCM_RX);
273         cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
274             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
275         cpm_uart_ports[UART_SCC4].port.uartclk = (((bd_t *) __res)->bi_intfreq);
276         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
277 #endif
278         return 0;
279 }