2 * Freescale MPC85xx/MPC86xx RapidIO support
4 * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
5 * Zhang Wei <wei.zhang@freescale.com>
7 * Copyright 2005 MontaVista Software, Inc.
8 * Matt Porter <mporter@kernel.crashing.org>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/interrupt.h>
21 #include <linux/device.h>
22 #include <linux/rio.h>
23 #include <linux/rio_drv.h>
24 #include <linux/of_platform.h>
25 #include <linux/delay.h>
29 /* RapidIO definition irq, which read from OF-tree */
30 #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq)
31 #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq)
32 #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
34 #define RIO_ATMU_REGS_OFFSET 0x10c00
35 #define RIO_P_MSG_REGS_OFFSET 0x11000
36 #define RIO_S_MSG_REGS_OFFSET 0x13000
37 #define RIO_ESCSR 0x158
38 #define RIO_CCSR 0x15c
39 #define RIO_ISR_AACR 0x10120
40 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
41 #define RIO_MAINT_WIN_SIZE 0x400000
42 #define RIO_DBELL_WIN_SIZE 0x1000
44 #define RIO_MSG_OMR_MUI 0x00000002
45 #define RIO_MSG_OSR_TE 0x00000080
46 #define RIO_MSG_OSR_QOI 0x00000020
47 #define RIO_MSG_OSR_QFI 0x00000010
48 #define RIO_MSG_OSR_MUB 0x00000004
49 #define RIO_MSG_OSR_EOMI 0x00000002
50 #define RIO_MSG_OSR_QEI 0x00000001
52 #define RIO_MSG_IMR_MI 0x00000002
53 #define RIO_MSG_ISR_TE 0x00000080
54 #define RIO_MSG_ISR_QFI 0x00000010
55 #define RIO_MSG_ISR_DIQI 0x00000001
57 #define RIO_MSG_DESC_SIZE 32
58 #define RIO_MSG_BUFFER_SIZE 4096
59 #define RIO_MIN_TX_RING_SIZE 2
60 #define RIO_MAX_TX_RING_SIZE 2048
61 #define RIO_MIN_RX_RING_SIZE 2
62 #define RIO_MAX_RX_RING_SIZE 2048
64 #define DOORBELL_DMR_DI 0x00000002
65 #define DOORBELL_DSR_TE 0x00000080
66 #define DOORBELL_DSR_QFI 0x00000010
67 #define DOORBELL_DSR_DIQI 0x00000001
68 #define DOORBELL_TID_OFFSET 0x02
69 #define DOORBELL_SID_OFFSET 0x04
70 #define DOORBELL_INFO_OFFSET 0x06
72 #define DOORBELL_MESSAGE_SIZE 0x08
73 #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
74 #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
75 #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
77 struct rio_atmu_regs {
138 struct rio_dbell_ring {
143 struct rio_msg_tx_ring {
146 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
147 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
153 struct rio_msg_rx_ring {
156 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
164 void __iomem *regs_win;
165 struct rio_atmu_regs __iomem *atmu_regs;
166 struct rio_atmu_regs __iomem *maint_atmu_regs;
167 struct rio_atmu_regs __iomem *dbell_atmu_regs;
168 void __iomem *dbell_win;
169 void __iomem *maint_win;
170 struct rio_msg_regs __iomem *msg_regs;
171 struct rio_dbell_ring dbell_ring;
172 struct rio_msg_tx_ring msg_tx_ring;
173 struct rio_msg_rx_ring msg_rx_ring;
180 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
181 * @mport: RapidIO master port info
182 * @index: ID of RapidIO interface
183 * @destid: Destination ID of target device
184 * @data: 16-bit info field of RapidIO doorbell message
186 * Sends a MPC85xx doorbell message. Returns %0 on success or
187 * %-EINVAL on failure.
189 static int fsl_rio_doorbell_send(struct rio_mport *mport,
190 int index, u16 destid, u16 data)
192 struct rio_priv *priv = mport->priv;
193 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
194 index, destid, data);
195 switch (mport->phy_type) {
196 case RIO_PHY_PARALLEL:
197 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
198 out_be16(priv->dbell_win, data);
201 /* In the serial version silicons, such as MPC8548, MPC8641,
202 * below operations is must be.
204 out_be32(&priv->msg_regs->odmr, 0x00000000);
205 out_be32(&priv->msg_regs->odretcr, 0x00000004);
206 out_be32(&priv->msg_regs->oddpr, destid << 16);
207 out_be32(&priv->msg_regs->oddatr, data);
208 out_be32(&priv->msg_regs->odmr, 0x00000001);
216 * fsl_local_config_read - Generate a MPC85xx local config space read
217 * @mport: RapidIO master port info
218 * @index: ID of RapdiIO interface
219 * @offset: Offset into configuration space
220 * @len: Length (in bytes) of the maintenance transaction
221 * @data: Value to be read into
223 * Generates a MPC85xx local configuration space read. Returns %0 on
224 * success or %-EINVAL on failure.
226 static int fsl_local_config_read(struct rio_mport *mport,
227 int index, u32 offset, int len, u32 *data)
229 struct rio_priv *priv = mport->priv;
230 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
232 *data = in_be32(priv->regs_win + offset);
238 * fsl_local_config_write - Generate a MPC85xx local config space write
239 * @mport: RapidIO master port info
240 * @index: ID of RapdiIO interface
241 * @offset: Offset into configuration space
242 * @len: Length (in bytes) of the maintenance transaction
243 * @data: Value to be written
245 * Generates a MPC85xx local configuration space write. Returns %0 on
246 * success or %-EINVAL on failure.
248 static int fsl_local_config_write(struct rio_mport *mport,
249 int index, u32 offset, int len, u32 data)
251 struct rio_priv *priv = mport->priv;
253 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
254 index, offset, data);
255 out_be32(priv->regs_win + offset, data);
261 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
262 * @mport: RapidIO master port info
263 * @index: ID of RapdiIO interface
264 * @destid: Destination ID of transaction
265 * @hopcount: Number of hops to target device
266 * @offset: Offset into configuration space
267 * @len: Length (in bytes) of the maintenance transaction
268 * @val: Location to be read into
270 * Generates a MPC85xx read maintenance transaction. Returns %0 on
271 * success or %-EINVAL on failure.
274 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
275 u8 hopcount, u32 offset, int len, u32 *val)
277 struct rio_priv *priv = mport->priv;
281 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
282 index, destid, hopcount, offset, len);
283 out_be32(&priv->maint_atmu_regs->rowtar,
284 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
286 data = (u8 *) priv->maint_win + offset;
289 *val = in_8((u8 *) data);
292 *val = in_be16((u16 *) data);
295 *val = in_be32((u32 *) data);
303 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
304 * @mport: RapidIO master port info
305 * @index: ID of RapdiIO interface
306 * @destid: Destination ID of transaction
307 * @hopcount: Number of hops to target device
308 * @offset: Offset into configuration space
309 * @len: Length (in bytes) of the maintenance transaction
310 * @val: Value to be written
312 * Generates an MPC85xx write maintenance transaction. Returns %0 on
313 * success or %-EINVAL on failure.
316 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
317 u8 hopcount, u32 offset, int len, u32 val)
319 struct rio_priv *priv = mport->priv;
322 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
323 index, destid, hopcount, offset, len, val);
324 out_be32(&priv->maint_atmu_regs->rowtar,
325 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
327 data = (u8 *) priv->maint_win + offset;
330 out_8((u8 *) data, val);
333 out_be16((u16 *) data, val);
336 out_be32((u32 *) data, val);
344 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
345 * @mport: Master port with outbound message queue
346 * @rdev: Target of outbound message
347 * @mbox: Outbound mailbox
348 * @buffer: Message to add to outbound queue
349 * @len: Length of message
351 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
352 * %0 on success or %-EINVAL on failure.
355 rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
356 void *buffer, size_t len)
358 struct rio_priv *priv = mport->priv;
360 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
361 + priv->msg_tx_ring.tx_slot;
365 ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
366 rdev->destid, mbox, (int)buffer, len);
368 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
373 /* Copy and clear rest of buffer */
374 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
376 if (len < (RIO_MAX_MSG_SIZE - 4))
377 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
378 + len, 0, RIO_MAX_MSG_SIZE - len);
380 switch (mport->phy_type) {
381 case RIO_PHY_PARALLEL:
382 /* Set mbox field for message */
383 desc->dport = mbox & 0x3;
385 /* Enable EOMI interrupt, set priority, and set destid */
386 desc->dattr = 0x28000000 | (rdev->destid << 2);
389 /* Set mbox field for message, and set destid */
390 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
392 /* Enable EOMI interrupt and priority */
393 desc->dattr = 0x28000000;
397 /* Set transfer size aligned to next power of 2 (in double words) */
398 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
400 /* Set snooping and source buffer address */
401 desc->saddr = 0x00000004
402 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
404 /* Increment enqueue pointer */
405 omr = in_be32(&priv->msg_regs->omr);
406 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
408 /* Go to next descriptor */
409 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
410 priv->msg_tx_ring.tx_slot = 0;
416 EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
419 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
420 * @irq: Linux interrupt number
421 * @dev_instance: Pointer to interrupt-specific data
423 * Handles outbound message interrupts. Executes a register outbound
424 * mailbox event handler and acks the interrupt occurrence.
427 fsl_rio_tx_handler(int irq, void *dev_instance)
430 struct rio_mport *port = (struct rio_mport *)dev_instance;
431 struct rio_priv *priv = port->priv;
433 osr = in_be32(&priv->msg_regs->osr);
435 if (osr & RIO_MSG_OSR_TE) {
436 pr_info("RIO: outbound message transmission error\n");
437 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
441 if (osr & RIO_MSG_OSR_QOI) {
442 pr_info("RIO: outbound message queue overflow\n");
443 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
447 if (osr & RIO_MSG_OSR_EOMI) {
448 u32 dqp = in_be32(&priv->msg_regs->odqdpar);
449 int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
450 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
453 /* Ack the end-of-message interrupt */
454 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
462 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
463 * @mport: Master port implementing the outbound message unit
464 * @dev_id: Device specific pointer to pass on event
465 * @mbox: Mailbox to open
466 * @entries: Number of entries in the outbound mailbox ring
468 * Initializes buffer ring, request the outbound message interrupt,
469 * and enables the outbound message unit. Returns %0 on success and
470 * %-EINVAL or %-ENOMEM on failure.
472 int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
475 struct rio_priv *priv = mport->priv;
477 if ((entries < RIO_MIN_TX_RING_SIZE) ||
478 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
483 /* Initialize shadow copy ring */
484 priv->msg_tx_ring.dev_id = dev_id;
485 priv->msg_tx_ring.size = entries;
487 for (i = 0; i < priv->msg_tx_ring.size; i++) {
488 priv->msg_tx_ring.virt_buffer[i] =
489 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
490 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
491 if (!priv->msg_tx_ring.virt_buffer[i]) {
493 for (j = 0; j < priv->msg_tx_ring.size; j++)
494 if (priv->msg_tx_ring.virt_buffer[j])
495 dma_free_coherent(priv->dev,
505 /* Initialize outbound message descriptor ring */
506 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
507 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
508 &priv->msg_tx_ring.phys, GFP_KERNEL);
509 if (!priv->msg_tx_ring.virt) {
513 memset(priv->msg_tx_ring.virt, 0,
514 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
515 priv->msg_tx_ring.tx_slot = 0;
517 /* Point dequeue/enqueue pointers at first entry in ring */
518 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
519 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
521 /* Configure for snooping */
522 out_be32(&priv->msg_regs->osar, 0x00000004);
524 /* Clear interrupt status */
525 out_be32(&priv->msg_regs->osr, 0x000000b3);
527 /* Hook up outbound message handler */
528 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
529 "msg_tx", (void *)mport);
534 * Configure outbound message unit
536 * Interrupts (all enabled, except QEIE)
540 out_be32(&priv->msg_regs->omr, 0x00100220);
542 /* Set number of entries */
543 out_be32(&priv->msg_regs->omr,
544 in_be32(&priv->msg_regs->omr) |
545 ((get_bitmask_order(entries) - 2) << 12));
547 /* Now enable the unit */
548 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
554 dma_free_coherent(priv->dev,
555 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
556 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
559 for (i = 0; i < priv->msg_tx_ring.size; i++)
560 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
561 priv->msg_tx_ring.virt_buffer[i],
562 priv->msg_tx_ring.phys_buffer[i]);
568 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
569 * @mport: Master port implementing the outbound message unit
570 * @mbox: Mailbox to close
572 * Disables the outbound message unit, free all buffers, and
573 * frees the outbound message interrupt.
575 void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
577 struct rio_priv *priv = mport->priv;
578 /* Disable inbound message unit */
579 out_be32(&priv->msg_regs->omr, 0);
582 dma_free_coherent(priv->dev,
583 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
584 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
587 free_irq(IRQ_RIO_TX(mport), (void *)mport);
591 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
592 * @irq: Linux interrupt number
593 * @dev_instance: Pointer to interrupt-specific data
595 * Handles inbound message interrupts. Executes a registered inbound
596 * mailbox event handler and acks the interrupt occurrence.
599 fsl_rio_rx_handler(int irq, void *dev_instance)
602 struct rio_mport *port = (struct rio_mport *)dev_instance;
603 struct rio_priv *priv = port->priv;
605 isr = in_be32(&priv->msg_regs->isr);
607 if (isr & RIO_MSG_ISR_TE) {
608 pr_info("RIO: inbound message reception error\n");
609 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
613 /* XXX Need to check/dispatch until queue empty */
614 if (isr & RIO_MSG_ISR_DIQI) {
616 * We implement *only* mailbox 0, but can receive messages
617 * for any mailbox/letter to that mailbox destination. So,
618 * make the callback with an unknown/invalid mailbox number
621 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
623 /* Ack the queueing interrupt */
624 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
632 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
633 * @mport: Master port implementing the inbound message unit
634 * @dev_id: Device specific pointer to pass on event
635 * @mbox: Mailbox to open
636 * @entries: Number of entries in the inbound mailbox ring
638 * Initializes buffer ring, request the inbound message interrupt,
639 * and enables the inbound message unit. Returns %0 on success
640 * and %-EINVAL or %-ENOMEM on failure.
642 int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
645 struct rio_priv *priv = mport->priv;
647 if ((entries < RIO_MIN_RX_RING_SIZE) ||
648 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
653 /* Initialize client buffer ring */
654 priv->msg_rx_ring.dev_id = dev_id;
655 priv->msg_rx_ring.size = entries;
656 priv->msg_rx_ring.rx_slot = 0;
657 for (i = 0; i < priv->msg_rx_ring.size; i++)
658 priv->msg_rx_ring.virt_buffer[i] = NULL;
660 /* Initialize inbound message ring */
661 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
662 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
663 &priv->msg_rx_ring.phys, GFP_KERNEL);
664 if (!priv->msg_rx_ring.virt) {
669 /* Point dequeue/enqueue pointers at first entry in ring */
670 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
671 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
673 /* Clear interrupt status */
674 out_be32(&priv->msg_regs->isr, 0x00000091);
676 /* Hook up inbound message handler */
677 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
678 "msg_rx", (void *)mport);
680 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
681 priv->msg_tx_ring.virt_buffer[i],
682 priv->msg_tx_ring.phys_buffer[i]);
687 * Configure inbound message unit:
689 * 4KB max message size
690 * Unmask all interrupt sources
693 out_be32(&priv->msg_regs->imr, 0x001b0060);
695 /* Set number of queue entries */
696 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
698 /* Now enable the unit */
699 setbits32(&priv->msg_regs->imr, 0x1);
706 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
707 * @mport: Master port implementing the inbound message unit
708 * @mbox: Mailbox to close
710 * Disables the inbound message unit, free all buffers, and
711 * frees the inbound message interrupt.
713 void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
715 struct rio_priv *priv = mport->priv;
716 /* Disable inbound message unit */
717 out_be32(&priv->msg_regs->imr, 0);
720 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
721 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
724 free_irq(IRQ_RIO_RX(mport), (void *)mport);
728 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
729 * @mport: Master port implementing the inbound message unit
730 * @mbox: Inbound mailbox number
731 * @buf: Buffer to add to inbound queue
733 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
734 * %0 on success or %-EINVAL on failure.
736 int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
739 struct rio_priv *priv = mport->priv;
741 pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
742 priv->msg_rx_ring.rx_slot);
744 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
746 "RIO: error adding inbound buffer %d, buffer exists\n",
747 priv->msg_rx_ring.rx_slot);
752 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
753 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
754 priv->msg_rx_ring.rx_slot = 0;
760 EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
763 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
764 * @mport: Master port implementing the inbound message unit
765 * @mbox: Inbound mailbox number
767 * Gets the next available inbound message from the inbound message queue.
768 * A pointer to the message is returned on success or NULL on failure.
770 void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
772 struct rio_priv *priv = mport->priv;
773 u32 phys_buf, virt_buf;
777 phys_buf = in_be32(&priv->msg_regs->ifqdpar);
779 /* If no more messages, then bail out */
780 if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
783 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
784 - priv->msg_rx_ring.phys);
785 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
786 buf = priv->msg_rx_ring.virt_buffer[buf_idx];
790 "RIO: inbound message copy failed, no buffers\n");
794 /* Copy max message size, caller is expected to allocate that big */
795 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
797 /* Clear the available buffer */
798 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
801 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
807 EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
810 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
811 * @irq: Linux interrupt number
812 * @dev_instance: Pointer to interrupt-specific data
814 * Handles doorbell interrupts. Parses a list of registered
815 * doorbell event handlers and executes a matching event handler.
818 fsl_rio_dbell_handler(int irq, void *dev_instance)
821 struct rio_mport *port = (struct rio_mport *)dev_instance;
822 struct rio_priv *priv = port->priv;
824 dsr = in_be32(&priv->msg_regs->dsr);
826 if (dsr & DOORBELL_DSR_TE) {
827 pr_info("RIO: doorbell reception error\n");
828 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
832 if (dsr & DOORBELL_DSR_QFI) {
833 pr_info("RIO: doorbell queue full\n");
834 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
838 /* XXX Need to check/dispatch until queue empty */
839 if (dsr & DOORBELL_DSR_DIQI) {
841 (u32) priv->dbell_ring.virt +
842 (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
843 struct rio_dbell *dbell;
847 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
848 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
850 list_for_each_entry(dbell, &port->dbells, node) {
851 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
852 (dbell->res->end >= DBELL_INF(dmsg))) {
858 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
862 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
863 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
865 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
866 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
874 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
875 * @mport: Master port implementing the inbound doorbell unit
877 * Initializes doorbell unit hardware and inbound DMA buffer
878 * ring. Called from fsl_rio_setup(). Returns %0 on success
879 * or %-ENOMEM on failure.
881 static int fsl_rio_doorbell_init(struct rio_mport *mport)
883 struct rio_priv *priv = mport->priv;
886 /* Map outbound doorbell window immediately after maintenance window */
887 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
889 if (!priv->dbell_win) {
891 "RIO: unable to map outbound doorbell window\n");
896 /* Initialize inbound doorbells */
897 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
898 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
899 if (!priv->dbell_ring.virt) {
900 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
902 iounmap(priv->dbell_win);
906 /* Point dequeue/enqueue pointers at first entry in ring */
907 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
908 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
910 /* Clear interrupt status */
911 out_be32(&priv->msg_regs->dsr, 0x00000091);
913 /* Hook up doorbell handler */
914 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
915 "dbell_rx", (void *)mport);
917 iounmap(priv->dbell_win);
918 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
919 priv->dbell_ring.virt, priv->dbell_ring.phys);
921 "MPC85xx RIO: unable to request inbound doorbell irq");
925 /* Configure doorbells for snooping, 512 entries, and enable */
926 out_be32(&priv->msg_regs->dmr, 0x00108161);
932 static char *cmdline = NULL;
934 static int fsl_rio_get_hdid(int index)
936 /* XXX Need to parse multiple entries in some format */
940 return simple_strtol(cmdline, NULL, 0);
943 static int fsl_rio_get_cmdline(char *s)
952 __setup("riohdid=", fsl_rio_get_cmdline);
954 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
959 switch (ccsr >> 30) {
970 dev_info(dev, "Hardware port width: %s\n", str);
972 switch ((ccsr >> 27) & 7) {
974 str = "Single-lane 0";
977 str = "Single-lane 2";
986 dev_info(dev, "Training connection status: %s\n", str);
989 if (!(ccsr & 0x80000000))
990 dev_info(dev, "Output port operating in 8-bit mode\n");
991 if (!(ccsr & 0x08000000))
992 dev_info(dev, "Input port operating in 8-bit mode\n");
997 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
998 * @dev: of_device pointer
1000 * Initializes MPC85xx RapidIO hardware interface, configures
1001 * master port with system-specific info, and registers the
1002 * master port with the RapidIO subsystem.
1004 int fsl_rio_setup(struct of_device *dev)
1006 struct rio_ops *ops;
1007 struct rio_mport *port;
1008 struct rio_priv *priv;
1010 const u32 *dt_range, *cell;
1011 struct resource regs;
1014 u64 law_start, law_size;
1018 dev_err(&dev->dev, "Device OF-Node is NULL");
1022 rc = of_address_to_resource(dev->node, 0, ®s);
1024 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1025 dev->node->full_name);
1028 dev_info(&dev->dev, "Of-device full name %s\n", dev->node->full_name);
1029 dev_info(&dev->dev, "Regs: %pR\n", ®s);
1031 dt_range = of_get_property(dev->node, "ranges", &rlen);
1033 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
1034 dev->node->full_name);
1038 /* Get node address wide */
1039 cell = of_get_property(dev->node, "#address-cells", NULL);
1043 aw = of_n_addr_cells(dev->node);
1044 /* Get node size wide */
1045 cell = of_get_property(dev->node, "#size-cells", NULL);
1049 sw = of_n_size_cells(dev->node);
1050 /* Get parent address wide wide */
1051 paw = of_n_addr_cells(dev->node);
1053 law_start = of_read_number(dt_range + aw, paw);
1054 law_size = of_read_number(dt_range + aw + paw, sw);
1056 dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
1057 law_start, law_size);
1059 ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
1060 ops->lcread = fsl_local_config_read;
1061 ops->lcwrite = fsl_local_config_write;
1062 ops->cread = fsl_rio_config_read;
1063 ops->cwrite = fsl_rio_config_write;
1064 ops->dsend = fsl_rio_doorbell_send;
1066 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
1070 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
1072 printk(KERN_ERR "Can't alloc memory for 'priv'\n");
1077 INIT_LIST_HEAD(&port->dbells);
1078 port->iores.start = law_start;
1079 port->iores.end = law_start + law_size - 1;
1080 port->iores.flags = IORESOURCE_MEM;
1081 port->iores.name = "rio_io_win";
1083 priv->bellirq = irq_of_parse_and_map(dev->node, 2);
1084 priv->txirq = irq_of_parse_and_map(dev->node, 3);
1085 priv->rxirq = irq_of_parse_and_map(dev->node, 4);
1086 dev_info(&dev->dev, "bellirq: %d, txirq: %d, rxirq %d\n", priv->bellirq,
1087 priv->txirq, priv->rxirq);
1089 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1090 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1091 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1092 strcpy(port->name, "RIO0 mport");
1094 priv->dev = &dev->dev;
1097 port->host_deviceid = fsl_rio_get_hdid(port->id);
1100 rio_register_mport(port);
1102 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
1104 /* Probe the master port phy type */
1105 ccsr = in_be32(priv->regs_win + RIO_CCSR);
1106 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
1107 dev_info(&dev->dev, "RapidIO PHY type: %s\n",
1108 (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" :
1109 ((port->phy_type == RIO_PHY_SERIAL) ? "serial" :
1111 /* Checking the port training status */
1112 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1113 dev_err(&dev->dev, "Port is not ready. "
1114 "Try to restart connection...\n");
1115 switch (port->phy_type) {
1116 case RIO_PHY_SERIAL:
1118 out_be32(priv->regs_win + RIO_CCSR, 0);
1120 setbits32(priv->regs_win + RIO_CCSR, 0x02000000);
1122 setbits32(priv->regs_win + RIO_CCSR, 0x00600000);
1124 case RIO_PHY_PARALLEL:
1126 out_be32(priv->regs_win + RIO_CCSR, 0x22000000);
1128 out_be32(priv->regs_win + RIO_CCSR, 0x44000000);
1132 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1133 dev_err(&dev->dev, "Port restart failed.\n");
1137 dev_info(&dev->dev, "Port restart success!\n");
1139 fsl_rio_info(&dev->dev, ccsr);
1141 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
1142 & RIO_PEF_CTLS) >> 4;
1143 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
1144 port->sys_size ? 65536 : 256);
1146 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
1147 + RIO_ATMU_REGS_OFFSET);
1148 priv->maint_atmu_regs = priv->atmu_regs + 1;
1149 priv->dbell_atmu_regs = priv->atmu_regs + 2;
1150 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1151 ((port->phy_type == RIO_PHY_SERIAL) ?
1152 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1154 /* Set to receive any dist ID for serial RapidIO controller. */
1155 if (port->phy_type == RIO_PHY_SERIAL)
1156 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
1158 /* Configure maintenance transaction window */
1159 out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12);
1160 out_be32(&priv->maint_atmu_regs->rowar, 0x80077015); /* 4M */
1162 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
1164 /* Configure outbound doorbell window */
1165 out_be32(&priv->dbell_atmu_regs->rowbar,
1166 (law_start + RIO_MAINT_WIN_SIZE) >> 12);
1167 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */
1168 fsl_rio_doorbell_init(port);
1173 iounmap(priv->regs_win);
1180 /* The probe function for RapidIO peer-to-peer network.
1182 static int __devinit fsl_of_rio_rpn_probe(struct of_device *dev,
1183 const struct of_device_id *match)
1186 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
1187 dev->node->full_name);
1189 rc = fsl_rio_setup(dev);
1193 /* Enumerate all registered ports */
1194 rc = rio_init_mports();
1199 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
1201 .compatible = "fsl,rapidio-delta",
1206 static struct of_platform_driver fsl_of_rio_rpn_driver = {
1207 .name = "fsl-of-rio",
1208 .match_table = fsl_of_rio_rpn_ids,
1209 .probe = fsl_of_rio_rpn_probe,
1212 static __init int fsl_of_rio_rpn_init(void)
1214 return of_register_platform_driver(&fsl_of_rio_rpn_driver);
1217 subsys_initcall(fsl_of_rio_rpn_init);