Merge git://oss.sgi.com:8090/oss/git/xfs-2.6
[linux-2.6] / drivers / media / dvb / frontends / tda1004x.c
1   /*
2      Driver for Philips tda1004xh OFDM Demodulator
3
4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
5
6      This program is free software; you can redistribute it and/or modify
7      it under the terms of the GNU General Public License as published by
8      the Free Software Foundation; either version 2 of the License, or
9      (at your option) any later version.
10
11      This program is distributed in the hope that it will be useful,
12      but WITHOUT ANY WARRANTY; without even the implied warranty of
13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
15      GNU General Public License for more details.
16
17      You should have received a copy of the GNU General Public License
18      along with this program; if not, write to the Free Software
19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21    */
22 /*
23  * This driver needs external firmware. Please use the commands
24  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
25  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
26  * download/extract them, and then copy them to /usr/lib/hotplug/firmware
27  * or /lib/firmware (depending on configuration of firmware hotplug).
28  */
29 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
30 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
31
32 #include <linux/init.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/device.h>
36 #include <linux/jiffies.h>
37 #include <linux/string.h>
38 #include <linux/slab.h>
39
40 #include "dvb_frontend.h"
41 #include "tda1004x.h"
42
43 enum tda1004x_demod {
44         TDA1004X_DEMOD_TDA10045,
45         TDA1004X_DEMOD_TDA10046,
46 };
47
48 struct tda1004x_state {
49         struct i2c_adapter* i2c;
50         struct dvb_frontend_ops ops;
51         const struct tda1004x_config* config;
52         struct dvb_frontend frontend;
53
54         /* private demod data */
55         u8 initialised;
56         enum tda1004x_demod demod_type;
57 };
58
59 static int debug;
60 #define dprintk(args...) \
61         do { \
62                 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
63         } while (0)
64
65 #define TDA1004X_CHIPID          0x00
66 #define TDA1004X_AUTO            0x01
67 #define TDA1004X_IN_CONF1        0x02
68 #define TDA1004X_IN_CONF2        0x03
69 #define TDA1004X_OUT_CONF1       0x04
70 #define TDA1004X_OUT_CONF2       0x05
71 #define TDA1004X_STATUS_CD       0x06
72 #define TDA1004X_CONFC4          0x07
73 #define TDA1004X_DSSPARE2        0x0C
74 #define TDA10045H_CODE_IN        0x0D
75 #define TDA10045H_FWPAGE         0x0E
76 #define TDA1004X_SCAN_CPT        0x10
77 #define TDA1004X_DSP_CMD         0x11
78 #define TDA1004X_DSP_ARG         0x12
79 #define TDA1004X_DSP_DATA1       0x13
80 #define TDA1004X_DSP_DATA2       0x14
81 #define TDA1004X_CONFADC1        0x15
82 #define TDA1004X_CONFC1          0x16
83 #define TDA10045H_S_AGC          0x1a
84 #define TDA10046H_AGC_TUN_LEVEL  0x1a
85 #define TDA1004X_SNR             0x1c
86 #define TDA1004X_CONF_TS1        0x1e
87 #define TDA1004X_CONF_TS2        0x1f
88 #define TDA1004X_CBER_RESET      0x20
89 #define TDA1004X_CBER_MSB        0x21
90 #define TDA1004X_CBER_LSB        0x22
91 #define TDA1004X_CVBER_LUT       0x23
92 #define TDA1004X_VBER_MSB        0x24
93 #define TDA1004X_VBER_MID        0x25
94 #define TDA1004X_VBER_LSB        0x26
95 #define TDA1004X_UNCOR           0x27
96
97 #define TDA10045H_CONFPLL_P      0x2D
98 #define TDA10045H_CONFPLL_M_MSB  0x2E
99 #define TDA10045H_CONFPLL_M_LSB  0x2F
100 #define TDA10045H_CONFPLL_N      0x30
101
102 #define TDA10046H_CONFPLL1       0x2D
103 #define TDA10046H_CONFPLL2       0x2F
104 #define TDA10046H_CONFPLL3       0x30
105 #define TDA10046H_TIME_WREF1     0x31
106 #define TDA10046H_TIME_WREF2     0x32
107 #define TDA10046H_TIME_WREF3     0x33
108 #define TDA10046H_TIME_WREF4     0x34
109 #define TDA10046H_TIME_WREF5     0x35
110
111 #define TDA10045H_UNSURW_MSB     0x31
112 #define TDA10045H_UNSURW_LSB     0x32
113 #define TDA10045H_WREF_MSB       0x33
114 #define TDA10045H_WREF_MID       0x34
115 #define TDA10045H_WREF_LSB       0x35
116 #define TDA10045H_MUXOUT         0x36
117 #define TDA1004X_CONFADC2        0x37
118
119 #define TDA10045H_IOFFSET        0x38
120
121 #define TDA10046H_CONF_TRISTATE1 0x3B
122 #define TDA10046H_CONF_TRISTATE2 0x3C
123 #define TDA10046H_CONF_POLARITY  0x3D
124 #define TDA10046H_FREQ_OFFSET    0x3E
125 #define TDA10046H_GPIO_OUT_SEL   0x41
126 #define TDA10046H_GPIO_SELECT    0x42
127 #define TDA10046H_AGC_CONF       0x43
128 #define TDA10046H_AGC_THR        0x44
129 #define TDA10046H_AGC_RENORM     0x45
130 #define TDA10046H_AGC_GAINS      0x46
131 #define TDA10046H_AGC_TUN_MIN    0x47
132 #define TDA10046H_AGC_TUN_MAX    0x48
133 #define TDA10046H_AGC_IF_MIN     0x49
134 #define TDA10046H_AGC_IF_MAX     0x4A
135
136 #define TDA10046H_FREQ_PHY2_MSB  0x4D
137 #define TDA10046H_FREQ_PHY2_LSB  0x4E
138
139 #define TDA10046H_CVBER_CTRL     0x4F
140 #define TDA10046H_AGC_IF_LEVEL   0x52
141 #define TDA10046H_CODE_CPT       0x57
142 #define TDA10046H_CODE_IN        0x58
143
144
145 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
146 {
147         int ret;
148         u8 buf[] = { reg, data };
149         struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
150
151         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
152
153         msg.addr = state->config->demod_address;
154         ret = i2c_transfer(state->i2c, &msg, 1);
155
156         if (ret != 1)
157                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
158                         __FUNCTION__, reg, data, ret);
159
160         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
161                 reg, data, ret);
162         return (ret != 1) ? -1 : 0;
163 }
164
165 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
166 {
167         int ret;
168         u8 b0[] = { reg };
169         u8 b1[] = { 0 };
170         struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
171                                 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
172
173         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
174
175         msg[0].addr = state->config->demod_address;
176         msg[1].addr = state->config->demod_address;
177         ret = i2c_transfer(state->i2c, msg, 2);
178
179         if (ret != 2) {
180                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
181                         ret);
182                 return -1;
183         }
184
185         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
186                 reg, b1[0], ret);
187         return b1[0];
188 }
189
190 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
191 {
192         int val;
193         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
194                 mask, data);
195
196         // read a byte and check
197         val = tda1004x_read_byte(state, reg);
198         if (val < 0)
199                 return val;
200
201         // mask if off
202         val = val & ~mask;
203         val |= data & 0xff;
204
205         // write it out again
206         return tda1004x_write_byteI(state, reg, val);
207 }
208
209 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
210 {
211         int i;
212         int result;
213
214         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
215
216         result = 0;
217         for (i = 0; i < len; i++) {
218                 result = tda1004x_write_byteI(state, reg + i, buf[i]);
219                 if (result != 0)
220                         break;
221         }
222
223         return result;
224 }
225
226 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
227 {
228         int result;
229         dprintk("%s\n", __FUNCTION__);
230
231         result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
232         msleep(1);
233         return result;
234 }
235
236 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
237 {
238         dprintk("%s\n", __FUNCTION__);
239
240         return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
241 }
242
243 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
244                                    fe_bandwidth_t bandwidth)
245 {
246         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
247         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
248         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
249
250         switch (bandwidth) {
251         case BANDWIDTH_6_MHZ:
252                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
253                 break;
254
255         case BANDWIDTH_7_MHZ:
256                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
257                 break;
258
259         case BANDWIDTH_8_MHZ:
260                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
261                 break;
262
263         default:
264                 return -EINVAL;
265         }
266
267         tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
268
269         return 0;
270 }
271
272 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
273                                    fe_bandwidth_t bandwidth)
274 {
275         static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
276         static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
277         static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
278
279         static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
280         static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
281         static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
282         int tda10046_clk53m;
283
284         if ((state->config->if_freq == TDA10046_FREQ_045) ||
285             (state->config->if_freq == TDA10046_FREQ_052))
286                 tda10046_clk53m = 0;
287         else
288                 tda10046_clk53m = 1;
289         switch (bandwidth) {
290         case BANDWIDTH_6_MHZ:
291                 if (tda10046_clk53m)
292                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
293                                                   sizeof(bandwidth_6mhz_53M));
294                 else
295                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
296                                                   sizeof(bandwidth_6mhz_48M));
297                 if (state->config->if_freq == TDA10046_FREQ_045) {
298                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
299                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
300                 }
301                 break;
302
303         case BANDWIDTH_7_MHZ:
304                 if (tda10046_clk53m)
305                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
306                                                   sizeof(bandwidth_7mhz_53M));
307                 else
308                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
309                                                   sizeof(bandwidth_7mhz_48M));
310                 if (state->config->if_freq == TDA10046_FREQ_045) {
311                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
312                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
313                 }
314                 break;
315
316         case BANDWIDTH_8_MHZ:
317                 if (tda10046_clk53m)
318                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
319                                                   sizeof(bandwidth_8mhz_53M));
320                 else
321                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
322                                                   sizeof(bandwidth_8mhz_48M));
323                 if (state->config->if_freq == TDA10046_FREQ_045) {
324                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
325                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
326                 }
327                 break;
328
329         default:
330                 return -EINVAL;
331         }
332
333         return 0;
334 }
335
336 static int tda1004x_do_upload(struct tda1004x_state *state,
337                               unsigned char *mem, unsigned int len,
338                               u8 dspCodeCounterReg, u8 dspCodeInReg)
339 {
340         u8 buf[65];
341         struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
342         int tx_size;
343         int pos = 0;
344
345         /* clear code counter */
346         tda1004x_write_byteI(state, dspCodeCounterReg, 0);
347         fw_msg.addr = state->config->demod_address;
348
349         buf[0] = dspCodeInReg;
350         while (pos != len) {
351                 // work out how much to send this time
352                 tx_size = len - pos;
353                 if (tx_size > 0x10)
354                         tx_size = 0x10;
355
356                 // send the chunk
357                 memcpy(buf + 1, mem + pos, tx_size);
358                 fw_msg.len = tx_size + 1;
359                 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
360                         printk(KERN_ERR "tda1004x: Error during firmware upload\n");
361                         return -EIO;
362                 }
363                 pos += tx_size;
364
365                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
366         }
367         // give the DSP a chance to settle 03/10/05 Hac
368         msleep(100);
369
370         return 0;
371 }
372
373 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
374 {
375         u8 data1, data2;
376         unsigned long timeout;
377
378         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
379                 timeout = jiffies + 2 * HZ;
380                 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
381                         if (time_after(jiffies, timeout)) {
382                                 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
383                                 break;
384                         }
385                         msleep(1);
386                 }
387         } else
388                 msleep(100);
389
390         // check upload was OK
391         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
392         tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
393
394         data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
395         data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
396         if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
397                 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
398                 return -EIO;
399         }
400         printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
401         return 0;
402 }
403
404 static int tda10045_fwupload(struct dvb_frontend* fe)
405 {
406         struct tda1004x_state* state = fe->demodulator_priv;
407         int ret;
408         const struct firmware *fw;
409
410         /* don't re-upload unless necessary */
411         if (tda1004x_check_upload_ok(state) == 0)
412                 return 0;
413
414         /* request the firmware, this will block until someone uploads it */
415         printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
416         ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
417         if (ret) {
418                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
419                 return ret;
420         }
421
422         /* reset chip */
423         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
424         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
425         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
426         msleep(10);
427
428         /* set parameters */
429         tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
430
431         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
432         release_firmware(fw);
433         if (ret)
434                 return ret;
435         printk(KERN_INFO "tda1004x: firmware upload complete\n");
436
437         /* wait for DSP to initialise */
438         /* DSPREADY doesn't seem to work on the TDA10045H */
439         msleep(100);
440
441         return tda1004x_check_upload_ok(state);
442 }
443
444 static void tda10046_init_plls(struct dvb_frontend* fe)
445 {
446         struct tda1004x_state* state = fe->demodulator_priv;
447         int tda10046_clk53m;
448
449         if ((state->config->if_freq == TDA10046_FREQ_045) ||
450             (state->config->if_freq == TDA10046_FREQ_052))
451                 tda10046_clk53m = 0;
452         else
453                 tda10046_clk53m = 1;
454
455         tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
456         if(tda10046_clk53m) {
457                 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
458                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
459         } else {
460                 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
461                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
462         }
463         if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
464                 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
465                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
466         } else {
467                 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
468                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
469         }
470         if(tda10046_clk53m)
471                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
472         else
473                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
474         /* Note clock frequency is handled implicitly */
475         switch (state->config->if_freq) {
476         case TDA10046_FREQ_045:
477                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
478                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
479                 break;
480         case TDA10046_FREQ_052:
481                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
482                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
483                 break;
484         case TDA10046_FREQ_3617:
485                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
486                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
487                 break;
488         case TDA10046_FREQ_3613:
489                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
490                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
491                 break;
492         }
493         tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
494         /* let the PLLs settle */
495         msleep(120);
496 }
497
498 static int tda10046_fwupload(struct dvb_frontend* fe)
499 {
500         struct tda1004x_state* state = fe->demodulator_priv;
501         int ret;
502         const struct firmware *fw;
503
504         /* reset + wake up chip */
505         tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
506         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
507         /* let the clocks recover from sleep */
508         msleep(5);
509
510         /* The PLLs need to be reprogrammed after sleep */
511         tda10046_init_plls(fe);
512
513         /* don't re-upload unless necessary */
514         if (tda1004x_check_upload_ok(state) == 0)
515                 return 0;
516
517         if (state->config->request_firmware != NULL) {
518                 /* request the firmware, this will block until someone uploads it */
519                 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
520                 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
521                 if (ret) {
522                         printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
523                         return ret;
524                 }
525                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
526                 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
527                 release_firmware(fw);
528                 if (ret)
529                         return ret;
530         } else {
531                 /* boot from firmware eeprom */
532                 printk(KERN_INFO "tda1004x: booting from eeprom\n");
533                 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
534                 msleep(300);
535         }
536         return tda1004x_check_upload_ok(state);
537 }
538
539 static int tda1004x_encode_fec(int fec)
540 {
541         // convert known FEC values
542         switch (fec) {
543         case FEC_1_2:
544                 return 0;
545         case FEC_2_3:
546                 return 1;
547         case FEC_3_4:
548                 return 2;
549         case FEC_5_6:
550                 return 3;
551         case FEC_7_8:
552                 return 4;
553         }
554
555         // unsupported
556         return -EINVAL;
557 }
558
559 static int tda1004x_decode_fec(int tdafec)
560 {
561         // convert known FEC values
562         switch (tdafec) {
563         case 0:
564                 return FEC_1_2;
565         case 1:
566                 return FEC_2_3;
567         case 2:
568                 return FEC_3_4;
569         case 3:
570                 return FEC_5_6;
571         case 4:
572                 return FEC_7_8;
573         }
574
575         // unsupported
576         return -1;
577 }
578
579 int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
580 {
581         struct tda1004x_state* state = fe->demodulator_priv;
582
583         return tda1004x_write_byteI(state, reg, data);
584 }
585
586 static int tda10045_init(struct dvb_frontend* fe)
587 {
588         struct tda1004x_state* state = fe->demodulator_priv;
589
590         dprintk("%s\n", __FUNCTION__);
591
592         if (state->initialised)
593                 return 0;
594
595         if (tda10045_fwupload(fe)) {
596                 printk("tda1004x: firmware upload failed\n");
597                 return -EIO;
598         }
599
600         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
601
602         // Init the PLL
603         if (state->config->pll_init) {
604                 tda1004x_enable_tuner_i2c(state);
605                 state->config->pll_init(fe);
606                 tda1004x_disable_tuner_i2c(state);
607         }
608
609         // tda setup
610         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
611         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
612         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
613         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
614         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
615         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
616         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
617         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
618         tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
619         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
620         tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
621
622         tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
623
624         state->initialised = 1;
625         return 0;
626 }
627
628 static int tda10046_init(struct dvb_frontend* fe)
629 {
630         struct tda1004x_state* state = fe->demodulator_priv;
631         dprintk("%s\n", __FUNCTION__);
632
633         if (state->initialised)
634                 return 0;
635
636         if (tda10046_fwupload(fe)) {
637                 printk("tda1004x: firmware upload failed\n");
638                         return -EIO;
639         }
640
641         // Init the tuner PLL
642         if (state->config->pll_init) {
643                 tda1004x_enable_tuner_i2c(state);
644                 if (state->config->pll_init(fe)) {
645                         printk(KERN_ERR "tda1004x: pll init failed\n");
646                         return  -EIO;
647                 }
648                 tda1004x_disable_tuner_i2c(state);
649         }
650
651         // tda setup
652         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
653         tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87);    // 100 ppm crystal, select HP stream
654         tda1004x_write_byteI(state, TDA1004X_CONFC1, 8);      // disable pulse killer
655
656         switch (state->config->agc_config) {
657         case TDA10046_AGC_DEFAULT:
658                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
659                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
660                 break;
661         case TDA10046_AGC_IFO_AUTO_NEG:
662                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
663                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
664                 break;
665         case TDA10046_AGC_IFO_AUTO_POS:
666                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
667                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x00); // set AGC polarities
668                 break;
669         case TDA10046_AGC_TDA827X:
670                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
671                 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
672                 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
673                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x6a); // set AGC polarities
674                 break;
675         }
676         tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
677         tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
678         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
679         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
680         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
681         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
682         tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
683         tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
684         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
685         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
686         tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
687
688         state->initialised = 1;
689         return 0;
690 }
691
692 static int tda1004x_set_fe(struct dvb_frontend* fe,
693                            struct dvb_frontend_parameters *fe_params)
694 {
695         struct tda1004x_state* state = fe->demodulator_priv;
696         int tmp;
697         int inversion;
698
699         dprintk("%s\n", __FUNCTION__);
700
701         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
702                 // setup auto offset
703                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
704                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
705                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
706
707                 // disable agc_conf[2]
708                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
709         }
710
711         // set frequency
712         tda1004x_enable_tuner_i2c(state);
713         if (state->config->pll_set(fe, fe_params)) {
714                 printk(KERN_ERR "tda1004x: pll set failed\n");
715                 return  -EIO;
716         }
717         tda1004x_disable_tuner_i2c(state);
718
719         // Hardcoded to use auto as much as possible on the TDA10045 as it
720         // is very unreliable if AUTO mode is _not_ used.
721         if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
722                 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
723                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
724                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
725         }
726
727         // Set standard params.. or put them to auto
728         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
729                 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
730                 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
731                 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
732                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);        // enable auto
733                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
734                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
735                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
736         } else {
737                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);        // disable auto
738
739                 // set HP FEC
740                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
741                 if (tmp < 0)
742                         return tmp;
743                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
744
745                 // set LP FEC
746                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
747                 if (tmp < 0)
748                         return tmp;
749                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
750
751                 // set constellation
752                 switch (fe_params->u.ofdm.constellation) {
753                 case QPSK:
754                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
755                         break;
756
757                 case QAM_16:
758                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
759                         break;
760
761                 case QAM_64:
762                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
763                         break;
764
765                 default:
766                         return -EINVAL;
767                 }
768
769                 // set hierarchy
770                 switch (fe_params->u.ofdm.hierarchy_information) {
771                 case HIERARCHY_NONE:
772                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
773                         break;
774
775                 case HIERARCHY_1:
776                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
777                         break;
778
779                 case HIERARCHY_2:
780                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
781                         break;
782
783                 case HIERARCHY_4:
784                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
785                         break;
786
787                 default:
788                         return -EINVAL;
789                 }
790         }
791
792         // set bandwidth
793         switch (state->demod_type) {
794         case TDA1004X_DEMOD_TDA10045:
795                 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
796                 break;
797
798         case TDA1004X_DEMOD_TDA10046:
799                 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
800                 break;
801         }
802
803         // set inversion
804         inversion = fe_params->inversion;
805         if (state->config->invert)
806                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
807         switch (inversion) {
808         case INVERSION_OFF:
809                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
810                 break;
811
812         case INVERSION_ON:
813                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
814                 break;
815
816         default:
817                 return -EINVAL;
818         }
819
820         // set guard interval
821         switch (fe_params->u.ofdm.guard_interval) {
822         case GUARD_INTERVAL_1_32:
823                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
824                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
825                 break;
826
827         case GUARD_INTERVAL_1_16:
828                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
829                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
830                 break;
831
832         case GUARD_INTERVAL_1_8:
833                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
834                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
835                 break;
836
837         case GUARD_INTERVAL_1_4:
838                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
839                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
840                 break;
841
842         case GUARD_INTERVAL_AUTO:
843                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
844                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
845                 break;
846
847         default:
848                 return -EINVAL;
849         }
850
851         // set transmission mode
852         switch (fe_params->u.ofdm.transmission_mode) {
853         case TRANSMISSION_MODE_2K:
854                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
855                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
856                 break;
857
858         case TRANSMISSION_MODE_8K:
859                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
860                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
861                 break;
862
863         case TRANSMISSION_MODE_AUTO:
864                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
865                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
866                 break;
867
868         default:
869                 return -EINVAL;
870         }
871
872         // start the lock
873         switch (state->demod_type) {
874         case TDA1004X_DEMOD_TDA10045:
875                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
876                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
877                 break;
878
879         case TDA1004X_DEMOD_TDA10046:
880                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
881                 msleep(1);
882                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
883                 break;
884         }
885
886         msleep(10);
887
888         return 0;
889 }
890
891 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
892 {
893         struct tda1004x_state* state = fe->demodulator_priv;
894
895         dprintk("%s\n", __FUNCTION__);
896
897         // inversion status
898         fe_params->inversion = INVERSION_OFF;
899         if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
900                 fe_params->inversion = INVERSION_ON;
901         if (state->config->invert)
902                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
903
904         // bandwidth
905         switch (state->demod_type) {
906         case TDA1004X_DEMOD_TDA10045:
907                 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
908                 case 0x14:
909                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
910                         break;
911                 case 0xdb:
912                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
913                         break;
914                 case 0x4f:
915                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
916                         break;
917                 }
918                 break;
919         case TDA1004X_DEMOD_TDA10046:
920                 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
921                 case 0x5c:
922                 case 0x54:
923                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
924                         break;
925                 case 0x6a:
926                 case 0x60:
927                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
928                         break;
929                 case 0x7b:
930                 case 0x70:
931                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
932                         break;
933                 }
934                 break;
935         }
936
937         // FEC
938         fe_params->u.ofdm.code_rate_HP =
939             tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
940         fe_params->u.ofdm.code_rate_LP =
941             tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
942
943         // constellation
944         switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
945         case 0:
946                 fe_params->u.ofdm.constellation = QPSK;
947                 break;
948         case 1:
949                 fe_params->u.ofdm.constellation = QAM_16;
950                 break;
951         case 2:
952                 fe_params->u.ofdm.constellation = QAM_64;
953                 break;
954         }
955
956         // transmission mode
957         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
958         if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
959                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
960
961         // guard interval
962         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
963         case 0:
964                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
965                 break;
966         case 1:
967                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
968                 break;
969         case 2:
970                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
971                 break;
972         case 3:
973                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
974                 break;
975         }
976
977         // hierarchy
978         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
979         case 0:
980                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
981                 break;
982         case 1:
983                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
984                 break;
985         case 2:
986                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
987                 break;
988         case 3:
989                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
990                 break;
991         }
992
993         return 0;
994 }
995
996 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
997 {
998         struct tda1004x_state* state = fe->demodulator_priv;
999         int status;
1000         int cber;
1001         int vber;
1002
1003         dprintk("%s\n", __FUNCTION__);
1004
1005         // read status
1006         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
1007         if (status == -1)
1008                 return -EIO;
1009
1010         // decode
1011         *fe_status = 0;
1012         if (status & 4)
1013                 *fe_status |= FE_HAS_SIGNAL;
1014         if (status & 2)
1015                 *fe_status |= FE_HAS_CARRIER;
1016         if (status & 8)
1017                 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1018
1019         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1020         // is getting anything valid
1021         if (!(*fe_status & FE_HAS_VITERBI)) {
1022                 // read the CBER
1023                 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1024                 if (cber == -1)
1025                         return -EIO;
1026                 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1027                 if (status == -1)
1028                         return -EIO;
1029                 cber |= (status << 8);
1030                 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1031
1032                 if (cber != 65535)
1033                         *fe_status |= FE_HAS_VITERBI;
1034         }
1035
1036         // if we DO have some valid VITERBI output, but don't already have SYNC
1037         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1038         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1039                 // read the VBER
1040                 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1041                 if (vber == -1)
1042                         return -EIO;
1043                 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1044                 if (status == -1)
1045                         return -EIO;
1046                 vber |= (status << 8);
1047                 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1048                 if (status == -1)
1049                         return -EIO;
1050                 vber |= ((status << 16) & 0x0f);
1051                 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1052
1053                 // if RS has passed some valid TS packets, then we must be
1054                 // getting some SYNC bytes
1055                 if (vber < 16632)
1056                         *fe_status |= FE_HAS_SYNC;
1057         }
1058
1059         // success
1060         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1061         return 0;
1062 }
1063
1064 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1065 {
1066         struct tda1004x_state* state = fe->demodulator_priv;
1067         int tmp;
1068         int reg = 0;
1069
1070         dprintk("%s\n", __FUNCTION__);
1071
1072         // determine the register to use
1073         switch (state->demod_type) {
1074         case TDA1004X_DEMOD_TDA10045:
1075                 reg = TDA10045H_S_AGC;
1076                 break;
1077
1078         case TDA1004X_DEMOD_TDA10046:
1079                 reg = TDA10046H_AGC_IF_LEVEL;
1080                 break;
1081         }
1082
1083         // read it
1084         tmp = tda1004x_read_byte(state, reg);
1085         if (tmp < 0)
1086                 return -EIO;
1087
1088         *signal = (tmp << 8) | tmp;
1089         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1090         return 0;
1091 }
1092
1093 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1094 {
1095         struct tda1004x_state* state = fe->demodulator_priv;
1096         int tmp;
1097
1098         dprintk("%s\n", __FUNCTION__);
1099
1100         // read it
1101         tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1102         if (tmp < 0)
1103                 return -EIO;
1104         tmp = 255 - tmp;
1105
1106         *snr = ((tmp << 8) | tmp);
1107         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1108         return 0;
1109 }
1110
1111 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1112 {
1113         struct tda1004x_state* state = fe->demodulator_priv;
1114         int tmp;
1115         int tmp2;
1116         int counter;
1117
1118         dprintk("%s\n", __FUNCTION__);
1119
1120         // read the UCBLOCKS and reset
1121         counter = 0;
1122         tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1123         if (tmp < 0)
1124                 return -EIO;
1125         tmp &= 0x7f;
1126         while (counter++ < 5) {
1127                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1128                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1129                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1130
1131                 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1132                 if (tmp2 < 0)
1133                         return -EIO;
1134                 tmp2 &= 0x7f;
1135                 if ((tmp2 < tmp) || (tmp2 == 0))
1136                         break;
1137         }
1138
1139         if (tmp != 0x7f)
1140                 *ucblocks = tmp;
1141         else
1142                 *ucblocks = 0xffffffff;
1143
1144         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1145         return 0;
1146 }
1147
1148 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1149 {
1150         struct tda1004x_state* state = fe->demodulator_priv;
1151         int tmp;
1152
1153         dprintk("%s\n", __FUNCTION__);
1154
1155         // read it in
1156         tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1157         if (tmp < 0)
1158                 return -EIO;
1159         *ber = tmp << 1;
1160         tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1161         if (tmp < 0)
1162                 return -EIO;
1163         *ber |= (tmp << 9);
1164         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1165
1166         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1167         return 0;
1168 }
1169
1170 static int tda1004x_sleep(struct dvb_frontend* fe)
1171 {
1172         struct tda1004x_state* state = fe->demodulator_priv;
1173
1174         switch (state->demod_type) {
1175         case TDA1004X_DEMOD_TDA10045:
1176                 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1177                 break;
1178
1179         case TDA1004X_DEMOD_TDA10046:
1180                 if (state->config->pll_sleep != NULL) {
1181                         tda1004x_enable_tuner_i2c(state);
1182                         state->config->pll_sleep(fe);
1183                         if (state->config->if_freq != TDA10046_FREQ_052) {
1184                                 /* special hack for Philips EUROPA Based boards:
1185                                  * keep the I2c bridge open for tuner access in analog mode
1186                                  */
1187                                 tda1004x_disable_tuner_i2c(state);
1188                         }
1189                 }
1190                 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1191                 break;
1192         }
1193         state->initialised = 0;
1194
1195         return 0;
1196 }
1197
1198 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1199 {
1200         fesettings->min_delay_ms = 800;
1201         /* Drift compensation makes no sense for DVB-T */
1202         fesettings->step_size = 0;
1203         fesettings->max_drift = 0;
1204         return 0;
1205 }
1206
1207 static void tda1004x_release(struct dvb_frontend* fe)
1208 {
1209         struct tda1004x_state *state = fe->demodulator_priv;
1210         kfree(state);
1211 }
1212
1213 static struct dvb_frontend_ops tda10045_ops = {
1214         .info = {
1215                 .name = "Philips TDA10045H DVB-T",
1216                 .type = FE_OFDM,
1217                 .frequency_min = 51000000,
1218                 .frequency_max = 858000000,
1219                 .frequency_stepsize = 166667,
1220                 .caps =
1221                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1222                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1223                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1224                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1225         },
1226
1227         .release = tda1004x_release,
1228
1229         .init = tda10045_init,
1230         .sleep = tda1004x_sleep,
1231
1232         .set_frontend = tda1004x_set_fe,
1233         .get_frontend = tda1004x_get_fe,
1234         .get_tune_settings = tda1004x_get_tune_settings,
1235
1236         .read_status = tda1004x_read_status,
1237         .read_ber = tda1004x_read_ber,
1238         .read_signal_strength = tda1004x_read_signal_strength,
1239         .read_snr = tda1004x_read_snr,
1240         .read_ucblocks = tda1004x_read_ucblocks,
1241 };
1242
1243 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1244                                      struct i2c_adapter* i2c)
1245 {
1246         struct tda1004x_state *state;
1247
1248         /* allocate memory for the internal state */
1249         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1250         if (!state)
1251                 return NULL;
1252
1253         /* setup the state */
1254         state->config = config;
1255         state->i2c = i2c;
1256         memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1257         state->initialised = 0;
1258         state->demod_type = TDA1004X_DEMOD_TDA10045;
1259
1260         /* check if the demod is there */
1261         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1262                 kfree(state);
1263                 return NULL;
1264         }
1265
1266         /* create dvb_frontend */
1267         state->frontend.ops = &state->ops;
1268         state->frontend.demodulator_priv = state;
1269         return &state->frontend;
1270 }
1271
1272 static struct dvb_frontend_ops tda10046_ops = {
1273         .info = {
1274                 .name = "Philips TDA10046H DVB-T",
1275                 .type = FE_OFDM,
1276                 .frequency_min = 51000000,
1277                 .frequency_max = 858000000,
1278                 .frequency_stepsize = 166667,
1279                 .caps =
1280                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1281                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1282                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1283                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1284         },
1285
1286         .release = tda1004x_release,
1287
1288         .init = tda10046_init,
1289         .sleep = tda1004x_sleep,
1290
1291         .set_frontend = tda1004x_set_fe,
1292         .get_frontend = tda1004x_get_fe,
1293         .get_tune_settings = tda1004x_get_tune_settings,
1294
1295         .read_status = tda1004x_read_status,
1296         .read_ber = tda1004x_read_ber,
1297         .read_signal_strength = tda1004x_read_signal_strength,
1298         .read_snr = tda1004x_read_snr,
1299         .read_ucblocks = tda1004x_read_ucblocks,
1300 };
1301
1302 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1303                                      struct i2c_adapter* i2c)
1304 {
1305         struct tda1004x_state *state;
1306
1307         /* allocate memory for the internal state */
1308         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1309         if (!state)
1310                 return NULL;
1311
1312         /* setup the state */
1313         state->config = config;
1314         state->i2c = i2c;
1315         memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1316         state->initialised = 0;
1317         state->demod_type = TDA1004X_DEMOD_TDA10046;
1318
1319         /* check if the demod is there */
1320         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1321                 kfree(state);
1322                 return NULL;
1323         }
1324
1325         /* create dvb_frontend */
1326         state->frontend.ops = &state->ops;
1327         state->frontend.demodulator_priv = state;
1328         return &state->frontend;
1329 }
1330
1331 module_param(debug, int, 0644);
1332 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1333
1334 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1335 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1336 MODULE_LICENSE("GPL");
1337
1338 EXPORT_SYMBOL(tda10045_attach);
1339 EXPORT_SYMBOL(tda10046_attach);
1340 EXPORT_SYMBOL(tda1004x_write_byte);