2 * linux/drivers/video/s3c2410fb.c
3 * Copyright (c) Arnaud Patard, Ben Dooks
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
9 * S3C2410 LCD Controller Frame Buffer Driver
10 * based on skeletonfb.c, sa1100fb.c and others
13 * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
14 * - u32 state -> pm_message_t state
15 * - S3C2410_{VA,SZ}_LCD -> S3C24XX
17 * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
19 * - use readl/writel instead of __raw_writel/__raw_readl
21 * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
22 * - Added the possibility to set on or off the
24 * - Replaced 0 and 1 by on or off when reading the
27 * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
28 * - added non 16bpp modes
29 * - updated platform information for range of x/y/bpp
30 * - add code to ensure palette is written correctly
31 * - add pixel clock divisor control
33 * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
34 * - Removed the use of currcon as it no more exist
35 * - Added LCD power sysfs interface
37 * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
39 * - add suspend/resume support
40 * - s3c2410fb_setcolreg() not valid in >8bpp modes
41 * - removed last CONFIG_FB_S3C2410_FIXED
42 * - ensure lcd controller stopped before cleanup
43 * - added sysfs interface for backlight power
44 * - added mask for gpio configuration
45 * - ensured IRQs disabled during GPIO configuration
46 * - disable TPAL before enabling video
48 * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
49 * - Suppress command line options
51 * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
54 * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
55 * - Renamed from h1940fb.c to s3c2410fb.c
56 * - Add support for different devices
59 * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
60 * - added clock (de-)allocation code
61 * - added fixem fbmem option
63 * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
65 * - added a forgotten return in h1940fb_init
67 * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
68 * - code cleanup and extended debugging
70 * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
74 #include <linux/module.h>
75 #include <linux/kernel.h>
76 #include <linux/errno.h>
77 #include <linux/string.h>
79 #include <linux/tty.h>
80 #include <linux/slab.h>
81 #include <linux/delay.h>
83 #include <linux/init.h>
84 #include <linux/dma-mapping.h>
85 #include <linux/interrupt.h>
86 #include <linux/workqueue.h>
87 #include <linux/wait.h>
88 #include <linux/platform_device.h>
89 #include <linux/clk.h>
92 #include <asm/uaccess.h>
93 #include <asm/div64.h>
95 #include <asm/mach/map.h>
96 #include <asm/arch/regs-lcd.h>
97 #include <asm/arch/regs-gpio.h>
98 #include <asm/arch/fb.h>
101 #include <linux/pm.h>
104 #include "s3c2410fb.h"
107 static struct s3c2410fb_mach_info *mach_info;
109 /* Debugging stuff */
110 #ifdef CONFIG_FB_S3C2410_DEBUG
111 static int debug = 1;
113 static int debug = 0;
116 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
118 /* useful functions */
120 /* s3c2410fb_set_lcdaddr
122 * initialise lcd controller address pointers
125 static void s3c2410fb_set_lcdaddr(struct s3c2410fb_info *fbi)
127 struct fb_var_screeninfo *var = &fbi->fb->var;
128 unsigned long saddr1, saddr2, saddr3;
130 saddr1 = fbi->fb->fix.smem_start >> 1;
131 saddr2 = fbi->fb->fix.smem_start;
132 saddr2 += (var->xres * var->yres * var->bits_per_pixel)/8;
135 saddr3 = S3C2410_OFFSIZE(0) | S3C2410_PAGEWIDTH(var->xres);
137 dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
138 dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
139 dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
141 writel(saddr1, S3C2410_LCDSADDR1);
142 writel(saddr2, S3C2410_LCDSADDR2);
143 writel(saddr3, S3C2410_LCDSADDR3);
146 /* s3c2410fb_calc_pixclk()
148 * calculate divisor for clk->pixclk
151 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
152 unsigned long pixclk)
154 unsigned long clk = clk_get_rate(fbi->clk);
155 unsigned long long div;
157 /* pixclk is in picoseoncds, our clock is in Hz
159 * Hz -> picoseconds is / 10^-12
162 div = (unsigned long long)clk * pixclk;
163 do_div(div,1000000UL);
164 do_div(div,1000000UL);
166 dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
171 * s3c2410fb_check_var():
172 * Get the video params out of 'var'. If a value doesn't fit, round it up,
173 * if it's too big, return -EINVAL.
176 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
177 struct fb_info *info)
179 struct s3c2410fb_info *fbi = info->par;
181 dprintk("check_var(var=%p, info=%p)\n", var, info);
183 /* validate x/y resolution */
185 if (var->yres > fbi->mach_info->yres.max)
186 var->yres = fbi->mach_info->yres.max;
187 else if (var->yres < fbi->mach_info->yres.min)
188 var->yres = fbi->mach_info->yres.min;
190 if (var->xres > fbi->mach_info->xres.max)
191 var->yres = fbi->mach_info->xres.max;
192 else if (var->xres < fbi->mach_info->xres.min)
193 var->xres = fbi->mach_info->xres.min;
197 if (var->bits_per_pixel > fbi->mach_info->bpp.max)
198 var->bits_per_pixel = fbi->mach_info->bpp.max;
199 else if (var->bits_per_pixel < fbi->mach_info->bpp.min)
200 var->bits_per_pixel = fbi->mach_info->bpp.min;
202 /* set r/g/b positions */
204 if (var->bits_per_pixel == 16) {
205 var->red.offset = 11;
206 var->green.offset = 5;
207 var->blue.offset = 0;
209 var->green.length = 6;
210 var->blue.length = 5;
211 var->transp.length = 0;
213 var->red.length = var->bits_per_pixel;
215 var->green.length = var->bits_per_pixel;
216 var->green.offset = 0;
217 var->blue.length = var->bits_per_pixel;
218 var->blue.offset = 0;
219 var->transp.length = 0;
225 /* s3c2410fb_activate_var
227 * activate (set) the controller from the given framebuffer
231 static void s3c2410fb_activate_var(struct s3c2410fb_info *fbi,
232 struct fb_var_screeninfo *var)
234 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
236 dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
237 dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
238 dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
240 switch (var->bits_per_pixel) {
242 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
245 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
248 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
251 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
254 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
258 /* check to see if we need to update sync/borders */
260 if (!fbi->mach_info->fixed_syncs) {
261 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
262 var->upper_margin, var->lower_margin,
265 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
266 var->left_margin, var->right_margin,
270 S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
271 S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
272 S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
275 S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
276 S3C2410_LCDCON3_HFPD(var->left_margin - 1);
278 fbi->regs.lcdcon4 &= ~S3C2410_LCDCON4_HSPW(0xff);
279 fbi->regs.lcdcon4 |= S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
282 /* update X/Y info */
284 fbi->regs.lcdcon2 &= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
285 fbi->regs.lcdcon2 |= S3C2410_LCDCON2_LINEVAL(var->yres - 1);
287 fbi->regs.lcdcon3 &= ~S3C2410_LCDCON3_HOZVAL(0x7ff);
288 fbi->regs.lcdcon3 |= S3C2410_LCDCON3_HOZVAL(var->xres - 1);
290 if (var->pixclock > 0) {
291 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
293 clkdiv = (clkdiv / 2) -1;
297 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
298 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
301 /* write new registers */
303 dprintk("new register set:\n");
304 dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
305 dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
306 dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
307 dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
308 dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
310 writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
311 writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
312 writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
313 writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
314 writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
316 /* set lcd address pointers */
317 s3c2410fb_set_lcdaddr(fbi);
319 writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
324 * s3c2410fb_set_par - Optional function. Alters the hardware state.
325 * @info: frame buffer structure that represents a single frame buffer
328 static int s3c2410fb_set_par(struct fb_info *info)
330 struct s3c2410fb_info *fbi = info->par;
331 struct fb_var_screeninfo *var = &info->var;
333 if (var->bits_per_pixel == 16)
334 fbi->fb->fix.visual = FB_VISUAL_TRUECOLOR;
336 fbi->fb->fix.visual = FB_VISUAL_PSEUDOCOLOR;
338 fbi->fb->fix.line_length = (var->width*var->bits_per_pixel)/8;
340 /* activate this new configuration */
342 s3c2410fb_activate_var(fbi, var);
346 static void schedule_palette_update(struct s3c2410fb_info *fbi,
347 unsigned int regno, unsigned int val)
352 local_irq_save(flags);
354 fbi->palette_buffer[regno] = val;
356 if (!fbi->palette_ready) {
357 fbi->palette_ready = 1;
360 irqen = readl(S3C2410_LCDINTMSK);
361 irqen &= ~S3C2410_LCDINT_FRSYNC;
362 writel(irqen, S3C2410_LCDINTMSK);
365 local_irq_restore(flags);
369 static inline unsigned int chan_to_field(unsigned int chan, struct fb_bitfield *bf)
372 chan >>= 16 - bf->length;
373 return chan << bf->offset;
376 static int s3c2410fb_setcolreg(unsigned regno,
377 unsigned red, unsigned green, unsigned blue,
378 unsigned transp, struct fb_info *info)
380 struct s3c2410fb_info *fbi = info->par;
383 /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n", regno, red, green, blue); */
385 switch (fbi->fb->fix.visual) {
386 case FB_VISUAL_TRUECOLOR:
387 /* true-colour, use pseuo-palette */
390 u32 *pal = fbi->fb->pseudo_palette;
392 val = chan_to_field(red, &fbi->fb->var.red);
393 val |= chan_to_field(green, &fbi->fb->var.green);
394 val |= chan_to_field(blue, &fbi->fb->var.blue);
400 case FB_VISUAL_PSEUDOCOLOR:
402 /* currently assume RGB 5-6-5 mode */
404 val = ((red >> 0) & 0xf800);
405 val |= ((green >> 5) & 0x07e0);
406 val |= ((blue >> 11) & 0x001f);
408 writel(val, S3C2410_TFTPAL(regno));
409 schedule_palette_update(fbi, regno, val);
415 return 1; /* unknown type */
424 * @blank_mode: the blank mode we want.
425 * @info: frame buffer structure that represents a single frame buffer
427 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
428 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
429 * video mode which doesn't support it. Implements VESA suspend
430 * and powerdown modes on hardware that supports disabling hsync/vsync:
431 * blank_mode == 2: suspend vsync
432 * blank_mode == 3: suspend hsync
433 * blank_mode == 4: powerdown
435 * Returns negative errno on error, or zero on success.
438 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
440 dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
442 if (mach_info == NULL)
445 if (blank_mode == FB_BLANK_UNBLANK)
446 writel(0x0, S3C2410_TPAL);
448 dprintk("setting TPAL to output 0x000000\n");
449 writel(S3C2410_TPAL_EN, S3C2410_TPAL);
455 static int s3c2410fb_debug_show(struct device *dev, struct device_attribute *attr, char *buf)
457 return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
459 static int s3c2410fb_debug_store(struct device *dev, struct device_attribute *attr,
460 const char *buf, size_t len)
462 if (mach_info == NULL)
468 if (strnicmp(buf, "on", 2) == 0 ||
469 strnicmp(buf, "1", 1) == 0) {
471 printk(KERN_DEBUG "s3c2410fb: Debug On");
472 } else if (strnicmp(buf, "off", 3) == 0 ||
473 strnicmp(buf, "0", 1) == 0) {
475 printk(KERN_DEBUG "s3c2410fb: Debug Off");
484 static DEVICE_ATTR(debug, 0666,
485 s3c2410fb_debug_show,
486 s3c2410fb_debug_store);
488 static struct fb_ops s3c2410fb_ops = {
489 .owner = THIS_MODULE,
490 .fb_check_var = s3c2410fb_check_var,
491 .fb_set_par = s3c2410fb_set_par,
492 .fb_blank = s3c2410fb_blank,
493 .fb_setcolreg = s3c2410fb_setcolreg,
494 .fb_fillrect = cfb_fillrect,
495 .fb_copyarea = cfb_copyarea,
496 .fb_imageblit = cfb_imageblit,
501 * s3c2410fb_map_video_memory():
502 * Allocates the DRAM memory for the frame buffer. This buffer is
503 * remapped into a non-cached, non-buffered, memory region to
504 * allow palette and pixel writes to occur without flushing the
505 * cache. Once this area is remapped, all virtual memory
506 * access to the video memory should occur at the new region.
508 static int __init s3c2410fb_map_video_memory(struct s3c2410fb_info *fbi)
510 dprintk("map_video_memory(fbi=%p)\n", fbi);
512 fbi->map_size = PAGE_ALIGN(fbi->fb->fix.smem_len + PAGE_SIZE);
513 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
514 &fbi->map_dma, GFP_KERNEL);
516 fbi->map_size = fbi->fb->fix.smem_len;
519 /* prevent initial garbage on screen */
520 dprintk("map_video_memory: clear %p:%08x\n",
521 fbi->map_cpu, fbi->map_size);
522 memset(fbi->map_cpu, 0xf0, fbi->map_size);
524 fbi->screen_dma = fbi->map_dma;
525 fbi->fb->screen_base = fbi->map_cpu;
526 fbi->fb->fix.smem_start = fbi->screen_dma;
528 dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
529 fbi->map_dma, fbi->map_cpu, fbi->fb->fix.smem_len);
532 return fbi->map_cpu ? 0 : -ENOMEM;
535 static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info *fbi)
537 dma_free_writecombine(fbi->dev,fbi->map_size,fbi->map_cpu, fbi->map_dma);
540 static inline void modify_gpio(void __iomem *reg,
541 unsigned long set, unsigned long mask)
545 tmp = readl(reg) & ~mask;
546 writel(tmp | set, reg);
551 * s3c2410fb_init_registers - Initialise all LCD-related registers
554 static int s3c2410fb_init_registers(struct s3c2410fb_info *fbi)
558 /* Initialise LCD with values from haret */
560 local_irq_save(flags);
562 /* modify the gpio(s) with interrupts set (bjd) */
564 modify_gpio(S3C2410_GPCUP, mach_info->gpcup, mach_info->gpcup_mask);
565 modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
566 modify_gpio(S3C2410_GPDUP, mach_info->gpdup, mach_info->gpdup_mask);
567 modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
569 local_irq_restore(flags);
571 writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
572 writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
573 writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
574 writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
575 writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
577 s3c2410fb_set_lcdaddr(fbi);
579 dprintk("LPCSEL = 0x%08lx\n", mach_info->lpcsel);
580 writel(mach_info->lpcsel, S3C2410_LPCSEL);
582 dprintk("replacing TPAL %08x\n", readl(S3C2410_TPAL));
584 /* ensure temporary palette disabled */
585 writel(0x00, S3C2410_TPAL);
587 /* Enable video by setting the ENVID bit to 1 */
588 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
589 writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
593 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
598 fbi->palette_ready = 0;
600 for (i = 0; i < 256; i++) {
601 if ((ent = fbi->palette_buffer[i]) == PALETTE_BUFF_CLEAR)
604 writel(ent, S3C2410_TFTPAL(i));
606 /* it seems the only way to know exactly
607 * if the palette wrote ok, is to check
608 * to see if the value verifies ok
611 if (readw(S3C2410_TFTPAL(i)) == ent)
612 fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
614 fbi->palette_ready = 1; /* retry */
618 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id, struct pt_regs *r)
620 struct s3c2410fb_info *fbi = dev_id;
621 unsigned long lcdirq = readl(S3C2410_LCDINTPND);
623 if (lcdirq & S3C2410_LCDINT_FRSYNC) {
624 if (fbi->palette_ready)
625 s3c2410fb_write_palette(fbi);
627 writel(S3C2410_LCDINT_FRSYNC, S3C2410_LCDINTPND);
628 writel(S3C2410_LCDINT_FRSYNC, S3C2410_LCDSRCPND);
634 static char driver_name[]="s3c2410fb";
636 static int __init s3c2410fb_probe(struct platform_device *pdev)
638 struct s3c2410fb_info *info;
639 struct fb_info *fbinfo;
640 struct s3c2410fb_hw *mregs;
645 mach_info = pdev->dev.platform_data;
646 if (mach_info == NULL) {
647 dev_err(&pdev->dev,"no platform data for lcd, cannot attach\n");
651 mregs = &mach_info->regs;
653 irq = platform_get_irq(pdev, 0);
655 dev_err(&pdev->dev, "no irq for device\n");
659 fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
667 platform_set_drvdata(pdev, fbinfo);
669 dprintk("devinit\n");
671 strcpy(fbinfo->fix.id, driver_name);
673 memcpy(&info->regs, &mach_info->regs, sizeof(info->regs));
675 info->mach_info = pdev->dev.platform_data;
677 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
678 fbinfo->fix.type_aux = 0;
679 fbinfo->fix.xpanstep = 0;
680 fbinfo->fix.ypanstep = 0;
681 fbinfo->fix.ywrapstep = 0;
682 fbinfo->fix.accel = FB_ACCEL_NONE;
684 fbinfo->var.nonstd = 0;
685 fbinfo->var.activate = FB_ACTIVATE_NOW;
686 fbinfo->var.height = mach_info->height;
687 fbinfo->var.width = mach_info->width;
688 fbinfo->var.accel_flags = 0;
689 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
691 fbinfo->fbops = &s3c2410fb_ops;
692 fbinfo->flags = FBINFO_FLAG_DEFAULT;
693 fbinfo->pseudo_palette = &info->pseudo_pal;
695 fbinfo->var.xres = mach_info->xres.defval;
696 fbinfo->var.xres_virtual = mach_info->xres.defval;
697 fbinfo->var.yres = mach_info->yres.defval;
698 fbinfo->var.yres_virtual = mach_info->yres.defval;
699 fbinfo->var.bits_per_pixel = mach_info->bpp.defval;
701 fbinfo->var.upper_margin = S3C2410_LCDCON2_GET_VBPD(mregs->lcdcon2) + 1;
702 fbinfo->var.lower_margin = S3C2410_LCDCON2_GET_VFPD(mregs->lcdcon2) + 1;
703 fbinfo->var.vsync_len = S3C2410_LCDCON2_GET_VSPW(mregs->lcdcon2) + 1;
705 fbinfo->var.left_margin = S3C2410_LCDCON3_GET_HFPD(mregs->lcdcon3) + 1;
706 fbinfo->var.right_margin = S3C2410_LCDCON3_GET_HBPD(mregs->lcdcon3) + 1;
707 fbinfo->var.hsync_len = S3C2410_LCDCON4_GET_HSPW(mregs->lcdcon4) + 1;
709 fbinfo->var.red.offset = 11;
710 fbinfo->var.green.offset = 5;
711 fbinfo->var.blue.offset = 0;
712 fbinfo->var.transp.offset = 0;
713 fbinfo->var.red.length = 5;
714 fbinfo->var.green.length = 6;
715 fbinfo->var.blue.length = 5;
716 fbinfo->var.transp.length = 0;
717 fbinfo->fix.smem_len = mach_info->xres.max *
718 mach_info->yres.max *
719 mach_info->bpp.max / 8;
721 for (i = 0; i < 256; i++)
722 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
724 if (!request_mem_region((unsigned long)S3C24XX_VA_LCD, SZ_1M, "s3c2410-lcd")) {
730 dprintk("got LCD region\n");
732 ret = request_irq(irq, s3c2410fb_irq, SA_INTERRUPT, pdev->name, info);
734 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
739 info->clk = clk_get(NULL, "lcd");
740 if (!info->clk || IS_ERR(info->clk)) {
741 printk(KERN_ERR "failed to get lcd clock source\n");
746 clk_enable(info->clk);
747 dprintk("got and enabled clock\n");
751 /* Initialize video memory */
752 ret = s3c2410fb_map_video_memory(info);
754 printk( KERN_ERR "Failed to allocate video RAM: %d\n", ret);
758 dprintk("got video memory\n");
760 ret = s3c2410fb_init_registers(info);
762 ret = s3c2410fb_check_var(&fbinfo->var, fbinfo);
764 ret = register_framebuffer(fbinfo);
766 printk(KERN_ERR "Failed to register framebuffer device: %d\n", ret);
767 goto free_video_memory;
770 /* create device files */
771 device_create_file(&pdev->dev, &dev_attr_debug);
773 printk(KERN_INFO "fb%d: %s frame buffer device\n",
774 fbinfo->node, fbinfo->fix.id);
779 s3c2410fb_unmap_video_memory(info);
781 clk_disable(info->clk);
786 release_mem_region((unsigned long)S3C24XX_VA_LCD, S3C24XX_SZ_LCD);
788 framebuffer_release(fbinfo);
792 /* s3c2410fb_stop_lcd
794 * shutdown the lcd controller
797 static void s3c2410fb_stop_lcd(void)
802 local_irq_save(flags);
804 tmp = readl(S3C2410_LCDCON1);
805 writel(tmp & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
807 local_irq_restore(flags);
813 static int s3c2410fb_remove(struct platform_device *pdev)
815 struct fb_info *fbinfo = platform_get_drvdata(pdev);
816 struct s3c2410fb_info *info = fbinfo->par;
819 s3c2410fb_stop_lcd();
822 s3c2410fb_unmap_video_memory(info);
825 clk_disable(info->clk);
830 irq = platform_get_irq(pdev, 0);
832 release_mem_region((unsigned long)S3C24XX_VA_LCD, S3C24XX_SZ_LCD);
833 unregister_framebuffer(fbinfo);
840 /* suspend and resume support for the lcd controller */
842 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
844 struct fb_info *fbinfo = platform_get_drvdata(dev);
845 struct s3c2410fb_info *info = fbinfo->par;
847 s3c2410fb_stop_lcd();
849 /* sleep before disabling the clock, we need to ensure
850 * the LCD DMA engine is not going to get back on the bus
851 * before the clock goes off again (bjd) */
854 clk_disable(info->clk);
859 static int s3c2410fb_resume(struct platform_device *dev)
861 struct fb_info *fbinfo = platform_get_drvdata(dev);
862 struct s3c2410fb_info *info = fbinfo->par;
864 clk_enable(info->clk);
867 s3c2410fb_init_registers(info);
873 #define s3c2410fb_suspend NULL
874 #define s3c2410fb_resume NULL
877 static struct platform_driver s3c2410fb_driver = {
878 .probe = s3c2410fb_probe,
879 .remove = s3c2410fb_remove,
880 .suspend = s3c2410fb_suspend,
881 .resume = s3c2410fb_resume,
883 .name = "s3c2410-lcd",
884 .owner = THIS_MODULE,
888 int __devinit s3c2410fb_init(void)
890 return platform_driver_register(&s3c2410fb_driver);
893 static void __exit s3c2410fb_cleanup(void)
895 platform_driver_unregister(&s3c2410fb_driver);
899 module_init(s3c2410fb_init);
900 module_exit(s3c2410fb_cleanup);
902 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, Ben Dooks <ben-linux@fluff.org>");
903 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
904 MODULE_LICENSE("GPL");