Merge master.kernel.org:/pub/scm/linux/kernel/git/herbert/crypto-2.6
[linux-2.6] / arch / arm / plat-omap / clock.c
1 /*
2  *  linux/arch/arm/plat-omap/clock.c
3  *
4  *  Copyright (C) 2004 Nokia corporation
5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/list.h>
14 #include <linux/errno.h>
15 #include <linux/err.h>
16
17 #include <asm/io.h>
18 #include <asm/semaphore.h>
19 #include <asm/hardware/clock.h>
20 #include <asm/arch/board.h>
21 #include <asm/arch/usb.h>
22
23 #include "clock.h"
24 #include "sram.h"
25
26 static LIST_HEAD(clocks);
27 static DECLARE_MUTEX(clocks_sem);
28 static DEFINE_SPINLOCK(clockfw_lock);
29 static void propagate_rate(struct clk *  clk);
30 /* UART clock function */
31 static int set_uart_rate(struct clk * clk, unsigned long rate);
32 /* External clock (MCLK & BCLK) functions */
33 static int set_ext_clk_rate(struct clk *  clk, unsigned long rate);
34 static long round_ext_clk_rate(struct clk *  clk, unsigned long rate);
35 static void init_ext_clk(struct clk *  clk);
36 /* MPU virtual clock functions */
37 static int select_table_rate(struct clk *  clk, unsigned long rate);
38 static long round_to_table_rate(struct clk *  clk, unsigned long rate);
39 void clk_setdpll(__u16, __u16);
40
41 static struct mpu_rate rate_table[] = {
42         /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
43          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
44          */
45 #if defined(CONFIG_OMAP_ARM_216MHZ)
46         { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
47 #endif
48 #if defined(CONFIG_OMAP_ARM_195MHZ)
49         { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
50 #endif
51 #if defined(CONFIG_OMAP_ARM_192MHZ)
52         { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
53         { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
54         {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
55         {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/8/4/4/8/8 */
56         {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
57 #endif
58 #if defined(CONFIG_OMAP_ARM_182MHZ)
59         { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
60 #endif
61 #if defined(CONFIG_OMAP_ARM_168MHZ)
62         { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
63 #endif
64 #if defined(CONFIG_OMAP_ARM_150MHZ)
65         { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
66 #endif
67 #if defined(CONFIG_OMAP_ARM_120MHZ)
68         { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
69 #endif
70 #if defined(CONFIG_OMAP_ARM_96MHZ)
71         {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
72 #endif
73 #if defined(CONFIG_OMAP_ARM_60MHZ)
74         {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
75 #endif
76 #if defined(CONFIG_OMAP_ARM_30MHZ)
77         {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
78 #endif
79         { 0, 0, 0, 0, 0 },
80 };
81
82
83 static void ckctl_recalc(struct clk *  clk);
84 int __clk_enable(struct clk *clk);
85 void __clk_disable(struct clk *clk);
86 void __clk_unuse(struct clk *clk);
87 int __clk_use(struct clk *clk);
88
89
90 static void followparent_recalc(struct clk *  clk)
91 {
92         clk->rate = clk->parent->rate;
93 }
94
95
96 static void watchdog_recalc(struct clk *  clk)
97 {
98         clk->rate = clk->parent->rate / 14;
99 }
100
101 static void uart_recalc(struct clk * clk)
102 {
103         unsigned int val = omap_readl(clk->enable_reg);
104         if (val & clk->enable_bit)
105                 clk->rate = 48000000;
106         else
107                 clk->rate = 12000000;
108 }
109
110 static struct clk ck_ref = {
111         .name           = "ck_ref",
112         .rate           = 12000000,
113         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
114                           ALWAYS_ENABLED,
115 };
116
117 static struct clk ck_dpll1 = {
118         .name           = "ck_dpll1",
119         .parent         = &ck_ref,
120         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
121                           RATE_PROPAGATES | ALWAYS_ENABLED,
122 };
123
124 static struct clk ck_dpll1out = {
125         .name           = "ck_dpll1out",
126         .parent         = &ck_dpll1,
127         .flags          = CLOCK_IN_OMAP16XX,
128         .enable_reg     = ARM_IDLECT2,
129         .enable_bit     = EN_CKOUT_ARM,
130         .recalc         = &followparent_recalc,
131 };
132
133 static struct clk arm_ck = {
134         .name           = "arm_ck",
135         .parent         = &ck_dpll1,
136         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
137                           RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
138         .rate_offset    = CKCTL_ARMDIV_OFFSET,
139         .recalc         = &ckctl_recalc,
140 };
141
142 static struct clk armper_ck = {
143         .name           = "armper_ck",
144         .parent         = &ck_dpll1,
145         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
146                           RATE_CKCTL,
147         .enable_reg     = ARM_IDLECT2,
148         .enable_bit     = EN_PERCK,
149         .rate_offset    = CKCTL_PERDIV_OFFSET,
150         .recalc         = &ckctl_recalc,
151 };
152
153 static struct clk arm_gpio_ck = {
154         .name           = "arm_gpio_ck",
155         .parent         = &ck_dpll1,
156         .flags          = CLOCK_IN_OMAP1510,
157         .enable_reg     = ARM_IDLECT2,
158         .enable_bit     = EN_GPIOCK,
159         .recalc         = &followparent_recalc,
160 };
161
162 static struct clk armxor_ck = {
163         .name           = "armxor_ck",
164         .parent         = &ck_ref,
165         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
166         .enable_reg     = ARM_IDLECT2,
167         .enable_bit     = EN_XORPCK,
168         .recalc         = &followparent_recalc,
169 };
170
171 static struct clk armtim_ck = {
172         .name           = "armtim_ck",
173         .parent         = &ck_ref,
174         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
175         .enable_reg     = ARM_IDLECT2,
176         .enable_bit     = EN_TIMCK,
177         .recalc         = &followparent_recalc,
178 };
179
180 static struct clk armwdt_ck = {
181         .name           = "armwdt_ck",
182         .parent         = &ck_ref,
183         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
184         .enable_reg     = ARM_IDLECT2,
185         .enable_bit     = EN_WDTCK,
186         .recalc         = &watchdog_recalc,
187 };
188
189 static struct clk arminth_ck16xx = {
190         .name           = "arminth_ck",
191         .parent         = &arm_ck,
192         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
193         .recalc         = &followparent_recalc,
194         /* Note: On 16xx the frequency can be divided by 2 by programming
195          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
196          *
197          * 1510 version is in TC clocks.
198          */
199 };
200
201 static struct clk dsp_ck = {
202         .name           = "dsp_ck",
203         .parent         = &ck_dpll1,
204         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
205                           RATE_CKCTL,
206         .enable_reg     = ARM_CKCTL,
207         .enable_bit     = EN_DSPCK,
208         .rate_offset    = CKCTL_DSPDIV_OFFSET,
209         .recalc         = &ckctl_recalc,
210 };
211
212 static struct clk dspmmu_ck = {
213         .name           = "dspmmu_ck",
214         .parent         = &ck_dpll1,
215         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
216                           RATE_CKCTL | ALWAYS_ENABLED,
217         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
218         .recalc         = &ckctl_recalc,
219 };
220
221 static struct clk dspper_ck = {
222         .name           = "dspper_ck",
223         .parent         = &ck_dpll1,
224         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
225                           RATE_CKCTL | DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
226         .enable_reg     = DSP_IDLECT2,
227         .enable_bit     = EN_PERCK,
228         .rate_offset    = CKCTL_PERDIV_OFFSET,
229         .recalc         = &followparent_recalc,
230         //.recalc               = &ckctl_recalc,
231 };
232
233 static struct clk dspxor_ck = {
234         .name           = "dspxor_ck",
235         .parent         = &ck_ref,
236         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
237                           DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
238         .enable_reg     = DSP_IDLECT2,
239         .enable_bit     = EN_XORPCK,
240         .recalc         = &followparent_recalc,
241 };
242
243 static struct clk dsptim_ck = {
244         .name           = "dsptim_ck",
245         .parent         = &ck_ref,
246         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
247                           DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
248         .enable_reg     = DSP_IDLECT2,
249         .enable_bit     = EN_DSPTIMCK,
250         .recalc         = &followparent_recalc,
251 };
252
253 static struct clk tc_ck = {
254         .name           = "tc_ck",
255         .parent         = &ck_dpll1,
256         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
257                           RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
258         .rate_offset    = CKCTL_TCDIV_OFFSET,
259         .recalc         = &ckctl_recalc,
260 };
261
262 static struct clk arminth_ck1510 = {
263         .name           = "arminth_ck",
264         .parent         = &tc_ck,
265         .flags          = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
266         .recalc         = &followparent_recalc,
267         /* Note: On 1510 the frequency follows TC_CK
268          *
269          * 16xx version is in MPU clocks.
270          */
271 };
272
273 static struct clk tipb_ck = {
274         .name           = "tibp_ck",
275         .parent         = &tc_ck,
276         .flags          = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
277         .recalc         = &followparent_recalc,
278 };
279
280 static struct clk l3_ocpi_ck = {
281         .name           = "l3_ocpi_ck",
282         .parent         = &tc_ck,
283         .flags          = CLOCK_IN_OMAP16XX,
284         .enable_reg     = ARM_IDLECT3,
285         .enable_bit     = EN_OCPI_CK,
286         .recalc         = &followparent_recalc,
287 };
288
289 static struct clk tc1_ck = {
290         .name           = "tc1_ck",
291         .parent         = &tc_ck,
292         .flags          = CLOCK_IN_OMAP16XX,
293         .enable_reg     = ARM_IDLECT3,
294         .enable_bit     = EN_TC1_CK,
295         .recalc         = &followparent_recalc,
296 };
297
298 static struct clk tc2_ck = {
299         .name           = "tc2_ck",
300         .parent         = &tc_ck,
301         .flags          = CLOCK_IN_OMAP16XX,
302         .enable_reg     = ARM_IDLECT3,
303         .enable_bit     = EN_TC2_CK,
304         .recalc         = &followparent_recalc,
305 };
306
307 static struct clk dma_ck = {
308         .name           = "dma_ck",
309         .parent         = &tc_ck,
310         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
311                           ALWAYS_ENABLED,
312         .recalc         = &followparent_recalc,
313 };
314
315 static struct clk dma_lcdfree_ck = {
316         .name           = "dma_lcdfree_ck",
317         .parent         = &tc_ck,
318         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
319         .recalc         = &followparent_recalc,
320 };
321
322 static struct clk api_ck = {
323         .name           = "api_ck",
324         .parent         = &tc_ck,
325         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
326         .enable_reg     = ARM_IDLECT2,
327         .enable_bit     = EN_APICK,
328         .recalc         = &followparent_recalc,
329 };
330
331 static struct clk lb_ck = {
332         .name           = "lb_ck",
333         .parent         = &tc_ck,
334         .flags          = CLOCK_IN_OMAP1510,
335         .enable_reg     = ARM_IDLECT2,
336         .enable_bit     = EN_LBCK,
337         .recalc         = &followparent_recalc,
338 };
339
340 static struct clk rhea1_ck = {
341         .name           = "rhea1_ck",
342         .parent         = &tc_ck,
343         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
344         .recalc         = &followparent_recalc,
345 };
346
347 static struct clk rhea2_ck = {
348         .name           = "rhea2_ck",
349         .parent         = &tc_ck,
350         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
351         .recalc         = &followparent_recalc,
352 };
353
354 static struct clk lcd_ck = {
355         .name           = "lcd_ck",
356         .parent         = &ck_dpll1,
357         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
358                           RATE_CKCTL,
359         .enable_reg     = ARM_IDLECT2,
360         .enable_bit     = EN_LCDCK,
361         .rate_offset    = CKCTL_LCDDIV_OFFSET,
362         .recalc         = &ckctl_recalc,
363 };
364
365 static struct clk uart1_1510 = {
366         .name           = "uart1_ck",
367         /* Direct from ULPD, no parent */
368         .rate           = 12000000,
369         .flags          = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
370         .enable_reg     = MOD_CONF_CTRL_0,
371         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
372         .set_rate       = &set_uart_rate,
373         .recalc         = &uart_recalc,
374 };
375
376 static struct clk uart1_16xx = {
377         .name           = "uart1_ck",
378         /* Direct from ULPD, no parent */
379         .rate           = 48000000,
380         .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
381         .enable_reg     = MOD_CONF_CTRL_0,
382         .enable_bit     = 29,
383 };
384
385 static struct clk uart2_ck = {
386         .name           = "uart2_ck",
387         /* Direct from ULPD, no parent */
388         .rate           = 12000000,
389         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT |
390                           ALWAYS_ENABLED,
391         .enable_reg     = MOD_CONF_CTRL_0,
392         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
393         .set_rate       = &set_uart_rate,
394         .recalc         = &uart_recalc,
395 };
396
397 static struct clk uart3_1510 = {
398         .name           = "uart3_ck",
399         /* Direct from ULPD, no parent */
400         .rate           = 12000000,
401         .flags          = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
402         .enable_reg     = MOD_CONF_CTRL_0,
403         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
404         .set_rate       = &set_uart_rate,
405         .recalc         = &uart_recalc,
406 };
407
408 static struct clk uart3_16xx = {
409         .name           = "uart3_ck",
410         /* Direct from ULPD, no parent */
411         .rate           = 48000000,
412         .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
413         .enable_reg     = MOD_CONF_CTRL_0,
414         .enable_bit     = 31,
415 };
416
417 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
418         .name           = "usb_clko",
419         /* Direct from ULPD, no parent */
420         .rate           = 6000000,
421         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
422                           RATE_FIXED | ENABLE_REG_32BIT,
423         .enable_reg     = ULPD_CLOCK_CTRL,
424         .enable_bit     = USB_MCLK_EN_BIT,
425 };
426
427 static struct clk usb_hhc_ck1510 = {
428         .name           = "usb_hhc_ck",
429         /* Direct from ULPD, no parent */
430         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
431         .flags          = CLOCK_IN_OMAP1510 |
432                           RATE_FIXED | ENABLE_REG_32BIT,
433         .enable_reg     = MOD_CONF_CTRL_0,
434         .enable_bit     = USB_HOST_HHC_UHOST_EN,
435 };
436
437 static struct clk usb_hhc_ck16xx = {
438         .name           = "usb_hhc_ck",
439         /* Direct from ULPD, no parent */
440         .rate           = 48000000,
441         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
442         .flags          = CLOCK_IN_OMAP16XX |
443                           RATE_FIXED | ENABLE_REG_32BIT,
444         .enable_reg     = OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
445         .enable_bit     = 8 /* UHOST_EN */,
446 };
447
448 static struct clk usb_dc_ck = {
449         .name           = "usb_dc_ck",
450         /* Direct from ULPD, no parent */
451         .rate           = 48000000,
452         .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED,
453         .enable_reg     = SOFT_REQ_REG,
454         .enable_bit     = 4,
455 };
456
457 static struct clk mclk_1510 = {
458         .name           = "mclk",
459         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
460         .rate           = 12000000,
461         .flags          = CLOCK_IN_OMAP1510 | RATE_FIXED,
462 };
463
464 static struct clk mclk_16xx = {
465         .name           = "mclk",
466         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
467         .flags          = CLOCK_IN_OMAP16XX,
468         .enable_reg     = COM_CLK_DIV_CTRL_SEL,
469         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
470         .set_rate       = &set_ext_clk_rate,
471         .round_rate     = &round_ext_clk_rate,
472         .init           = &init_ext_clk,
473 };
474
475 static struct clk bclk_1510 = {
476         .name           = "bclk",
477         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
478         .rate           = 12000000,
479         .flags          = CLOCK_IN_OMAP1510 | RATE_FIXED,
480 };
481
482 static struct clk bclk_16xx = {
483         .name           = "bclk",
484         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
485         .flags          = CLOCK_IN_OMAP16XX,
486         .enable_reg     = SWD_CLK_DIV_CTRL_SEL,
487         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
488         .set_rate       = &set_ext_clk_rate,
489         .round_rate     = &round_ext_clk_rate,
490         .init           = &init_ext_clk,
491 };
492
493 static struct clk mmc1_ck = {
494         .name           = "mmc1_ck",
495         /* Functional clock is direct from ULPD, interface clock is ARMPER */
496         .parent         = &armper_ck,
497         .rate           = 48000000,
498         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
499                           RATE_FIXED | ENABLE_REG_32BIT,
500         .enable_reg     = MOD_CONF_CTRL_0,
501         .enable_bit     = 23,
502 };
503
504 static struct clk mmc2_ck = {
505         .name           = "mmc2_ck",
506         /* Functional clock is direct from ULPD, interface clock is ARMPER */
507         .parent         = &armper_ck,
508         .rate           = 48000000,
509         .flags          = CLOCK_IN_OMAP16XX |
510                           RATE_FIXED | ENABLE_REG_32BIT,
511         .enable_reg     = MOD_CONF_CTRL_0,
512         .enable_bit     = 20,
513 };
514
515 static struct clk virtual_ck_mpu = {
516         .name           = "mpu",
517         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
518                           VIRTUAL_CLOCK | ALWAYS_ENABLED,
519         .parent         = &arm_ck, /* Is smarter alias for */
520         .recalc         = &followparent_recalc,
521         .set_rate       = &select_table_rate,
522         .round_rate     = &round_to_table_rate,
523 };
524
525
526 static struct clk *  onchip_clks[] = {
527         /* non-ULPD clocks */
528         &ck_ref,
529         &ck_dpll1,
530         /* CK_GEN1 clocks */
531         &ck_dpll1out,
532         &arm_ck,
533         &armper_ck,
534         &arm_gpio_ck,
535         &armxor_ck,
536         &armtim_ck,
537         &armwdt_ck,
538         &arminth_ck1510,  &arminth_ck16xx,
539         /* CK_GEN2 clocks */
540         &dsp_ck,
541         &dspmmu_ck,
542         &dspper_ck,
543         &dspxor_ck,
544         &dsptim_ck,
545         /* CK_GEN3 clocks */
546         &tc_ck,
547         &tipb_ck,
548         &l3_ocpi_ck,
549         &tc1_ck,
550         &tc2_ck,
551         &dma_ck,
552         &dma_lcdfree_ck,
553         &api_ck,
554         &lb_ck,
555         &rhea1_ck,
556         &rhea2_ck,
557         &lcd_ck,
558         /* ULPD clocks */
559         &uart1_1510,
560         &uart1_16xx,
561         &uart2_ck,
562         &uart3_1510,
563         &uart3_16xx,
564         &usb_clko,
565         &usb_hhc_ck1510, &usb_hhc_ck16xx,
566         &usb_dc_ck,
567         &mclk_1510,  &mclk_16xx,
568         &bclk_1510,  &bclk_16xx,
569         &mmc1_ck,
570         &mmc2_ck,
571         /* Virtual clocks */
572         &virtual_ck_mpu,
573 };
574
575 struct clk *clk_get(struct device *dev, const char *id)
576 {
577         struct clk *p, *clk = ERR_PTR(-ENOENT);
578
579         down(&clocks_sem);
580         list_for_each_entry(p, &clocks, node) {
581                 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
582                         clk = p;
583                         break;
584                 }
585         }
586         up(&clocks_sem);
587
588         return clk;
589 }
590 EXPORT_SYMBOL(clk_get);
591
592
593 void clk_put(struct clk *clk)
594 {
595         if (clk && !IS_ERR(clk))
596                 module_put(clk->owner);
597 }
598 EXPORT_SYMBOL(clk_put);
599
600
601 int __clk_enable(struct clk *clk)
602 {
603         __u16 regval16;
604         __u32 regval32;
605
606         if (clk->flags & ALWAYS_ENABLED)
607                 return 0;
608
609         if (unlikely(clk->enable_reg == 0)) {
610                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
611                        clk->name);
612                 return 0;
613         }
614
615         if (clk->flags & DSP_DOMAIN_CLOCK) {
616                 __clk_use(&api_ck);
617         }
618
619         if (clk->flags & ENABLE_REG_32BIT) {
620                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
621                         regval32 = __raw_readl(clk->enable_reg);
622                         regval32 |= (1 << clk->enable_bit);
623                         __raw_writel(regval32, clk->enable_reg);
624                 } else {
625                         regval32 = omap_readl(clk->enable_reg);
626                         regval32 |= (1 << clk->enable_bit);
627                         omap_writel(regval32, clk->enable_reg);
628                 }
629         } else {
630                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
631                         regval16 = __raw_readw(clk->enable_reg);
632                         regval16 |= (1 << clk->enable_bit);
633                         __raw_writew(regval16, clk->enable_reg);
634                 } else {
635                         regval16 = omap_readw(clk->enable_reg);
636                         regval16 |= (1 << clk->enable_bit);
637                         omap_writew(regval16, clk->enable_reg);
638                 }
639         }
640
641         if (clk->flags & DSP_DOMAIN_CLOCK) {
642                 __clk_unuse(&api_ck);
643         }
644
645         return 0;
646 }
647
648
649 void __clk_disable(struct clk *clk)
650 {
651         __u16 regval16;
652         __u32 regval32;
653
654         if (clk->enable_reg == 0)
655                 return;
656
657         if (clk->flags & DSP_DOMAIN_CLOCK) {
658                 __clk_use(&api_ck);
659         }
660
661         if (clk->flags & ENABLE_REG_32BIT) {
662                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
663                         regval32 = __raw_readl(clk->enable_reg);
664                         regval32 &= ~(1 << clk->enable_bit);
665                         __raw_writel(regval32, clk->enable_reg);
666                 } else {
667                         regval32 = omap_readl(clk->enable_reg);
668                         regval32 &= ~(1 << clk->enable_bit);
669                         omap_writel(regval32, clk->enable_reg);
670                 }
671         } else {
672                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
673                         regval16 = __raw_readw(clk->enable_reg);
674                         regval16 &= ~(1 << clk->enable_bit);
675                         __raw_writew(regval16, clk->enable_reg);
676                 } else {
677                         regval16 = omap_readw(clk->enable_reg);
678                         regval16 &= ~(1 << clk->enable_bit);
679                         omap_writew(regval16, clk->enable_reg);
680                 }
681         }
682
683         if (clk->flags & DSP_DOMAIN_CLOCK) {
684                 __clk_unuse(&api_ck);
685         }
686 }
687
688
689 void __clk_unuse(struct clk *clk)
690 {
691         if (clk->usecount > 0 && !(--clk->usecount)) {
692                 __clk_disable(clk);
693                 if (likely(clk->parent))
694                         __clk_unuse(clk->parent);
695         }
696 }
697
698
699 int __clk_use(struct clk *clk)
700 {
701         int ret = 0;
702         if (clk->usecount++ == 0) {
703                 if (likely(clk->parent))
704                         ret = __clk_use(clk->parent);
705
706                 if (unlikely(ret != 0)) {
707                         clk->usecount--;
708                         return ret;
709                 }
710
711                 ret = __clk_enable(clk);
712
713                 if (unlikely(ret != 0) && clk->parent) {
714                         __clk_unuse(clk->parent);
715                         clk->usecount--;
716                 }
717         }
718
719         return ret;
720 }
721
722
723 int clk_enable(struct clk *clk)
724 {
725         unsigned long flags;
726         int ret;
727
728         spin_lock_irqsave(&clockfw_lock, flags);
729         ret = __clk_enable(clk);
730         spin_unlock_irqrestore(&clockfw_lock, flags);
731         return ret;
732 }
733 EXPORT_SYMBOL(clk_enable);
734
735
736 void clk_disable(struct clk *clk)
737 {
738         unsigned long flags;
739
740         spin_lock_irqsave(&clockfw_lock, flags);
741         __clk_disable(clk);
742         spin_unlock_irqrestore(&clockfw_lock, flags);
743 }
744 EXPORT_SYMBOL(clk_disable);
745
746
747 int clk_use(struct clk *clk)
748 {
749         unsigned long flags;
750         int ret = 0;
751
752         spin_lock_irqsave(&clockfw_lock, flags);
753         ret = __clk_use(clk);
754         spin_unlock_irqrestore(&clockfw_lock, flags);
755         return ret;
756 }
757 EXPORT_SYMBOL(clk_use);
758
759
760 void clk_unuse(struct clk *clk)
761 {
762         unsigned long flags;
763
764         spin_lock_irqsave(&clockfw_lock, flags);
765         __clk_unuse(clk);
766         spin_unlock_irqrestore(&clockfw_lock, flags);
767 }
768 EXPORT_SYMBOL(clk_unuse);
769
770
771 int clk_get_usecount(struct clk *clk)
772 {
773         return clk->usecount;
774 }
775 EXPORT_SYMBOL(clk_get_usecount);
776
777
778 unsigned long clk_get_rate(struct clk *clk)
779 {
780         return clk->rate;
781 }
782 EXPORT_SYMBOL(clk_get_rate);
783
784
785 static __u16 verify_ckctl_value(__u16 newval)
786 {
787         /* This function checks for following limitations set
788          * by the hardware (all conditions must be true):
789          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
790          * ARM_CK >= TC_CK
791          * DSP_CK >= TC_CK
792          * DSPMMU_CK >= TC_CK
793          *
794          * In addition following rules are enforced:
795          * LCD_CK <= TC_CK
796          * ARMPER_CK <= TC_CK
797          *
798          * However, maximum frequencies are not checked for!
799          */
800         __u8 per_exp;
801         __u8 lcd_exp;
802         __u8 arm_exp;
803         __u8 dsp_exp;
804         __u8 tc_exp;
805         __u8 dspmmu_exp;
806
807         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
808         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
809         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
810         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
811         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
812         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
813
814         if (dspmmu_exp < dsp_exp)
815                 dspmmu_exp = dsp_exp;
816         if (dspmmu_exp > dsp_exp+1)
817                 dspmmu_exp = dsp_exp+1;
818         if (tc_exp < arm_exp)
819                 tc_exp = arm_exp;
820         if (tc_exp < dspmmu_exp)
821                 tc_exp = dspmmu_exp;
822         if (tc_exp > lcd_exp)
823                 lcd_exp = tc_exp;
824         if (tc_exp > per_exp)
825                 per_exp = tc_exp;
826
827         newval &= 0xf000;
828         newval |= per_exp << CKCTL_PERDIV_OFFSET;
829         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
830         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
831         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
832         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
833         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
834
835         return newval;
836 }
837
838
839 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
840 {
841         /* Note: If target frequency is too low, this function will return 4,
842          * which is invalid value. Caller must check for this value and act
843          * accordingly.
844          *
845          * Note: This function does not check for following limitations set
846          * by the hardware (all conditions must be true):
847          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
848          * ARM_CK >= TC_CK
849          * DSP_CK >= TC_CK
850          * DSPMMU_CK >= TC_CK
851          */
852         unsigned long realrate;
853         struct clk *  parent;
854         unsigned  dsor_exp;
855
856         if (unlikely(!(clk->flags & RATE_CKCTL)))
857                 return -EINVAL;
858
859         parent = clk->parent;
860         if (unlikely(parent == 0))
861                 return -EIO;
862
863         realrate = parent->rate;
864         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
865                 if (realrate <= rate)
866                         break;
867
868                 realrate /= 2;
869         }
870
871         return dsor_exp;
872 }
873
874
875 static void ckctl_recalc(struct clk *  clk)
876 {
877         int dsor;
878
879         /* Calculate divisor encoded as 2-bit exponent */
880         if (clk->flags & DSP_DOMAIN_CLOCK) {
881                 /* The clock control bits are in DSP domain,
882                  * so api_ck is needed for access.
883                  * Note that DSP_CKCTL virt addr = phys addr, so
884                  * we must use __raw_readw() instead of omap_readw().
885                  */
886                 __clk_use(&api_ck);
887                 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
888                 __clk_unuse(&api_ck);
889         } else {
890                 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
891         }
892         if (unlikely(clk->rate == clk->parent->rate / dsor))
893                 return; /* No change, quick exit */
894         clk->rate = clk->parent->rate / dsor;
895
896         if (unlikely(clk->flags & RATE_PROPAGATES))
897                 propagate_rate(clk);
898 }
899
900
901 long clk_round_rate(struct clk *clk, unsigned long rate)
902 {
903         int dsor_exp;
904
905         if (clk->flags & RATE_FIXED)
906                 return clk->rate;
907
908         if (clk->flags & RATE_CKCTL) {
909                 dsor_exp = calc_dsor_exp(clk, rate);
910                 if (dsor_exp < 0)
911                         return dsor_exp;
912                 if (dsor_exp > 3)
913                         dsor_exp = 3;
914                 return clk->parent->rate / (1 << dsor_exp);
915         }
916
917         if(clk->round_rate != 0)
918                 return clk->round_rate(clk, rate);
919
920         return clk->rate;
921 }
922 EXPORT_SYMBOL(clk_round_rate);
923
924
925 static void propagate_rate(struct clk *  clk)
926 {
927         struct clk **  clkp;
928
929         for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
930                 if (likely((*clkp)->parent != clk)) continue;
931                 if (likely((*clkp)->recalc))
932                         (*clkp)->recalc(*clkp);
933         }
934 }
935
936
937 static int select_table_rate(struct clk *  clk, unsigned long rate)
938 {
939         /* Find the highest supported frequency <= rate and switch to it */
940         struct mpu_rate *  ptr;
941
942         if (clk != &virtual_ck_mpu)
943                 return -EINVAL;
944
945         for (ptr = rate_table; ptr->rate; ptr++) {
946                 if (ptr->xtal != ck_ref.rate)
947                         continue;
948
949                 /* DPLL1 cannot be reprogrammed without risking system crash */
950                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
951                         continue;
952
953                 /* Can check only after xtal frequency check */
954                 if (ptr->rate <= rate)
955                         break;
956         }
957
958         if (!ptr->rate)
959                 return -EINVAL;
960
961         /*
962          * In most cases we should not need to reprogram DPLL.
963          * Reprogramming the DPLL is tricky, it must be done from SRAM.
964          */
965         omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
966
967         ck_dpll1.rate = ptr->pll_rate;
968         propagate_rate(&ck_dpll1);
969         return 0;
970 }
971
972
973 static long round_to_table_rate(struct clk *  clk, unsigned long rate)
974 {
975         /* Find the highest supported frequency <= rate */
976         struct mpu_rate *  ptr;
977         long  highest_rate;
978
979         if (clk != &virtual_ck_mpu)
980                 return -EINVAL;
981
982         highest_rate = -EINVAL;
983
984         for (ptr = rate_table; ptr->rate; ptr++) {
985                 if (ptr->xtal != ck_ref.rate)
986                         continue;
987
988                 highest_rate = ptr->rate;
989
990                 /* Can check only after xtal frequency check */
991                 if (ptr->rate <= rate)
992                         break;
993         }
994
995         return highest_rate;
996 }
997
998
999 int clk_set_rate(struct clk *clk, unsigned long rate)
1000 {
1001         int  ret = -EINVAL;
1002         int  dsor_exp;
1003         __u16  regval;
1004         unsigned long  flags;
1005
1006         if (clk->flags & RATE_CKCTL) {
1007                 dsor_exp = calc_dsor_exp(clk, rate);
1008                 if (dsor_exp > 3)
1009                         dsor_exp = -EINVAL;
1010                 if (dsor_exp < 0)
1011                         return dsor_exp;
1012
1013                 spin_lock_irqsave(&clockfw_lock, flags);
1014                 regval = omap_readw(ARM_CKCTL);
1015                 regval &= ~(3 << clk->rate_offset);
1016                 regval |= dsor_exp << clk->rate_offset;
1017                 regval = verify_ckctl_value(regval);
1018                 omap_writew(regval, ARM_CKCTL);
1019                 clk->rate = clk->parent->rate / (1 << dsor_exp);
1020                 spin_unlock_irqrestore(&clockfw_lock, flags);
1021                 ret = 0;
1022         } else if(clk->set_rate != 0) {
1023                 spin_lock_irqsave(&clockfw_lock, flags);
1024                 ret = clk->set_rate(clk, rate);
1025                 spin_unlock_irqrestore(&clockfw_lock, flags);
1026         }
1027
1028         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
1029                 propagate_rate(clk);
1030
1031         return ret;
1032 }
1033 EXPORT_SYMBOL(clk_set_rate);
1034
1035
1036 static unsigned calc_ext_dsor(unsigned long rate)
1037 {
1038         unsigned dsor;
1039
1040         /* MCLK and BCLK divisor selection is not linear:
1041          * freq = 96MHz / dsor
1042          *
1043          * RATIO_SEL range: dsor <-> RATIO_SEL
1044          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
1045          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
1046          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
1047          * can not be used.
1048          */
1049         for (dsor = 2; dsor < 96; ++dsor) {
1050                 if ((dsor & 1) && dsor > 8)
1051                         continue;
1052                 if (rate >= 96000000 / dsor)
1053                         break;
1054         }
1055         return dsor;
1056 }
1057
1058 /* Only needed on 1510 */
1059 static int set_uart_rate(struct clk * clk, unsigned long rate)
1060 {
1061         unsigned int val;
1062
1063         val = omap_readl(clk->enable_reg);
1064         if (rate == 12000000)
1065                 val &= ~(1 << clk->enable_bit);
1066         else if (rate == 48000000)
1067                 val |= (1 << clk->enable_bit);
1068         else
1069                 return -EINVAL;
1070         omap_writel(val, clk->enable_reg);
1071         clk->rate = rate;
1072
1073         return 0;
1074 }
1075
1076 static int set_ext_clk_rate(struct clk *  clk, unsigned long rate)
1077 {
1078         unsigned dsor;
1079         __u16 ratio_bits;
1080
1081         dsor = calc_ext_dsor(rate);
1082         clk->rate = 96000000 / dsor;
1083         if (dsor > 8)
1084                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
1085         else
1086                 ratio_bits = (dsor - 2) << 2;
1087
1088         ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
1089         omap_writew(ratio_bits, clk->enable_reg);
1090
1091         return 0;
1092 }
1093
1094
1095 static long round_ext_clk_rate(struct clk *  clk, unsigned long rate)
1096 {
1097         return 96000000 / calc_ext_dsor(rate);
1098 }
1099
1100
1101 static void init_ext_clk(struct clk *  clk)
1102 {
1103         unsigned dsor;
1104         __u16 ratio_bits;
1105
1106         /* Determine current rate and ensure clock is based on 96MHz APLL */
1107         ratio_bits = omap_readw(clk->enable_reg) & ~1;
1108         omap_writew(ratio_bits, clk->enable_reg);
1109
1110         ratio_bits = (ratio_bits & 0xfc) >> 2;
1111         if (ratio_bits > 6)
1112                 dsor = (ratio_bits - 6) * 2 + 8;
1113         else
1114                 dsor = ratio_bits + 2;
1115
1116         clk-> rate = 96000000 / dsor;
1117 }
1118
1119
1120 int clk_register(struct clk *clk)
1121 {
1122         down(&clocks_sem);
1123         list_add(&clk->node, &clocks);
1124         if (clk->init)
1125                 clk->init(clk);
1126         up(&clocks_sem);
1127         return 0;
1128 }
1129 EXPORT_SYMBOL(clk_register);
1130
1131 void clk_unregister(struct clk *clk)
1132 {
1133         down(&clocks_sem);
1134         list_del(&clk->node);
1135         up(&clocks_sem);
1136 }
1137 EXPORT_SYMBOL(clk_unregister);
1138
1139 #ifdef CONFIG_OMAP_RESET_CLOCKS
1140 /*
1141  * Resets some clocks that may be left on from bootloader,
1142  * but leaves serial clocks on. See also omap_late_clk_reset().
1143  */
1144 static inline void omap_early_clk_reset(void)
1145 {
1146         //omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
1147 }
1148 #else
1149 #define omap_early_clk_reset()  {}
1150 #endif
1151
1152 int __init clk_init(void)
1153 {
1154         struct clk **  clkp;
1155         const struct omap_clock_config *info;
1156         int crystal_type = 0; /* Default 12 MHz */
1157
1158         omap_early_clk_reset();
1159
1160         for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
1161                 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
1162                         clk_register(*clkp);
1163                         continue;
1164                 }
1165
1166                 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
1167                         clk_register(*clkp);
1168                         continue;
1169                 }
1170
1171                 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
1172                         clk_register(*clkp);
1173                         continue;
1174                 }
1175         }
1176
1177         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
1178         if (info != NULL) {
1179                 if (!cpu_is_omap1510())
1180                         crystal_type = info->system_clock_type;
1181         }
1182
1183 #if defined(CONFIG_ARCH_OMAP730)
1184         ck_ref.rate = 13000000;
1185 #elif defined(CONFIG_ARCH_OMAP16XX)
1186         if (crystal_type == 2)
1187                 ck_ref.rate = 19200000;
1188 #endif
1189
1190         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
1191                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
1192                omap_readw(ARM_CKCTL));
1193
1194         /* We want to be in syncronous scalable mode */
1195         omap_writew(0x1000, ARM_SYSST);
1196
1197 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
1198         /* Use values set by bootloader. Determine PLL rate and recalculate
1199          * dependent clocks as if kernel had changed PLL or divisors.
1200          */
1201         {
1202                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
1203
1204                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
1205                 if (pll_ctl_val & 0x10) {
1206                         /* PLL enabled, apply multiplier and divisor */
1207                         if (pll_ctl_val & 0xf80)
1208                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
1209                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
1210                 } else {
1211                         /* PLL disabled, apply bypass divisor */
1212                         switch (pll_ctl_val & 0xc) {
1213                         case 0:
1214                                 break;
1215                         case 0x4:
1216                                 ck_dpll1.rate /= 2;
1217                                 break;
1218                         default:
1219                                 ck_dpll1.rate /= 4;
1220                                 break;
1221                         }
1222                 }
1223         }
1224         propagate_rate(&ck_dpll1);
1225 #else
1226         /* Find the highest supported frequency and enable it */
1227         if (select_table_rate(&virtual_ck_mpu, ~0)) {
1228                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
1229                 /* Guess sane values (60MHz) */
1230                 omap_writew(0x2290, DPLL_CTL);
1231                 omap_writew(0x1005, ARM_CKCTL);
1232                 ck_dpll1.rate = 60000000;
1233                 propagate_rate(&ck_dpll1);
1234         }
1235 #endif
1236         /* Cache rates for clocks connected to ck_ref (not dpll1) */
1237         propagate_rate(&ck_ref);
1238         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
1239                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
1240                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
1241                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
1242                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
1243
1244 #ifdef CONFIG_MACH_OMAP_PERSEUS2
1245         /* Select slicer output as OMAP input clock */
1246         omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
1247 #endif
1248
1249         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
1250         omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
1251
1252         /* Put DSP/MPUI into reset until needed */
1253         omap_writew(0, ARM_RSTCT1);
1254         omap_writew(1, ARM_RSTCT2);
1255         omap_writew(0x400, ARM_IDLECT1);
1256
1257         /*
1258          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
1259          * of the ARM_IDLECT2 register must be set to zero. The power-on
1260          * default value of this bit is one.
1261          */
1262         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
1263
1264         /*
1265          * Only enable those clocks we will need, let the drivers
1266          * enable other clocks as necessary
1267          */
1268         clk_use(&armper_ck);
1269         clk_use(&armxor_ck);
1270         clk_use(&armtim_ck);
1271
1272         if (cpu_is_omap1510())
1273                 clk_enable(&arm_gpio_ck);
1274
1275         return 0;
1276 }
1277
1278
1279 #ifdef CONFIG_OMAP_RESET_CLOCKS
1280
1281 static int __init omap_late_clk_reset(void)
1282 {
1283         /* Turn off all unused clocks */
1284         struct clk *p;
1285         __u32 regval32;
1286
1287         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
1288         regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4);
1289         omap_writew(regval32, SOFT_REQ_REG);
1290         omap_writew(0, SOFT_REQ_REG2);
1291
1292         list_for_each_entry(p, &clocks, node) {
1293                 if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) ||
1294                         p->enable_reg == 0)
1295                         continue;
1296
1297                 /* Assume no DSP clocks have been activated by bootloader */
1298                 if (p->flags & DSP_DOMAIN_CLOCK)
1299                         continue;
1300
1301                 /* Is the clock already disabled? */
1302                 if (p->flags & ENABLE_REG_32BIT) {
1303                         if (p->flags & VIRTUAL_IO_ADDRESS)
1304                                 regval32 = __raw_readl(p->enable_reg);
1305                         else
1306                                 regval32 = omap_readl(p->enable_reg);
1307                 } else {
1308                         if (p->flags & VIRTUAL_IO_ADDRESS)
1309                                 regval32 = __raw_readw(p->enable_reg);
1310                         else
1311                                 regval32 = omap_readw(p->enable_reg);
1312                 }
1313
1314                 if ((regval32 & (1 << p->enable_bit)) == 0)
1315                         continue;
1316
1317                 /* FIXME: This clock seems to be necessary but no-one
1318                  * has asked for its activation. */
1319                 if (p == &tc2_ck         // FIX: pm.c (SRAM), CCP, Camera
1320                     || p == &ck_dpll1out // FIX: SoSSI, SSR
1321                     || p == &arm_gpio_ck // FIX: GPIO code for 1510
1322                     ) {
1323                         printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
1324                                p->name);
1325                         continue;
1326                 }
1327
1328                 printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name);
1329                 __clk_disable(p);
1330                 printk(" done\n");
1331         }
1332
1333         return 0;
1334 }
1335
1336 late_initcall(omap_late_clk_reset);
1337
1338 #endif