git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-core.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *****************************************************************************/
  28
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <net/mac80211.h>
  32
  33 #include "iwl-eeprom.h"
  34 #include "iwl-dev.h" /* FIXME: remove */
  35 #include "iwl-debug.h"
  36 #include "iwl-core.h"
  37 #include "iwl-io.h"
  38 #include "iwl-rfkill.h"
  39 #include "iwl-power.h"
  40 #include "iwl-sta.h"
  41
  42
  43 MODULE_DESCRIPTION("iwl core");
  44 MODULE_VERSION(IWLWIFI_VERSION);
  45 MODULE_AUTHOR(DRV_COPYRIGHT);
  46 MODULE_LICENSE("GPL");
  47
  48 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np)    \
  49         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,      \
  50                                     IWL_RATE_SISO_##s##M_PLCP, \
  51                                     IWL_RATE_MIMO2_##s##M_PLCP,\
  52                                     IWL_RATE_MIMO3_##s##M_PLCP,\
  53                                     IWL_RATE_##r##M_IEEE,      \
  54                                     IWL_RATE_##ip##M_INDEX,    \
  55                                     IWL_RATE_##in##M_INDEX,    \
  56                                     IWL_RATE_##rp##M_INDEX,    \
  57                                     IWL_RATE_##rn##M_INDEX,    \
  58                                     IWL_RATE_##pp##M_INDEX,    \
  59                                     IWL_RATE_##np##M_INDEX }
  60
  61 /*
  62  * Parameter order:
  63  *   rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  64  *
  65  * If there isn't a valid next or previous rate then INV is used which
  66  * maps to IWL_RATE_INVALID
  67  *
  68  */
  69 const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  70         IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  71         IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  72         IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  73         IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18),      /* 11mbps */
  74         IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  75         IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11),       /*  9mbps */
  76         IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  77         IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  78         IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  79         IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  80         IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  81         IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  82         IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  83         /* FIXME:RS:          ^^    should be INV (legacy) */
  84 };
  85 EXPORT_SYMBOL(iwl_rates);
  86
  87 /**
  88  * translate ucode response to mac80211 tx status control values
  89  */
  90 void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  91                                   struct ieee80211_tx_info *info)
  92 {
  93         int rate_index;
  94         struct ieee80211_tx_rate *r = &info->control.rates[0];
  95
  96         info->antenna_sel_tx =
  97                 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  98         if (rate_n_flags & RATE_MCS_HT_MSK)
  99                 r->flags |= IEEE80211_TX_RC_MCS;
 100         if (rate_n_flags & RATE_MCS_GF_MSK)
 101                 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
 102         if (rate_n_flags & RATE_MCS_FAT_MSK)
 103                 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
 104         if (rate_n_flags & RATE_MCS_DUP_MSK)
 105                 r->flags |= IEEE80211_TX_RC_DUP_DATA;
 106         if (rate_n_flags & RATE_MCS_SGI_MSK)
 107                 r->flags |= IEEE80211_TX_RC_SHORT_GI;
 108         rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
 109         if (info->band == IEEE80211_BAND_5GHZ)
 110                 rate_index -= IWL_FIRST_OFDM_RATE;
 111         r->idx = rate_index;
 112 }
 113 EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
 114
 115 int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
 116 {
 117         int idx = 0;
 118
 119         /* HT rate format */
 120         if (rate_n_flags & RATE_MCS_HT_MSK) {
 121                 idx = (rate_n_flags & 0xff);
 122
 123                 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
 124                         idx = idx - IWL_RATE_MIMO3_6M_PLCP;
 125                 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
 126                         idx = idx - IWL_RATE_MIMO2_6M_PLCP;
 127
 128                 idx += IWL_FIRST_OFDM_RATE;
 129                 /* skip 9M not supported in ht*/
 130                 if (idx >= IWL_RATE_9M_INDEX)
 131                         idx += 1;
 132                 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
 133                         return idx;
 134
 135         /* legacy rate format, search for match in table */
 136         } else {
 137                 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
 138                         if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
 139                                 return idx;
 140         }
 141
 142         return -1;
 143 }
 144 EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
 145
 146 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
 147 {
 148         int i;
 149         u8 ind = ant;
 150         for (i = 0; i < RATE_ANT_NUM - 1; i++) {
 151                 ind = (ind + 1) < RATE_ANT_NUM ?  ind + 1 : 0;
 152                 if (priv->hw_params.valid_tx_ant & BIT(ind))
 153                         return ind;
 154         }
 155         return ant;
 156 }
 157
 158 const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
 159 EXPORT_SYMBOL(iwl_bcast_addr);
 160
 161
 162 /* This function both allocates and initializes hw and priv. */
 163 struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
 164                 struct ieee80211_ops *hw_ops)
 165 {
 166         struct iwl_priv *priv;
 167
 168         /* mac80211 allocates memory for this device instance, including
 169          *   space for this driver's private structure */
 170         struct ieee80211_hw *hw =
 171                 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
 172         if (hw == NULL) {
 173                 IWL_ERROR("Can not allocate network device\n");
 174                 goto out;
 175         }
 176
 177         priv = hw->priv;
 178         priv->hw = hw;
 179
 180 out:
 181         return hw;
 182 }
 183 EXPORT_SYMBOL(iwl_alloc_all);
 184
 185 void iwl_hw_detect(struct iwl_priv *priv)
 186 {
 187         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
 188         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
 189         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
 190 }
 191 EXPORT_SYMBOL(iwl_hw_detect);
 192
 193 int iwl_hw_nic_init(struct iwl_priv *priv)
 194 {
 195         unsigned long flags;
 196         struct iwl_rx_queue *rxq = &priv->rxq;
 197         int ret;
 198
 199         /* nic_init */
 200         spin_lock_irqsave(&priv->lock, flags);
 201         priv->cfg->ops->lib->apm_ops.init(priv);
 202         iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
 203         spin_unlock_irqrestore(&priv->lock, flags);
 204
 205         ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
 206
 207         priv->cfg->ops->lib->apm_ops.config(priv);
 208
 209         /* Allocate the RX queue, or reset if it is already allocated */
 210         if (!rxq->bd) {
 211                 ret = iwl_rx_queue_alloc(priv);
 212                 if (ret) {
 213                         IWL_ERROR("Unable to initialize Rx queue\n");
 214                         return -ENOMEM;
 215                 }
 216         } else
 217                 iwl_rx_queue_reset(priv, rxq);
 218
 219         iwl_rx_replenish(priv);
 220
 221         iwl_rx_init(priv, rxq);
 222
 223         spin_lock_irqsave(&priv->lock, flags);
 224
 225         rxq->need_update = 1;
 226         iwl_rx_queue_update_write_ptr(priv, rxq);
 227
 228         spin_unlock_irqrestore(&priv->lock, flags);
 229
 230         /* Allocate and init all Tx and Command queues */
 231         ret = iwl_txq_ctx_reset(priv);
 232         if (ret)
 233                 return ret;
 234
 235         set_bit(STATUS_INIT, &priv->status);
 236
 237         return 0;
 238 }
 239 EXPORT_SYMBOL(iwl_hw_nic_init);
 240
 241 void iwl_reset_qos(struct iwl_priv *priv)
 242 {
 243         u16 cw_min = 15;
 244         u16 cw_max = 1023;
 245         u8 aifs = 2;
 246         u8 is_legacy = 0;
 247         unsigned long flags;
 248         int i;
 249
 250         spin_lock_irqsave(&priv->lock, flags);
 251         priv->qos_data.qos_active = 0;
 252
 253         if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
 254                 if (priv->qos_data.qos_enable)
 255                         priv->qos_data.qos_active = 1;
 256                 if (!(priv->active_rate & 0xfff0)) {
 257                         cw_min = 31;
 258                         is_legacy = 1;
 259                 }
 260         } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
 261                 if (priv->qos_data.qos_enable)
 262                         priv->qos_data.qos_active = 1;
 263         } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
 264                 cw_min = 31;
 265                 is_legacy = 1;
 266         }
 267
 268         if (priv->qos_data.qos_active)
 269                 aifs = 3;
 270
 271         priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
 272         priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
 273         priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
 274         priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
 275         priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
 276
 277         if (priv->qos_data.qos_active) {
 278                 i = 1;
 279                 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
 280                 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
 281                 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
 282                 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
 283                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 284
 285                 i = 2;
 286                 priv->qos_data.def_qos_parm.ac[i].cw_min =
 287                         cpu_to_le16((cw_min + 1) / 2 - 1);
 288                 priv->qos_data.def_qos_parm.ac[i].cw_max =
 289                         cpu_to_le16(cw_max);
 290                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
 291                 if (is_legacy)
 292                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 293                                 cpu_to_le16(6016);
 294                 else
 295                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 296                                 cpu_to_le16(3008);
 297                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 298
 299                 i = 3;
 300                 priv->qos_data.def_qos_parm.ac[i].cw_min =
 301                         cpu_to_le16((cw_min + 1) / 4 - 1);
 302                 priv->qos_data.def_qos_parm.ac[i].cw_max =
 303                         cpu_to_le16((cw_max + 1) / 2 - 1);
 304                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
 305                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 306                 if (is_legacy)
 307                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 308                                 cpu_to_le16(3264);
 309                 else
 310                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 311                                 cpu_to_le16(1504);
 312         } else {
 313                 for (i = 1; i < 4; i++) {
 314                         priv->qos_data.def_qos_parm.ac[i].cw_min =
 315                                 cpu_to_le16(cw_min);
 316                         priv->qos_data.def_qos_parm.ac[i].cw_max =
 317                                 cpu_to_le16(cw_max);
 318                         priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
 319                         priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
 320                         priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 321                 }
 322         }
 323         IWL_DEBUG_QOS("set QoS to default \n");
 324
 325         spin_unlock_irqrestore(&priv->lock, flags);
 326 }
 327 EXPORT_SYMBOL(iwl_reset_qos);
 328
 329 #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
 330 #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
 331 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
 332                               struct ieee80211_sta_ht_cap *ht_info,
 333                               enum ieee80211_band band)
 334 {
 335         u16 max_bit_rate = 0;
 336         u8 rx_chains_num = priv->hw_params.rx_chains_num;
 337         u8 tx_chains_num = priv->hw_params.tx_chains_num;
 338
 339         ht_info->cap = 0;
 340         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 341
 342         ht_info->ht_supported = true;
 343
 344         ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
 345         ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
 346         ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
 347                              (WLAN_HT_CAP_SM_PS_DISABLED << 2));
 348
 349         max_bit_rate = MAX_BIT_RATE_20_MHZ;
 350         if (priv->hw_params.fat_channel & BIT(band)) {
 351                 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
 352                 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
 353                 ht_info->mcs.rx_mask[4] = 0x01;
 354                 max_bit_rate = MAX_BIT_RATE_40_MHZ;
 355         }
 356
 357         if (priv->cfg->mod_params->amsdu_size_8K)
 358                 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
 359
 360         ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
 361         ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
 362
 363         ht_info->mcs.rx_mask[0] = 0xFF;
 364         if (rx_chains_num >= 2)
 365                 ht_info->mcs.rx_mask[1] = 0xFF;
 366         if (rx_chains_num >= 3)
 367                 ht_info->mcs.rx_mask[2] = 0xFF;
 368
 369         /* Highest supported Rx data rate */
 370         max_bit_rate *= rx_chains_num;
 371         WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
 372         ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
 373
 374         /* Tx MCS capabilities */
 375         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 376         if (tx_chains_num != rx_chains_num) {
 377                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
 378                 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
 379                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
 380         }
 381 }
 382
 383 static void iwlcore_init_hw_rates(struct iwl_priv *priv,
 384                               struct ieee80211_rate *rates)
 385 {
 386         int i;
 387
 388         for (i = 0; i < IWL_RATE_COUNT; i++) {
 389                 rates[i].bitrate = iwl_rates[i].ieee * 5;
 390                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
 391                 rates[i].hw_value_short = i;
 392                 rates[i].flags = 0;
 393                 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
 394                         /*
 395                          * If CCK != 1M then set short preamble rate flag.
 396                          */
 397                         rates[i].flags |=
 398                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
 399                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
 400                 }
 401         }
 402 }
 403
 404 /**
 405  * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
 406  */
 407 static int iwlcore_init_geos(struct iwl_priv *priv)
 408 {
 409         struct iwl_channel_info *ch;
 410         struct ieee80211_supported_band *sband;
 411         struct ieee80211_channel *channels;
 412         struct ieee80211_channel *geo_ch;
 413         struct ieee80211_rate *rates;
 414         int i = 0;
 415
 416         if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
 417             priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
 418                 IWL_DEBUG_INFO("Geography modes already initialized.\n");
 419                 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
 420                 return 0;
 421         }
 422
 423         channels = kzalloc(sizeof(struct ieee80211_channel) *
 424                            priv->channel_count, GFP_KERNEL);
 425         if (!channels)
 426                 return -ENOMEM;
 427
 428         rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
 429                         GFP_KERNEL);
 430         if (!rates) {
 431                 kfree(channels);
 432                 return -ENOMEM;
 433         }
 434
 435         /* 5.2GHz channels start after the 2.4GHz channels */
 436         sband = &priv->bands[IEEE80211_BAND_5GHZ];
 437         sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
 438         /* just OFDM */
 439         sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
 440         sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
 441
 442         if (priv->cfg->sku & IWL_SKU_N)
 443                 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
 444                                          IEEE80211_BAND_5GHZ);
 445
 446         sband = &priv->bands[IEEE80211_BAND_2GHZ];
 447         sband->channels = channels;
 448         /* OFDM & CCK */
 449         sband->bitrates = rates;
 450         sband->n_bitrates = IWL_RATE_COUNT;
 451
 452         if (priv->cfg->sku & IWL_SKU_N)
 453                 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
 454                                          IEEE80211_BAND_2GHZ);
 455
 456         priv->ieee_channels = channels;
 457         priv->ieee_rates = rates;
 458
 459         iwlcore_init_hw_rates(priv, rates);
 460
 461         for (i = 0;  i < priv->channel_count; i++) {
 462                 ch = &priv->channel_info[i];
 463
 464                 /* FIXME: might be removed if scan is OK */
 465                 if (!is_channel_valid(ch))
 466                         continue;
 467
 468                 if (is_channel_a_band(ch))
 469                         sband =  &priv->bands[IEEE80211_BAND_5GHZ];
 470                 else
 471                         sband =  &priv->bands[IEEE80211_BAND_2GHZ];
 472
 473                 geo_ch = &sband->channels[sband->n_channels++];
 474
 475                 geo_ch->center_freq =
 476                                 ieee80211_channel_to_frequency(ch->channel);
 477                 geo_ch->max_power = ch->max_power_avg;
 478                 geo_ch->max_antenna_gain = 0xff;
 479                 geo_ch->hw_value = ch->channel;
 480
 481                 if (is_channel_valid(ch)) {
 482                         if (!(ch->flags & EEPROM_CHANNEL_IBSS))
 483                                 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
 484
 485                         if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
 486                                 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 487
 488                         if (ch->flags & EEPROM_CHANNEL_RADAR)
 489                                 geo_ch->flags |= IEEE80211_CHAN_RADAR;
 490
 491                         geo_ch->flags |= ch->fat_extension_channel;
 492
 493                         if (ch->max_power_avg > priv->tx_power_channel_lmt)
 494                                 priv->tx_power_channel_lmt = ch->max_power_avg;
 495                 } else {
 496                         geo_ch->flags |= IEEE80211_CHAN_DISABLED;
 497                 }
 498
 499                 /* Save flags for reg domain usage */
 500                 geo_ch->orig_flags = geo_ch->flags;
 501
 502                 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
 503                                 ch->channel, geo_ch->center_freq,
 504                                 is_channel_a_band(ch) ?  "5.2" : "2.4",
 505                                 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
 506                                 "restricted" : "valid",
 507                                  geo_ch->flags);
 508         }
 509
 510         if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
 511              priv->cfg->sku & IWL_SKU_A) {
 512                 printk(KERN_INFO DRV_NAME
 513                        ": Incorrectly detected BG card as ABG.  Please send "
 514                        "your PCI ID 0x%04X:0x%04X to maintainer.\n",
 515                        priv->pci_dev->device, priv->pci_dev->subsystem_device);
 516                 priv->cfg->sku &= ~IWL_SKU_A;
 517         }
 518
 519         printk(KERN_INFO DRV_NAME
 520                ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
 521                priv->bands[IEEE80211_BAND_2GHZ].n_channels,
 522                priv->bands[IEEE80211_BAND_5GHZ].n_channels);
 523
 524
 525         set_bit(STATUS_GEO_CONFIGURED, &priv->status);
 526
 527         return 0;
 528 }
 529
 530 /*
 531  * iwlcore_free_geos - undo allocations in iwlcore_init_geos
 532  */
 533 static void iwlcore_free_geos(struct iwl_priv *priv)
 534 {
 535         kfree(priv->ieee_channels);
 536         kfree(priv->ieee_rates);
 537         clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
 538 }
 539
 540 static bool is_single_rx_stream(struct iwl_priv *priv)
 541 {
 542         return !priv->current_ht_config.is_ht ||
 543                ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
 544                 (priv->current_ht_config.mcs.rx_mask[2] == 0));
 545 }
 546
 547 static u8 iwl_is_channel_extension(struct iwl_priv *priv,
 548                                    enum ieee80211_band band,
 549                                    u16 channel, u8 extension_chan_offset)
 550 {
 551         const struct iwl_channel_info *ch_info;
 552
 553         ch_info = iwl_get_channel_info(priv, band, channel);
 554         if (!is_channel_valid(ch_info))
 555                 return 0;
 556
 557         if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
 558                 return !(ch_info->fat_extension_channel &
 559                                         IEEE80211_CHAN_NO_FAT_ABOVE);
 560         else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
 561                 return !(ch_info->fat_extension_channel &
 562                                         IEEE80211_CHAN_NO_FAT_BELOW);
 563
 564         return 0;
 565 }
 566
 567 u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
 568                          struct ieee80211_sta_ht_cap *sta_ht_inf)
 569 {
 570         struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
 571
 572         if ((!iwl_ht_conf->is_ht) ||
 573            (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
 574            (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE))
 575                 return 0;
 576
 577         if (sta_ht_inf) {
 578                 if ((!sta_ht_inf->ht_supported) ||
 579                    (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)))
 580                         return 0;
 581         }
 582
 583         return iwl_is_channel_extension(priv, priv->band,
 584                                         le16_to_cpu(priv->staging_rxon.channel),
 585                                         iwl_ht_conf->extension_chan_offset);
 586 }
 587 EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
 588
 589 void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
 590 {
 591         struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
 592         u32 val;
 593
 594         if (!ht_info->is_ht) {
 595                 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
 596                         RXON_FLG_CHANNEL_MODE_PURE_40_MSK |
 597                         RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
 598                         RXON_FLG_FAT_PROT_MSK |
 599                         RXON_FLG_HT_PROT_MSK);
 600                 return;
 601         }
 602
 603         /* Set up channel bandwidth:  20 MHz only, or 20/40 mixed if fat ok */
 604         if (iwl_is_fat_tx_allowed(priv, NULL))
 605                 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
 606         else
 607                 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
 608                                  RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
 609
 610         /* Note: control channel is opposite of extension channel */
 611         switch (ht_info->extension_chan_offset) {
 612         case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
 613                 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
 614                 break;
 615         case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
 616                 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
 617                 break;
 618         case IEEE80211_HT_PARAM_CHA_SEC_NONE:
 619         default:
 620                 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
 621                 break;
 622         }
 623
 624         val = ht_info->ht_protection;
 625
 626         rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
 627
 628         iwl_set_rxon_chain(priv);
 629
 630         IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
 631                         "rxon flags 0x%X operation mode :0x%X "
 632                         "extension channel offset 0x%x\n",
 633                         ht_info->mcs.rx_mask[0],
 634                         ht_info->mcs.rx_mask[1],
 635                         ht_info->mcs.rx_mask[2],
 636                         le32_to_cpu(rxon->flags), ht_info->ht_protection,
 637                         ht_info->extension_chan_offset);
 638         return;
 639 }
 640 EXPORT_SYMBOL(iwl_set_rxon_ht);
 641
 642 #define IWL_NUM_RX_CHAINS_MULTIPLE      3
 643 #define IWL_NUM_RX_CHAINS_SINGLE        2
 644 #define IWL_NUM_IDLE_CHAINS_DUAL        2
 645 #define IWL_NUM_IDLE_CHAINS_SINGLE      1
 646
 647 /* Determine how many receiver/antenna chains to use.
 648  * More provides better reception via diversity.  Fewer saves power.
 649  * MIMO (dual stream) requires at least 2, but works better with 3.
 650  * This does not determine *which* chains to use, just how many.
 651  */
 652 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
 653 {
 654         bool is_single = is_single_rx_stream(priv);
 655         bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
 656
 657         /* # of Rx chains to use when expecting MIMO. */
 658         if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
 659                                                  WLAN_HT_CAP_SM_PS_STATIC)))
 660                 return IWL_NUM_RX_CHAINS_SINGLE;
 661         else
 662                 return IWL_NUM_RX_CHAINS_MULTIPLE;
 663 }
 664
 665 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
 666 {
 667         int idle_cnt;
 668         bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
 669         /* # Rx chains when idling and maybe trying to save power */
 670         switch (priv->current_ht_config.sm_ps) {
 671         case WLAN_HT_CAP_SM_PS_STATIC:
 672         case WLAN_HT_CAP_SM_PS_DYNAMIC:
 673                 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
 674                                         IWL_NUM_IDLE_CHAINS_SINGLE;
 675                 break;
 676         case WLAN_HT_CAP_SM_PS_DISABLED:
 677                 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
 678                 break;
 679         case WLAN_HT_CAP_SM_PS_INVALID:
 680         default:
 681                 IWL_ERROR("invalid mimo ps mode %d\n",
 682                            priv->current_ht_config.sm_ps);
 683                 WARN_ON(1);
 684                 idle_cnt = -1;
 685                 break;
 686         }
 687         return idle_cnt;
 688 }
 689
 690 /* up to 4 chains */
 691 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
 692 {
 693         u8 res;
 694         res = (chain_bitmap & BIT(0)) >> 0;
 695         res += (chain_bitmap & BIT(1)) >> 1;
 696         res += (chain_bitmap & BIT(2)) >> 2;
 697         res += (chain_bitmap & BIT(4)) >> 4;
 698         return res;
 699 }
 700
 701 /**
 702  * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
 703  *
 704  * Selects how many and which Rx receivers/antennas/chains to use.
 705  * This should not be used for scan command ... it puts data in wrong place.
 706  */
 707 void iwl_set_rxon_chain(struct iwl_priv *priv)
 708 {
 709         bool is_single = is_single_rx_stream(priv);
 710         bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
 711         u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
 712         u32 active_chains;
 713         u16 rx_chain;
 714
 715         /* Tell uCode which antennas are actually connected.
 716          * Before first association, we assume all antennas are connected.
 717          * Just after first association, iwl_chain_noise_calibration()
 718          *    checks which antennas actually *are* connected. */
 719          if (priv->chain_noise_data.active_chains)
 720                 active_chains = priv->chain_noise_data.active_chains;
 721         else
 722                 active_chains = priv->hw_params.valid_rx_ant;
 723
 724         rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
 725
 726         /* How many receivers should we use? */
 727         active_rx_cnt = iwl_get_active_rx_chain_count(priv);
 728         idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
 729
 730
 731         /* correct rx chain count according hw settings
 732          * and chain noise calibration
 733          */
 734         valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
 735         if (valid_rx_cnt < active_rx_cnt)
 736                 active_rx_cnt = valid_rx_cnt;
 737
 738         if (valid_rx_cnt < idle_rx_cnt)
 739                 idle_rx_cnt = valid_rx_cnt;
 740
 741         rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
 742         rx_chain |= idle_rx_cnt  << RXON_RX_CHAIN_CNT_POS;
 743
 744         priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
 745
 746         if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
 747                 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
 748         else
 749                 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
 750
 751         IWL_DEBUG_ASSOC("rx_chain=0x%X active=%d idle=%d\n",
 752                         priv->staging_rxon.rx_chain,
 753                         active_rx_cnt, idle_rx_cnt);
 754
 755         WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
 756                 active_rx_cnt < idle_rx_cnt);
 757 }
 758 EXPORT_SYMBOL(iwl_set_rxon_chain);
 759
 760 /**
 761  * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
 762  * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
 763  * @channel: Any channel valid for the requested phymode
 764
 765  * In addition to setting the staging RXON, priv->phymode is also set.
 766  *
 767  * NOTE:  Does not commit to the hardware; it sets appropriate bit fields
 768  * in the staging RXON flag structure based on the phymode
 769  */
 770 int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
 771 {
 772         enum ieee80211_band band = ch->band;
 773         u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
 774
 775         if (!iwl_get_channel_info(priv, band, channel)) {
 776                 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
 777                                channel, band);
 778                 return -EINVAL;
 779         }
 780
 781         if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
 782             (priv->band == band))
 783                 return 0;
 784
 785         priv->staging_rxon.channel = cpu_to_le16(channel);
 786         if (band == IEEE80211_BAND_5GHZ)
 787                 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
 788         else
 789                 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
 790
 791         priv->band = band;
 792
 793         IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
 794
 795         return 0;
 796 }
 797 EXPORT_SYMBOL(iwl_set_rxon_channel);
 798
 799 int iwl_setup_mac(struct iwl_priv *priv)
 800 {
 801         int ret;
 802         struct ieee80211_hw *hw = priv->hw;
 803         hw->rate_control_algorithm = "iwl-agn-rs";
 804
 805         /* Tell mac80211 our characteristics */
 806         hw->flags = IEEE80211_HW_SIGNAL_DBM |
 807                     IEEE80211_HW_NOISE_DBM |
 808                     IEEE80211_HW_AMPDU_AGGREGATION;
 809         hw->wiphy->interface_modes =
 810                 BIT(NL80211_IFTYPE_STATION) |
 811                 BIT(NL80211_IFTYPE_ADHOC);
 812
 813         hw->wiphy->fw_handles_regulatory = true;
 814
 815         /* Default value; 4 EDCA QOS priorities */
 816         hw->queues = 4;
 817         /* queues to support 11n aggregation */
 818         if (priv->cfg->sku & IWL_SKU_N)
 819                 hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
 820
 821         hw->conf.beacon_int = 100;
 822         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
 823
 824         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
 825                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
 826                         &priv->bands[IEEE80211_BAND_2GHZ];
 827         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
 828                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
 829                         &priv->bands[IEEE80211_BAND_5GHZ];
 830
 831         ret = ieee80211_register_hw(priv->hw);
 832         if (ret) {
 833                 IWL_ERROR("Failed to register hw (error %d)\n", ret);
 834                 return ret;
 835         }
 836         priv->mac80211_registered = 1;
 837
 838         return 0;
 839 }
 840 EXPORT_SYMBOL(iwl_setup_mac);
 841
 842 int iwl_set_hw_params(struct iwl_priv *priv)
 843 {
 844         priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
 845         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
 846         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
 847         if (priv->cfg->mod_params->amsdu_size_8K)
 848                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
 849         else
 850                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
 851         priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
 852
 853         if (priv->cfg->mod_params->disable_11n)
 854                 priv->cfg->sku &= ~IWL_SKU_N;
 855
 856         /* Device-specific setup */
 857         return priv->cfg->ops->lib->set_hw_params(priv);
 858 }
 859 EXPORT_SYMBOL(iwl_set_hw_params);
 860
 861 int iwl_init_drv(struct iwl_priv *priv)
 862 {
 863         int ret;
 864
 865         priv->retry_rate = 1;
 866         priv->ibss_beacon = NULL;
 867
 868         spin_lock_init(&priv->lock);
 869         spin_lock_init(&priv->power_data.lock);
 870         spin_lock_init(&priv->sta_lock);
 871         spin_lock_init(&priv->hcmd_lock);
 872
 873         INIT_LIST_HEAD(&priv->free_frames);
 874
 875         mutex_init(&priv->mutex);
 876
 877         /* Clear the driver's (not device's) station table */
 878         iwl_clear_stations_table(priv);
 879
 880         priv->data_retry_limit = -1;
 881         priv->ieee_channels = NULL;
 882         priv->ieee_rates = NULL;
 883         priv->band = IEEE80211_BAND_2GHZ;
 884
 885         priv->iw_mode = NL80211_IFTYPE_STATION;
 886
 887         priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
 888
 889         /* Choose which receivers/antennas to use */
 890         iwl_set_rxon_chain(priv);
 891         iwl_init_scan_params(priv);
 892
 893         if (priv->cfg->mod_params->enable_qos)
 894                 priv->qos_data.qos_enable = 1;
 895
 896         iwl_reset_qos(priv);
 897
 898         priv->qos_data.qos_active = 0;
 899         priv->qos_data.qos_cap.val = 0;
 900
 901         priv->rates_mask = IWL_RATES_MASK;
 902         /* If power management is turned on, default to AC mode */
 903         priv->power_mode = IWL_POWER_AC;
 904         priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
 905
 906         ret = iwl_init_channel_map(priv);
 907         if (ret) {
 908                 IWL_ERROR("initializing regulatory failed: %d\n", ret);
 909                 goto err;
 910         }
 911
 912         ret = iwlcore_init_geos(priv);
 913         if (ret) {
 914                 IWL_ERROR("initializing geos failed: %d\n", ret);
 915                 goto err_free_channel_map;
 916         }
 917
 918         return 0;
 919
 920 err_free_channel_map:
 921         iwl_free_channel_map(priv);
 922 err:
 923         return ret;
 924 }
 925 EXPORT_SYMBOL(iwl_init_drv);
 926
 927 int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
 928 {
 929         int ret = 0;
 930         if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
 931                 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
 932                             priv->tx_power_user_lmt);
 933                 return -EINVAL;
 934         }
 935
 936         if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
 937                 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
 938                             priv->tx_power_user_lmt);
 939                 return -EINVAL;
 940         }
 941
 942         if (priv->tx_power_user_lmt != tx_power)
 943                 force = true;
 944
 945         priv->tx_power_user_lmt = tx_power;
 946
 947         if (force && priv->cfg->ops->lib->send_tx_power)
 948                 ret = priv->cfg->ops->lib->send_tx_power(priv);
 949
 950         return ret;
 951 }
 952 EXPORT_SYMBOL(iwl_set_tx_power);
 953
 954 void iwl_uninit_drv(struct iwl_priv *priv)
 955 {
 956         iwl_calib_free_results(priv);
 957         iwlcore_free_geos(priv);
 958         iwl_free_channel_map(priv);
 959         kfree(priv->scan);
 960 }
 961 EXPORT_SYMBOL(iwl_uninit_drv);
 962
 963
 964 void iwl_disable_interrupts(struct iwl_priv *priv)
 965 {
 966         clear_bit(STATUS_INT_ENABLED, &priv->status);
 967
 968         /* disable interrupts from uCode/NIC to host */
 969         iwl_write32(priv, CSR_INT_MASK, 0x00000000);
 970
 971         /* acknowledge/clear/reset any interrupts still pending
 972          * from uCode or flow handler (Rx/Tx DMA) */
 973         iwl_write32(priv, CSR_INT, 0xffffffff);
 974         iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
 975         IWL_DEBUG_ISR("Disabled interrupts\n");
 976 }
 977 EXPORT_SYMBOL(iwl_disable_interrupts);
 978
 979 void iwl_enable_interrupts(struct iwl_priv *priv)
 980 {
 981         IWL_DEBUG_ISR("Enabling interrupts\n");
 982         set_bit(STATUS_INT_ENABLED, &priv->status);
 983         iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
 984 }
 985 EXPORT_SYMBOL(iwl_enable_interrupts);
 986
 987 int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
 988 {
 989         u32 stat_flags = 0;
 990         struct iwl_host_cmd cmd = {
 991                 .id = REPLY_STATISTICS_CMD,
 992                 .meta.flags = flags,
 993                 .len = sizeof(stat_flags),
 994                 .data = (u8 *) &stat_flags,
 995         };
 996         return iwl_send_cmd(priv, &cmd);
 997 }
 998 EXPORT_SYMBOL(iwl_send_statistics_request);
 999
1000 /**
1001  * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1002  *   using sample data 100 bytes apart.  If these sample points are good,
1003  *   it's a pretty good bet that everything between them is good, too.
1004  */
1005 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1006 {
1007         u32 val;
1008         int ret = 0;
1009         u32 errcnt = 0;
1010         u32 i;
1011
1012         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1013
1014         ret = iwl_grab_nic_access(priv);
1015         if (ret)
1016                 return ret;
1017
1018         for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1019                 /* read data comes through single port, auto-incr addr */
1020                 /* NOTE: Use the debugless read so we don't flood kernel log
1021                  * if IWL_DL_IO is set */
1022                 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1023                         i + RTC_INST_LOWER_BOUND);
1024                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1025                 if (val != le32_to_cpu(*image)) {
1026                         ret = -EIO;
1027                         errcnt++;
1028                         if (errcnt >= 3)
1029                                 break;
1030                 }
1031         }
1032
1033         iwl_release_nic_access(priv);
1034
1035         return ret;
1036 }
1037
1038 /**
1039  * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1040  *     looking at all data.
1041  */
1042 static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1043                                  u32 len)
1044 {
1045         u32 val;
1046         u32 save_len = len;
1047         int ret = 0;
1048         u32 errcnt;
1049
1050         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1051
1052         ret = iwl_grab_nic_access(priv);
1053         if (ret)
1054                 return ret;
1055
1056         iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1057
1058         errcnt = 0;
1059         for (; len > 0; len -= sizeof(u32), image++) {
1060                 /* read data comes through single port, auto-incr addr */
1061                 /* NOTE: Use the debugless read so we don't flood kernel log
1062                  * if IWL_DL_IO is set */
1063                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1064                 if (val != le32_to_cpu(*image)) {
1065                         IWL_ERROR("uCode INST section is invalid at "
1066                                   "offset 0x%x, is 0x%x, s/b 0x%x\n",
1067                                   save_len - len, val, le32_to_cpu(*image));
1068                         ret = -EIO;
1069                         errcnt++;
1070                         if (errcnt >= 20)
1071                                 break;
1072                 }
1073         }
1074
1075         iwl_release_nic_access(priv);
1076
1077         if (!errcnt)
1078                 IWL_DEBUG_INFO
1079                     ("ucode image in INSTRUCTION memory is good\n");
1080
1081         return ret;
1082 }
1083
1084 /**
1085  * iwl_verify_ucode - determine which instruction image is in SRAM,
1086  *    and verify its contents
1087  */
1088 int iwl_verify_ucode(struct iwl_priv *priv)
1089 {
1090         __le32 *image;
1091         u32 len;
1092         int ret;
1093
1094         /* Try bootstrap */
1095         image = (__le32 *)priv->ucode_boot.v_addr;
1096         len = priv->ucode_boot.len;
1097         ret = iwlcore_verify_inst_sparse(priv, image, len);
1098         if (!ret) {
1099                 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1100                 return 0;
1101         }
1102
1103         /* Try initialize */
1104         image = (__le32 *)priv->ucode_init.v_addr;
1105         len = priv->ucode_init.len;
1106         ret = iwlcore_verify_inst_sparse(priv, image, len);
1107         if (!ret) {
1108                 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1109                 return 0;
1110         }
1111
1112         /* Try runtime/protocol */
1113         image = (__le32 *)priv->ucode_code.v_addr;
1114         len = priv->ucode_code.len;
1115         ret = iwlcore_verify_inst_sparse(priv, image, len);
1116         if (!ret) {
1117                 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1118                 return 0;
1119         }
1120
1121         IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1122
1123         /* Since nothing seems to match, show first several data entries in
1124          * instruction SRAM, so maybe visual inspection will give a clue.
1125          * Selection of bootstrap image (vs. other images) is arbitrary. */
1126         image = (__le32 *)priv->ucode_boot.v_addr;
1127         len = priv->ucode_boot.len;
1128         ret = iwl_verify_inst_full(priv, image, len);
1129
1130         return ret;
1131 }
1132 EXPORT_SYMBOL(iwl_verify_ucode);
1133
1134
1135 static const char *desc_lookup_text[] = {
1136         "OK",
1137         "FAIL",
1138         "BAD_PARAM",
1139         "BAD_CHECKSUM",
1140         "NMI_INTERRUPT_WDG",
1141         "SYSASSERT",
1142         "FATAL_ERROR",
1143         "BAD_COMMAND",
1144         "HW_ERROR_TUNE_LOCK",
1145         "HW_ERROR_TEMPERATURE",
1146         "ILLEGAL_CHAN_FREQ",
1147         "VCC_NOT_STABLE",
1148         "FH_ERROR",
1149         "NMI_INTERRUPT_HOST",
1150         "NMI_INTERRUPT_ACTION_PT",
1151         "NMI_INTERRUPT_UNKNOWN",
1152         "UCODE_VERSION_MISMATCH",
1153         "HW_ERROR_ABS_LOCK",
1154         "HW_ERROR_CAL_LOCK_FAIL",
1155         "NMI_INTERRUPT_INST_ACTION_PT",
1156         "NMI_INTERRUPT_DATA_ACTION_PT",
1157         "NMI_TRM_HW_ER",
1158         "NMI_INTERRUPT_TRM",
1159         "NMI_INTERRUPT_BREAK_POINT"
1160         "DEBUG_0",
1161         "DEBUG_1",
1162         "DEBUG_2",
1163         "DEBUG_3",
1164         "UNKNOWN"
1165 };
1166
1167 static const char *desc_lookup(int i)
1168 {
1169         int max = ARRAY_SIZE(desc_lookup_text) - 1;
1170
1171         if (i < 0 || i > max)
1172                 i = max;
1173
1174         return desc_lookup_text[i];
1175 }
1176
1177 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1178 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1179
1180 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1181 {
1182         u32 data2, line;
1183         u32 desc, time, count, base, data1;
1184         u32 blink1, blink2, ilink1, ilink2;
1185         int ret;
1186
1187         if (priv->ucode_type == UCODE_INIT)
1188                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1189         else
1190                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1191
1192         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1193                 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1194                 return;
1195         }
1196
1197         ret = iwl_grab_nic_access(priv);
1198         if (ret) {
1199                 IWL_WARNING("Can not read from adapter at this time.\n");
1200                 return;
1201         }
1202
1203         count = iwl_read_targ_mem(priv, base);
1204
1205         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1206                 IWL_ERROR("Start IWL Error Log Dump:\n");
1207                 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1208         }
1209
1210         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1211         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1212         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1213         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1214         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1215         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1216         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1217         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1218         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1219
1220         IWL_ERROR("Desc                               Time       "
1221                 "data1      data2      line\n");
1222         IWL_ERROR("%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1223                 desc_lookup(desc), desc, time, data1, data2, line);
1224         IWL_ERROR("blink1  blink2  ilink1  ilink2\n");
1225         IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1226                 ilink1, ilink2);
1227
1228         iwl_release_nic_access(priv);
1229 }
1230 EXPORT_SYMBOL(iwl_dump_nic_error_log);
1231
1232 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1233
1234 /**
1235  * iwl_print_event_log - Dump error event log to syslog
1236  *
1237  * NOTE: Must be called with iwl_grab_nic_access() already obtained!
1238  */
1239 static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1240                                 u32 num_events, u32 mode)
1241 {
1242         u32 i;
1243         u32 base;       /* SRAM byte address of event log header */
1244         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1245         u32 ptr;        /* SRAM byte address of log data */
1246         u32 ev, time, data; /* event log data */
1247
1248         if (num_events == 0)
1249                 return;
1250         if (priv->ucode_type == UCODE_INIT)
1251                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1252         else
1253                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1254
1255         if (mode == 0)
1256                 event_size = 2 * sizeof(u32);
1257         else
1258                 event_size = 3 * sizeof(u32);
1259
1260         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1261
1262         /* "time" is actually "data" for mode 0 (no timestamp).
1263         * place event id # at far right for easier visual parsing. */
1264         for (i = 0; i < num_events; i++) {
1265                 ev = iwl_read_targ_mem(priv, ptr);
1266                 ptr += sizeof(u32);
1267                 time = iwl_read_targ_mem(priv, ptr);
1268                 ptr += sizeof(u32);
1269                 if (mode == 0) {
1270                         /* data, ev */
1271                         IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1272                 } else {
1273                         data = iwl_read_targ_mem(priv, ptr);
1274                         ptr += sizeof(u32);
1275                         IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1276                                         time, data, ev);
1277                 }
1278         }
1279 }
1280
1281 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1282 {
1283         int ret;
1284         u32 base;       /* SRAM byte address of event log header */
1285         u32 capacity;   /* event log capacity in # entries */
1286         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
1287         u32 num_wraps;  /* # times uCode wrapped to top of log */
1288         u32 next_entry; /* index of next entry to be written by uCode */
1289         u32 size;       /* # entries that we'll print */
1290
1291         if (priv->ucode_type == UCODE_INIT)
1292                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1293         else
1294                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1295
1296         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1297                 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1298                 return;
1299         }
1300
1301         ret = iwl_grab_nic_access(priv);
1302         if (ret) {
1303                 IWL_WARNING("Can not read from adapter at this time.\n");
1304                 return;
1305         }
1306
1307         /* event log header */
1308         capacity = iwl_read_targ_mem(priv, base);
1309         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1310         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1311         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1312
1313         size = num_wraps ? capacity : next_entry;
1314
1315         /* bail out if nothing in log */
1316         if (size == 0) {
1317                 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1318                 iwl_release_nic_access(priv);
1319                 return;
1320         }
1321
1322         IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1323                         size, num_wraps);
1324
1325         /* if uCode has wrapped back to top of log, start at the oldest entry,
1326          * i.e the next one that uCode would fill. */
1327         if (num_wraps)
1328                 iwl_print_event_log(priv, next_entry,
1329                                         capacity - next_entry, mode);
1330         /* (then/else) start at top of log */
1331         iwl_print_event_log(priv, 0, next_entry, mode);
1332
1333         iwl_release_nic_access(priv);
1334 }
1335 EXPORT_SYMBOL(iwl_dump_nic_event_log);
1336
1337 void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1338 {
1339         struct iwl_ct_kill_config cmd;
1340         unsigned long flags;
1341         int ret = 0;
1342
1343         spin_lock_irqsave(&priv->lock, flags);
1344         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1345                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1346         spin_unlock_irqrestore(&priv->lock, flags);
1347
1348         cmd.critical_temperature_R =
1349                 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1350
1351         ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1352                                sizeof(cmd), &cmd);
1353         if (ret)
1354                 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1355         else
1356                 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1357                         "critical temperature is %d\n",
1358                         cmd.critical_temperature_R);
1359 }
1360 EXPORT_SYMBOL(iwl_rf_kill_ct_config);
1361
1362
1363 /*
1364  * CARD_STATE_CMD
1365  *
1366  * Use: Sets the device's internal card state to enable, disable, or halt
1367  *
1368  * When in the 'enable' state the card operates as normal.
1369  * When in the 'disable' state, the card enters into a low power mode.
1370  * When in the 'halt' state, the card is shut down and must be fully
1371  * restarted to come back on.
1372  */
1373 static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1374 {
1375         struct iwl_host_cmd cmd = {
1376                 .id = REPLY_CARD_STATE_CMD,
1377                 .len = sizeof(u32),
1378                 .data = &flags,
1379                 .meta.flags = meta_flag,
1380         };
1381
1382         return iwl_send_cmd(priv, &cmd);
1383 }
1384
1385 void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1386 {
1387         unsigned long flags;
1388
1389         if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1390                 return;
1391
1392         IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1393
1394         iwl_scan_cancel(priv);
1395         /* FIXME: This is a workaround for AP */
1396         if (priv->iw_mode != NL80211_IFTYPE_AP) {
1397                 spin_lock_irqsave(&priv->lock, flags);
1398                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1399                             CSR_UCODE_SW_BIT_RFKILL);
1400                 spin_unlock_irqrestore(&priv->lock, flags);
1401                 /* call the host command only if no hw rf-kill set */
1402                 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1403                     iwl_is_ready(priv))
1404                         iwl_send_card_state(priv,
1405                                 CARD_STATE_CMD_DISABLE, 0);
1406                 set_bit(STATUS_RF_KILL_SW, &priv->status);
1407                         /* make sure mac80211 stop sending Tx frame */
1408                 if (priv->mac80211_registered)
1409                         ieee80211_stop_queues(priv->hw);
1410         }
1411 }
1412 EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1413
1414 int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1415 {
1416         unsigned long flags;
1417
1418         if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1419                 return 0;
1420
1421         IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1422
1423         spin_lock_irqsave(&priv->lock, flags);
1424         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1425
1426         /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1427          * notification where it will clear SW rfkill status.
1428          * Setting it here would break the handler. Only if the
1429          * interface is down we can set here since we don't
1430          * receive any further notification.
1431          */
1432         if (!priv->is_open)
1433                 clear_bit(STATUS_RF_KILL_SW, &priv->status);
1434         spin_unlock_irqrestore(&priv->lock, flags);
1435
1436         /* wake up ucode */
1437         msleep(10);
1438
1439         spin_lock_irqsave(&priv->lock, flags);
1440         iwl_read32(priv, CSR_UCODE_DRV_GP1);
1441         if (!iwl_grab_nic_access(priv))
1442                 iwl_release_nic_access(priv);
1443         spin_unlock_irqrestore(&priv->lock, flags);
1444
1445         if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1446                 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1447                                   "disabled by HW switch\n");
1448                 return 0;
1449         }
1450
1451         /* If the driver is already loaded, it will receive
1452          * CARD_STATE_NOTIFICATION notifications and the handler will
1453          * call restart to reload the driver.
1454          */
1455         return 1;
1456 }
1457 EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);