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   1 /*
   2  * linux/drivers/video/s3c2410fb.c
   3  *      Copyright (c) Arnaud Patard, Ben Dooks
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive for
   7  * more details.
   8  *
   9  *          S3C2410 LCD Controller Frame Buffer Driver
  10  *          based on skeletonfb.c, sa1100fb.c and others
  11  *
  12  * ChangeLog
  13  * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  14  *      - u32 state -> pm_message_t state
  15  *      - S3C2410_{VA,SZ}_LCD -> S3C24XX
  16  *
  17  * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  18  *      - Removed the ioctl
  19  *      - use readl/writel instead of __raw_writel/__raw_readl
  20  *
  21  * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
  22  *      - Added the possibility to set on or off the
  23  *      debugging messages
  24  *      - Replaced 0 and 1 by on or off when reading the
  25  *      /sys files
  26  *
  27  * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
  28  *      - added non 16bpp modes
  29  *      - updated platform information for range of x/y/bpp
  30  *      - add code to ensure palette is written correctly
  31  *      - add pixel clock divisor control
  32  *
  33  * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
  34  *      - Removed the use of currcon as it no more exists
  35  *      - Added LCD power sysfs interface
  36  *
  37  * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
  38  *      - minor cleanups
  39  *      - add suspend/resume support
  40  *      - s3c2410fb_setcolreg() not valid in >8bpp modes
  41  *      - removed last CONFIG_FB_S3C2410_FIXED
  42  *      - ensure lcd controller stopped before cleanup
  43  *      - added sysfs interface for backlight power
  44  *      - added mask for gpio configuration
  45  *      - ensured IRQs disabled during GPIO configuration
  46  *      - disable TPAL before enabling video
  47  *
  48  * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
  49  *      - Suppress command line options
  50  *
  51  * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  52  *      - code cleanup
  53  *
  54  * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  55  *      - Renamed from h1940fb.c to s3c2410fb.c
  56  *      - Add support for different devices
  57  *      - Backlight support
  58  *
  59  * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
  60  *      - added clock (de-)allocation code
  61  *      - added fixem fbmem option
  62  *
  63  * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
  64  *      - code cleanup
  65  *      - added a forgotten return in h1940fb_init
  66  *
  67  * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
  68  *      - code cleanup and extended debugging
  69  *
  70  * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  71  *      - First version
  72  */
  73
  74 #include <linux/module.h>
  75 #include <linux/kernel.h>
  76 #include <linux/errno.h>
  77 #include <linux/string.h>
  78 #include <linux/mm.h>
  79 #include <linux/slab.h>
  80 #include <linux/delay.h>
  81 #include <linux/fb.h>
  82 #include <linux/init.h>
  83 #include <linux/dma-mapping.h>
  84 #include <linux/interrupt.h>
  85 #include <linux/platform_device.h>
  86 #include <linux/clk.h>
  87
  88 #include <asm/io.h>
  89 #include <asm/div64.h>
  90
  91 #include <asm/mach/map.h>
  92 #include <asm/arch/regs-lcd.h>
  93 #include <asm/arch/regs-gpio.h>
  94 #include <asm/arch/fb.h>
  95
  96 #ifdef CONFIG_PM
  97 #include <linux/pm.h>
  98 #endif
  99
 100 #include "s3c2410fb.h"
 101
 102 /* Debugging stuff */
 103 #ifdef CONFIG_FB_S3C2410_DEBUG
 104 static int debug        = 1;
 105 #else
 106 static int debug        = 0;
 107 #endif
 108
 109 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
 110
 111 /* useful functions */
 112
 113 /* s3c2410fb_set_lcdaddr
 114  *
 115  * initialise lcd controller address pointers
 116  */
 117 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
 118 {
 119         unsigned long saddr1, saddr2, saddr3;
 120         struct s3c2410fb_info *fbi = info->par;
 121         void __iomem *regs = fbi->io;
 122
 123         saddr1  = info->fix.smem_start >> 1;
 124         saddr2  = info->fix.smem_start;
 125         saddr2 += info->fix.line_length * info->var.yres;
 126         saddr2 >>= 1;
 127
 128         saddr3 = S3C2410_OFFSIZE(0) |
 129                  S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
 130
 131         dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
 132         dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
 133         dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
 134
 135         writel(saddr1, regs + S3C2410_LCDSADDR1);
 136         writel(saddr2, regs + S3C2410_LCDSADDR2);
 137         writel(saddr3, regs + S3C2410_LCDSADDR3);
 138 }
 139
 140 /* s3c2410fb_calc_pixclk()
 141  *
 142  * calculate divisor for clk->pixclk
 143  */
 144 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
 145                                           unsigned long pixclk)
 146 {
 147         unsigned long clk = clk_get_rate(fbi->clk);
 148         unsigned long long div;
 149
 150         /* pixclk is in picoseconds, our clock is in Hz
 151          *
 152          * Hz -> picoseconds is / 10^-12
 153          */
 154
 155         div = (unsigned long long)clk * pixclk;
 156         div >>= 12;                     /* div / 2^12 */
 157         do_div(div, 625 * 625UL * 625); /* div / 5^12 */
 158
 159         dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 160         return div;
 161 }
 162
 163 /*
 164  *      s3c2410fb_check_var():
 165  *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 166  *      if it's too big, return -EINVAL.
 167  *
 168  */
 169 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 170                                struct fb_info *info)
 171 {
 172         struct s3c2410fb_info *fbi = info->par;
 173         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 174         struct s3c2410fb_display *display = NULL;
 175         unsigned i;
 176
 177         dprintk("check_var(var=%p, info=%p)\n", var, info);
 178
 179         /* validate x/y resolution */
 180
 181         for (i = 0; i < mach_info->num_displays; i++)
 182                 if (var->yres == mach_info->displays[i].yres &&
 183                     var->xres == mach_info->displays[i].xres &&
 184                     var->bits_per_pixel == mach_info->displays[i].bpp) {
 185                         display = mach_info->displays + i;
 186                         break;
 187                 }
 188
 189         if (!display) {
 190                 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
 191                         var->xres, var->yres, var->bits_per_pixel);
 192                 return -EINVAL;
 193         }
 194
 195         /* it is always the size as the display */
 196         var->xres_virtual = display->xres;
 197         var->yres_virtual = display->yres;
 198         var->height = display->height;
 199         var->width = display->width;
 200
 201         /* copy lcd settings */
 202         var->left_margin = display->left_margin;
 203         var->right_margin = display->right_margin;
 204         var->upper_margin = display->upper_margin;
 205         var->lower_margin = display->lower_margin;
 206         var->vsync_len = display->vsync_len;
 207         var->hsync_len = display->hsync_len;
 208
 209         fbi->regs.lcdcon1 = display->lcdcon1;
 210         fbi->regs.lcdcon5 = display->lcdcon5;
 211         /* set display type */
 212         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
 213         fbi->regs.lcdcon1 |= display->type;
 214
 215         var->transp.offset = 0;
 216         var->transp.length = 0;
 217         /* set r/g/b positions */
 218         switch (var->bits_per_pixel) {
 219         case 1:
 220         case 2:
 221         case 4:
 222                 var->red.offset = 0;
 223                 var->red.length = var->bits_per_pixel;
 224                 var->green      = var->red;
 225                 var->blue       = var->red;
 226                 break;
 227         case 8:
 228                 if (display->type != S3C2410_LCDCON1_TFT) {
 229                         /* 8 bpp 332 */
 230                         var->red.length         = 3;
 231                         var->red.offset         = 5;
 232                         var->green.length       = 3;
 233                         var->green.offset       = 2;
 234                         var->blue.length        = 2;
 235                         var->blue.offset        = 0;
 236                 } else {
 237                         var->red.offset         = 0;
 238                         var->red.length         = 8;
 239                         var->green              = var->red;
 240                         var->blue               = var->red;
 241                 }
 242                 break;
 243         case 12:
 244                 /* 12 bpp 444 */
 245                 var->red.length         = 4;
 246                 var->red.offset         = 8;
 247                 var->green.length       = 4;
 248                 var->green.offset       = 4;
 249                 var->blue.length        = 4;
 250                 var->blue.offset        = 0;
 251                 break;
 252
 253         default:
 254         case 16:
 255                 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
 256                         /* 16 bpp, 565 format */
 257                         var->red.offset         = 11;
 258                         var->green.offset       = 5;
 259                         var->blue.offset        = 0;
 260                         var->red.length         = 5;
 261                         var->green.length       = 6;
 262                         var->blue.length        = 5;
 263                 } else {
 264                         /* 16 bpp, 5551 format */
 265                         var->red.offset         = 11;
 266                         var->green.offset       = 6;
 267                         var->blue.offset        = 1;
 268                         var->red.length         = 5;
 269                         var->green.length       = 5;
 270                         var->blue.length        = 5;
 271                 }
 272                 break;
 273         case 32:
 274                 /* 24 bpp 888 and 8 dummy */
 275                 var->red.length         = 8;
 276                 var->red.offset         = 16;
 277                 var->green.length       = 8;
 278                 var->green.offset       = 8;
 279                 var->blue.length        = 8;
 280                 var->blue.offset        = 0;
 281                 break;
 282         }
 283         return 0;
 284 }
 285
 286 /* s3c2410fb_calculate_stn_lcd_regs
 287  *
 288  * calculate register values from var settings
 289  */
 290 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
 291                                              struct s3c2410fb_hw *regs)
 292 {
 293         const struct s3c2410fb_info *fbi = info->par;
 294         const struct fb_var_screeninfo *var = &info->var;
 295         int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
 296         int hs = var->xres >> 2;
 297         unsigned wdly = (var->left_margin >> 4) - 1;
 298         unsigned wlh = (var->hsync_len >> 4) - 1;
 299
 300         dprintk("%s: var->xres  = %d\n", __FUNCTION__, var->xres);
 301         dprintk("%s: var->yres  = %d\n", __FUNCTION__, var->yres);
 302         dprintk("%s: var->bpp   = %d\n", __FUNCTION__, var->bits_per_pixel);
 303
 304         if (type != S3C2410_LCDCON1_STN4)
 305                 hs >>= 1;
 306
 307         regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
 308
 309         switch (var->bits_per_pixel) {
 310         case 1:
 311                 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 312                 break;
 313         case 2:
 314                 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 315                 break;
 316         case 4:
 317                 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 318                 break;
 319         case 8:
 320                 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 321                 hs *= 3;
 322                 break;
 323         case 12:
 324                 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 325                 hs *= 3;
 326                 break;
 327
 328         default:
 329                 /* invalid pixel depth */
 330                 dev_err(fbi->dev, "invalid bpp %d\n",
 331                         var->bits_per_pixel);
 332         }
 333         /* update X/Y info */
 334         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 335                 var->left_margin, var->right_margin, var->hsync_len);
 336
 337         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 338
 339         if (wdly > 3)
 340                 wdly = 3;
 341
 342         if (wlh > 3)
 343                 wlh = 3;
 344
 345         regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
 346                         S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
 347                         S3C2410_LCDCON3_HOZVAL(hs - 1);
 348
 349         regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
 350 }
 351
 352 /* s3c2410fb_calculate_tft_lcd_regs
 353  *
 354  * calculate register values from var settings
 355  */
 356 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
 357                                              struct s3c2410fb_hw *regs)
 358 {
 359         const struct s3c2410fb_info *fbi = info->par;
 360         const struct fb_var_screeninfo *var = &info->var;
 361
 362         dprintk("%s: var->xres  = %d\n", __FUNCTION__, var->xres);
 363         dprintk("%s: var->yres  = %d\n", __FUNCTION__, var->yres);
 364         dprintk("%s: var->bpp   = %d\n", __FUNCTION__, var->bits_per_pixel);
 365
 366         regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
 367
 368         switch (var->bits_per_pixel) {
 369         case 1:
 370                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 371                 break;
 372         case 2:
 373                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 374                 break;
 375         case 4:
 376                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 377                 break;
 378         case 8:
 379                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 380                 regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
 381                                  S3C2410_LCDCON5_FRM565;
 382                 regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
 383                 break;
 384         case 16:
 385                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 386                 regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
 387                 regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
 388                 break;
 389         case 32:
 390                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
 391                 regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
 392                                    S3C2410_LCDCON5_HWSWP |
 393                                    S3C2410_LCDCON5_BPP24BL);
 394                 break;
 395         default:
 396                 /* invalid pixel depth */
 397                 dev_err(fbi->dev, "invalid bpp %d\n",
 398                         var->bits_per_pixel);
 399         }
 400         /* update X/Y info */
 401         dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 402                 var->upper_margin, var->lower_margin, var->vsync_len);
 403
 404         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 405                 var->left_margin, var->right_margin, var->hsync_len);
 406
 407         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
 408                         S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
 409                         S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
 410                         S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 411
 412         regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 413                         S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
 414                         S3C2410_LCDCON3_HOZVAL(var->xres - 1);
 415
 416         regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 417 }
 418
 419 /* s3c2410fb_activate_var
 420  *
 421  * activate (set) the controller from the given framebuffer
 422  * information
 423  */
 424 static void s3c2410fb_activate_var(struct fb_info *info)
 425 {
 426         struct s3c2410fb_info *fbi = info->par;
 427         void __iomem *regs = fbi->io;
 428         int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
 429         struct fb_var_screeninfo *var = &info->var;
 430
 431         if (var->pixclock > 0) {
 432                 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
 433
 434                 if (type == S3C2410_LCDCON1_TFT) {
 435                         clkdiv = (clkdiv / 2) - 1;
 436                         if (clkdiv < 0)
 437                                 clkdiv = 0;
 438                 } else {
 439                         clkdiv = (clkdiv / 2);
 440                         if (clkdiv < 2)
 441                                 clkdiv = 2;
 442                 }
 443
 444                 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
 445                 fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 446         }
 447
 448         if (type == S3C2410_LCDCON1_TFT)
 449                 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
 450         else
 451                 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
 452
 453         /* write new registers */
 454
 455         dprintk("new register set:\n");
 456         dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 457         dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 458         dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 459         dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 460         dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 461
 462         writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
 463                 regs + S3C2410_LCDCON1);
 464         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 465         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 466         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 467         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 468
 469         /* set lcd address pointers */
 470         s3c2410fb_set_lcdaddr(info);
 471
 472         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
 473         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 474 }
 475
 476 /*
 477  *      s3c2410fb_set_par - Alters the hardware state.
 478  *      @info: frame buffer structure that represents a single frame buffer
 479  *
 480  */
 481 static int s3c2410fb_set_par(struct fb_info *info)
 482 {
 483         struct fb_var_screeninfo *var = &info->var;
 484
 485         switch (var->bits_per_pixel) {
 486         case 32:
 487         case 16:
 488         case 12:
 489                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 490                 break;
 491         case 1:
 492                 info->fix.visual = FB_VISUAL_MONO01;
 493                 break;
 494         default:
 495                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 496                 break;
 497         }
 498
 499         info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
 500
 501         /* activate this new configuration */
 502
 503         s3c2410fb_activate_var(info);
 504         return 0;
 505 }
 506
 507 static void schedule_palette_update(struct s3c2410fb_info *fbi,
 508                                     unsigned int regno, unsigned int val)
 509 {
 510         unsigned long flags;
 511         unsigned long irqen;
 512         void __iomem *regs = fbi->io;
 513
 514         local_irq_save(flags);
 515
 516         fbi->palette_buffer[regno] = val;
 517
 518         if (!fbi->palette_ready) {
 519                 fbi->palette_ready = 1;
 520
 521                 /* enable IRQ */
 522                 irqen = readl(regs + S3C2410_LCDINTMSK);
 523                 irqen &= ~S3C2410_LCDINT_FRSYNC;
 524                 writel(irqen, regs + S3C2410_LCDINTMSK);
 525         }
 526
 527         local_irq_restore(flags);
 528 }
 529
 530 /* from pxafb.c */
 531 static inline unsigned int chan_to_field(unsigned int chan,
 532                                          struct fb_bitfield *bf)
 533 {
 534         chan &= 0xffff;
 535         chan >>= 16 - bf->length;
 536         return chan << bf->offset;
 537 }
 538
 539 static int s3c2410fb_setcolreg(unsigned regno,
 540                                unsigned red, unsigned green, unsigned blue,
 541                                unsigned transp, struct fb_info *info)
 542 {
 543         struct s3c2410fb_info *fbi = info->par;
 544         void __iomem *regs = fbi->io;
 545         unsigned int val;
 546
 547         /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 548                    regno, red, green, blue); */
 549
 550         switch (info->fix.visual) {
 551         case FB_VISUAL_TRUECOLOR:
 552                 /* true-colour, use pseudo-palette */
 553
 554                 if (regno < 16) {
 555                         u32 *pal = info->pseudo_palette;
 556
 557                         val  = chan_to_field(red,   &info->var.red);
 558                         val |= chan_to_field(green, &info->var.green);
 559                         val |= chan_to_field(blue,  &info->var.blue);
 560
 561                         pal[regno] = val;
 562                 }
 563                 break;
 564
 565         case FB_VISUAL_PSEUDOCOLOR:
 566                 if (regno < 256) {
 567                         /* currently assume RGB 5-6-5 mode */
 568
 569                         val  = (red   >>  0) & 0xf800;
 570                         val |= (green >>  5) & 0x07e0;
 571                         val |= (blue  >> 11) & 0x001f;
 572
 573                         writel(val, regs + S3C2410_TFTPAL(regno));
 574                         schedule_palette_update(fbi, regno, val);
 575                 }
 576
 577                 break;
 578
 579         default:
 580                 return 1;       /* unknown type */
 581         }
 582
 583         return 0;
 584 }
 585
 586 /*
 587  *      s3c2410fb_blank
 588  *      @blank_mode: the blank mode we want.
 589  *      @info: frame buffer structure that represents a single frame buffer
 590  *
 591  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 592  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 593  *      video mode which doesn't support it. Implements VESA suspend
 594  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 595  *      blank_mode == 2: suspend vsync
 596  *      blank_mode == 3: suspend hsync
 597  *      blank_mode == 4: powerdown
 598  *
 599  *      Returns negative errno on error, or zero on success.
 600  *
 601  */
 602 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 603 {
 604         struct s3c2410fb_info *fbi = info->par;
 605         void __iomem *regs = fbi->io;
 606
 607         dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 608
 609         if (blank_mode == FB_BLANK_UNBLANK)
 610                 writel(0x0, regs + S3C2410_TPAL);
 611         else {
 612                 dprintk("setting TPAL to output 0x000000\n");
 613                 writel(S3C2410_TPAL_EN, regs + S3C2410_TPAL);
 614         }
 615
 616         return 0;
 617 }
 618
 619 static int s3c2410fb_debug_show(struct device *dev,
 620                                 struct device_attribute *attr, char *buf)
 621 {
 622         return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 623 }
 624
 625 static int s3c2410fb_debug_store(struct device *dev,
 626                                  struct device_attribute *attr,
 627                                  const char *buf, size_t len)
 628 {
 629         if (len < 1)
 630                 return -EINVAL;
 631
 632         if (strnicmp(buf, "on", 2) == 0 ||
 633             strnicmp(buf, "1", 1) == 0) {
 634                 debug = 1;
 635                 printk(KERN_DEBUG "s3c2410fb: Debug On");
 636         } else if (strnicmp(buf, "off", 3) == 0 ||
 637                    strnicmp(buf, "0", 1) == 0) {
 638                 debug = 0;
 639                 printk(KERN_DEBUG "s3c2410fb: Debug Off");
 640         } else {
 641                 return -EINVAL;
 642         }
 643
 644         return len;
 645 }
 646
 647 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
 648
 649 static struct fb_ops s3c2410fb_ops = {
 650         .owner          = THIS_MODULE,
 651         .fb_check_var   = s3c2410fb_check_var,
 652         .fb_set_par     = s3c2410fb_set_par,
 653         .fb_blank       = s3c2410fb_blank,
 654         .fb_setcolreg   = s3c2410fb_setcolreg,
 655         .fb_fillrect    = cfb_fillrect,
 656         .fb_copyarea    = cfb_copyarea,
 657         .fb_imageblit   = cfb_imageblit,
 658 };
 659
 660 /*
 661  * s3c2410fb_map_video_memory():
 662  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 663  *      remapped into a non-cached, non-buffered, memory region to
 664  *      allow palette and pixel writes to occur without flushing the
 665  *      cache.  Once this area is remapped, all virtual memory
 666  *      access to the video memory should occur at the new region.
 667  */
 668 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
 669 {
 670         struct s3c2410fb_info *fbi = info->par;
 671         dma_addr_t map_dma;
 672         unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
 673
 674         dprintk("map_video_memory(fbi=%p)\n", fbi);
 675
 676         info->screen_base = dma_alloc_writecombine(fbi->dev, map_size,
 677                                                    &map_dma, GFP_KERNEL);
 678
 679         if (info->screen_base) {
 680                 /* prevent initial garbage on screen */
 681                 dprintk("map_video_memory: clear %p:%08x\n",
 682                         info->screen_base, map_size);
 683                 memset(info->screen_base, 0xf0, map_size);
 684
 685                 info->fix.smem_start = map_dma;
 686
 687                 dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
 688                         info->fix.smem_start, info->screen_base, map_size);
 689         }
 690
 691         return info->screen_base ? 0 : -ENOMEM;
 692 }
 693
 694 static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
 695 {
 696         struct s3c2410fb_info *fbi = info->par;
 697
 698         dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
 699                               info->screen_base, info->fix.smem_start);
 700 }
 701
 702 static inline void modify_gpio(void __iomem *reg,
 703                                unsigned long set, unsigned long mask)
 704 {
 705         unsigned long tmp;
 706
 707         tmp = readl(reg) & ~mask;
 708         writel(tmp | set, reg);
 709 }
 710
 711 /*
 712  * s3c2410fb_init_registers - Initialise all LCD-related registers
 713  */
 714 static int s3c2410fb_init_registers(struct fb_info *info)
 715 {
 716         struct s3c2410fb_info *fbi = info->par;
 717         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 718         unsigned long flags;
 719         void __iomem *regs = fbi->io;
 720
 721         /* Initialise LCD with values from haret */
 722
 723         local_irq_save(flags);
 724
 725         /* modify the gpio(s) with interrupts set (bjd) */
 726
 727         modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 728         modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 729         modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 730         modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 731
 732         local_irq_restore(flags);
 733
 734         dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 735         writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
 736
 737         dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL));
 738
 739         /* ensure temporary palette disabled */
 740         writel(0x00, regs + S3C2410_TPAL);
 741
 742         return 0;
 743 }
 744
 745 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 746 {
 747         unsigned int i;
 748         void __iomem *regs = fbi->io;
 749
 750         fbi->palette_ready = 0;
 751
 752         for (i = 0; i < 256; i++) {
 753                 unsigned long ent = fbi->palette_buffer[i];
 754                 if (ent == PALETTE_BUFF_CLEAR)
 755                         continue;
 756
 757                 writel(ent, regs + S3C2410_TFTPAL(i));
 758
 759                 /* it seems the only way to know exactly
 760                  * if the palette wrote ok, is to check
 761                  * to see if the value verifies ok
 762                  */
 763
 764                 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 765                         fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 766                 else
 767                         fbi->palette_ready = 1;   /* retry */
 768         }
 769 }
 770
 771 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 772 {
 773         struct s3c2410fb_info *fbi = dev_id;
 774         void __iomem *regs = fbi->io;
 775         unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND);
 776
 777         if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 778                 if (fbi->palette_ready)
 779                         s3c2410fb_write_palette(fbi);
 780
 781                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND);
 782                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND);
 783         }
 784
 785         return IRQ_HANDLED;
 786 }
 787
 788 static char driver_name[] = "s3c2410fb";
 789
 790 static int __init s3c2410fb_probe(struct platform_device *pdev)
 791 {
 792         struct s3c2410fb_info *info;
 793         struct s3c2410fb_display *display;
 794         struct fb_info *fbinfo;
 795         struct s3c2410fb_mach_info *mach_info;
 796         struct resource *res;
 797         int ret;
 798         int irq;
 799         int i;
 800         int size;
 801         u32 lcdcon1;
 802
 803         mach_info = pdev->dev.platform_data;
 804         if (mach_info == NULL) {
 805                 dev_err(&pdev->dev,
 806                         "no platform data for lcd, cannot attach\n");
 807                 return -EINVAL;
 808         }
 809
 810         display = mach_info->displays + mach_info->default_display;
 811
 812         irq = platform_get_irq(pdev, 0);
 813         if (irq < 0) {
 814                 dev_err(&pdev->dev, "no irq for device\n");
 815                 return -ENOENT;
 816         }
 817
 818         fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
 819         if (!fbinfo)
 820                 return -ENOMEM;
 821
 822         platform_set_drvdata(pdev, fbinfo);
 823
 824         info = fbinfo->par;
 825         info->dev = &pdev->dev;
 826
 827         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 828         if (res == NULL) {
 829                 dev_err(&pdev->dev, "failed to get memory registers\n");
 830                 ret = -ENXIO;
 831                 goto dealloc_fb;
 832         }
 833
 834         size = (res->end - res->start) + 1;
 835         info->mem = request_mem_region(res->start, size, pdev->name);
 836         if (info->mem == NULL) {
 837                 dev_err(&pdev->dev, "failed to get memory region\n");
 838                 ret = -ENOENT;
 839                 goto dealloc_fb;
 840         }
 841
 842         info->io = ioremap(res->start, size);
 843         if (info->io == NULL) {
 844                 dev_err(&pdev->dev, "ioremap() of registers failed\n");
 845                 ret = -ENXIO;
 846                 goto release_mem;
 847         }
 848
 849         dprintk("devinit\n");
 850
 851         strcpy(fbinfo->fix.id, driver_name);
 852
 853         /* Stop the video */
 854         lcdcon1 = readl(info->io + S3C2410_LCDCON1);
 855         writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
 856
 857         fbinfo->fix.type            = FB_TYPE_PACKED_PIXELS;
 858         fbinfo->fix.type_aux        = 0;
 859         fbinfo->fix.xpanstep        = 0;
 860         fbinfo->fix.ypanstep        = 0;
 861         fbinfo->fix.ywrapstep       = 0;
 862         fbinfo->fix.accel           = FB_ACCEL_NONE;
 863
 864         fbinfo->var.nonstd          = 0;
 865         fbinfo->var.activate        = FB_ACTIVATE_NOW;
 866         fbinfo->var.accel_flags     = 0;
 867         fbinfo->var.vmode           = FB_VMODE_NONINTERLACED;
 868
 869         fbinfo->fbops               = &s3c2410fb_ops;
 870         fbinfo->flags               = FBINFO_FLAG_DEFAULT;
 871         fbinfo->pseudo_palette      = &info->pseudo_pal;
 872
 873         for (i = 0; i < 256; i++)
 874                 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 875
 876         ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
 877         if (ret) {
 878                 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
 879                 ret = -EBUSY;
 880                 goto release_regs;
 881         }
 882
 883         info->clk = clk_get(NULL, "lcd");
 884         if (!info->clk || IS_ERR(info->clk)) {
 885                 printk(KERN_ERR "failed to get lcd clock source\n");
 886                 ret = -ENOENT;
 887                 goto release_irq;
 888         }
 889
 890         clk_enable(info->clk);
 891         dprintk("got and enabled clock\n");
 892
 893         msleep(1);
 894
 895         /* find maximum required memory size for display */
 896         for (i = 0; i < mach_info->num_displays; i++) {
 897                 unsigned long smem_len = mach_info->displays[i].xres;
 898
 899                 smem_len *= mach_info->displays[i].yres;
 900                 smem_len *= mach_info->displays[i].bpp;
 901                 smem_len >>= 3;
 902                 if (fbinfo->fix.smem_len < smem_len)
 903                         fbinfo->fix.smem_len = smem_len;
 904         }
 905
 906         /* Initialize video memory */
 907         ret = s3c2410fb_map_video_memory(fbinfo);
 908         if (ret) {
 909                 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
 910                 ret = -ENOMEM;
 911                 goto release_clock;
 912         }
 913
 914         dprintk("got video memory\n");
 915
 916         fbinfo->var.xres = display->xres;
 917         fbinfo->var.yres = display->yres;
 918         fbinfo->var.bits_per_pixel = display->bpp;
 919
 920         s3c2410fb_init_registers(fbinfo);
 921
 922         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 923
 924         ret = register_framebuffer(fbinfo);
 925         if (ret < 0) {
 926                 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
 927                         ret);
 928                 goto free_video_memory;
 929         }
 930
 931         /* create device files */
 932         device_create_file(&pdev->dev, &dev_attr_debug);
 933
 934         printk(KERN_INFO "fb%d: %s frame buffer device\n",
 935                 fbinfo->node, fbinfo->fix.id);
 936
 937         return 0;
 938
 939 free_video_memory:
 940         s3c2410fb_unmap_video_memory(fbinfo);
 941 release_clock:
 942         clk_disable(info->clk);
 943         clk_put(info->clk);
 944 release_irq:
 945         free_irq(irq, info);
 946 release_regs:
 947         iounmap(info->io);
 948 release_mem:
 949         release_resource(info->mem);
 950         kfree(info->mem);
 951 dealloc_fb:
 952         platform_set_drvdata(pdev, NULL);
 953         framebuffer_release(fbinfo);
 954         return ret;
 955 }
 956
 957 /* s3c2410fb_stop_lcd
 958  *
 959  * shutdown the lcd controller
 960  */
 961 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
 962 {
 963         unsigned long flags;
 964
 965         local_irq_save(flags);
 966
 967         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 968         writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
 969
 970         local_irq_restore(flags);
 971 }
 972
 973 /*
 974  *  Cleanup
 975  */
 976 static int s3c2410fb_remove(struct platform_device *pdev)
 977 {
 978         struct fb_info *fbinfo = platform_get_drvdata(pdev);
 979         struct s3c2410fb_info *info = fbinfo->par;
 980         int irq;
 981
 982         unregister_framebuffer(fbinfo);
 983
 984         s3c2410fb_stop_lcd(info);
 985         msleep(1);
 986
 987         s3c2410fb_unmap_video_memory(fbinfo);
 988
 989         if (info->clk) {
 990                 clk_disable(info->clk);
 991                 clk_put(info->clk);
 992                 info->clk = NULL;
 993         }
 994
 995         irq = platform_get_irq(pdev, 0);
 996         free_irq(irq, info);
 997
 998         iounmap(info->io);
 999
1000         release_resource(info->mem);
1001         kfree(info->mem);
1002
1003         platform_set_drvdata(pdev, NULL);
1004         framebuffer_release(fbinfo);
1005
1006         return 0;
1007 }
1008
1009 #ifdef CONFIG_PM
1010
1011 /* suspend and resume support for the lcd controller */
1012 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1013 {
1014         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1015         struct s3c2410fb_info *info = fbinfo->par;
1016
1017         s3c2410fb_stop_lcd(info);
1018
1019         /* sleep before disabling the clock, we need to ensure
1020          * the LCD DMA engine is not going to get back on the bus
1021          * before the clock goes off again (bjd) */
1022
1023         msleep(1);
1024         clk_disable(info->clk);
1025
1026         return 0;
1027 }
1028
1029 static int s3c2410fb_resume(struct platform_device *dev)
1030 {
1031         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1032         struct s3c2410fb_info *info = fbinfo->par;
1033
1034         clk_enable(info->clk);
1035         msleep(1);
1036
1037         s3c2410fb_init_registers(info);
1038
1039         return 0;
1040 }
1041
1042 #else
1043 #define s3c2410fb_suspend NULL
1044 #define s3c2410fb_resume  NULL
1045 #endif
1046
1047 static struct platform_driver s3c2410fb_driver = {
1048         .probe          = s3c2410fb_probe,
1049         .remove         = s3c2410fb_remove,
1050         .suspend        = s3c2410fb_suspend,
1051         .resume         = s3c2410fb_resume,
1052         .driver         = {
1053                 .name   = "s3c2410-lcd",
1054                 .owner  = THIS_MODULE,
1055         },
1056 };
1057
1058 int __init s3c2410fb_init(void)
1059 {
1060         return platform_driver_register(&s3c2410fb_driver);
1061 }
1062
1063 static void __exit s3c2410fb_cleanup(void)
1064 {
1065         platform_driver_unregister(&s3c2410fb_driver);
1066 }
1067
1068 module_init(s3c2410fb_init);
1069 module_exit(s3c2410fb_cleanup);
1070
1071 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1072               "Ben Dooks <ben-linux@fluff.org>");
1073 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1074 MODULE_LICENSE("GPL");