1 comment "Processor Type"
7 # Select CPU types depending on the architecture selected. This selects
8 # which CPUs we support in the kernel image, and the compiler instruction
13 bool "Support ARM610 processor" if ARCH_RPC
18 select CPU_COPY_V3 if MMU
19 select CPU_TLB_V3 if MMU
20 select CPU_PABRT_NOIFAR
22 The ARM610 is the successor to the ARM3 processor
23 and was produced by VLSI Technology Inc.
25 Say Y if you want support for the ARM610 processor.
30 bool "Support ARM7TDMI processor"
34 select CPU_PABRT_NOIFAR
37 A 32-bit RISC microprocessor based on the ARM7 processor core
38 which has no memory control unit and cache.
40 Say Y if you want support for the ARM7TDMI processor.
45 bool "Support ARM710 processor" if ARCH_RPC
50 select CPU_COPY_V3 if MMU
51 select CPU_TLB_V3 if MMU
52 select CPU_PABRT_NOIFAR
54 A 32-bit RISC microprocessor based on the ARM7 processor core
55 designed by Advanced RISC Machines Ltd. The ARM710 is the
56 successor to the ARM610 processor. It was released in
57 July 1994 by VLSI Technology Inc.
59 Say Y if you want support for the ARM710 processor.
64 bool "Support ARM720T processor" if ARCH_INTEGRATOR
67 select CPU_PABRT_NOIFAR
71 select CPU_COPY_V4WT if MMU
72 select CPU_TLB_V4WT if MMU
74 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
75 MMU built around an ARM7TDMI core.
77 Say Y if you want support for the ARM720T processor.
82 bool "Support ARM740T processor" if ARCH_INTEGRATOR
86 select CPU_PABRT_NOIFAR
87 select CPU_CACHE_V3 # although the core is v4t
90 A 32-bit RISC processor with 8KB cache or 4KB variants,
91 write buffer and MPU(Protection Unit) built around
94 Say Y if you want support for the ARM740T processor.
99 bool "Support ARM9TDMI processor"
102 select CPU_ABRT_NOMMU
103 select CPU_PABRT_NOIFAR
106 A 32-bit RISC microprocessor based on the ARM9 processor core
107 which has no memory control unit and cache.
109 Say Y if you want support for the ARM9TDMI processor.
114 bool "Support ARM920T processor" if ARCH_INTEGRATOR
117 select CPU_PABRT_NOIFAR
118 select CPU_CACHE_V4WT
119 select CPU_CACHE_VIVT
121 select CPU_COPY_V4WB if MMU
122 select CPU_TLB_V4WBI if MMU
124 The ARM920T is licensed to be produced by numerous vendors,
125 and is used in the Maverick EP9312 and the Samsung S3C2410.
127 More information on the Maverick EP9312 at
128 <http://linuxdevices.com/products/PD2382866068.html>.
130 Say Y if you want support for the ARM920T processor.
135 bool "Support ARM922T processor" if ARCH_INTEGRATOR
138 select CPU_PABRT_NOIFAR
139 select CPU_CACHE_V4WT
140 select CPU_CACHE_VIVT
142 select CPU_COPY_V4WB if MMU
143 select CPU_TLB_V4WBI if MMU
145 The ARM922T is a version of the ARM920T, but with smaller
146 instruction and data caches. It is used in Altera's
147 Excalibur XA device family and Micrel's KS8695 Centaur.
149 Say Y if you want support for the ARM922T processor.
154 bool "Support ARM925T processor" if ARCH_OMAP1
157 select CPU_PABRT_NOIFAR
158 select CPU_CACHE_V4WT
159 select CPU_CACHE_VIVT
161 select CPU_COPY_V4WB if MMU
162 select CPU_TLB_V4WBI if MMU
164 The ARM925T is a mix between the ARM920T and ARM926T, but with
165 different instruction and data caches. It is used in TI's OMAP
168 Say Y if you want support for the ARM925T processor.
173 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
175 select CPU_ABRT_EV5TJ
176 select CPU_PABRT_NOIFAR
177 select CPU_CACHE_VIVT
179 select CPU_COPY_V4WB if MMU
180 select CPU_TLB_V4WBI if MMU
182 This is a variant of the ARM920. It has slightly different
183 instruction sequences for cache and TLB operations. Curiously,
184 there is no documentation on it at the ARM corporate website.
186 Say Y if you want support for the ARM926T processor.
194 select CPU_PABRT_NOIFAR
195 select CPU_CACHE_VIVT
198 select CPU_COPY_FA if MMU
199 select CPU_TLB_FA if MMU
201 The FA526 is a version of the ARMv4 compatible processor with
202 Branch Target Buffer, Unified TLB and cache line size 16.
204 Say Y if you want support for the FA526 processor.
209 bool "Support ARM940T processor" if ARCH_INTEGRATOR
212 select CPU_ABRT_NOMMU
213 select CPU_PABRT_NOIFAR
214 select CPU_CACHE_VIVT
217 ARM940T is a member of the ARM9TDMI family of general-
218 purpose microprocessors with MPU and separate 4KB
219 instruction and 4KB data cases, each with a 4-word line
222 Say Y if you want support for the ARM940T processor.
227 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
230 select CPU_ABRT_NOMMU
231 select CPU_PABRT_NOIFAR
232 select CPU_CACHE_VIVT
235 ARM946E-S is a member of the ARM9E-S family of high-
236 performance, 32-bit system-on-chip processor solutions.
237 The TCM and ARMv5TE 32-bit instruction set is supported.
239 Say Y if you want support for the ARM946E-S processor.
242 # ARM1020 - needs validating
244 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
247 select CPU_PABRT_NOIFAR
248 select CPU_CACHE_V4WT
249 select CPU_CACHE_VIVT
251 select CPU_COPY_V4WB if MMU
252 select CPU_TLB_V4WBI if MMU
254 The ARM1020 is the 32K cached version of the ARM10 processor,
255 with an addition of a floating-point unit.
257 Say Y if you want support for the ARM1020 processor.
260 # ARM1020E - needs validating
262 bool "Support ARM1020E processor" if ARCH_INTEGRATOR
265 select CPU_PABRT_NOIFAR
266 select CPU_CACHE_V4WT
267 select CPU_CACHE_VIVT
269 select CPU_COPY_V4WB if MMU
270 select CPU_TLB_V4WBI if MMU
275 bool "Support ARM1022E processor" if ARCH_INTEGRATOR
278 select CPU_PABRT_NOIFAR
279 select CPU_CACHE_VIVT
281 select CPU_COPY_V4WB if MMU # can probably do better
282 select CPU_TLB_V4WBI if MMU
284 The ARM1022E is an implementation of the ARMv5TE architecture
285 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
286 embedded trace macrocell, and a floating-point unit.
288 Say Y if you want support for the ARM1022E processor.
293 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
295 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
296 select CPU_PABRT_NOIFAR
297 select CPU_CACHE_VIVT
299 select CPU_COPY_V4WB if MMU # can probably do better
300 select CPU_TLB_V4WBI if MMU
302 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
303 based upon the ARM10 integer core.
305 Say Y if you want support for the ARM1026EJ-S processor.
310 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
311 select CPU_32v3 if ARCH_RPC
312 select CPU_32v4 if !ARCH_RPC
314 select CPU_PABRT_NOIFAR
315 select CPU_CACHE_V4WB
316 select CPU_CACHE_VIVT
318 select CPU_COPY_V4WB if MMU
319 select CPU_TLB_V4WB if MMU
321 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
322 is available at five speeds ranging from 100 MHz to 233 MHz.
323 More information is available at
324 <http://developer.intel.com/design/strong/sa110.htm>.
326 Say Y if you want support for the SA-110 processor.
334 select CPU_PABRT_NOIFAR
335 select CPU_CACHE_V4WB
336 select CPU_CACHE_VIVT
338 select CPU_TLB_V4WB if MMU
345 select CPU_PABRT_NOIFAR
346 select CPU_CACHE_VIVT
348 select CPU_TLB_V4WBI if MMU
350 # XScale Core Version 3
355 select CPU_PABRT_NOIFAR
356 select CPU_CACHE_VIVT
358 select CPU_TLB_V4WBI if MMU
361 # Marvell PJ1 (Mohawk)
366 select CPU_PABRT_NOIFAR
367 select CPU_CACHE_VIVT
369 select CPU_TLB_V4WBI if MMU
370 select CPU_COPY_V4WB if MMU
377 select CPU_PABRT_NOIFAR
378 select CPU_CACHE_VIVT
380 select CPU_COPY_FEROCEON if MMU
381 select CPU_TLB_FEROCEON if MMU
383 config CPU_FEROCEON_OLD_ID
384 bool "Accept early Feroceon cores with an ARM926 ID"
385 depends on CPU_FEROCEON && !CPU_ARM926T
388 This enables the usage of some old Feroceon cores
389 for which the CPU ID is equal to the ARM926 ID.
390 Relevant for Feroceon-1850 and early Feroceon-2850.
394 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
397 select CPU_PABRT_NOIFAR
399 select CPU_CACHE_VIPT
401 select CPU_HAS_ASID if MMU
402 select CPU_COPY_V6 if MMU
403 select CPU_TLB_V6 if MMU
407 bool "Support ARM V6K processor extensions" if !SMP
409 default y if SMP && !ARCH_MX3
411 Say Y here if your ARMv6 processor supports the 'K' extension.
412 This enables the kernel to use some instructions not present
413 on previous processors, and as such a kernel build with this
414 enabled will not boot on processors with do not support these
419 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
423 select CPU_PABRT_IFAR
425 select CPU_CACHE_VIPT
427 select CPU_HAS_ASID if MMU
428 select CPU_COPY_V6 if MMU
429 select CPU_TLB_V7 if MMU
431 # Figure out what processor architecture version we should be using.
432 # This defines the compiler instruction set which depends on the machine type.
435 select TLS_REG_EMUL if SMP || !MMU
436 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
440 select TLS_REG_EMUL if SMP || !MMU
441 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
445 select TLS_REG_EMUL if SMP || !MMU
446 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
450 select TLS_REG_EMUL if SMP || !MMU
451 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
455 select TLS_REG_EMUL if !CPU_32v6K && !MMU
461 config CPU_ABRT_NOMMU
476 config CPU_ABRT_EV5TJ
485 config CPU_PABRT_IFAR
488 config CPU_PABRT_NOIFAR
498 config CPU_CACHE_V4WT
501 config CPU_CACHE_V4WB
510 config CPU_CACHE_VIVT
513 config CPU_CACHE_VIPT
520 # The copy-page model
530 config CPU_COPY_FEROCEON
539 # This selects the TLB model
543 ARM Architecture Version 3 TLB.
548 ARM Architecture Version 4 TLB with writethrough cache.
553 ARM Architecture Version 4 TLB with writeback cache.
558 ARM Architecture Version 4 TLB with writeback cache and invalidate
559 instruction cache entry.
561 config CPU_TLB_FEROCEON
564 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
569 Faraday ARM FA526 architecture, unified TLB with writeback cache
570 and invalidate instruction cache entry. Branch target buffer is
584 This indicates whether the CPU has the ASID register; used to
585 tag TLB and possibly cache entries.
590 Processor has the CP15 register.
596 Processor has the CP15 register, which has MMU related registers.
602 Processor has the CP15 register, which has MPU related registers.
605 # CPU supports 36-bit I/O
610 comment "Processor Features"
613 bool "Support Thumb user binaries"
614 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON
617 Say Y if you want to include kernel support for running user space
620 The Thumb instruction set is a compressed form of the standard ARM
621 instruction set resulting in smaller binaries at the expense of
622 slightly less efficient code.
624 If you don't know what this all is, saying Y is a safe choice.
627 bool "Enable ThumbEE CPU extension"
630 Say Y here if you have a CPU with the ThumbEE extension and code to
631 make use of it. Say N for code that can run on CPUs without ThumbEE.
633 config CPU_BIG_ENDIAN
634 bool "Build big-endian kernel"
635 depends on ARCH_SUPPORTS_BIG_ENDIAN
637 Say Y if you plan on running a kernel in big-endian mode.
638 Note that your board must be properly built and your board
639 port must properly enable any big-endian related features
640 of your chipset/board/processor.
642 config CPU_ENDIAN_BE8
644 depends on CPU_BIG_ENDIAN
645 default CPU_V6 || CPU_V7
647 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
649 config CPU_ENDIAN_BE32
651 depends on CPU_BIG_ENDIAN
652 default !CPU_ENDIAN_BE8
654 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
656 config CPU_HIGH_VECTOR
657 depends on !MMU && CPU_CP15 && !CPU_ARM740T
658 bool "Select the High exception vector"
660 Say Y here to select high exception vector(0xFFFF0000~).
661 The exception vector can be vary depending on the platform
662 design in nommu mode. If your platform needs to select
663 high exception vector, say Y.
664 Otherwise or if you are unsure, say N, and the low exception
665 vector (0x00000000~) will be used.
667 config CPU_ICACHE_DISABLE
668 bool "Disable I-Cache (I-bit)"
669 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
671 Say Y here to disable the processor instruction cache. Unless
672 you have a reason not to or are unsure, say N.
674 config CPU_DCACHE_DISABLE
675 bool "Disable D-Cache (C-bit)"
678 Say Y here to disable the processor data cache. Unless
679 you have a reason not to or are unsure, say N.
681 config CPU_DCACHE_SIZE
683 depends on CPU_ARM740T || CPU_ARM946E
684 default 0x00001000 if CPU_ARM740T
685 default 0x00002000 # default size for ARM946E-S
687 Some cores are synthesizable to have various sized cache. For
688 ARM946E-S case, it can vary from 0KB to 1MB.
689 To support such cache operations, it is efficient to know the size
691 If your SoC is configured to have a different size, define the value
692 here with proper conditions.
694 config CPU_DCACHE_WRITETHROUGH
695 bool "Force write through D-cache"
696 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
697 default y if CPU_ARM925T
699 Say Y here to use the data cache in writethrough mode. Unless you
700 specifically require this or are unsure, say N.
702 config CPU_CACHE_ROUND_ROBIN
703 bool "Round robin I and D cache replacement algorithm"
704 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
706 Say Y here to use the predictable round-robin cache replacement
707 policy. Unless you specifically require this or are unsure, say N.
709 config CPU_BPREDICT_DISABLE
710 bool "Disable branch prediction"
711 depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
713 Say Y here to disable branch prediction. If unsure, say N.
718 An SMP system using a pre-ARMv6 processor (there are apparently
719 a few prototypes like that in existence) and therefore access to
720 that required register must be emulated.
724 depends on !TLS_REG_EMUL
725 default y if SMP || CPU_32v7
727 This selects support for the CP15 thread register.
728 It is defined to be available on some ARMv6 processors (including
729 all SMP capable ARMv6's) or later processors. User space may
730 assume directly accessing that register and always obtain the
731 expected value only on ARMv7 and above.
733 config NEEDS_SYSCALL_FOR_CMPXCHG
736 SMP on a pre-ARMv6 processor? Well OK then.
737 Forget about fast user space cmpxchg support.
738 It is just not possible.
743 config CACHE_FEROCEON_L2
744 bool "Enable the Feroceon L2 cache controller"
745 depends on ARCH_KIRKWOOD || ARCH_MV78XX0
749 This option enables the Feroceon L2 cache controller.
751 config CACHE_FEROCEON_L2_WRITETHROUGH
752 bool "Force Feroceon L2 cache write through"
753 depends on CACHE_FEROCEON_L2
755 Say Y here to use the Feroceon L2 cache in writethrough mode.
756 Unless you specifically require this, say N for writeback mode.
759 bool "Enable the L2x0 outer cache controller"
760 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
761 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX
765 This option enables the L2x0 PrimeCell.
768 bool "Enable the L2 cache on XScale3"
773 This option enables the L2 cache on XScale3.