git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc832x_rdb.dts

   1 /*
   2  * MPC832x RDB Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8323ERDB";
  16         compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet1;
  22                 ethernet1 = &enet0;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 PowerPC,8323@0 {
  33                         device_type = "cpu";
  34                         reg = <0x0>;
  35                         d-cache-line-size = <0x20>;     // 32 bytes
  36                         i-cache-line-size = <0x20>;     // 32 bytes
  37                         d-cache-size = <16384>; // L1, 16K
  38                         i-cache-size = <16384>; // L1, 16K
  39                         timebase-frequency = <0>;
  40                         bus-frequency = <0>;
  41                         clock-frequency = <0>;
  42                 };
  43         };
  44
  45         memory {
  46                 device_type = "memory";
  47                 reg = <0x00000000 0x04000000>;
  48         };
  49
  50         soc8323@e0000000 {
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 device_type = "soc";
  54                 compatible = "simple-bus";
  55                 ranges = <0x0 0xe0000000 0x00100000>;
  56                 reg = <0xe0000000 0x00000200>;
  57                 bus-frequency = <0>;
  58
  59                 wdt@200 {
  60                         device_type = "watchdog";
  61                         compatible = "mpc83xx_wdt";
  62                         reg = <0x200 0x100>;
  63                 };
  64
  65                 i2c@3000 {
  66                         #address-cells = <1>;
  67                         #size-cells = <0>;
  68                         cell-index = <0>;
  69                         compatible = "fsl-i2c";
  70                         reg = <0x3000 0x100>;
  71                         interrupts = <14 0x8>;
  72                         interrupt-parent = <&ipic>;
  73                         dfsrr;
  74                 };
  75
  76                 serial0: serial@4500 {
  77                         cell-index = <0>;
  78                         device_type = "serial";
  79                         compatible = "ns16550";
  80                         reg = <0x4500 0x100>;
  81                         clock-frequency = <0>;
  82                         interrupts = <9 0x8>;
  83                         interrupt-parent = <&ipic>;
  84                 };
  85
  86                 serial1: serial@4600 {
  87                         cell-index = <1>;
  88                         device_type = "serial";
  89                         compatible = "ns16550";
  90                         reg = <0x4600 0x100>;
  91                         clock-frequency = <0>;
  92                         interrupts = <10 0x8>;
  93                         interrupt-parent = <&ipic>;
  94                 };
  95
  96                 dma@82a8 {
  97                         #address-cells = <1>;
  98                         #size-cells = <1>;
  99                         compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
 100                         reg = <0x82a8 4>;
 101                         ranges = <0 0x8100 0x1a8>;
 102                         interrupt-parent = <&ipic>;
 103                         interrupts = <71 8>;
 104                         cell-index = <0>;
 105                         dma-channel@0 {
 106                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 107                                 reg = <0 0x80>;
 108                                 cell-index = <0>;
 109                                 interrupt-parent = <&ipic>;
 110                                 interrupts = <71 8>;
 111                         };
 112                         dma-channel@80 {
 113                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 114                                 reg = <0x80 0x80>;
 115                                 cell-index = <1>;
 116                                 interrupt-parent = <&ipic>;
 117                                 interrupts = <71 8>;
 118                         };
 119                         dma-channel@100 {
 120                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 121                                 reg = <0x100 0x80>;
 122                                 cell-index = <2>;
 123                                 interrupt-parent = <&ipic>;
 124                                 interrupts = <71 8>;
 125                         };
 126                         dma-channel@180 {
 127                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 128                                 reg = <0x180 0x28>;
 129                                 cell-index = <3>;
 130                                 interrupt-parent = <&ipic>;
 131                                 interrupts = <71 8>;
 132                         };
 133                 };
 134
 135                 crypto@30000 {
 136                         compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
 137                         reg = <0x30000 0x10000>;
 138                         interrupts = <11 0x8>;
 139                         interrupt-parent = <&ipic>;
 140                         fsl,num-channels = <1>;
 141                         fsl,channel-fifo-len = <24>;
 142                         fsl,exec-units-mask = <0x4c>;
 143                         fsl,descriptor-types-mask = <0x0122003f>;
 144                 };
 145
 146                 ipic:pic@700 {
 147                         interrupt-controller;
 148                         #address-cells = <0>;
 149                         #interrupt-cells = <2>;
 150                         reg = <0x700 0x100>;
 151                         device_type = "ipic";
 152                 };
 153
 154                 par_io@1400 {
 155                         #address-cells = <1>;
 156                         #size-cells = <1>;
 157                         reg = <0x1400 0x100>;
 158                         ranges = <3 0x1448 0x18>;
 159                         compatible = "fsl,mpc8323-qe-pario";
 160                         device_type = "par_io";
 161                         num-ports = <7>;
 162
 163                         qe_pio_d: gpio-controller@1448 {
 164                                 #gpio-cells = <2>;
 165                                 compatible = "fsl,mpc8323-qe-pario-bank";
 166                                 reg = <3 0x18>;
 167                                 gpio-controller;
 168                         };
 169
 170                         ucc2pio:ucc_pin@02 {
 171                                 pio-map = <
 172                         /* port  pin  dir  open_drain  assignment  has_irq */
 173                                         3  4  3  0  2  0        /* MDIO */
 174                                         3  5  1  0  2  0        /* MDC */
 175                                         3 21  2  0  1  0        /* RX_CLK (CLK16) */
 176                                         3 23  2  0  1  0        /* TX_CLK (CLK3) */
 177                                         0 18  1  0  1  0        /* TxD0 */
 178                                         0 19  1  0  1  0        /* TxD1 */
 179                                         0 20  1  0  1  0        /* TxD2 */
 180                                         0 21  1  0  1  0        /* TxD3 */
 181                                         0 22  2  0  1  0        /* RxD0 */
 182                                         0 23  2  0  1  0        /* RxD1 */
 183                                         0 24  2  0  1  0        /* RxD2 */
 184                                         0 25  2  0  1  0        /* RxD3 */
 185                                         0 26  2  0  1  0        /* RX_ER */
 186                                         0 27  1  0  1  0        /* TX_ER */
 187                                         0 28  2  0  1  0        /* RX_DV */
 188                                         0 29  2  0  1  0        /* COL */
 189                                         0 30  1  0  1  0        /* TX_EN */
 190                                         0 31  2  0  1  0>;      /* CRS */
 191                         };
 192                         ucc3pio:ucc_pin@03 {
 193                                 pio-map = <
 194                         /* port  pin  dir  open_drain  assignment  has_irq */
 195                                         0 13  2  0  1  0        /* RX_CLK (CLK9) */
 196                                         3 24  2  0  1  0        /* TX_CLK (CLK10) */
 197                                         1  0  1  0  1  0        /* TxD0 */
 198                                         1  1  1  0  1  0        /* TxD1 */
 199                                         1  2  1  0  1  0        /* TxD2 */
 200                                         1  3  1  0  1  0        /* TxD3 */
 201                                         1  4  2  0  1  0        /* RxD0 */
 202                                         1  5  2  0  1  0        /* RxD1 */
 203                                         1  6  2  0  1  0        /* RxD2 */
 204                                         1  7  2  0  1  0        /* RxD3 */
 205                                         1  8  2  0  1  0        /* RX_ER */
 206                                         1  9  1  0  1  0        /* TX_ER */
 207                                         1 10  2  0  1  0        /* RX_DV */
 208                                         1 11  2  0  1  0        /* COL */
 209                                         1 12  1  0  1  0        /* TX_EN */
 210                                         1 13  2  0  1  0>;      /* CRS */
 211                         };
 212                 };
 213         };
 214
 215         qe@e0100000 {
 216                 #address-cells = <1>;
 217                 #size-cells = <1>;
 218                 device_type = "qe";
 219                 compatible = "fsl,qe";
 220                 ranges = <0x0 0xe0100000 0x00100000>;
 221                 reg = <0xe0100000 0x480>;
 222                 brg-frequency = <0>;
 223                 bus-frequency = <198000000>;
 224                 fsl,qe-num-riscs = <1>;
 225                 fsl,qe-num-snums = <28>;
 226
 227                 muram@10000 {
 228                         #address-cells = <1>;
 229                         #size-cells = <1>;
 230                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 231                         ranges = <0x0 0x00010000 0x00004000>;
 232
 233                         data-only@0 {
 234                                 compatible = "fsl,qe-muram-data",
 235                                              "fsl,cpm-muram-data";
 236                                 reg = <0x0 0x4000>;
 237                         };
 238                 };
 239
 240                 spi@4c0 {
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243                         cell-index = <0>;
 244                         compatible = "fsl,spi";
 245                         reg = <0x4c0 0x40>;
 246                         interrupts = <2>;
 247                         interrupt-parent = <&qeic>;
 248                         gpios = <&qe_pio_d 13 0>;
 249                         mode = "cpu-qe";
 250
 251                         mmc-slot@0 {
 252                                 compatible = "fsl,mpc8323rdb-mmc-slot",
 253                                              "mmc-spi-slot";
 254                                 reg = <0>;
 255                                 gpios = <&qe_pio_d 14 1
 256                                          &qe_pio_d 15 0>;
 257                                 voltage-ranges = <3300 3300>;
 258                                 spi-max-frequency = <50000000>;
 259                         };
 260                 };
 261
 262                 spi@500 {
 263                         cell-index = <1>;
 264                         compatible = "fsl,spi";
 265                         reg = <0x500 0x40>;
 266                         interrupts = <1>;
 267                         interrupt-parent = <&qeic>;
 268                         mode = "cpu";
 269                 };
 270
 271                 enet0: ucc@3000 {
 272                         device_type = "network";
 273                         compatible = "ucc_geth";
 274                         cell-index = <2>;
 275                         reg = <0x3000 0x200>;
 276                         interrupts = <33>;
 277                         interrupt-parent = <&qeic>;
 278                         local-mac-address = [ 00 00 00 00 00 00 ];
 279                         rx-clock-name = "clk16";
 280                         tx-clock-name = "clk3";
 281                         phy-handle = <&phy00>;
 282                         pio-handle = <&ucc2pio>;
 283                 };
 284
 285                 enet1: ucc@2200 {
 286                         device_type = "network";
 287                         compatible = "ucc_geth";
 288                         cell-index = <3>;
 289                         reg = <0x2200 0x200>;
 290                         interrupts = <34>;
 291                         interrupt-parent = <&qeic>;
 292                         local-mac-address = [ 00 00 00 00 00 00 ];
 293                         rx-clock-name = "clk9";
 294                         tx-clock-name = "clk10";
 295                         phy-handle = <&phy04>;
 296                         pio-handle = <&ucc3pio>;
 297                 };
 298
 299                 mdio@3120 {
 300                         #address-cells = <1>;
 301                         #size-cells = <0>;
 302                         reg = <0x3120 0x18>;
 303                         compatible = "fsl,ucc-mdio";
 304
 305                         phy00:ethernet-phy@00 {
 306                                 interrupt-parent = <&ipic>;
 307                                 interrupts = <0>;
 308                                 reg = <0x0>;
 309                                 device_type = "ethernet-phy";
 310                         };
 311                         phy04:ethernet-phy@04 {
 312                                 interrupt-parent = <&ipic>;
 313                                 interrupts = <0>;
 314                                 reg = <0x4>;
 315                                 device_type = "ethernet-phy";
 316                         };
 317                 };
 318
 319                 qeic:interrupt-controller@80 {
 320                         interrupt-controller;
 321                         compatible = "fsl,qe-ic";
 322                         #address-cells = <0>;
 323                         #interrupt-cells = <1>;
 324                         reg = <0x80 0x80>;
 325                         big-endian;
 326                         interrupts = <32 0x8 33 0x8>; //high:32 low:33
 327                         interrupt-parent = <&ipic>;
 328                 };
 329         };
 330
 331         pci0: pci@e0008500 {
 332                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 333                 interrupt-map = <
 334                                 /* IDSEL 0x10 AD16 (USB) */
 335                                  0x8000 0x0 0x0 0x1 &ipic 17 0x8
 336
 337                                 /* IDSEL 0x11 AD17 (Mini1)*/
 338                                  0x8800 0x0 0x0 0x1 &ipic 18 0x8
 339                                  0x8800 0x0 0x0 0x2 &ipic 19 0x8
 340                                  0x8800 0x0 0x0 0x3 &ipic 20 0x8
 341                                  0x8800 0x0 0x0 0x4 &ipic 48 0x8
 342
 343                                 /* IDSEL 0x12 AD18 (PCI/Mini2) */
 344                                  0x9000 0x0 0x0 0x1 &ipic 19 0x8
 345                                  0x9000 0x0 0x0 0x2 &ipic 20 0x8
 346                                  0x9000 0x0 0x0 0x3 &ipic 48 0x8
 347                                  0x9000 0x0 0x0 0x4 &ipic 17 0x8>;
 348
 349                 interrupt-parent = <&ipic>;
 350                 interrupts = <66 0x8>;
 351                 bus-range = <0x0 0x0>;
 352                 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 353                           0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 354                           0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
 355                 clock-frequency = <0>;
 356                 #interrupt-cells = <1>;
 357                 #size-cells = <2>;
 358                 #address-cells = <3>;
 359                 reg = <0xe0008500 0x100         /* internal registers */
 360                        0xe0008300 0x8>;         /* config space access registers */
 361                 compatible = "fsl,mpc8349-pci";
 362                 device_type = "pci";
 363         };
 364 };