2 * Copyright (C) 1995 Linus Torvalds
3 * Adapted from 'alpha' version by Gary Thomas
4 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 #include <linux/config.h>
12 #include <linux/errno.h>
13 #include <linux/sched.h>
14 #include <linux/kernel.h>
16 #include <linux/stddef.h>
17 #include <linux/unistd.h>
18 #include <linux/ptrace.h>
19 #include <linux/slab.h>
20 #include <linux/user.h>
21 #include <linux/a.out.h>
22 #include <linux/tty.h>
23 #include <linux/major.h>
24 #include <linux/interrupt.h>
25 #include <linux/reboot.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/version.h>
29 #include <linux/adb.h>
30 #include <linux/module.h>
31 #include <linux/delay.h>
32 #include <linux/ide.h>
33 #include <linux/console.h>
34 #include <linux/seq_file.h>
35 #include <linux/root_dev.h>
36 #include <linux/initrd.h>
37 #include <linux/module.h>
40 #include <asm/pgtable.h>
43 #include <asm/pci-bridge.h>
45 #include <asm/machdep.h>
47 #include <asm/hydra.h>
48 #include <asm/sections.h>
50 #include <asm/i8259.h>
57 void rtas_indicator_progress(char *, unsigned short);
60 EXPORT_SYMBOL(_chrp_type);
62 struct mpic *chrp_mpic;
65 * XXX this should be in xmon.h, but putting it there means xmon.h
66 * has to include <linux/interrupt.h> (to get irqreturn_t), which
67 * causes all sorts of problems. -- paulus
69 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
71 extern unsigned long loops_per_jiffy;
74 extern struct smp_ops_t chrp_smp_ops;
77 static const char *gg2_memtypes[4] = {
78 "FPM", "SDRAM", "EDO", "BEDO"
80 static const char *gg2_cachesizes[4] = {
81 "256 KB", "512 KB", "1 MB", "Reserved"
83 static const char *gg2_cachetypes[4] = {
84 "Asynchronous", "Reserved", "Flow-Through Synchronous",
85 "Pipelined Synchronous"
87 static const char *gg2_cachemodes[4] = {
88 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
91 void chrp_show_cpuinfo(struct seq_file *m)
95 struct device_node *root;
96 const char *model = "";
98 root = find_path_device("/");
100 model = get_property(root, "model", NULL);
101 seq_printf(m, "machine\t\t: CHRP %s\n", model);
103 /* longtrail (goldengate) stuff */
104 if (!strncmp(model, "IBM,LongTrail", 13)) {
105 /* VLSI VAS96011/12 `Golden Gate 2' */
107 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
109 for (i = 0; i < (sdramen ? 4 : 6); i++) {
110 t = in_le32(gg2_pci_config_base+
115 switch ((t>>8) & 0x1f) {
138 seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
139 gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
142 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
143 seq_printf(m, "board l2\t: %s %s (%s)\n",
144 gg2_cachesizes[(t>>7) & 3],
145 gg2_cachetypes[(t>>2) & 3],
146 gg2_cachemodes[t & 3]);
151 * Fixes for the National Semiconductor PC78308VUL SuperI/O
153 * Some versions of Open Firmware incorrectly initialize the IRQ settings
154 * for keyboard and mouse
156 static inline void __init sio_write(u8 val, u8 index)
162 static inline u8 __init sio_read(u8 index)
168 static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
171 u8 level0, type0, active;
173 /* select logical device */
174 sio_write(device, 0x07);
175 active = sio_read(0x30);
176 level0 = sio_read(0x70);
177 type0 = sio_read(0x71);
178 if (level0 != level || type0 != type || !active) {
179 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
180 "remapping to level %d, type %d, active\n",
181 name, level0, type0, !active ? "in" : "", level, type);
182 sio_write(0x01, 0x30);
183 sio_write(level, 0x70);
184 sio_write(type, 0x71);
188 static void __init sio_init(void)
190 struct device_node *root;
192 if ((root = find_path_device("/")) &&
193 !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
194 /* logical device 0 (KBC/Keyboard) */
195 sio_fixup_irq("keyboard", 0, 1, 2);
196 /* select logical device 1 (KBC/Mouse) */
197 sio_fixup_irq("mouse", 1, 12, 2);
202 static void __init pegasos_set_l2cr(void)
204 struct device_node *np;
206 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
207 if (_chrp_type != _CHRP_Pegasos)
210 /* Enable L2 cache if needed */
211 np = find_type_devices("cpu");
213 unsigned int *l2cr = (unsigned int *)
214 get_property (np, "l2cr", NULL);
216 printk ("Pegasos l2cr : no cpu l2cr property found\n");
219 if (!((*l2cr) & 0x80000000)) {
220 printk ("Pegasos l2cr : L2 cache was not active, "
223 _set_L2CR((*l2cr) | 0x80000000);
228 void __init chrp_setup_arch(void)
230 struct device_node *root = find_path_device ("/");
231 char *machine = NULL;
232 struct device_node *device;
233 unsigned int *p = NULL;
235 /* init to some ~sane value until calibrate_delay() runs */
236 loops_per_jiffy = 50000000/HZ;
239 machine = get_property(root, "model", NULL);
240 if (machine && strncmp(machine, "Pegasos", 7) == 0) {
241 _chrp_type = _CHRP_Pegasos;
242 } else if (machine && strncmp(machine, "IBM", 3) == 0) {
243 _chrp_type = _CHRP_IBM;
244 } else if (machine && strncmp(machine, "MOT", 3) == 0) {
245 _chrp_type = _CHRP_Motorola;
247 /* Let's assume it is an IBM chrp if all else fails */
248 _chrp_type = _CHRP_IBM;
250 printk("chrp type = %x\n", _chrp_type);
253 if (rtas_token("display-character") >= 0)
254 ppc_md.progress = rtas_progress;
256 /* use RTAS time-of-day routines if available */
257 if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
258 ppc_md.get_boot_time = rtas_get_boot_time;
259 ppc_md.get_rtc_time = rtas_get_rtc_time;
260 ppc_md.set_rtc_time = rtas_set_rtc_time;
263 #ifdef CONFIG_BLK_DEV_INITRD
264 /* this is fine for chrp */
265 initrd_below_start_ok = 1;
268 ROOT_DEV = Root_RAM0;
271 ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
273 /* On pegasos, enable the L2 cache if not already done by OF */
276 /* Lookup PCI host bridges */
280 * Temporary fixes for PCI devices.
283 hydra_init(); /* Mac I/O */
286 * Fix the Super I/O configuration
290 /* Get the event scan rate for the rtas so we know how
291 * often it expects a heartbeat. -- Cort
293 device = find_devices("rtas");
295 p = (unsigned int *) get_property
296 (device, "rtas-event-scan-rate", NULL);
298 ppc_md.heartbeat = chrp_event_scan;
299 ppc_md.heartbeat_reset = HZ / (*p * 30) - 1;
300 ppc_md.heartbeat_count = 1;
301 printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
302 *p, ppc_md.heartbeat_reset);
305 pci_create_OF_bus_map();
308 * Print the banner, then scroll down so boot progress
309 * can be printed. -- Cort
311 if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
315 chrp_event_scan(void)
317 unsigned char log[1024];
320 /* XXX: we should loop until the hardware says no more error logs -- Cort */
321 rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
323 ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
327 * Finds the open-pic node and sets up the mpic driver.
329 static void __init chrp_find_openpic(void)
331 struct device_node *np, *root;
332 int len, i, j, irq_count;
333 int isu_size, idu_size;
334 unsigned int *iranges, *opprop = NULL;
336 unsigned long opaddr;
338 unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];
340 np = find_type_devices("open-pic");
343 root = find_path_device("/");
345 opprop = (unsigned int *) get_property
346 (root, "platform-open-pic", &oplen);
347 na = prom_n_addr_cells(root);
349 if (opprop && oplen >= na * sizeof(unsigned int)) {
350 opaddr = opprop[na-1]; /* assume 32-bit */
351 oplen /= na * sizeof(unsigned int);
354 if (of_address_to_resource(np, 0, &r))
360 printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
362 irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */
363 prom_get_irq_senses(init_senses, NUM_ISA_INTERRUPTS, NR_IRQS - 4);
364 /* i8259 cascade is always positive level */
365 init_senses[0] = IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE;
367 iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
369 len = 0; /* non-distributed mpic */
371 len /= 2 * sizeof(unsigned int);
374 * The first pair of cells in interrupt-ranges refers to the
375 * IDU; subsequent pairs refer to the ISUs.
378 printk(KERN_ERR "Insufficient addresses for distributed"
379 " OpenPIC (%d < %d)\n", oplen, len);
385 if (len > 0 && iranges[1] != 0) {
386 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
387 iranges[0], iranges[0] + iranges[1] - 1);
388 idu_size = iranges[1];
391 isu_size = iranges[3];
393 chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY,
394 isu_size, NUM_ISA_INTERRUPTS, irq_count,
395 NR_IRQS - 4, init_senses, irq_count,
397 if (chrp_mpic == NULL) {
398 printk(KERN_ERR "Failed to allocate MPIC structure\n");
403 for (i = 1; i < len; ++i) {
406 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
407 iranges[0], iranges[0] + iranges[1] - 1,
409 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
412 mpic_init(chrp_mpic);
413 mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL);
416 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
417 static struct irqaction xmon_irqaction = {
419 .mask = CPU_MASK_NONE,
420 .name = "XMON break",
424 void __init chrp_init_IRQ(void)
426 struct device_node *np;
427 unsigned long chrp_int_ack = 0;
428 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
429 struct device_node *kbd;
432 for (np = find_devices("pci"); np != NULL; np = np->next) {
433 unsigned int *addrp = (unsigned int *)
434 get_property(np, "8259-interrupt-acknowledge", NULL);
438 chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
442 printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
446 i8259_init(chrp_int_ack, 0);
448 if (_chrp_type == _CHRP_Pegasos)
449 ppc_md.get_irq = i8259_irq;
451 ppc_md.get_irq = mpic_get_irq;
453 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
454 /* see if there is a keyboard in the device tree
455 with a parent of type "adb" */
456 for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
457 if (kbd->parent && kbd->parent->type
458 && strcmp(kbd->parent->type, "adb") == 0)
461 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
472 request_region(0x20,0x20,"pic1");
473 request_region(0xa0,0x20,"pic2");
474 request_region(0x00,0x20,"dma1");
475 request_region(0x40,0x20,"timer");
476 request_region(0x80,0x10,"dma page reg");
477 request_region(0xc0,0x20,"dma2");
480 ppc_md.progress(" Have fun! ", 0x7777);
483 void __init chrp_init(void)
485 ISA_DMA_THRESHOLD = ~0L;
486 DMA_MODE_READ = 0x44;
487 DMA_MODE_WRITE = 0x48;
488 isa_io_base = CHRP_ISA_IO_BASE; /* default value */
489 ppc_do_canonicalize_irqs = 1;
491 /* Assume we have an 8259... */
492 __irq_offset_value = NUM_ISA_INTERRUPTS;
494 ppc_md.setup_arch = chrp_setup_arch;
495 ppc_md.show_cpuinfo = chrp_show_cpuinfo;
497 ppc_md.init_IRQ = chrp_init_IRQ;
498 ppc_md.init = chrp_init2;
500 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
502 ppc_md.restart = rtas_restart;
503 ppc_md.power_off = rtas_power_off;
504 ppc_md.halt = rtas_halt;
506 ppc_md.time_init = chrp_time_init;
507 ppc_md.calibrate_decr = generic_calibrate_decr;
509 /* this may get overridden with rtas routines later... */
510 ppc_md.set_rtc_time = chrp_set_rtc_time;
511 ppc_md.get_rtc_time = chrp_get_rtc_time;
514 smp_ops = &chrp_smp_ops;
515 #endif /* CONFIG_SMP */