git.oblomov.eu Git - linux-2.6/blob - arch/ppc/boot/simple/rw4/rw4_init_brd.S

   1 /*----------------------------------------------------------------------------+
   2 |       This source code has been made available to you by IBM on an AS-IS
   3 |       basis.  Anyone receiving this source is licensed under IBM
   4 |       copyrights to use it in any way he or she deems fit, including
   5 |       copying it, modifying it, compiling it, and redistributing it either
   6 |       with or without modifications.  No license under IBM patents or
   7 |       patent applications is to be implied by the copyright license.
   8 |
   9 |       Any user of this software should understand that IBM cannot provide
  10 |       technical support for this software and will not be responsible for
  11 |       any consequences resulting from the use of this software.
  12 |
  13 |       Any person who transfers this source code or any derivative work
  14 |       must include the IBM copyright notice, this paragraph, and the
  15 |       preceding two paragraphs in the transferred software.
  16 |
  17 |       COPYRIGHT   I B M   CORPORATION 1997
  18 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  19 +----------------------------------------------------------------------------*/
  20 /*----------------------------------------------------------------------------+
  21 | Author:    Tony J. Cerreto
  22 | Component: BSPS
  23 | File:      init_brd.s
  24 | Purpose:   Vesta Evaluation Board initialization subroutines.  The following
  25 |            routines are available:
  26 |              1. INITB_EBIU0:    Initialize EBIU0.
  27 |              2. INITB_CONFIG:   Configure board.
  28 |              3. INITB_HSMC0:    Initialize HSMC0 (SDRAM).
  29 |              4. INITB_HSMC1:    Initialize HSMC1 (SDRAM).
  30 |              5. INITB_CACHE:    Initialize Data and Instruction Cache.
  31 |              6. INITB_DCACHE:   Initialize Data Cache.
  32 |              7. INITB_ICACHE:   Initialize Instruction Cache.
  33 |              8. INITB_GET_CSPD: Get CPU Speed (Bus Speed and Processor Speed)
  34 |
  35 | Changes:
  36 | Date:      Author  Comment:
  37 | ---------  ------  --------
  38 | 01-Mar-00  tjc     Created
  39 | 04-Mar-00  jfh     Modified CIC_SEL3_VAL to support 1284 (Mux3 & GPIO 21-28)
  40 | 04-Mar-00  jfh     Modified XILINIX Reg 0 to support 1284 (Mux3 & GPIO 21-28)
  41 | 04-Mar-00  jfh     Modified XILINIX Reg 1 to support 1284 (Mux3 & GPIO 21-28)
  42 | 04-Mar-00  jfh     Modified XILINIX Reg 4 to support 1284 (Mux3 & GPIO 21-28)
  43 | 19-May-00  rlb     Relcoated HSMC0 to 0x1F000000 to support 32MB of contiguous
  44 |                    SDRAM space.  Changed cache ctl regs to reflect this.
  45 | 22-May-00  tjc     Changed initb_get_cspd interface and eliminated
  46 |                    initb_get_bspd routines.
  47 | 26-May-00  tjc     Added two nop instructions after all mtxxx/mfxxx
  48 |                    instructions due to PPC405 bug.
  49 +----------------------------------------------------------------------------*/
  50 #define VESTA
  51 #include "ppc_40x.h"
  52 #include "stb.h"
  53
  54 /*----------------------------------------------------------------------------+
  55 | BOARD CONFIGURATION DEFINES
  56 +----------------------------------------------------------------------------*/
  57 #define CBS0_CR_VAL          0x00000002          /* CBS control reg value    */
  58 #define CIC0_CR_VAL          0xD0800448          /* CIC control reg value    */
  59 #define CIC0_SEL3_VAL        0x11500000          /* CIC select 3 reg value   */
  60 #define CIC0_VCR_VAL         0x00631700          /* CIC video cntl reg value */
  61
  62 /*----------------------------------------------------------------------------+
  63 | EBIU0 BANK REGISTERS DEFINES
  64 +----------------------------------------------------------------------------*/
  65 #define EBIU0_BRCRH0_VAL     0x00000000          /* BR High 0 (Extension Reg)*/
  66 #define EBIU0_BRCRH1_VAL     0x00000000          /* BR High 1 (Extension Reg)*/
  67 #define EBIU0_BRCRH2_VAL     0x40000000          /* BR High 2 (Extension Reg)*/
  68 #define EBIU0_BRCRH3_VAL     0x40000000          /* BR High 3 (Extension Reg)*/
  69 #define EBIU0_BRCRH4_VAL     0x00000000          /* BR High 4 (Extension Reg)*/
  70 #define EBIU0_BRCRH5_VAL     0x00000000          /* BR High 5 (Extension Reg)*/
  71 #define EBIU0_BRCRH6_VAL     0x00000000          /* BR High 6 (Extension Reg)*/
  72 #define EBIU0_BRCRH7_VAL     0x40000000          /* BR High 7 (Extension Reg)*/
  73
  74 #define EBIU0_BRCR0_VAL      0xFC58BFFE          /* BR 0: 16 bit Flash  4 MB */
  75 #define EBIU0_BRCR1_VAL      0xFF00BFFE          /* BR 1: Ext Connector 1 MB */
  76 #if 1
  77 #define EBIU0_BRCR2_VAL      0x207CFFBE          /* BR 2: Xilinx        8 MB */
  78                                                  /* twt == 0x3f              */
  79 #else
  80 #define EBIU0_BRCR2_VAL      0x207CCFBE          /* BR 2: Xilinx        8 MB */
  81                                                  /* twt == 0x0f              */
  82 #endif
  83 #define EBIU0_BRCR3_VAL      0x407CBFBE          /* BR 3: IDE Drive     8 MB */
  84 #define EBIU0_BRCR4_VAL      0xFF00BFFF          /* BR 4: Disabled.     0 MB */
  85 #define EBIU0_BRCR5_VAL      0xFF00BFFF          /* BR 5: Disabled.     0 MB */
  86 #define EBIU0_BRCR6_VAL      0xFF00BFFF          /* BR 6: Disabled.     0 MB */
  87 #define EBIU0_BRCR7_VAL      0xCE3F0003          /* BR 7: Line Mode DMA 2 MB */
  88
  89 /*----------------------------------------------------------------------------+
  90 | GPIO DEFINES
  91 +----------------------------------------------------------------------------*/
  92 #define STB_GPIO0_OUTPUT     (STB_GPIO0_BASE_ADDRESS+ 0x00)
  93 #define STB_GPIO0_TC         (STB_GPIO0_BASE_ADDRESS+ 0x04)
  94 #define STB_GPIO0_OS_0_31    (STB_GPIO0_BASE_ADDRESS+ 0x08)
  95 #define STB_GPIO0_OS_32_63   (STB_GPIO0_BASE_ADDRESS+ 0x0C)
  96 #define STB_GPIO0_TS_0_31    (STB_GPIO0_BASE_ADDRESS+ 0x10)
  97 #define STB_GPIO0_TS_32_63   (STB_GPIO0_BASE_ADDRESS+ 0x14)
  98 #define STB_GPIO0_OD         (STB_GPIO0_BASE_ADDRESS+ 0x18)
  99 #define STB_GPIO0_INPUT      (STB_GPIO0_BASE_ADDRESS+ 0x1C)
 100 #define STB_GPIO0_R1         (STB_GPIO0_BASE_ADDRESS+ 0x20)
 101 #define STB_GPIO0_R2         (STB_GPIO0_BASE_ADDRESS+ 0x24)
 102 #define STB_GPIO0_R3         (STB_GPIO0_BASE_ADDRESS+ 0x28)
 103 #define STB_GPIO0_IS_1_0_31  (STB_GPIO0_BASE_ADDRESS+ 0x30)
 104 #define STB_GPIO0_IS_1_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x34)
 105 #define STB_GPIO0_IS_2_0_31  (STB_GPIO0_BASE_ADDRESS+ 0x38)
 106 #define STB_GPIO0_IS_2_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x3C)
 107 #define STB_GPIO0_IS_3_0_31  (STB_GPIO0_BASE_ADDRESS+ 0x40)
 108 #define STB_GPIO0_IS_3_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x44)
 109 #define STB_GPIO0_SS_1       (STB_GPIO0_BASE_ADDRESS+ 0x50)
 110 #define STB_GPIO0_SS_2       (STB_GPIO0_BASE_ADDRESS+ 0x54)
 111 #define STB_GPIO0_SS_3       (STB_GPIO0_BASE_ADDRESS+ 0x58)
 112
 113 #define GPIO0_TC_VAL         0x0C020004          /* three-state control val  */
 114 #define GPIO0_OS_0_31_VAL    0x51A00004          /* output select 0-31  val  */
 115 #define GPIO0_OS_32_63_VAL   0x0000002F          /* output select 32-63 val  */
 116 #define GPIO0_TS_0_31_VAL    0x51A00000          /* three-state sel 0-31  val*/
 117 #define GPIO0_TS_32_63_VAL   0x0000000F          /* three-state sel 32-63 val*/
 118 #define GPIO0_OD_VAL         0xC0000004          /* open drain val           */
 119 #define GPIO0_IS_1_0_31_VAL  0x50000151          /* input select 1 0-31  val */
 120 #define GPIO0_IS_1_32_63_VAL 0x00000000          /* input select 1 32-63 val */
 121 #define GPIO0_IS_2_0_31_VAL  0x00000000          /* input select 2 0-31  val */
 122 #define GPIO0_IS_2_32_63_VAL 0x00000000          /* input select 2 32-63 val */
 123 #define GPIO0_IS_3_0_31_VAL  0x00000440          /* input select 3 0-31  val */
 124 #define GPIO0_IS_3_32_63_VAL 0x00000000          /* input select 3 32-63 val */
 125 #define GPIO0_SS_1_VAL       0x00000000          /* sync select 1 val        */
 126 #define GPIO0_SS_2_VAL       0x00000000          /* sync select 2 val        */
 127 #define GPIO0_SS_3_VAL       0x00000000          /* sync select 3 val        */
 128
 129 /*----------------------------------------------------------------------------+
 130 | XILINX DEFINES
 131 +----------------------------------------------------------------------------*/
 132 #define STB_XILINX_LED       (STB_FPGA_BASE_ADDRESS+ 0x0100)
 133 #define STB_XILINX1_REG0     (STB_FPGA_BASE_ADDRESS+ 0x40000)
 134 #define STB_XILINX1_REG1     (STB_FPGA_BASE_ADDRESS+ 0x40002)
 135 #define STB_XILINX1_REG2     (STB_FPGA_BASE_ADDRESS+ 0x40004)
 136 #define STB_XILINX1_REG3     (STB_FPGA_BASE_ADDRESS+ 0x40006)
 137 #define STB_XILINX1_REG4     (STB_FPGA_BASE_ADDRESS+ 0x40008)
 138 #define STB_XILINX1_REG5     (STB_FPGA_BASE_ADDRESS+ 0x4000A)
 139 #define STB_XILINX1_REG6     (STB_FPGA_BASE_ADDRESS+ 0x4000C)
 140 #define STB_XILINX1_ID       (STB_FPGA_BASE_ADDRESS+ 0x4000E)
 141 #define STB_XILINX1_FLUSH    (STB_FPGA_BASE_ADDRESS+ 0x4000E)
 142 #define STB_XILINX2_REG0     (STB_FPGA_BASE_ADDRESS+ 0x80000)
 143 #define STB_XILINX2_REG1     (STB_FPGA_BASE_ADDRESS+ 0x80002)
 144 #define STB_XILINX2_REG2     (STB_FPGA_BASE_ADDRESS+ 0x80004)
 145
 146 #define XILINX1_R0_VAL       0x2440              /* Xilinx 1 Register 0 Val  */
 147 #define XILINX1_R1_VAL       0x0025              /* Xilinx 1 Register 1 Val  */
 148 #define XILINX1_R2_VAL       0x0441              /* Xilinx 1 Register 2 Val  */
 149 #define XILINX1_R3_VAL       0x0008              /* Xilinx 1 Register 3 Val  */
 150 #define XILINX1_R4_VAL       0x0100              /* Xilinx 1 Register 4 Val  */
 151 #define XILINX1_R5_VAL       0x6810              /* Xilinx 1 Register 5 Val  */
 152 #define XILINX1_R6_VAL       0x0000              /* Xilinx 1 Register 6 Val  */
 153 #if 0
 154 #define XILINX2_R0_VAL       0x0008              /* Xilinx 2 Register 0 Val  */
 155 #define XILINX2_R1_VAL       0x0000              /* Xilinx 2 Register 1 Val  */
 156 #else
 157 #define XILINX2_R0_VAL       0x0018              /* disable IBM IrDA RxD     */
 158 #define XILINX2_R1_VAL       0x0008              /* enable SICC MAX chip     */
 159 #endif
 160 #define XILINX2_R2_VAL       0x0000              /* Xilinx 2 Register 2 Val  */
 161
 162 /*----------------------------------------------------------------------------+
 163 | HSMC BANK REGISTERS DEFINES
 164 +----------------------------------------------------------------------------*/
 165 #ifdef SDRAM16MB
 166 #define HSMC0_BR0_VAL        0x000D2D55          /* 0x1F000000-007FFFFF R/W  */
 167 #define HSMC0_BR1_VAL        0x008D2D55          /* 0x1F800000-1FFFFFFF R/W  */
 168 #else
 169 #define HSMC0_BR0_VAL        0x1F0D2D55          /* 0x1F000000-007FFFFF R/W  */
 170 #define HSMC0_BR1_VAL        0x1F8D2D55          /* 0x1F800000-1FFFFFFF R/W  */
 171 #endif
 172 #define HSMC1_BR0_VAL        0xA00D2D55          /* 0xA0000000-A07FFFFF R/W  */
 173 #define HSMC1_BR1_VAL        0xA08D2D55          /* 0xA0800000-A0FFFFFF R/W  */
 174
 175 /*----------------------------------------------------------------------------+
 176 | CACHE DEFINES
 177 +----------------------------------------------------------------------------*/
 178 #define DCACHE_NLINES               128          /* no. D-cache lines        */
 179 #define DCACHE_NBYTES                32          /* no. bytes/ D-cache line  */
 180 #define ICACHE_NLINES               256          /* no. I-cache lines        */
 181 #define ICACHE_NBYTES                32          /* no. bytes/ I-cache line  */
 182 #ifdef SDRAM16MB
 183 #define DCACHE_ENABLE        0x80000000          /* D-cache regions to enable*/
 184 #define ICACHE_ENABLE        0x80000001          /* I-cache regions to enable*/
 185 #else
 186 #define DCACHE_ENABLE        0x18000000          /* D-cache regions to enable*/
 187 #define ICACHE_ENABLE        0x18000001          /* I-cache regions to enable*/
 188 #endif
 189
 190 /*----------------------------------------------------------------------------+
 191 | CPU CORE SPEED CALCULATION DEFINES
 192 +----------------------------------------------------------------------------*/
 193 #define GCS_LCNT                 500000          /* CPU speed loop count     */
 194 #define GCS_TROW_BYTES                8          /* no. bytes in table row   */
 195 #define GCS_CTICK_TOL               100          /* allowable clock tick tol */
 196 #define GCS_NMULT                     4          /* no. of core speed mults  */
 197
 198         /*--------------------------------------------------------------------+
 199         |        No. 13.5Mhz
 200         |        Clock Ticks
 201         |        based on a
 202         |        loop count    Bus
 203         |        of 100,000    Speed
 204         +--------------------------------------------------------------------*/
 205 gcs_lookup_table:
 206         .int           50000,  54000000          /* 54.0 Mhz                 */
 207         .int           66667,  40500000          /* 40.5 Mhz                 */
 208         .int           54545,  49500000          /* 49.5 Mhz                 */
 209         .int           46154,  58500000          /* 58.5 Mhz                 */
 210         .int               0,         0          /* end of table flag        */
 211
 212
 213 /*****************************************************************************+
 214 | XXXXXXX  XXX XXX   XXXXXX  XXXXXXX  XXXXXX   XX   XX     XX    XXXX
 215 |  XX   X   XX XX    X XX X   XX   X   XX  XX  XXX  XX    XXXX    XX
 216 |  XX X      XXX       XX     XX X     XX  XX  XXXX XX   XX  XX   XX
 217 |  XXXX       X        XX     XXXX     XXXXX   XX XXXX   XX  XX   XX
 218 |  XX X      XXX       XX     XX X     XX XX   XX  XXX   XXXXXX   XX
 219 |  XX   X   XX XX      XX     XX   X   XX  XX  XX   XX   XX  XX   XX  XX
 220 | XXXXXXX  XXX XXX    XXXX   XXXXXXX  XXX  XX  XX   XX   XX  XX  XXXXXXX
 221 +*****************************************************************************/
 222 /******************************************************************************
 223 |
 224 | Routine:    INITB_EBIU0.
 225 |
 226 | Purpose:    Initialize all the EBIU0 Bank Registers
 227 | Parameters: None.
 228 | Returns:    None.
 229 |
 230 ******************************************************************************/
 231         function_prolog(initb_ebiu0)
 232         /*--------------------------------------------------------------------+
 233         |  Set EBIU0 Bank 0
 234         +--------------------------------------------------------------------*/
 235         lis     r10,EBIU0_BRCR0_VAL@h
 236         ori     r10,r10,EBIU0_BRCR0_VAL@l
 237         mtdcr   ebiu0_brcr0,r10
 238         lis     r10,EBIU0_BRCRH0_VAL@h
 239         ori     r10,r10,EBIU0_BRCRH0_VAL@l
 240         mtdcr   ebiu0_brcrh0,r10
 241
 242         /*--------------------------------------------------------------------+
 243         |  Set EBIU0 Bank 1
 244         +--------------------------------------------------------------------*/
 245         lis     r10,EBIU0_BRCR1_VAL@h
 246         ori     r10,r10,EBIU0_BRCR1_VAL@l
 247         mtdcr   ebiu0_brcr1,r10
 248         lis     r10,EBIU0_BRCRH1_VAL@h
 249         ori     r10,r10,EBIU0_BRCRH1_VAL@l
 250         mtdcr   ebiu0_brcrh1,r10
 251
 252         /*--------------------------------------------------------------------+
 253         |  Set EBIU0 Bank 2
 254         +--------------------------------------------------------------------*/
 255         lis     r10,EBIU0_BRCR2_VAL@h
 256         ori     r10,r10,EBIU0_BRCR2_VAL@l
 257         mtdcr   ebiu0_brcr2,r10
 258         lis     r10,EBIU0_BRCRH2_VAL@h
 259         ori     r10,r10,EBIU0_BRCRH2_VAL@l
 260         mtdcr   ebiu0_brcrh2,r10
 261
 262         /*--------------------------------------------------------------------+
 263         |  Set EBIU0 Bank 3
 264         +--------------------------------------------------------------------*/
 265         lis     r10,EBIU0_BRCR3_VAL@h
 266         ori     r10,r10,EBIU0_BRCR3_VAL@l
 267         mtdcr   ebiu0_brcr3,r10
 268         lis     r10,EBIU0_BRCRH3_VAL@h
 269         ori     r10,r10,EBIU0_BRCRH3_VAL@l
 270         mtdcr   ebiu0_brcrh3,r10
 271
 272         /*--------------------------------------------------------------------+
 273         |  Set EBIU0 Bank 4
 274         +--------------------------------------------------------------------*/
 275         lis     r10,EBIU0_BRCR4_VAL@h
 276         ori     r10,r10,EBIU0_BRCR4_VAL@l
 277         mtdcr   ebiu0_brcr4,r10
 278         lis     r10,EBIU0_BRCRH4_VAL@h
 279         ori     r10,r10,EBIU0_BRCRH4_VAL@l
 280         mtdcr   ebiu0_brcrh4,r10
 281
 282         /*--------------------------------------------------------------------+
 283         |  Set EBIU0 Bank 5
 284         +--------------------------------------------------------------------*/
 285         lis     r10,EBIU0_BRCR5_VAL@h
 286         ori     r10,r10,EBIU0_BRCR5_VAL@l
 287         mtdcr   ebiu0_brcr5,r10
 288         lis     r10,EBIU0_BRCRH5_VAL@h
 289         ori     r10,r10,EBIU0_BRCRH5_VAL@l
 290         mtdcr   ebiu0_brcrh5,r10
 291
 292         /*--------------------------------------------------------------------+
 293         |  Set EBIU0 Bank 6
 294         +--------------------------------------------------------------------*/
 295         lis     r10,EBIU0_BRCR6_VAL@h
 296         ori     r10,r10,EBIU0_BRCR6_VAL@l
 297         mtdcr   ebiu0_brcr6,r10
 298         lis     r10,EBIU0_BRCRH6_VAL@h
 299         ori     r10,r10,EBIU0_BRCRH6_VAL@l
 300         mtdcr   ebiu0_brcrh6,r10
 301
 302         /*--------------------------------------------------------------------+
 303         |  Set EBIU0 Bank 7
 304         +--------------------------------------------------------------------*/
 305         lis     r10,EBIU0_BRCR7_VAL@h
 306         ori     r10,r10,EBIU0_BRCR7_VAL@l
 307         mtdcr   ebiu0_brcr7,r10
 308         lis     r10,EBIU0_BRCRH7_VAL@h
 309         ori     r10,r10,EBIU0_BRCRH7_VAL@l
 310         mtdcr   ebiu0_brcrh7,r10
 311
 312         blr
 313         function_epilog(initb_ebiu0)
 314
 315
 316 /******************************************************************************
 317 |
 318 | Routine:    INITB_CONFIG
 319 |
 320 | Purpose:    Configure the Vesta Evaluation Board.  The following items
 321 |             will be configured:
 322 |               1.  Cross-Bar Switch.
 323 |               2.  Chip Interconnect.
 324 |               3.  Clear/reset key PPC registers.
 325 |               4.  Xilinx and GPIO Registers.
 326 |
 327 | Returns:    None.
 328 |
 329 ******************************************************************************/
 330         function_prolog(initb_config)
 331         /*--------------------------------------------------------------------+
 332         |  Init CROSS-BAR SWITCH
 333         +--------------------------------------------------------------------*/
 334         lis     r10,CBS0_CR_VAL@h                /* r10 <- CBS Cntl Reg val  */
 335         ori     r10,r10,CBS0_CR_VAL@l
 336         mtdcr   cbs0_cr,r10
 337
 338         /*--------------------------------------------------------------------+
 339         |  Init Chip-Interconnect (CIC) Registers
 340         +--------------------------------------------------------------------*/
 341         lis     r10,CIC0_CR_VAL@h                /* r10 <- CIC Cntl Reg val  */
 342         ori     r10,r10,CIC0_CR_VAL@l
 343         mtdcr   cic0_cr,r10
 344
 345         lis     r10,CIC0_SEL3_VAL@h              /* r10 <- CIC SEL3 Reg val  */
 346         ori     r10,r10,CIC0_SEL3_VAL@l
 347         mtdcr   cic0_sel3,r10
 348
 349         lis     r10,CIC0_VCR_VAL@h               /* r10 <- CIC Vid C-Reg val */
 350         ori     r10,r10,CIC0_VCR_VAL@l
 351         mtdcr   cic0_vcr,r10
 352
 353         /*--------------------------------------------------------------------+
 354         | Clear SGR and DCWR
 355         +--------------------------------------------------------------------*/
 356         li      r10,0x0000
 357         mtspr   sgr,r10
 358         mtspr   dcwr,r10
 359
 360         /*--------------------------------------------------------------------+
 361         | Clear/set up some machine state registers.
 362         +--------------------------------------------------------------------*/
 363         li      r10,0x0000                       /* r10 <- 0                 */
 364         mtdcr   ebiu0_besr,r10                   /* clr Bus Err Syndrome Reg */
 365         mtspr   esr,r10                          /* clr Exceptn Syndrome Reg */
 366         mttcr   r10                              /* timer control register   */
 367
 368         mtdcr   uic0_er,r10                      /* disable all interrupts   */
 369
 370         /* UIC_IIC0 | UIC_IIC1 | UIC_U0 | UIC_IR_RCV | UIC_IR_XMIT */
 371         lis     r10,    0x00600e00@h
 372         ori     r10,r10,0x00600e00@l
 373         mtdcr   uic0_pr,r10
 374
 375         li      r10,0x00000020                  /* UIC_EIR1 */
 376         mtdcr   uic0_tr,r10
 377
 378         lis     r10,0xFFFF                       /* r10 <- 0xFFFFFFFF        */
 379         ori     r10,r10,0xFFFF                   /*                          */
 380         mtdbsr  r10                              /* clear/reset the dbsr     */
 381         mtdcr   uic0_sr,r10                      /* clear pending interrupts */
 382
 383         li      r10,0x1000                       /* set Machine Exception bit*/
 384         oris    r10,r10,0x2                      /* set Criticl Exception bit*/
 385         mtmsr   r10                              /* change MSR               */
 386
 387         /*--------------------------------------------------------------------+
 388         |  Clear XER.
 389         +--------------------------------------------------------------------*/
 390         li      r10,0x0000
 391         mtxer   r10
 392
 393         /*--------------------------------------------------------------------+
 394         |  Init GPIO0 Registers
 395         +--------------------------------------------------------------------*/
 396         lis     r10,    STB_GPIO0_TC@h           /* Three-state control      */
 397         ori     r10,r10,STB_GPIO0_TC@l
 398         lis     r11,    GPIO0_TC_VAL@h
 399         ori     r11,r11,GPIO0_TC_VAL@l
 400         stw     r11,0(r10)
 401
 402         lis     r10,    STB_GPIO0_OS_0_31@h      /* output select 0-31       */
 403         ori     r10,r10,STB_GPIO0_OS_0_31@l
 404         lis     r11,    GPIO0_OS_0_31_VAL@h
 405         ori     r11,r11,GPIO0_OS_0_31_VAL@l
 406         stw     r11,0(r10)
 407
 408         lis     r10,    STB_GPIO0_OS_32_63@h     /* output select 32-63      */
 409         ori     r10,r10,STB_GPIO0_OS_32_63@l
 410         lis     r11,    GPIO0_OS_32_63_VAL@h
 411         ori     r11,r11,GPIO0_OS_32_63_VAL@l
 412         stw     r11,0(r10)
 413
 414         lis     r10,    STB_GPIO0_TS_0_31@h      /* three-state select 0-31  */
 415         ori     r10,r10,STB_GPIO0_TS_0_31@l
 416         lis     r11,    GPIO0_TS_0_31_VAL@h
 417         ori     r11,r11,GPIO0_TS_0_31_VAL@l
 418         stw     r11,0(r10)
 419
 420         lis     r10,    STB_GPIO0_TS_32_63@h     /* three-state select 32-63 */
 421         ori     r10,r10,STB_GPIO0_TS_32_63@l
 422         lis     r11,    GPIO0_TS_32_63_VAL@h
 423         ori     r11,r11,GPIO0_TS_32_63_VAL@l
 424         stw     r11,0(r10)
 425
 426         lis     r10,    STB_GPIO0_OD@h           /* open drain               */
 427         ori     r10,r10,STB_GPIO0_OD@l
 428         lis     r11,    GPIO0_OD_VAL@h
 429         ori     r11,r11,GPIO0_OD_VAL@l
 430         stw     r11,0(r10)
 431
 432         lis     r10,    STB_GPIO0_IS_1_0_31@h    /* input select 1, 0-31     */
 433         ori     r10,r10,STB_GPIO0_IS_1_0_31@l
 434         lis     r11,    GPIO0_IS_1_0_31_VAL@h
 435         ori     r11,r11,GPIO0_IS_1_0_31_VAL@l
 436         stw     r11,0(r10)
 437
 438         lis     r10,    STB_GPIO0_IS_1_32_63@h   /* input select 1, 32-63    */
 439         ori     r10,r10,STB_GPIO0_IS_1_32_63@l
 440         lis     r11,    GPIO0_IS_1_32_63_VAL@h
 441         ori     r11,r11,GPIO0_IS_1_32_63_VAL@l
 442         stw     r11,0(r10)
 443
 444         lis     r10,    STB_GPIO0_IS_2_0_31@h    /* input select 2, 0-31     */
 445         ori     r10,r10,STB_GPIO0_IS_2_0_31@l
 446         lis     r11,    GPIO0_IS_2_0_31_VAL@h
 447         ori     r11,r11,GPIO0_IS_2_0_31_VAL@l
 448         stw     r11,0(r10)
 449
 450         lis     r10,    STB_GPIO0_IS_2_32_63@h   /* input select 2, 32-63    */
 451         ori     r10,r10,STB_GPIO0_IS_2_32_63@l
 452         lis     r11,    GPIO0_IS_2_32_63_VAL@h
 453         ori     r11,r11,GPIO0_IS_2_32_63_VAL@l
 454         stw     r11,0(r10)
 455
 456         lis     r10,    STB_GPIO0_IS_3_0_31@h    /* input select 3, 0-31     */
 457         ori     r10,r10,STB_GPIO0_IS_3_0_31@l
 458         lis     r11,    GPIO0_IS_3_0_31_VAL@h
 459         ori     r11,r11,GPIO0_IS_3_0_31_VAL@l
 460         stw     r11,0(r10)
 461
 462         lis     r10,    STB_GPIO0_IS_3_32_63@h   /* input select 3, 32-63    */
 463         ori     r10,r10,STB_GPIO0_IS_3_32_63@l
 464         lis     r11,    GPIO0_IS_3_32_63_VAL@h
 465         ori     r11,r11,GPIO0_IS_3_32_63_VAL@l
 466         stw     r11,0(r10)
 467
 468         lis     r10,    STB_GPIO0_SS_1@h         /* sync select 1            */
 469         ori     r10,r10,STB_GPIO0_SS_1@l
 470         lis     r11,    GPIO0_SS_1_VAL@h
 471         ori     r11,r11,GPIO0_SS_1_VAL@l
 472         stw     r11,0(r10)
 473
 474         lis     r10,    STB_GPIO0_SS_2@h         /* sync select 2            */
 475         ori     r10,r10,STB_GPIO0_SS_2@l
 476         lis     r11,    GPIO0_SS_2_VAL@h
 477         ori     r11,r11,GPIO0_SS_2_VAL@l
 478         stw     r11,0(r10)
 479
 480         lis     r10,    STB_GPIO0_SS_3@h         /* sync select 3            */
 481         ori     r10,r10,STB_GPIO0_SS_3@l
 482         lis     r11,    GPIO0_SS_3_VAL@h
 483         ori     r11,r11,GPIO0_SS_3_VAL@l
 484         stw     r11,0(r10)
 485
 486         /*--------------------------------------------------------------------+
 487         |  Init Xilinx #1 Registers
 488         +--------------------------------------------------------------------*/
 489         lis     r10,    STB_XILINX1_REG0@h       /* init Xilinx1 Reg 0       */
 490         ori     r10,r10,STB_XILINX1_REG0@l
 491         li      r11,XILINX1_R0_VAL
 492         sth     r11,0(r10)
 493
 494         lis     r10,    STB_XILINX1_REG1@h       /* init Xilinx1 Reg 1       */
 495         ori     r10,r10,STB_XILINX1_REG1@l
 496         li      r11,XILINX1_R1_VAL
 497         sth     r11,0(r10)
 498
 499         lis     r10,    STB_XILINX1_REG2@h       /* init Xilinx1 Reg 2       */
 500         ori     r10,r10,STB_XILINX1_REG2@l
 501         li      r11,XILINX1_R2_VAL
 502         sth     r11,0(r10)
 503
 504         lis     r10,    STB_XILINX1_REG3@h       /* init Xilinx1 Reg 3       */
 505         ori     r10,r10,STB_XILINX1_REG3@l
 506         li      r11,XILINX1_R3_VAL
 507         sth     r11,0(r10)
 508
 509         lis     r10,    STB_XILINX1_REG4@h       /* init Xilinx1 Reg 4       */
 510         ori     r10,r10,STB_XILINX1_REG4@l
 511         li      r11,XILINX1_R4_VAL
 512         sth     r11,0(r10)
 513
 514         lis     r10,    STB_XILINX1_REG5@h       /* init Xilinx1 Reg 5       */
 515         ori     r10,r10,STB_XILINX1_REG5@l
 516         li      r11,XILINX1_R5_VAL
 517         sth     r11,0(r10)
 518
 519         lis     r10,    STB_XILINX1_REG6@h       /* init Xilinx1 Reg 6       */
 520         ori     r10,r10,STB_XILINX1_REG6@l
 521         li      r11,XILINX1_R6_VAL
 522         sth     r11,0(r10)
 523
 524         lis     r10,    STB_XILINX1_FLUSH@h      /* latch registers in Xilinx*/
 525         ori     r10,r10,STB_XILINX1_FLUSH@l
 526         li      r11,0x0000
 527         sth     r11,0(r10)
 528
 529         /*--------------------------------------------------------------------+
 530         |  Init Xilinx #2 Registers
 531         +--------------------------------------------------------------------*/
 532         lis     r10,    STB_XILINX2_REG0@h       /* init Xilinx2 Reg 0       */
 533         ori     r10,r10,STB_XILINX2_REG0@l
 534         li      r11,XILINX2_R0_VAL
 535         sth     r11,0(r10)
 536
 537         lis     r10,    STB_XILINX2_REG1@h       /* init Xilinx2 Reg 1       */
 538         ori     r10,r10,STB_XILINX2_REG1@l
 539         li      r11,XILINX2_R1_VAL
 540         sth     r11,0(r10)
 541
 542         lis     r10,    STB_XILINX2_REG2@h       /* init Xilinx2 Reg 2       */
 543         ori     r10,r10,STB_XILINX2_REG2@l
 544         li      r11,XILINX2_R2_VAL
 545         sth     r11,0(r10)
 546
 547         blr
 548         function_epilog(initb_config)
 549
 550
 551 /******************************************************************************
 552 |
 553 | Routine:    INITB_HSMC0.
 554 |
 555 | Purpose:    Initialize the HSMC0 Registers for SDRAM
 556 | Parameters: None.
 557 | Returns:    R3 =  0: Successful
 558 |                = -1: Unsuccessful, SDRAM did not reset properly.
 559 |
 560 ******************************************************************************/
 561         function_prolog(initb_hsmc0)
 562         mflr    r0                               /* Save return addr         */
 563
 564         /*--------------------------------------------------------------------+
 565         |  Set Global SDRAM Controller to recommended default
 566         +--------------------------------------------------------------------*/
 567         lis     r10,0x6C00
 568         ori     r10,r10,0x0000
 569         mtdcr   hsmc0_gr,r10
 570
 571         /*--------------------------------------------------------------------+
 572         |  Set HSMC0 Data Register to recommended default
 573         +--------------------------------------------------------------------*/
 574         lis     r10,0x0037
 575         ori     r10,r10,0x0000
 576         mtdcr   hsmc0_data,r10
 577
 578         /*--------------------------------------------------------------------+
 579         |  Init HSMC0 Bank Register 0
 580         +--------------------------------------------------------------------*/
 581         lis     r10,HSMC0_BR0_VAL@h
 582         ori     r10,r10,HSMC0_BR0_VAL@l
 583         mtdcr   hsmc0_br0,r10
 584
 585         /*--------------------------------------------------------------------+
 586         |  Init HSMC0 Bank Register 1
 587         +--------------------------------------------------------------------*/
 588         lis     r10,HSMC0_BR1_VAL@h
 589         ori     r10,r10,HSMC0_BR1_VAL@l
 590         mtdcr   hsmc0_br1,r10
 591
 592         /*--------------------------------------------------------------------+
 593         |  Set HSMC0 Control Reg 0
 594         +--------------------------------------------------------------------*/
 595         lis     r10,0x8077                       /* PRECHARGE ALL DEVICE BKS */
 596         ori     r10,r10,0x0000
 597         mtdcr   hsmc0_cr0,r10
 598         li      r3,0x0000
 599         bl      hsmc_cr_wait                     /* wait for op completion   */
 600         cmpwi   cr0,r3,0x0000
 601         bne     cr0,hsmc0_err
 602
 603         lis     r10,0x8078                       /* AUTO-REFRESH             */
 604         ori     r10,r10,0x0000
 605         mtdcr   hsmc0_cr0,r10
 606         li      r3,0x0000
 607         bl      hsmc_cr_wait                     /* wait for op completion   */
 608         cmpwi   cr0,r3,0x0000
 609         bne     cr0,hsmc0_err
 610
 611         lis     r10,0x8070                       /* PROG MODE W/DATA REG VAL */
 612         ori     r10,r10,0x8000
 613         mtdcr   hsmc0_cr0,r10
 614         li      r3,0x0000
 615         bl      hsmc_cr_wait                     /* wait for op completion   */
 616         cmpwi   cr0,r3,0x0000
 617         bne     hsmc0_err
 618
 619         /*--------------------------------------------------------------------+
 620         |  Set HSMC0 Control Reg 1
 621         +--------------------------------------------------------------------*/
 622         lis     r10,0x8077                       /* PRECHARGE ALL DEVICE BKS */
 623         ori     r10,r10,0x0000
 624         mtdcr   hsmc0_cr1,r10
 625         li      r3,0x0001
 626         bl      hsmc_cr_wait                     /* wait for op completion   */
 627         cmpwi   cr0,r3,0x0000
 628         bne     cr0,hsmc0_err
 629
 630         lis     r10,0x8078                       /* AUTO-REFRESH             */
 631         ori     r10,r10,0x0000
 632         mtdcr   hsmc0_cr1,r10
 633         li      r3,0x0001
 634         bl      hsmc_cr_wait                     /* wait for op completion   */
 635         cmpwi   cr0,r3,0x0000
 636         bne     cr0,hsmc0_err
 637
 638         lis     r10,0x8070                       /* PROG MODE W/DATA REG VAL */
 639         ori     r10,r10,0x8000
 640         mtdcr   hsmc0_cr1,r10
 641         li      r3,0x0001
 642         bl      hsmc_cr_wait                     /* wait for op completion   */
 643         cmpwi   cr0,r3,0x0000
 644         bne     cr0,hsmc0_err
 645
 646         /*--------------------------------------------------------------------+
 647         |  Set HSMC0 Refresh Register
 648         +--------------------------------------------------------------------*/
 649         lis     r10,0x0FE1
 650         ori     r10,r10,0x0000
 651         mtdcr   hsmc0_crr,r10
 652         li      r3,0
 653
 654 hsmc0_err:
 655         mtlr    r0
 656         blr
 657         function_epilog(initb_hsmc0)
 658
 659
 660 /******************************************************************************
 661 |
 662 | Routine:    INITB_HSMC1.
 663 |
 664 | Purpose:    Initialize the HSMC1 Registers for SDRAM
 665 | Parameters: None.
 666 | Returns:    R3 =  0: Successful
 667 |                = -1: Unsuccessful, SDRAM did not reset properly.
 668 |
 669 ******************************************************************************/
 670         function_prolog(initb_hsmc1)
 671         mflr    r0                               /* Save return addr         */
 672
 673         /*--------------------------------------------------------------------+
 674         |  Set Global SDRAM Controller to recommended default
 675         +--------------------------------------------------------------------*/
 676         lis     r10,0x6C00
 677         ori     r10,r10,0x0000
 678         mtdcr   hsmc1_gr,r10
 679
 680         /*--------------------------------------------------------------------+
 681         |  Set HSMC1 Data Register to recommended default
 682         +--------------------------------------------------------------------*/
 683         lis     r10,0x0037
 684         ori     r10,r10,0x0000
 685         mtdcr   hsmc1_data,r10
 686
 687         /*--------------------------------------------------------------------+
 688         |  Init HSMC1 Bank Register 0
 689         +--------------------------------------------------------------------*/
 690         lis     r10,HSMC1_BR0_VAL@h
 691         ori     r10,r10,HSMC1_BR0_VAL@l
 692         mtdcr   hsmc1_br0,r10
 693
 694         /*--------------------------------------------------------------------+
 695         |  Init HSMC1 Bank Register 1
 696         +--------------------------------------------------------------------*/
 697         lis     r10,HSMC1_BR1_VAL@h
 698         ori     r10,r10,HSMC1_BR1_VAL@l
 699         mtdcr   hsmc1_br1,r10
 700
 701         /*--------------------------------------------------------------------+
 702         |  Set HSMC1 Control Reg 0
 703         +--------------------------------------------------------------------*/
 704         lis     r10,0x8077                       /* PRECHARGE ALL DEVICE BANKS    */
 705         ori     r10,r10,0x0000
 706         mtdcr   hsmc1_cr0,r10
 707         li      r3,0x0002
 708         bl      hsmc_cr_wait                     /* wait for operation completion */
 709         cmpwi   cr0,r3,0x0000
 710         bne     hsmc1_err
 711
 712         lis     r10,0x8078                       /* AUTO-REFRESH                  */
 713         ori     r10,r10,0x0000
 714         mtdcr   hsmc1_cr0,r10
 715         li      r3,0x0002
 716         bl      hsmc_cr_wait                     /* wait for operation completion */
 717         cmpwi   cr0,r3,0x0000
 718         bne     hsmc1_err
 719
 720         lis     r10,0x8070                       /* PROGRAM MODE W/DATA REG VALUE */
 721         ori     r10,r10,0x8000
 722         mtdcr   hsmc1_cr0,r10
 723         li      r3,0x0002
 724         bl      hsmc_cr_wait                     /* wait for operation completion */
 725         cmpwi   cr0,r3,0x0000
 726         bne     hsmc1_err
 727
 728         /*--------------------------------------------------------------------+
 729         |  Set HSMC1 Control Reg 1
 730         +--------------------------------------------------------------------*/
 731         lis     r10,0x8077                       /* PRECHARGE ALL DEVICE BKS */
 732         ori     r10,r10,0x0000
 733         mtdcr   hsmc1_cr1,r10
 734         li      r3,0x0003
 735         bl      hsmc_cr_wait                     /* wait for op completion   */
 736         cmpwi   cr0,r3,0x0000
 737         bne     hsmc1_err
 738
 739         lis     r10,0x8078                       /* AUTO-REFRESH             */
 740         ori     r10,r10,0x0000
 741         mtdcr   hsmc1_cr1,r10
 742         li      r3,0x0003
 743         bl      hsmc_cr_wait                     /* wait for op completion   */
 744         cmpwi   cr0,r3,0x0000
 745         bne     hsmc1_err
 746
 747         lis     r10,0x8070                       /* PROG MODE W/DATA REG VAL */
 748         ori     r10,r10,0x8000
 749         mtdcr   hsmc1_cr1,r10
 750         li      r3,0x0003
 751         bl      hsmc_cr_wait                     /* wait for op completion   */
 752         cmpwi   cr0,r3,0x0000
 753         bne     hsmc1_err
 754
 755         /*--------------------------------------------------------------------+
 756         |  Set HSMC1 Refresh Register
 757         +--------------------------------------------------------------------*/
 758         lis     r10,0x0FE1
 759         ori     r10,r10,0x0000
 760         mtdcr   hsmc1_crr,r10
 761         xor     r3,r3,r3
 762
 763 hsmc1_err:
 764         mtlr    r0
 765         blr
 766         function_epilog(initb_hsmc1)
 767
 768
 769 /******************************************************************************
 770 |
 771 | Routine:    INITB_CACHE
 772 |
 773 | Purpose:    This routine will enable Data and Instruction Cache.
 774 |             The Data Cache is an 8K two-way set associative and the
 775 |             Instruction Cache is an 16K two-way set associative cache.
 776 |
 777 | Parameters: None.
 778 |
 779 | Returns:    None.
 780 |
 781 ******************************************************************************/
 782         function_prolog(initb_cache)
 783         mflr    r0                               /* Save return addr         */
 784
 785         bl      initb_Dcache                     /* enable D-Cache           */
 786         bl      initb_Icache                     /* enable I-Cache           */
 787
 788         mtlr    r0
 789         blr
 790        function_epilog(initb_cache)
 791
 792
 793 /******************************************************************************
 794 |
 795 | Routine:    INITB_DCACHE
 796 |
 797 | Purpose:    This routine will invalidate all data in the Data Cache and
 798 |             then enable D-Cache.  If cache is enabled already, the D-Cache
 799 |             will be flushed before the data is invalidated.
 800 |
 801 | Parameters: None.
 802 |
 803 | Returns:    None.
 804 |
 805 ******************************************************************************/
 806         function_prolog(initb_Dcache)
 807         /*--------------------------------------------------------------------+
 808         |  Flush Data Cache if enabled
 809         +--------------------------------------------------------------------*/
 810         mfdccr  r10                              /* r10 <- DCCR              */
 811         isync                                    /* ensure prev insts done   */
 812         cmpwi   r10,0x00
 813         beq     ic_dcinv                         /* D-cache off, invalidate  */
 814
 815         /*--------------------------------------------------------------------+
 816         |  Data Cache enabled, force known memory addresses to be Cached
 817         +--------------------------------------------------------------------*/
 818         lis     r10,HSMC0_BR0_VAL@h              /* r10 <- first memory loc  */
 819         andis.  r10,r10,0xFFF0
 820         li      r11,DCACHE_NLINES                /* r11 <- # A-way addresses */
 821         addi    r11,r11,DCACHE_NLINES            /* r11 <- # B-way addresses */
 822         mtctr   r11                              /* set loop counter         */
 823
 824 ic_dcload:
 825         lwz     r12,0(r10)                       /* force cache of address   */
 826         addi    r10,r10,DCACHE_NBYTES            /* r10 <- next memory loc   */
 827         bdnz    ic_dcload
 828         sync                                     /* ensure prev insts done   */
 829         isync
 830
 831         /*--------------------------------------------------------------------+
 832         |  Flush the known memory addresses from Cache
 833         +--------------------------------------------------------------------*/
 834         lis     r10,HSMC0_BR0_VAL@h              /* r10 <- first memory loc  */
 835         andis.  r10,r10,0xFFF0
 836         mtctr   r11                              /* set loop counter         */
 837
 838 ic_dcflush:
 839         dcbf    0,r10                            /* flush D-cache line       */
 840         addi    r10,r10,DCACHE_NBYTES            /* r10 <- next memory loc   */
 841         bdnz    ic_dcflush
 842         sync                                     /* ensure prev insts done   */
 843         isync
 844
 845         /*--------------------------------------------------------------------+
 846         |  Disable then invalidate Data Cache
 847         +--------------------------------------------------------------------*/
 848         li      r10,0                            /* r10 <- 0                 */
 849         mtdccr  r10                              /* disable the D-Cache      */
 850         isync                                    /* ensure prev insts done   */
 851
 852 ic_dcinv:
 853         li      r10,0                            /* r10 <- line address      */
 854         li      r11,DCACHE_NLINES                /* r11 <- # lines in cache  */
 855         mtctr   r11                              /* set loop counter         */
 856
 857 ic_dcloop:
 858         dccci   0,r10                            /* invalidate A/B cache lns */
 859         addi    r10,r10,DCACHE_NBYTES            /* bump to next line        */
 860         bdnz    ic_dcloop
 861         sync                                     /* ensure prev insts done   */
 862         isync
 863
 864         /*--------------------------------------------------------------------+
 865         |  Enable Data Cache
 866         +--------------------------------------------------------------------*/
 867         lis     r10,DCACHE_ENABLE@h              /* r10 <- D-cache enable msk*/
 868         ori     r10,r10,DCACHE_ENABLE@l
 869         mtdccr  r10
 870         sync                                     /* ensure prev insts done   */
 871         isync
 872
 873         blr
 874         function_epilog(initb_Dcache)
 875
 876
 877 /******************************************************************************
 878 |
 879 | Routine:    INITB_ICACHE
 880 |
 881 | Purpose:    This routine will invalidate all data in the Instruction
 882 |             Cache then enable I-Cache.
 883 |
 884 | Parameters: None.
 885 |
 886 | Returns:    None.
 887 |
 888 ******************************************************************************/
 889         function_prolog(initb_Icache)
 890         /*--------------------------------------------------------------------+
 891         |  Invalidate Instruction Cache
 892         +--------------------------------------------------------------------*/
 893         li      r10,0                            /* r10 <- lines address     */
 894         iccci   0,r10                            /* invalidate all I-cache   */
 895         sync                                     /* ensure prev insts done   */
 896         isync
 897
 898         /*--------------------------------------------------------------------+
 899         |  Enable Instruction Cache
 900         +--------------------------------------------------------------------*/
 901         lis     r10,ICACHE_ENABLE@h              /* r10 <- I-cache enable msk*/
 902         ori     r10,r10,ICACHE_ENABLE@l
 903         mticcr  r10
 904         sync                                     /* ensure prev insts done   */
 905         isync
 906
 907         blr
 908         function_epilog(initb_Icache)
 909
 910 #if 0
 911 /******************************************************************************
 912 |
 913 | Routine:    INITB_GET_CSPD
 914 |
 915 | Purpose:    Determine the CPU Core Speed.  The 13.5 Mhz Time Base
 916 |             Counter (TBC) is used to measure a conditional branch
 917 |             instruction.
 918 |
 919 | Parameters: R3 = Address of Bus Speed
 920 |             R4 = Address of Core Speed
 921 |
 922 | Returns:    (R3) = >0: Bus Speed.
 923 |                     0: Bus Speed not found in Look-Up Table.
 924 |             (R4) = >0: Core Speed.
 925 |                     0: Core Speed not found in Look-Up Table.
 926 |
 927 | Note:       1. This routine assumes the bdnz branch instruction takes
 928 |                two instruction cycles to complete.
 929 |             2. This routine must be called before interrupts are enabled.
 930 |
 931 ******************************************************************************/
 932         function_prolog(initb_get_cspd)
 933         mflr    r0                               /* Save return address      */
 934         /*--------------------------------------------------------------------+
 935         |  Set-up timed loop
 936         +--------------------------------------------------------------------*/
 937         lis     r9,gcs_time_loop@h               /* r9  <- addr loop instr   */
 938         ori     r9,r9,gcs_time_loop@l
 939         lis     r10,GCS_LCNT@h                   /* r10 <- loop count        */
 940         ori     r10,r10,GCS_LCNT@l
 941         mtctr   r10                              /* ctr <- loop count        */
 942         lis     r11,STB_TIMERS_TBC@h             /* r11 <- TBC register addr */
 943         ori     r11,r11,STB_TIMERS_TBC@l
 944         li      r12,0                            /* r12 <- 0                 */
 945
 946         /*--------------------------------------------------------------------+
 947         |  Cache timed-loop instruction
 948         +--------------------------------------------------------------------*/
 949         icbt    0,r9
 950         sync
 951         isync
 952
 953         /*--------------------------------------------------------------------+
 954         |  Get number of 13.5 Mhz cycles to execute time-loop
 955         +--------------------------------------------------------------------*/
 956         stw     r12,0(r11)                       /* reset TBC                */
 957 gcs_time_loop:
 958         bdnz+   gcs_time_loop                    /* force branch pred taken  */
 959         lwz     r5,0(r11)                        /* r5 <- num 13.5 Mhz ticks */
 960         li      r6,5                             /* LUT based on 1/5th the...*/
 961         divw    r5,r5,r6                         /*..loop count used         */
 962         sync
 963         isync
 964
 965         /*--------------------------------------------------------------------+
 966         |  Look-up core speed based on TBC value
 967         +--------------------------------------------------------------------*/
 968         lis     r6,gcs_lookup_table@h            /* r6 <- pts at core spd LUT*/
 969         ori     r6,r6,gcs_lookup_table@l
 970         bl      gcs_cspd_lookup                  /* find core speed in LUT   */
 971
 972         mtlr    r0                               /* set return address       */
 973         blr
 974         function_epilog(initb_get_cspd)
 975
 976 #endif
 977 /*****************************************************************************+
 978 | XXXX   XX   XX   XXXXXX  XXXXXXX  XXXXXX   XX   XX     XX    XXXX
 979 |  XX    XXX  XX   X XX X   XX   X   XX  XX  XXX  XX    XXXX    XX
 980 |  XX    XXXX XX     XX     XX X     XX  XX  XXXX XX   XX  XX   XX
 981 |  XX    XX XXXX     XX     XXXX     XXXXX   XX XXXX   XX  XX   XX
 982 |  XX    XX  XXX     XX     XX X     XX XX   XX  XXX   XXXXXX   XX
 983 |  XX    XX   XX     XX     XX   X   XX  XX  XX   XX   XX  XX   XX  XX
 984 | XXXX   XX   XX    XXXX   XXXXXXX  XXX  XX  XX   XX   XX  XX  XXXXXXX
 985 +*****************************************************************************/
 986 /******************************************************************************
 987 |
 988 | Routine:    HSMC_CR_WAIT
 989 |
 990 | Purpose:    Wait for the HSMC Control Register (bits 12-16) to be reset
 991 |             after an auto-refresh, pre-charge or program mode register
 992 |             command execution.
 993 |
 994 | Parameters: R3 = HSMC Control Register ID.
 995 |                  0: HSMC0 CR0
 996 |                  1: HSMC0 CR1
 997 |                  2: HSMC1 CR0
 998 |                  3: HSMC1 CR1
 999 |
1000 | Returns:    R3 = 0: Successful
1001 |                 -1: Unsuccessful
1002 |
1003 ******************************************************************************/
1004 hsmc_cr_wait:
1005
1006         li      r11,10                           /* r11 <- retry counter     */
1007         mtctr   r11                              /* set retry counter        */
1008         mr      r11,r3                           /* r11 <- HSMC CR reg id    */
1009
1010 hsmc_cr_rep:
1011         bdz     hsmc_cr_err                      /* branch if max retries hit*/
1012
1013         /*--------------------------------------------------------------------+
1014         |  GET HSMCx_CRx value based on HSMC Control Register ID
1015         +--------------------------------------------------------------------*/
1016 try_hsmc0_cr0:                                   /* CHECK IF ID=HSMC0 CR0 REG*/
1017         cmpwi   cr0,r11,0x0000
1018         bne     cr0,try_hsmc0_cr1
1019         mfdcr   r10,hsmc0_cr0                    /* r11 <- HSMC0 CR0 value   */
1020         b       hsmc_cr_read
1021
1022 try_hsmc0_cr1:                                   /* CHECK IF ID=HSMC0 CR1 REG*/
1023         cmpwi   cr0,r11,0x0001
1024         bne     cr0,try_hsmc1_cr0
1025         mfdcr   r10,hsmc0_cr1                    /* r10 <- HSMC0 CR1 value   */
1026         b       hsmc_cr_read
1027
1028 try_hsmc1_cr0:                                   /* CHECK IF ID=HSMC1 CR0 REG*/
1029         cmpwi   cr0,r11,0x0002
1030         bne     cr0,try_hsmc1_cr1
1031         mfdcr   r10,hsmc1_cr0                    /* r10 <- HSMC1 CR0 value   */
1032         b       hsmc_cr_read
1033
1034 try_hsmc1_cr1:                                   /* CHECK IF ID=HSMC1 CR1 REG*/
1035         cmpwi   cr0,r11,0x0003
1036         bne     cr0,hsmc_cr_err
1037         mfdcr   r10,hsmc1_cr1                    /* r10 <- HSMC1 CR1 value   */
1038
1039         /*--------------------------------------------------------------------+
1040         |  Check if HSMC CR register was reset after command execution
1041         +--------------------------------------------------------------------*/
1042 hsmc_cr_read:
1043         lis     r12,0x000F                       /* create "AND" mask        */
1044         ori     r12,r12,0x8000
1045         and.    r10,r10,r12                      /* r10 <- HSMC CR bits 12-16*/
1046         bne     cr0,hsmc_cr_rep                  /* wait for bits to reset   */
1047         li      r3,0                             /* set return code = success*/
1048         b       hsmc_cr_done
1049
1050 hsmc_cr_err:                                     /* ERROR: SDRAM didn't reset*/
1051         li      r3,-1                            /* set RC=unsuccessful      */
1052
1053 hsmc_cr_done:
1054         blr
1055
1056 #if 0
1057 /******************************************************************************
1058 |
1059 | Routine:    GCS_CSPD_LOOKUP
1060 |
1061 | Purpose:    Uses the number of 13.5 Mhz clock ticks found after executing
1062 |             the branch instruction time loop to look-up the CPU Core Speed
1063 |             in the Core Speed Look-up Table.
1064 |
1065 | Parameters: R3 = Address of Bus Speed
1066 |             R4 = Address of Core Speed
1067 |             R5 = Number of 13.5 Mhz clock ticks found in time loop.
1068 |             R6 = Pointer to Core-Speed Look-Up Table
1069 |
1070 | Returns:    (R3) = >0: Bus Speed.
1071 |                     0: Bus Speed not found in Look-Up Table.
1072 |             (R4) = >0: Core Speed.
1073 |                     0: Core Speed not found in Look-Up Table.
1074 |
1075 | Note:       Core Speed = Bus Speed * Mult Factor (1-4x).
1076 |
1077 ******************************************************************************/
1078 gcs_cspd_lookup:
1079
1080         li      r9,1                             /* r9 <- core speed mult    */
1081         /*--------------------------------------------------------------------+
1082         |  Get theoritical number 13.5 Mhz ticks for a given Bus Speed from
1083         |  Look-up Table.  Check all mult factors to determine if calculated
1084         |  value matches theoretical value (within a tolerance).
1085         +--------------------------------------------------------------------*/
1086 gcs_cspd_loop:
1087         lwz     r10,0(r6)                        /* r10 <- no. ticks from LUT*/
1088         divw    r10,r10,r9                       /* r10 <- div mult (1-4x)   */
1089         subi    r11,r10,GCS_CTICK_TOL            /* r11 <- no. tks low range */
1090         addi    r12,r10,GCS_CTICK_TOL            /* r12 <- no. tks high range*/
1091
1092         cmpw    cr0,r5,r11                       /* calc value within range? */
1093         blt     gcs_cspd_retry                   /* less than low range      */
1094         cmpw    cr0,r5,r12
1095         bgt     gcs_cspd_retry                   /* greater than high range  */
1096         b       gcs_cspd_fnd                     /* calc value within range  */
1097
1098         /*--------------------------------------------------------------------+
1099         |  SO FAR CORE SPEED NOT FOUND: Check next mult factor
1100         +--------------------------------------------------------------------*/
1101 gcs_cspd_retry:
1102         addi    r9,r9,1                          /* bump mult factor (1-4x)  */
1103         cmpwi   cr0,r9,GCS_NMULT
1104         ble     gcs_cspd_loop
1105
1106         /*--------------------------------------------------------------------+
1107         |  SO FAR CORE SPEED NOT FOUND: Point at next Bus Speed in LUT
1108         +--------------------------------------------------------------------*/
1109         li      r9,1                             /* reset mult factor        */
1110         addi    r6,r6,GCS_TROW_BYTES             /* point at next table entry*/
1111         lwz     r10,0(r6)
1112         cmpwi   cr0,r10,0                        /* check for EOT flag       */
1113         bne     gcs_cspd_loop
1114
1115         /*--------------------------------------------------------------------+
1116         |  COMPUTE CORE SPEED AND GET BUS SPEED FROM LOOK-UP TABLE
1117         +--------------------------------------------------------------------*/
1118 gcs_cspd_fnd:
1119         lwz     r5,4(r6)                         /*  r5  <- Bus Speed in LUT */
1120         mullw   r6,r5,r9                         /*  r6  <- Core speed       */
1121         stw     r5,0(r3)                         /* (r3) <- Bus Speed        */
1122         stw     r6,0(r4)                         /* (r4) <- Core Speed       */
1123
1124         blr
1125 #endif