IB/ipath: Include <linux/vmalloc.h> to fix ppc64 build
[linux-2.6] / drivers / infiniband / hw / ipath / ipath_iba6110.c
1 /*
2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4  *
5  * This software is available to you under a choice of one of two
6  * licenses.  You may choose to be licensed under the terms of the GNU
7  * General Public License (GPL) Version 2, available from the file
8  * COPYING in the main directory of this source tree, or the
9  * OpenIB.org BSD license below:
10  *
11  *     Redistribution and use in source and binary forms, with or
12  *     without modification, are permitted provided that the following
13  *     conditions are met:
14  *
15  *      - Redistributions of source code must retain the above
16  *        copyright notice, this list of conditions and the following
17  *        disclaimer.
18  *
19  *      - Redistributions in binary form must reproduce the above
20  *        copyright notice, this list of conditions and the following
21  *        disclaimer in the documentation and/or other materials
22  *        provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  */
33
34 /*
35  * This file contains all of the code that is specific to the InfiniPath
36  * HT chip.
37  */
38
39 #include <linux/vmalloc.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/htirq.h>
43
44 #include "ipath_kernel.h"
45 #include "ipath_registers.h"
46
47 static void ipath_setup_ht_setextled(struct ipath_devdata *, u64, u64);
48
49
50 /*
51  * This lists the InfiniPath registers, in the actual chip layout.
52  * This structure should never be directly accessed.
53  *
54  * The names are in InterCap form because they're taken straight from
55  * the chip specification.  Since they're only used in this file, they
56  * don't pollute the rest of the source.
57 */
58
59 struct _infinipath_do_not_use_kernel_regs {
60         unsigned long long Revision;
61         unsigned long long Control;
62         unsigned long long PageAlign;
63         unsigned long long PortCnt;
64         unsigned long long DebugPortSelect;
65         unsigned long long DebugPort;
66         unsigned long long SendRegBase;
67         unsigned long long UserRegBase;
68         unsigned long long CounterRegBase;
69         unsigned long long Scratch;
70         unsigned long long ReservedMisc1;
71         unsigned long long InterruptConfig;
72         unsigned long long IntBlocked;
73         unsigned long long IntMask;
74         unsigned long long IntStatus;
75         unsigned long long IntClear;
76         unsigned long long ErrorMask;
77         unsigned long long ErrorStatus;
78         unsigned long long ErrorClear;
79         unsigned long long HwErrMask;
80         unsigned long long HwErrStatus;
81         unsigned long long HwErrClear;
82         unsigned long long HwDiagCtrl;
83         unsigned long long MDIO;
84         unsigned long long IBCStatus;
85         unsigned long long IBCCtrl;
86         unsigned long long ExtStatus;
87         unsigned long long ExtCtrl;
88         unsigned long long GPIOOut;
89         unsigned long long GPIOMask;
90         unsigned long long GPIOStatus;
91         unsigned long long GPIOClear;
92         unsigned long long RcvCtrl;
93         unsigned long long RcvBTHQP;
94         unsigned long long RcvHdrSize;
95         unsigned long long RcvHdrCnt;
96         unsigned long long RcvHdrEntSize;
97         unsigned long long RcvTIDBase;
98         unsigned long long RcvTIDCnt;
99         unsigned long long RcvEgrBase;
100         unsigned long long RcvEgrCnt;
101         unsigned long long RcvBufBase;
102         unsigned long long RcvBufSize;
103         unsigned long long RxIntMemBase;
104         unsigned long long RxIntMemSize;
105         unsigned long long RcvPartitionKey;
106         unsigned long long ReservedRcv[10];
107         unsigned long long SendCtrl;
108         unsigned long long SendPIOBufBase;
109         unsigned long long SendPIOSize;
110         unsigned long long SendPIOBufCnt;
111         unsigned long long SendPIOAvailAddr;
112         unsigned long long TxIntMemBase;
113         unsigned long long TxIntMemSize;
114         unsigned long long ReservedSend[9];
115         unsigned long long SendBufferError;
116         unsigned long long SendBufferErrorCONT1;
117         unsigned long long SendBufferErrorCONT2;
118         unsigned long long SendBufferErrorCONT3;
119         unsigned long long ReservedSBE[4];
120         unsigned long long RcvHdrAddr0;
121         unsigned long long RcvHdrAddr1;
122         unsigned long long RcvHdrAddr2;
123         unsigned long long RcvHdrAddr3;
124         unsigned long long RcvHdrAddr4;
125         unsigned long long RcvHdrAddr5;
126         unsigned long long RcvHdrAddr6;
127         unsigned long long RcvHdrAddr7;
128         unsigned long long RcvHdrAddr8;
129         unsigned long long ReservedRHA[7];
130         unsigned long long RcvHdrTailAddr0;
131         unsigned long long RcvHdrTailAddr1;
132         unsigned long long RcvHdrTailAddr2;
133         unsigned long long RcvHdrTailAddr3;
134         unsigned long long RcvHdrTailAddr4;
135         unsigned long long RcvHdrTailAddr5;
136         unsigned long long RcvHdrTailAddr6;
137         unsigned long long RcvHdrTailAddr7;
138         unsigned long long RcvHdrTailAddr8;
139         unsigned long long ReservedRHTA[7];
140         unsigned long long Sync;        /* Software only */
141         unsigned long long Dump;        /* Software only */
142         unsigned long long SimVer;      /* Software only */
143         unsigned long long ReservedSW[5];
144         unsigned long long SerdesConfig0;
145         unsigned long long SerdesConfig1;
146         unsigned long long SerdesStatus;
147         unsigned long long XGXSConfig;
148         unsigned long long ReservedSW2[4];
149 };
150
151 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
152     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
153 #define IPATH_CREG_OFFSET(field) (offsetof( \
154     struct infinipath_counters, field) / sizeof(u64))
155
156 static const struct ipath_kregs ipath_ht_kregs = {
157         .kr_control = IPATH_KREG_OFFSET(Control),
158         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
159         .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
160         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
161         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
162         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
163         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
164         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
165         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
166         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
167         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
168         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
169         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
170         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
171         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
172         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
173         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
174         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
175         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
176         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
177         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
178         .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
179         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
180         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
181         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
182         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
183         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
184         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
185         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
186         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
187         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
188         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
189         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
190         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
191         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
192         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
193         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
194         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
195         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
196         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
197         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
198         .kr_revision = IPATH_KREG_OFFSET(Revision),
199         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
200         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
201         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
202         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
203         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
204         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
205         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
206         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
207         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
208         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
209         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
210         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
211         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
212         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
213         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
214         /*
215          * These should not be used directly via ipath_write_kreg64(),
216          * use them with ipath_write_kreg64_port(),
217          */
218         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
219         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
220 };
221
222 static const struct ipath_cregs ipath_ht_cregs = {
223         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
224         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
225         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
226         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
227         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
228         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
229         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
230         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
231         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
232         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
233         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
234         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
235         /* calc from Reg_CounterRegBase + offset */
236         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
237         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
238         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
239         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
240         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
241         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
242         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
243         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
244         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
245         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
246         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
247         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
248         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
249         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
250         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
251         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
252         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
253         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
254         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
255         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
256         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
257 };
258
259 /* kr_intstatus, kr_intclear, kr_intmask bits */
260 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
261 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
262
263 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
264 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
265 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
266 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR   0x0000000000800000ULL
267 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR   0x0000000001000000ULL
268 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR   0x0000000002000000ULL
269 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR   0x0000000004000000ULL
270 #define INFINIPATH_HWE_HTCMISCERR4          0x0000000008000000ULL
271 #define INFINIPATH_HWE_HTCMISCERR5          0x0000000010000000ULL
272 #define INFINIPATH_HWE_HTCMISCERR6          0x0000000020000000ULL
273 #define INFINIPATH_HWE_HTCMISCERR7          0x0000000040000000ULL
274 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR  0x0000000080000000ULL
275 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
276 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR  0x0000000200000000ULL
277 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
278 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
279 #define INFINIPATH_HWE_HTBPLL_FBSLIP        0x0200000000000000ULL
280 #define INFINIPATH_HWE_HTBPLL_RFSLIP        0x0400000000000000ULL
281 #define INFINIPATH_HWE_HTAPLL_FBSLIP        0x0800000000000000ULL
282 #define INFINIPATH_HWE_HTAPLL_RFSLIP        0x1000000000000000ULL
283 #define INFINIPATH_HWE_SERDESPLLFAILED      0x2000000000000000ULL
284
285 /* kr_extstatus bits */
286 #define INFINIPATH_EXTS_FREQSEL 0x2
287 #define INFINIPATH_EXTS_SERDESSEL 0x4
288 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
289 #define INFINIPATH_EXTS_MEMBIST_CORRECT     0x0000000000008000
290
291
292 /* TID entries (memory), HT-only */
293 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
294 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
295 #define INFINIPATH_RT_ADDR_SHIFT 0
296 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFFULL
297 #define INFINIPATH_RT_BUFSIZE_SHIFT 48
298
299 /*
300  * masks and bits that are different in different chips, or present only
301  * in one
302  */
303 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
304     INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
305 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
306     INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
307
308 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
309     INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
310 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
311     INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
312 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
313     INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
314 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
315     INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
316
317 #define _IPATH_GPIO_SDA_NUM 1
318 #define _IPATH_GPIO_SCL_NUM 0
319
320 #define IPATH_GPIO_SDA \
321         (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
322 #define IPATH_GPIO_SCL \
323         (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
324
325 /* keep the code below somewhat more readonable; not used elsewhere */
326 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
327                                 infinipath_hwe_htclnkabyte1crcerr)
328 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr |     \
329                                 infinipath_hwe_htclnkbbyte1crcerr)
330 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
331                                 infinipath_hwe_htclnkbbyte0crcerr)
332 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr |     \
333                                 infinipath_hwe_htclnkbbyte1crcerr)
334
335 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
336                           char *msg, size_t msgl)
337 {
338         char bitsmsg[64];
339         ipath_err_t crcbits = hwerrs &
340                 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
341         /* don't check if 8bit HT */
342         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
343                 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
344         /* don't check if 8bit HT */
345         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
346                 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
347         /*
348          * we'll want to ignore link errors on link that is
349          * not in use, if any.  For now, complain about both
350          */
351         if (crcbits) {
352                 u16 ctrl0, ctrl1;
353                 snprintf(bitsmsg, sizeof bitsmsg,
354                          "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
355                          !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
356                          "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
357                                     ? "1 (B)" : "0+1 (A+B)"),
358                          !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
359                          : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
360                             "0+1"), (unsigned long long) crcbits);
361                 strlcat(msg, bitsmsg, msgl);
362
363                 /*
364                  * print extra info for debugging.  slave/primary
365                  * config word 4, 8 (link control 0, 1)
366                  */
367
368                 if (pci_read_config_word(dd->pcidev,
369                                          dd->ipath_ht_slave_off + 0x4,
370                                          &ctrl0))
371                         dev_info(&dd->pcidev->dev, "Couldn't read "
372                                  "linkctrl0 of slave/primary "
373                                  "config block\n");
374                 else if (!(ctrl0 & 1 << 6))
375                         /* not if EOC bit set */
376                         ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
377                                   ((ctrl0 >> 8) & 7) ? " CRC" : "",
378                                   ((ctrl0 >> 4) & 1) ? "linkfail" :
379                                   "");
380                 if (pci_read_config_word(dd->pcidev,
381                                          dd->ipath_ht_slave_off + 0x8,
382                                          &ctrl1))
383                         dev_info(&dd->pcidev->dev, "Couldn't read "
384                                  "linkctrl1 of slave/primary "
385                                  "config block\n");
386                 else if (!(ctrl1 & 1 << 6))
387                         /* not if EOC bit set */
388                         ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
389                                   ((ctrl1 >> 8) & 7) ? " CRC" : "",
390                                   ((ctrl1 >> 4) & 1) ? "linkfail" :
391                                   "");
392
393                 /* disable until driver reloaded */
394                 dd->ipath_hwerrmask &= ~crcbits;
395                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
396                                  dd->ipath_hwerrmask);
397                 ipath_dbg("HT crc errs: %s\n", msg);
398         } else
399                 ipath_dbg("ignoring HT crc errors 0x%llx, "
400                           "not in use\n", (unsigned long long)
401                           (hwerrs & (_IPATH_HTLINK0_CRCBITS |
402                                      _IPATH_HTLINK1_CRCBITS)));
403 }
404
405 /* 6110 specific hardware errors... */
406 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
407         INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
408         INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
409         INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
410         INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
411         INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
412         INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
413         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
414         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
415 };
416
417 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
418                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
419                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
420 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
421                           << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
422
423 static int ipath_ht_txe_recover(struct ipath_devdata *);
424
425 /**
426  * ipath_ht_handle_hwerrors - display hardware errors.
427  * @dd: the infinipath device
428  * @msg: the output buffer
429  * @msgl: the size of the output buffer
430  *
431  * Use same msg buffer as regular errors to avoid excessive stack
432  * use.  Most hardware errors are catastrophic, but for right now,
433  * we'll print them and continue.  We reuse the same message buffer as
434  * ipath_handle_errors() to avoid excessive stack usage.
435  */
436 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
437                                      size_t msgl)
438 {
439         ipath_err_t hwerrs;
440         u32 bits, ctrl;
441         int isfatal = 0;
442         char bitsmsg[64];
443
444         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
445
446         if (!hwerrs) {
447                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
448                 /*
449                  * better than printing cofusing messages
450                  * This seems to be related to clearing the crc error, or
451                  * the pll error during init.
452                  */
453                 goto bail;
454         } else if (hwerrs == -1LL) {
455                 ipath_dev_err(dd, "Read of hardware error status failed "
456                               "(all bits set); ignoring\n");
457                 goto bail;
458         }
459         ipath_stats.sps_hwerrs++;
460
461         /* Always clear the error status register, except MEMBISTFAIL,
462          * regardless of whether we continue or stop using the chip.
463          * We want that set so we know it failed, even across driver reload.
464          * We'll still ignore it in the hwerrmask.  We do this partly for
465          * diagnostics, but also for support */
466         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
467                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
468
469         hwerrs &= dd->ipath_hwerrmask;
470
471         /*
472          * make sure we get this much out, unless told to be quiet,
473          * it's a parity error we may recover from,
474          * or it's occurred within the last 5 seconds
475          */
476         if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
477                 RXE_EAGER_PARITY)) ||
478                 (ipath_debug & __IPATH_VERBDBG))
479                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
480                          "(cleared)\n", (unsigned long long) hwerrs);
481         dd->ipath_lasthwerror |= hwerrs;
482
483         if (hwerrs & ~dd->ipath_hwe_bitsextant)
484                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
485                               "%llx set\n", (unsigned long long)
486                               (hwerrs & ~dd->ipath_hwe_bitsextant));
487
488         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
489         if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
490                 /*
491                  * parity errors in send memory are recoverable,
492                  * just cancel the send (if indicated in * sendbuffererror),
493                  * count the occurrence, unfreeze (if no other handled
494                  * hardware error bits are set), and continue. They can
495                  * occur if a processor speculative read is done to the PIO
496                  * buffer while we are sending a packet, for example.
497                  */
498                 if ((hwerrs & TXE_PIO_PARITY) && ipath_ht_txe_recover(dd))
499                         hwerrs &= ~TXE_PIO_PARITY;
500                 if (hwerrs & RXE_EAGER_PARITY)
501                         ipath_dev_err(dd, "RXE parity, Eager TID error is not "
502                                 "recoverable\n");
503                 if (!hwerrs) {
504                         ipath_dbg("Clearing freezemode on ignored or "
505                                   "recovered hardware error\n");
506                         ctrl &= ~INFINIPATH_C_FREEZEMODE;
507                         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
508                                          ctrl);
509                 }
510         }
511
512         *msg = '\0';
513
514         /*
515          * may someday want to decode into which bits are which
516          * functional area for parity errors, etc.
517          */
518         if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
519                       << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
520                 bits = (u32) ((hwerrs >>
521                                INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
522                               INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
523                 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
524                          bits);
525                 strlcat(msg, bitsmsg, msgl);
526         }
527
528         ipath_format_hwerrors(hwerrs,
529                               ipath_6110_hwerror_msgs,
530                               sizeof(ipath_6110_hwerror_msgs) /
531                               sizeof(ipath_6110_hwerror_msgs[0]),
532                               msg, msgl);
533
534         if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
535                 hwerr_crcbits(dd, hwerrs, msg, msgl);
536
537         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
538                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
539                         msgl);
540                 /* ignore from now on, so disable until driver reloaded */
541                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
542                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
543                                  dd->ipath_hwerrmask);
544         }
545 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
546                          INFINIPATH_HWE_COREPLL_RFSLIP |        \
547                          INFINIPATH_HWE_HTBPLL_FBSLIP |         \
548                          INFINIPATH_HWE_HTBPLL_RFSLIP |         \
549                          INFINIPATH_HWE_HTAPLL_FBSLIP |         \
550                          INFINIPATH_HWE_HTAPLL_RFSLIP)
551
552         if (hwerrs & _IPATH_PLL_FAIL) {
553                 snprintf(bitsmsg, sizeof bitsmsg,
554                          "[PLL failed (%llx), InfiniPath hardware unusable]",
555                          (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
556                 strlcat(msg, bitsmsg, msgl);
557                 /* ignore from now on, so disable until driver reloaded */
558                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
559                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
560                                  dd->ipath_hwerrmask);
561         }
562
563         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
564                 /*
565                  * If it occurs, it is left masked since the eternal
566                  * interface is unused
567                  */
568                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
569                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
570                                  dd->ipath_hwerrmask);
571         }
572
573         if (hwerrs) {
574                 /*
575                  * if any set that we aren't ignoring; only
576                  * make the complaint once, in case it's stuck
577                  * or recurring, and we get here multiple
578                  * times.
579                  * force link down, so switch knows, and
580                  * LEDs are turned off
581                  */
582                 if (dd->ipath_flags & IPATH_INITTED) {
583                         ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
584                         ipath_setup_ht_setextled(dd,
585                                 INFINIPATH_IBCS_L_STATE_DOWN,
586                                 INFINIPATH_IBCS_LT_STATE_DISABLED);
587                         ipath_dev_err(dd, "Fatal Hardware Error (freeze "
588                                           "mode), no longer usable, SN %.16s\n",
589                                           dd->ipath_serial);
590                         isfatal = 1;
591                 }
592                 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
593                 /* mark as having had error */
594                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
595                 /*
596                  * mark as not usable, at a minimum until driver
597                  * is reloaded, probably until reboot, since no
598                  * other reset is possible.
599                  */
600                 dd->ipath_flags &= ~IPATH_INITTED;
601         }
602         else
603                 *msg = 0; /* recovered from all of them */
604         if (*msg)
605                 ipath_dev_err(dd, "%s hardware error\n", msg);
606         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
607                 /*
608                  * for status file; if no trailing brace is copied,
609                  * we'll know it was truncated.
610                  */
611                 snprintf(dd->ipath_freezemsg,
612                          dd->ipath_freezelen, "{%s}", msg);
613
614 bail:;
615 }
616
617 /**
618  * ipath_ht_boardname - fill in the board name
619  * @dd: the infinipath device
620  * @name: the output buffer
621  * @namelen: the size of the output buffer
622  *
623  * fill in the board name, based on the board revision register
624  */
625 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
626                               size_t namelen)
627 {
628         char *n = NULL;
629         u8 boardrev = dd->ipath_boardrev;
630         int ret;
631
632         switch (boardrev) {
633         case 4:         /* Ponderosa is one of the bringup boards */
634                 n = "Ponderosa";
635                 break;
636         case 5:
637                 /*
638                  * original production board; two production levels, with
639                  * different serial number ranges.   See ipath_ht_early_init() for
640                  * case where we enable IPATH_GPIO_INTR for later serial # range.
641                  */
642                 n = "InfiniPath_QHT7040";
643                 break;
644         case 6:
645                 n = "OEM_Board_3";
646                 break;
647         case 7:
648                 /* small form factor production board */
649                 n = "InfiniPath_QHT7140";
650                 break;
651         case 8:
652                 n = "LS/X-1";
653                 break;
654         case 9:         /* Comstock bringup test board */
655                 n = "Comstock";
656                 break;
657         case 10:
658                 n = "OEM_Board_2";
659                 break;
660         case 11:
661                 n = "InfiniPath_HT-470"; /* obsoleted */
662                 break;
663         case 12:
664                 n = "OEM_Board_4";
665                 break;
666         default:                /* don't know, just print the number */
667                 ipath_dev_err(dd, "Don't yet know about board "
668                               "with ID %u\n", boardrev);
669                 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
670                          boardrev);
671                 break;
672         }
673         if (n)
674                 snprintf(name, namelen, "%s", n);
675
676         if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 ||
677                 dd->ipath_minrev > 3)) {
678                 /*
679                  * This version of the driver only supports Rev 3.2 and 3.3
680                  */
681                 ipath_dev_err(dd,
682                               "Unsupported InfiniPath hardware revision %u.%u!\n",
683                               dd->ipath_majrev, dd->ipath_minrev);
684                 ret = 1;
685                 goto bail;
686         }
687         /*
688          * pkt/word counters are 32 bit, and therefore wrap fast enough
689          * that we snapshot them from a timer, and maintain 64 bit shadow
690          * copies
691          */
692         dd->ipath_flags |= IPATH_32BITCOUNTERS;
693         if (dd->ipath_htspeed != 800)
694                 ipath_dev_err(dd,
695                               "Incorrectly configured for HT @ %uMHz\n",
696                               dd->ipath_htspeed);
697         if (dd->ipath_boardrev == 7 || dd->ipath_boardrev == 11 ||
698             dd->ipath_boardrev == 6)
699                 dd->ipath_flags |= IPATH_GPIO_INTR;
700         else
701                 dd->ipath_flags |= IPATH_POLL_RX_INTR;
702         if (dd->ipath_boardrev == 8) {  /* LS/X-1 */
703                 u64 val;
704                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
705                 if (val & INFINIPATH_EXTS_SERDESSEL) {
706                         /*
707                          * hardware disabled
708                          *
709                          * This means that the chip is hardware disabled,
710                          * and will not be able to bring up the link,
711                          * in any case.  We special case this and abort
712                          * early, to avoid later messages.  We also set
713                          * the DISABLED status bit
714                          */
715                         ipath_dbg("Unit %u is hardware-disabled\n",
716                                   dd->ipath_unit);
717                         *dd->ipath_statusp |= IPATH_STATUS_DISABLED;
718                         /* this value is handled differently */
719                         ret = 2;
720                         goto bail;
721                 }
722         }
723         ret = 0;
724
725 bail:
726         return ret;
727 }
728
729 static void ipath_check_htlink(struct ipath_devdata *dd)
730 {
731         u8 linkerr, link_off, i;
732
733         for (i = 0; i < 2; i++) {
734                 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
735                 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
736                         dev_info(&dd->pcidev->dev, "Couldn't read "
737                                  "linkerror%d of HT slave/primary block\n",
738                                  i);
739                 else if (linkerr & 0xf0) {
740                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
741                                    "clearing\n", linkerr >> 4, i);
742                         /*
743                          * writing the linkerr bits that are set should
744                          * clear them
745                          */
746                         if (pci_write_config_byte(dd->pcidev, link_off,
747                                                   linkerr))
748                                 ipath_dbg("Failed write to clear HT "
749                                           "linkerror%d\n", i);
750                         if (pci_read_config_byte(dd->pcidev, link_off,
751                                                  &linkerr))
752                                 dev_info(&dd->pcidev->dev,
753                                          "Couldn't reread linkerror%d of "
754                                          "HT slave/primary block\n", i);
755                         else if (linkerr & 0xf0)
756                                 dev_info(&dd->pcidev->dev,
757                                          "HT linkerror%d bits 0x%x "
758                                          "couldn't be cleared\n",
759                                          i, linkerr >> 4);
760                 }
761         }
762 }
763
764 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
765 {
766         ipath_dbg("No reset possible for this InfiniPath hardware\n");
767         return 0;
768 }
769
770 #define HT_INTR_DISC_CONFIG  0x80       /* HT interrupt and discovery cap */
771 #define HT_INTR_REG_INDEX    2  /* intconfig requires indirect accesses */
772
773 /*
774  * Bits 13-15 of command==0 is slave/primary block.  Clear any HT CRC
775  * errors.  We only bother to do this at load time, because it's OK if
776  * it happened before we were loaded (first time after boot/reset),
777  * but any time after that, it's fatal anyway.  Also need to not check
778  * for for upper byte errors if we are in 8 bit mode, so figure out
779  * our width.  For now, at least, also complain if it's 8 bit.
780  */
781 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
782                              int pos, u8 cap_type)
783 {
784         u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
785         u16 linkctrl = 0;
786         int i;
787
788         dd->ipath_ht_slave_off = pos;
789         /* command word, master_host bit */
790         /* master host || slave */
791         if ((cap_type >> 2) & 1)
792                 link_a_b_off = 4;
793         else
794                 link_a_b_off = 0;
795         ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
796                    link_a_b_off ? 1 : 0,
797                    link_a_b_off ? 'B' : 'A');
798
799         link_a_b_off += pos;
800
801         /*
802          * check both link control registers; clear both HT CRC sets if
803          * necessary.
804          */
805         for (i = 0; i < 2; i++) {
806                 link_off = pos + i * 4 + 0x4;
807                 if (pci_read_config_word(pdev, link_off, &linkctrl))
808                         ipath_dev_err(dd, "Couldn't read HT link control%d "
809                                       "register\n", i);
810                 else if (linkctrl & (0xf << 8)) {
811                         ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
812                                    "bits %x\n", i, linkctrl & (0xf << 8));
813                         /*
814                          * now write them back to clear the error.
815                          */
816                         pci_write_config_byte(pdev, link_off,
817                                               linkctrl & (0xf << 8));
818                 }
819         }
820
821         /*
822          * As with HT CRC bits, same for protocol errors that might occur
823          * during boot.
824          */
825         for (i = 0; i < 2; i++) {
826                 link_off = pos + i * 4 + 0xd;
827                 if (pci_read_config_byte(pdev, link_off, &linkerr))
828                         dev_info(&pdev->dev, "Couldn't read linkerror%d "
829                                  "of HT slave/primary block\n", i);
830                 else if (linkerr & 0xf0) {
831                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
832                                    "clearing\n", linkerr >> 4, i);
833                         /*
834                          * writing the linkerr bits that are set will clear
835                          * them
836                          */
837                         if (pci_write_config_byte
838                             (pdev, link_off, linkerr))
839                                 ipath_dbg("Failed write to clear HT "
840                                           "linkerror%d\n", i);
841                         if (pci_read_config_byte(pdev, link_off, &linkerr))
842                                 dev_info(&pdev->dev, "Couldn't reread "
843                                          "linkerror%d of HT slave/primary "
844                                          "block\n", i);
845                         else if (linkerr & 0xf0)
846                                 dev_info(&pdev->dev, "HT linkerror%d bits "
847                                          "0x%x couldn't be cleared\n",
848                                          i, linkerr >> 4);
849                 }
850         }
851
852         /*
853          * this is just for our link to the host, not devices connected
854          * through tunnel.
855          */
856
857         if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
858                 ipath_dev_err(dd, "Couldn't read HT link width "
859                               "config register\n");
860         else {
861                 u32 width;
862                 switch (linkwidth & 7) {
863                 case 5:
864                         width = 4;
865                         break;
866                 case 4:
867                         width = 2;
868                         break;
869                 case 3:
870                         width = 32;
871                         break;
872                 case 1:
873                         width = 16;
874                         break;
875                 case 0:
876                 default:        /* if wrong, assume 8 bit */
877                         width = 8;
878                         break;
879                 }
880
881                 dd->ipath_htwidth = width;
882
883                 if (linkwidth != 0x11) {
884                         ipath_dev_err(dd, "Not configured for 16 bit HT "
885                                       "(%x)\n", linkwidth);
886                         if (!(linkwidth & 0xf)) {
887                                 ipath_dbg("Will ignore HT lane1 errors\n");
888                                 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
889                         }
890                 }
891         }
892
893         /*
894          * this is just for our link to the host, not devices connected
895          * through tunnel.
896          */
897         if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
898                 ipath_dev_err(dd, "Couldn't read HT link frequency "
899                               "config register\n");
900         else {
901                 u32 speed;
902                 switch (linkwidth & 0xf) {
903                 case 6:
904                         speed = 1000;
905                         break;
906                 case 5:
907                         speed = 800;
908                         break;
909                 case 4:
910                         speed = 600;
911                         break;
912                 case 3:
913                         speed = 500;
914                         break;
915                 case 2:
916                         speed = 400;
917                         break;
918                 case 1:
919                         speed = 300;
920                         break;
921                 default:
922                         /*
923                          * assume reserved and vendor-specific are 200...
924                          */
925                 case 0:
926                         speed = 200;
927                         break;
928                 }
929                 dd->ipath_htspeed = speed;
930         }
931 }
932
933 static int ipath_ht_intconfig(struct ipath_devdata *dd)
934 {
935         int ret;
936
937         if (dd->ipath_intconfig) {
938                 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
939                                  dd->ipath_intconfig);  /* interrupt address */
940                 ret = 0;
941         } else {
942                 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
943                               "interrupt address\n");
944                 ret = -EINVAL;
945         }
946
947         return ret;
948 }
949
950 static void ipath_ht_irq_update(struct pci_dev *dev, int irq,
951                                 struct ht_irq_msg *msg)
952 {
953         struct ipath_devdata *dd = pci_get_drvdata(dev);
954         u64 prev_intconfig = dd->ipath_intconfig;
955
956         dd->ipath_intconfig = msg->address_lo;
957         dd->ipath_intconfig |= ((u64) msg->address_hi) << 32;
958
959         /*
960          * If the previous value of dd->ipath_intconfig is zero, we're
961          * getting configured for the first time, and must not program the
962          * intconfig register here (it will be programmed later, when the
963          * hardware is ready).  Otherwise, we should.
964          */
965         if (prev_intconfig)
966                 ipath_ht_intconfig(dd);
967 }
968
969 /**
970  * ipath_setup_ht_config - setup the interruptconfig register
971  * @dd: the infinipath device
972  * @pdev: the PCI device
973  *
974  * setup the interruptconfig register from the HT config info.
975  * Also clear CRC errors in HT linkcontrol, if necessary.
976  * This is done only for the real hardware.  It is done before
977  * chip address space is initted, so can't touch infinipath registers
978  */
979 static int ipath_setup_ht_config(struct ipath_devdata *dd,
980                                  struct pci_dev *pdev)
981 {
982         int pos, ret;
983
984         ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update);
985         if (ret < 0) {
986                 ipath_dev_err(dd, "Couldn't create interrupt handler: "
987                               "err %d\n", ret);
988                 goto bail;
989         }
990         dd->ipath_irq = ret;
991         ret = 0;
992
993         /*
994          * Handle clearing CRC errors in linkctrl register if necessary.  We
995          * do this early, before we ever enable errors or hardware errors,
996          * mostly to avoid causing the chip to enter freeze mode.
997          */
998         pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
999         if (!pos) {
1000                 ipath_dev_err(dd, "Couldn't find HyperTransport "
1001                               "capability; no interrupts\n");
1002                 ret = -ENODEV;
1003                 goto bail;
1004         }
1005         do {
1006                 u8 cap_type;
1007
1008                 /* the HT capability type byte is 3 bytes after the
1009                  * capability byte.
1010                  */
1011                 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
1012                         dev_info(&pdev->dev, "Couldn't read config "
1013                                  "command @ %d\n", pos);
1014                         continue;
1015                 }
1016                 if (!(cap_type & 0xE0))
1017                         slave_or_pri_blk(dd, pdev, pos, cap_type);
1018         } while ((pos = pci_find_next_capability(pdev, pos,
1019                                                  PCI_CAP_ID_HT)));
1020
1021 bail:
1022         return ret;
1023 }
1024
1025 /**
1026  * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1027  * @dd: the infinipath device
1028  *
1029  * Called during driver unload.
1030  * This is currently a nop for the HT chip, not for all chips
1031  */
1032 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1033 {
1034 }
1035
1036 /**
1037  * ipath_setup_ht_setextled - set the state of the two external LEDs
1038  * @dd: the infinipath device
1039  * @lst: the L state
1040  * @ltst: the LT state
1041  *
1042  * Set the state of the two external LEDs, to indicate physical and
1043  * logical state of IB link.   For this chip (at least with recommended
1044  * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1045  * (logical state)
1046  *
1047  * Note:  We try to match the Mellanox HCA LED behavior as best
1048  * we can.  Green indicates physical link state is OK (something is
1049  * plugged in, and we can train).
1050  * Amber indicates the link is logically up (ACTIVE).
1051  * Mellanox further blinks the amber LED to indicate data packet
1052  * activity, but we have no hardware support for that, so it would
1053  * require waking up every 10-20 msecs and checking the counters
1054  * on the chip, and then turning the LED off if appropriate.  That's
1055  * visible overhead, so not something we will do.
1056  *
1057  */
1058 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1059                                      u64 lst, u64 ltst)
1060 {
1061         u64 extctl;
1062
1063         /* the diags use the LED to indicate diag info, so we leave
1064          * the external LED alone when the diags are running */
1065         if (ipath_diag_inuse)
1066                 return;
1067
1068         /*
1069          * start by setting both LED control bits to off, then turn
1070          * on the appropriate bit(s).
1071          */
1072         if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1073                 /*
1074                  * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1075                  * is inverted,  because it is normally used to indicate
1076                  * a hardware fault at reset, if there were errors
1077                  */
1078                 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1079                         | INFINIPATH_EXTC_LEDGBLERR_OFF;
1080                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1081                         extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1082                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1083                         extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1084         }
1085         else {
1086                 extctl = dd->ipath_extctrl &
1087                         ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1088                           INFINIPATH_EXTC_LED2PRIPORT_ON);
1089                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1090                         extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1091                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1092                         extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1093         }
1094         dd->ipath_extctrl = extctl;
1095         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1096 }
1097
1098 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1099 {
1100         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1101         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1102         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1103         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1104
1105         dd->ipath_i_bitsextant =
1106                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1107                 (INFINIPATH_I_RCVAVAIL_MASK <<
1108                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1109                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1110                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1111
1112         dd->ipath_e_bitsextant =
1113                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1114                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1115                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1116                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1117                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1118                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1119                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1120                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1121                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1122                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1123                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1124                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1125                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1126                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1127                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1128                 INFINIPATH_E_HARDWARE;
1129
1130         dd->ipath_hwe_bitsextant =
1131                 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1132                  INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1133                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1134                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1135                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1136                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1137                 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1138                 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1139                 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1140                 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1141                 INFINIPATH_HWE_HTCMISCERR4 |
1142                 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1143                 INFINIPATH_HWE_HTCMISCERR7 |
1144                 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1145                 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1146                 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1147                 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1148                 INFINIPATH_HWE_MEMBISTFAILED |
1149                 INFINIPATH_HWE_COREPLL_FBSLIP |
1150                 INFINIPATH_HWE_COREPLL_RFSLIP |
1151                 INFINIPATH_HWE_HTBPLL_FBSLIP |
1152                 INFINIPATH_HWE_HTBPLL_RFSLIP |
1153                 INFINIPATH_HWE_HTAPLL_FBSLIP |
1154                 INFINIPATH_HWE_HTAPLL_RFSLIP |
1155                 INFINIPATH_HWE_SERDESPLLFAILED |
1156                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1157                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1158
1159         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1160         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1161 }
1162
1163 /**
1164  * ipath_ht_init_hwerrors - enable hardware errors
1165  * @dd: the infinipath device
1166  *
1167  * now that we have finished initializing everything that might reasonably
1168  * cause a hardware error, and cleared those errors bits as they occur,
1169  * we can enable hardware errors in the mask (potentially enabling
1170  * freeze mode), and enable hardware errors as errors (along with
1171  * everything else) in errormask
1172  */
1173 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1174 {
1175         ipath_err_t val;
1176         u64 extsval;
1177
1178         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1179
1180         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1181                 ipath_dev_err(dd, "MemBIST did not complete!\n");
1182         if (extsval & INFINIPATH_EXTS_MEMBIST_CORRECT)
1183                 ipath_dbg("MemBIST corrected\n");
1184
1185         ipath_check_htlink(dd);
1186
1187         /* barring bugs, all hwerrors become interrupts, which can */
1188         val = -1LL;
1189         /* don't look at crc lane1 if 8 bit */
1190         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1191                 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1192         /* don't look at crc lane1 if 8 bit */
1193         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1194                 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1195
1196         /*
1197          * disable RXDSYNCMEMPARITY because external serdes is unused,
1198          * and therefore the logic will never be used or initialized,
1199          * and uninitialized state will normally result in this error
1200          * being asserted.  Similarly for the external serdess pll
1201          * lock signal.
1202          */
1203         val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1204                  INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1205
1206         /*
1207          * Disable MISCERR4 because of an inversion in the HT core
1208          * logic checking for errors that cause this bit to be set.
1209          * The errata can also cause the protocol error bit to be set
1210          * in the HT config space linkerror register(s).
1211          */
1212         val &= ~INFINIPATH_HWE_HTCMISCERR4;
1213
1214         /*
1215          * PLL ignored because MDIO interface has a logic problem
1216          * for reads, on Comstock and Ponderosa.  BRINGUP
1217          */
1218         if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1219                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1220         dd->ipath_hwerrmask = val;
1221 }
1222
1223 /**
1224  * ipath_ht_bringup_serdes - bring up the serdes
1225  * @dd: the infinipath device
1226  */
1227 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1228 {
1229         u64 val, config1;
1230         int ret = 0, change = 0;
1231
1232         ipath_dbg("Trying to bringup serdes\n");
1233
1234         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1235             INFINIPATH_HWE_SERDESPLLFAILED)
1236         {
1237                 ipath_dbg("At start, serdes PLL failed bit set in "
1238                           "hwerrstatus, clearing and continuing\n");
1239                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1240                                  INFINIPATH_HWE_SERDESPLLFAILED);
1241         }
1242
1243         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1244         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1245
1246         ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1247                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1248                    (unsigned long long) val, (unsigned long long) config1,
1249                    (unsigned long long)
1250                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1251                    (unsigned long long)
1252                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1253
1254         /* force reset on */
1255         val |= INFINIPATH_SERDC0_RESET_PLL
1256                 /* | INFINIPATH_SERDC0_RESET_MASK */
1257                 ;
1258         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1259         udelay(15);             /* need pll reset set at least for a bit */
1260
1261         if (val & INFINIPATH_SERDC0_RESET_PLL) {
1262                 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1263                 /* set lane resets, and tx idle, during pll reset */
1264                 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1265                         INFINIPATH_SERDC0_TXIDLE;
1266                 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1267                            "%llx)\n", (unsigned long long) val2);
1268                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1269                                  val2);
1270                 /*
1271                  * be sure chip saw it
1272                  */
1273                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1274                 /*
1275                  * need pll reset clear at least 11 usec before lane
1276                  * resets cleared; give it a few more
1277                  */
1278                 udelay(15);
1279                 val = val2;     /* for check below */
1280         }
1281
1282         if (val & (INFINIPATH_SERDC0_RESET_PLL |
1283                    INFINIPATH_SERDC0_RESET_MASK |
1284                    INFINIPATH_SERDC0_TXIDLE)) {
1285                 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1286                          INFINIPATH_SERDC0_RESET_MASK |
1287                          INFINIPATH_SERDC0_TXIDLE);
1288                 /* clear them */
1289                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1290                                  val);
1291         }
1292
1293         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1294         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1295              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1296                 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1297                          INFINIPATH_XGXS_MDIOADDR_SHIFT);
1298                 /*
1299                  * we use address 3
1300                  */
1301                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1302                 change = 1;
1303         }
1304         if (val & INFINIPATH_XGXS_RESET) {
1305                 /* normally true after boot */
1306                 val &= ~INFINIPATH_XGXS_RESET;
1307                 change = 1;
1308         }
1309         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1310              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1311                 /* need to compensate for Tx inversion in partner */
1312                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1313                          INFINIPATH_XGXS_RX_POL_SHIFT);
1314                 val |= dd->ipath_rx_pol_inv <<
1315                         INFINIPATH_XGXS_RX_POL_SHIFT;
1316                 change = 1;
1317         }
1318         if (change)
1319                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1320
1321         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1322
1323         /* clear current and de-emphasis bits */
1324         config1 &= ~0x0ffffffff00ULL;
1325         /* set current to 20ma */
1326         config1 |= 0x00000000000ULL;
1327         /* set de-emphasis to -5.68dB */
1328         config1 |= 0x0cccc000000ULL;
1329         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1330
1331         ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1332                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1333                    (unsigned long long) val, (unsigned long long) config1,
1334                    (unsigned long long)
1335                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1336                    (unsigned long long)
1337                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1338
1339         if (!ipath_waitfor_mdio_cmdready(dd)) {
1340                 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1341                                  ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1342                                                 IPATH_MDIO_CTRL_XGXS_REG_8,
1343                                                 0));
1344                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1345                                            IPATH_MDIO_DATAVALID, &val))
1346                         ipath_dbg("Never got MDIO data for XGXS status "
1347                                   "read\n");
1348                 else
1349                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1350                                    "'bank' 31 %x\n", (u32) val);
1351         } else
1352                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1353
1354         return ret;             /* for now, say we always succeeded */
1355 }
1356
1357 /**
1358  * ipath_ht_quiet_serdes - set serdes to txidle
1359  * @dd: the infinipath device
1360  * driver is being unloaded
1361  */
1362 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1363 {
1364         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1365
1366         val |= INFINIPATH_SERDC0_TXIDLE;
1367         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1368                   (unsigned long long) val);
1369         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1370 }
1371
1372 /**
1373  * ipath_pe_put_tid - write a TID in chip
1374  * @dd: the infinipath device
1375  * @tidptr: pointer to the expected TID (in chip) to udpate
1376  * @tidtype: 0 for eager, 1 for expected
1377  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1378  *
1379  * This exists as a separate routine to allow for special locking etc.
1380  * It's used for both the full cleanup on exit, as well as the normal
1381  * setup and teardown.
1382  */
1383 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1384                              u64 __iomem *tidptr, u32 type,
1385                              unsigned long pa)
1386 {
1387         if (!dd->ipath_kregbase)
1388                 return;
1389
1390         if (pa != dd->ipath_tidinvalid) {
1391                 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1392                         dev_info(&dd->pcidev->dev,
1393                                  "physaddr %lx has more than "
1394                                  "40 bits, using only 40!!!\n", pa);
1395                         pa &= INFINIPATH_RT_ADDR_MASK;
1396                 }
1397                 if (type == 0)
1398                         pa |= dd->ipath_tidtemplate;
1399                 else {
1400                         /* in words (fixed, full page).  */
1401                         u64 lenvalid = PAGE_SIZE >> 2;
1402                         lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1403                         pa |= lenvalid | INFINIPATH_RT_VALID;
1404                 }
1405         }
1406         writeq(pa, tidptr);
1407 }
1408
1409
1410 /**
1411  * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1412  * @dd: the infinipath device
1413  * @port: the port
1414  *
1415  * Used from ipath_close(), and at chip initialization.
1416  */
1417 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1418 {
1419         u64 __iomem *tidbase;
1420         int i;
1421
1422         if (!dd->ipath_kregbase)
1423                 return;
1424
1425         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1426
1427         /*
1428          * need to invalidate all of the expected TID entries for this
1429          * port, so we don't have valid entries that might somehow get
1430          * used (early in next use of this port, or through some bug)
1431          */
1432         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1433                                    dd->ipath_rcvtidbase +
1434                                    port * dd->ipath_rcvtidcnt *
1435                                    sizeof(*tidbase));
1436         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1437                 ipath_ht_put_tid(dd, &tidbase[i], 1, dd->ipath_tidinvalid);
1438
1439         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1440                                    dd->ipath_rcvegrbase +
1441                                    port * dd->ipath_rcvegrcnt *
1442                                    sizeof(*tidbase));
1443
1444         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1445                 ipath_ht_put_tid(dd, &tidbase[i], 0, dd->ipath_tidinvalid);
1446 }
1447
1448 /**
1449  * ipath_ht_tidtemplate - setup constants for TID updates
1450  * @dd: the infinipath device
1451  *
1452  * We setup stuff that we use a lot, to avoid calculating each time
1453  */
1454 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1455 {
1456         dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1457         dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1458         dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1459
1460         /*
1461          * work around chip errata bug 7358, by marking invalid tids
1462          * as having max length
1463          */
1464         dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1465                 INFINIPATH_RT_BUFSIZE_SHIFT;
1466 }
1467
1468 static int ipath_ht_early_init(struct ipath_devdata *dd)
1469 {
1470         u32 __iomem *piobuf;
1471         u32 pioincr, val32;
1472         int i;
1473
1474         /*
1475          * one cache line; long IB headers will spill over into received
1476          * buffer
1477          */
1478         dd->ipath_rcvhdrentsize = 16;
1479         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1480
1481         /*
1482          * For HT, we allocate a somewhat overly large eager buffer,
1483          * such that we can guarantee that we can receive the largest
1484          * packet that we can send out.  To truly support a 4KB MTU,
1485          * we need to bump this to a large value.  To date, other than
1486          * testing, we have never encountered an HCA that can really
1487          * send 4KB MTU packets, so we do not handle that (we'll get
1488          * errors interrupts if we ever see one).
1489          */
1490         dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1491
1492         /*
1493          * the min() check here is currently a nop, but it may not
1494          * always be, depending on just how we do ipath_rcvegrbufsize
1495          */
1496         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1497                                  dd->ipath_rcvegrbufsize);
1498         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1499         ipath_ht_tidtemplate(dd);
1500
1501         /*
1502          * zero all the TID entries at startup.  We do this for sanity,
1503          * in case of a previous driver crash of some kind, and also
1504          * because the chip powers up with these memories in an unknown
1505          * state.  Use portcnt, not cfgports, since this is for the
1506          * full chip, not for current (possibly different) configuration
1507          * value.
1508          * Chip Errata bug 6447
1509          */
1510         for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1511                 ipath_ht_clear_tids(dd, val32);
1512
1513         /*
1514          * write the pbc of each buffer, to be sure it's initialized, then
1515          * cancel all the buffers, and also abort any packets that might
1516          * have been in flight for some reason (the latter is for driver
1517          * unload/reload, but isn't a bad idea at first init).  PIO send
1518          * isn't enabled at this point, so there is no danger of sending
1519          * these out on the wire.
1520          * Chip Errata bug 6610
1521          */
1522         piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1523                                   dd->ipath_piobufbase);
1524         pioincr = dd->ipath_palign / sizeof(*piobuf);
1525         for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1526                 /*
1527                  * reasonable word count, just to init pbc
1528                  */
1529                 writel(16, piobuf);
1530                 piobuf += pioincr;
1531         }
1532         /*
1533          * self-clearing
1534          */
1535         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1536                          INFINIPATH_S_ABORT);
1537
1538         ipath_get_eeprom_info(dd);
1539         if (dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1540                 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1541                 /*
1542                  * Later production QHT7040 has same changes as QHT7140, so
1543                  * can use GPIO interrupts.  They have serial #'s starting
1544                  * with 128, rather than 112.
1545                  */
1546                 dd->ipath_flags |= IPATH_GPIO_INTR;
1547                 dd->ipath_flags &= ~IPATH_POLL_RX_INTR;
1548         }
1549         return 0;
1550 }
1551
1552
1553 static int ipath_ht_txe_recover(struct ipath_devdata *dd)
1554 {
1555         int cnt = ++ipath_stats.sps_txeparity;
1556         if (cnt >= IPATH_MAX_PARITY_ATTEMPTS)  {
1557                 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1558                         ipath_dev_err(dd,
1559                                 "Too many attempts to recover from "
1560                                 "TXE parity, giving up\n");
1561                 return 0;
1562         }
1563         dev_info(&dd->pcidev->dev,
1564                 "Recovering from TXE PIO parity error\n");
1565         ipath_disarm_senderrbufs(dd, 1);
1566         return 1;
1567 }
1568
1569
1570 /**
1571  * ipath_init_ht_get_base_info - set chip-specific flags for user code
1572  * @dd: the infinipath device
1573  * @kbase: ipath_base_info pointer
1574  *
1575  * We set the PCIE flag because the lower bandwidth on PCIe vs
1576  * HyperTransport can affect some user packet algorithms.
1577  */
1578 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1579 {
1580         struct ipath_base_info *kinfo = kbase;
1581
1582         kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1583                 IPATH_RUNTIME_RCVHDR_COPY;
1584
1585         return 0;
1586 }
1587
1588 static void ipath_ht_free_irq(struct ipath_devdata *dd)
1589 {
1590         free_irq(dd->ipath_irq, dd);
1591         ht_destroy_irq(dd->ipath_irq);
1592         dd->ipath_irq = 0;
1593         dd->ipath_intconfig = 0;
1594 }
1595
1596 /**
1597  * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1598  * @dd: the infinipath device
1599  *
1600  * This is global, and is called directly at init to set up the
1601  * chip-specific function pointers for later use.
1602  */
1603 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1604 {
1605         dd->ipath_f_intrsetup = ipath_ht_intconfig;
1606         dd->ipath_f_bus = ipath_setup_ht_config;
1607         dd->ipath_f_reset = ipath_setup_ht_reset;
1608         dd->ipath_f_get_boardname = ipath_ht_boardname;
1609         dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1610         dd->ipath_f_early_init = ipath_ht_early_init;
1611         dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1612         dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1613         dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1614         dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1615         dd->ipath_f_put_tid = ipath_ht_put_tid;
1616         dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1617         dd->ipath_f_setextled = ipath_setup_ht_setextled;
1618         dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1619         dd->ipath_f_free_irq = ipath_ht_free_irq;
1620
1621         /*
1622          * initialize chip-specific variables
1623          */
1624         dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1625
1626         /*
1627          * setup the register offsets, since they are different for each
1628          * chip
1629          */
1630         dd->ipath_kregs = &ipath_ht_kregs;
1631         dd->ipath_cregs = &ipath_ht_cregs;
1632
1633         /*
1634          * do very early init that is needed before ipath_f_bus is
1635          * called
1636          */
1637         ipath_init_ht_variables(dd);
1638 }