1 /**************************************************************************
3 * Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above
13 * copyright notice, this list of conditions and the following
14 * disclaimer in the documentation and/or other materials provided
15 * with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
27 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * The views and conclusions contained in the software and documentation
31 * are those of the authors and should not be interpreted as representing
32 * official policies, either expressed or implied, of Alacritech, Inc.
34 **************************************************************************/
39 * This header file contains definitions that are common to our hardware.
44 #define PCI_VENDOR_ID_ALACRITECH 0x139A
45 #define SLIC_1GB_DEVICE_ID 0x0005
46 #define SLIC_2GB_DEVICE_ID 0x0007 /*Oasis Device ID */
48 #define SLIC_1GB_CICADA_SUBSYS_ID 0x0008
50 #define SLIC_NBR_MACS 4
52 #define SLIC_RCVBUF_SIZE 2048
53 #define SLIC_RCVBUF_HEADSIZE 34
54 #define SLIC_RCVBUF_TAILSIZE 0
55 #define SLIC_RCVBUF_DATASIZE (SLIC_RCVBUF_SIZE - (SLIC_RCVBUF_HEADSIZE +\
56 SLIC_RCVBUF_TAILSIZE))
58 #define VGBSTAT_XPERR 0x40000000
59 #define VGBSTAT_XERRSHFT 25
60 #define VGBSTAT_XCSERR 0x23
61 #define VGBSTAT_XUFLOW 0x22
62 #define VGBSTAT_XHLEN 0x20
63 #define VGBSTAT_NETERR 0x01000000
64 #define VGBSTAT_NERRSHFT 16
65 #define VGBSTAT_NERRMSK 0x1ff
66 #define VGBSTAT_NCSERR 0x103
67 #define VGBSTAT_NUFLOW 0x102
68 #define VGBSTAT_NHLEN 0x100
69 #define VGBSTAT_LNKERR 0x00000080
70 #define VGBSTAT_LERRMSK 0xff
71 #define VGBSTAT_LDEARLY 0x86
72 #define VGBSTAT_LBOFLO 0x85
73 #define VGBSTAT_LCODERR 0x84
74 #define VGBSTAT_LDBLNBL 0x83
75 #define VGBSTAT_LCRCERR 0x82
76 #define VGBSTAT_LOFLO 0x81
77 #define VGBSTAT_LUFLO 0x80
78 #define IRHDDR_FLEN_MSK 0x0000ffff
79 #define IRHDDR_SVALID 0x80000000
80 #define IRHDDR_ERR 0x10000000
81 #define VRHSTAT_802OE 0x80000000
82 #define VRHSTAT_TPOFLO 0x10000000
83 #define VRHSTATB_802UE 0x80000000
84 #define VRHSTATB_RCVE 0x40000000
85 #define VRHSTATB_BUFF 0x20000000
86 #define VRHSTATB_CARRE 0x08000000
87 #define VRHSTATB_LONGE 0x02000000
88 #define VRHSTATB_PREA 0x01000000
89 #define VRHSTATB_CRC 0x00800000
90 #define VRHSTATB_DRBL 0x00400000
91 #define VRHSTATB_CODE 0x00200000
92 #define VRHSTATB_TPCSUM 0x00100000
93 #define VRHSTATB_TPHLEN 0x00080000
94 #define VRHSTATB_IPCSUM 0x00040000
95 #define VRHSTATB_IPLERR 0x00020000
96 #define VRHSTATB_IPHERR 0x00010000
97 #define SLIC_MAX64_BCNT 23
98 #define SLIC_MAX32_BCNT 26
99 #define IHCMD_XMT_REQ 0x01
100 #define IHFLG_IFSHFT 2
101 #define SLIC_RSPBUF_SIZE 32
103 #define SLIC_RESET_MAGIC 0xDEAD
104 #define ICR_INT_OFF 0
106 #define ICR_INT_MASK 2
108 #define ISR_ERR 0x80000000
109 #define ISR_RCV 0x40000000
110 #define ISR_CMD 0x20000000
111 #define ISR_IO 0x60000000
112 #define ISR_UPC 0x10000000
113 #define ISR_LEVENT 0x08000000
114 #define ISR_RMISS 0x02000000
115 #define ISR_UPCERR 0x01000000
116 #define ISR_XDROP 0x00800000
117 #define ISR_UPCBSY 0x00020000
118 #define ISR_EVMSK 0xffff0000
119 #define ISR_PINGMASK 0x00700000
120 #define ISR_PINGDSMASK 0x00710000
121 #define ISR_UPCMASK 0x11000000
122 #define SLIC_WCS_START 0x80000000
123 #define SLIC_WCS_COMPARE 0x40000000
124 #define SLIC_RCVWCS_BEGIN 0x40000000
125 #define SLIC_RCVWCS_FINISH 0x80000000
126 #define SLIC_PM_MAXPATTERNS 6
127 #define SLIC_PM_PATTERNSIZE 128
128 #define SLIC_PMCAPS_WAKEONLAN 0x00000001
129 #define MIICR_REG_PCR 0x00000000
130 #define MIICR_REG_4 0x00040000
131 #define MIICR_REG_9 0x00090000
132 #define MIICR_REG_16 0x00100000
133 #define PCR_RESET 0x8000
134 #define PCR_POWERDOWN 0x0800
135 #define PCR_SPEED_100 0x2000
136 #define PCR_SPEED_1000 0x0040
137 #define PCR_AUTONEG 0x1000
138 #define PCR_AUTONEG_RST 0x0200
139 #define PCR_DUPLEX_FULL 0x0100
140 #define PSR_LINKUP 0x0004
142 #define PAR_ADV100FD 0x0100
143 #define PAR_ADV100HD 0x0080
144 #define PAR_ADV10FD 0x0040
145 #define PAR_ADV10HD 0x0020
146 #define PAR_ASYMPAUSE 0x0C00
147 #define PAR_802_3 0x0001
149 #define PAR_ADV1000XFD 0x0020
150 #define PAR_ADV1000XHD 0x0040
151 #define PAR_ASYMPAUSE_FIBER 0x0180
153 #define PGC_ADV1000FD 0x0200
154 #define PGC_ADV1000HD 0x0100
155 #define SEEQ_LINKFAIL 0x4000
156 #define SEEQ_SPEED 0x0080
157 #define SEEQ_DUPLEX 0x0040
158 #define TDK_DUPLEX 0x0800
159 #define TDK_SPEED 0x0400
160 #define MRV_REG16_XOVERON 0x0068
161 #define MRV_REG16_XOVEROFF 0x0008
162 #define MRV_SPEED_1000 0x8000
163 #define MRV_SPEED_100 0x4000
164 #define MRV_SPEED_10 0x0000
165 #define MRV_FULLDUPLEX 0x2000
166 #define MRV_LINKUP 0x0400
168 #define GIG_LINKUP 0x0001
169 #define GIG_FULLDUPLEX 0x0002
170 #define GIG_SPEED_MASK 0x000C
171 #define GIG_SPEED_1000 0x0008
172 #define GIG_SPEED_100 0x0004
173 #define GIG_SPEED_10 0x0000
175 #define MCR_RESET 0x80000000
176 #define MCR_CRCEN 0x40000000
177 #define MCR_FULLD 0x10000000
178 #define MCR_PAD 0x02000000
179 #define MCR_RETRYLATE 0x01000000
180 #define MCR_BOL_SHIFT 21
181 #define MCR_IPG1_SHIFT 14
182 #define MCR_IPG2_SHIFT 7
183 #define MCR_IPG3_SHIFT 0
184 #define GMCR_RESET 0x80000000
185 #define GMCR_GBIT 0x20000000
186 #define GMCR_FULLD 0x10000000
187 #define GMCR_GAPBB_SHIFT 14
188 #define GMCR_GAPR1_SHIFT 7
189 #define GMCR_GAPR2_SHIFT 0
190 #define GMCR_GAPBB_1000 0x60
191 #define GMCR_GAPR1_1000 0x2C
192 #define GMCR_GAPR2_1000 0x40
193 #define GMCR_GAPBB_100 0x70
194 #define GMCR_GAPR1_100 0x2C
195 #define GMCR_GAPR2_100 0x40
196 #define XCR_RESET 0x80000000
197 #define XCR_XMTEN 0x40000000
198 #define XCR_PAUSEEN 0x20000000
199 #define XCR_LOADRNG 0x10000000
200 #define RCR_RESET 0x80000000
201 #define RCR_RCVEN 0x40000000
202 #define RCR_RCVALL 0x20000000
203 #define RCR_RCVBAD 0x10000000
204 #define RCR_CTLEN 0x08000000
205 #define RCR_ADDRAEN 0x02000000
206 #define GXCR_RESET 0x80000000
207 #define GXCR_XMTEN 0x40000000
208 #define GXCR_PAUSEEN 0x20000000
209 #define GRCR_RESET 0x80000000
210 #define GRCR_RCVEN 0x40000000
211 #define GRCR_RCVALL 0x20000000
212 #define GRCR_RCVBAD 0x10000000
213 #define GRCR_CTLEN 0x08000000
214 #define GRCR_ADDRAEN 0x02000000
215 #define GRCR_HASHSIZE_SHIFT 17
216 #define GRCR_HASHSIZE 14
218 #define SLIC_EEPROM_ID 0xA5A5
219 #define SLIC_SRAM_SIZE2GB (64 * 1024)
220 #define SLIC_SRAM_SIZE1GB (32 * 1024)
221 #define SLIC_HOSTID_DEFAULT 0xFFFF /* uninitialized hostid */
222 #define SLIC_NBR_MACS 4
225 unsigned char pad1[6];
234 unsigned char data[SLIC_RCVBUF_DATASIZE];
237 struct slic_hddr_wds {
256 #define frame_status14 u0.hdrs_14port.frame_status
257 #define frame_status_b14 u0.hdrs_14port.frame_status_b
258 #define frame_statusGB u0.hdrs_gbit.frame_status
260 struct slic_host64sg {
266 struct slic_host64_cmd {
269 unsigned char command;
278 struct slic_host64sg bufs[SLIC_MAX64_BCNT];
293 u32 slic_reset; /* Reset Register */
296 u32 slic_icr; /* Interrupt Control Register */
298 #define SLIC_ICR 0x0008
300 u32 slic_isp; /* Interrupt status pointer */
302 #define SLIC_ISP 0x0010
304 u32 slic_isr; /* Interrupt status */
306 #define SLIC_ISR 0x0018
308 u32 slic_hbar; /* Header buffer address reg */
310 /* 31-8 - phy addr of set of contiguous hdr buffers
311 7-0 - number of buffers passed
312 Buffers are 256 bytes long on 256-byte boundaries. */
313 #define SLIC_HBAR 0x0020
314 #define SLIC_HBAR_CNT_MSK 0x000000FF
316 u32 slic_dbar; /* Data buffer handle & address reg */
319 /* 4 sets of registers; Buffers are 2K bytes long 2 per 4K page. */
320 #define SLIC_DBAR 0x0028
321 #define SLIC_DBAR_SIZE 2048
323 u32 slic_cbar; /* Xmt Cmd buf addr regs.*/
324 /* 1 per XMT interface
325 31-5 - phy addr of host command buffer
326 4-0 - length of cmd in multiples of 32 bytes
327 Buffers are 32 bytes up to 512 bytes long */
328 #define SLIC_CBAR 0x0030
329 #define SLIC_CBAR_LEN_MSK 0x0000001F
330 #define SLIC_CBAR_ALIGN 0x00000020
332 u32 slic_wcs; /* write control store*/
333 #define SLIC_WCS 0x0034
334 #define SLIC_WCS_START 0x80000000 /*Start the SLIC (Jump to WCS)*/
335 #define SLIC_WCS_COMPARE 0x40000000 /* Compare with value in WCS*/
337 u32 slic_rbar; /* Response buffer address reg.*/
339 /*31-8 - phy addr of set of contiguous response buffers
340 7-0 - number of buffers passed
341 Buffers are 32 bytes long on 32-byte boundaries.*/
342 #define SLIC_RBAR 0x0038
343 #define SLIC_RBAR_CNT_MSK 0x000000FF
344 #define SLIC_RBAR_SIZE 32
346 u32 slic_stats; /* read statistics (UPR) */
348 #define SLIC_RSTAT 0x0040
350 u32 slic_rlsr; /* read link status */
352 #define SLIC_LSTAT 0x0048
354 u32 slic_wmcfg; /* Write Mac Config */
356 #define SLIC_WMCFG 0x0050
358 u32 slic_wphy; /* Write phy register */
360 #define SLIC_WPHY 0x0058
362 u32 slic_rcbar; /*Rcv Cmd buf addr reg*/
364 #define SLIC_RCBAR 0x0060
366 u32 slic_rconfig; /* Read SLIC Config*/
368 #define SLIC_RCONFIG 0x0068
370 u32 slic_intagg; /* Interrupt aggregation time*/
372 #define SLIC_INTAGG 0x0070
374 u32 slic_wxcfg; /* Write XMIT config reg*/
376 #define SLIC_WXCFG 0x0078
378 u32 slic_wrcfg; /* Write RCV config reg*/
380 #define SLIC_WRCFG 0x0080
382 u32 slic_wraddral; /* Write rcv addr a low*/
384 #define SLIC_WRADDRAL 0x0088
386 u32 slic_wraddrah; /* Write rcv addr a high*/
388 #define SLIC_WRADDRAH 0x0090
390 u32 slic_wraddrbl; /* Write rcv addr b low*/
392 #define SLIC_WRADDRBL 0x0098
394 u32 slic_wraddrbh; /* Write rcv addr b high*/
396 #define SLIC_WRADDRBH 0x00a0
398 u32 slic_mcastlow; /* Low bits of mcast mask*/
400 #define SLIC_MCASTLOW 0x00a8
402 u32 slic_mcasthigh; /* High bits of mcast mask*/
404 #define SLIC_MCASTHIGH 0x00b0
406 u32 slic_ping; /* Ping the card*/
408 #define SLIC_PING 0x00b8
410 u32 slic_dump_cmd; /* Dump command */
412 #define SLIC_DUMP_CMD 0x00c0
414 u32 slic_dump_data; /* Dump data pointer */
416 #define SLIC_DUMP_DATA 0x00c8
418 u32 slic_pcistatus; /* Read card's pci_status register */
420 #define SLIC_PCISTATUS 0x00d0
422 u32 slic_wrhostid; /* Write hostid field */
424 #define SLIC_WRHOSTID 0x00d8
425 #define SLIC_RDHOSTID_1GB 0x1554
426 #define SLIC_RDHOSTID_2GB 0x1554
428 u32 slic_low_power; /* Put card in a low power state */
430 #define SLIC_LOW_POWER 0x00e0
432 u32 slic_quiesce; /* force slic into quiescent state
435 #define SLIC_QUIESCE 0x00e8
437 u32 slic_reset_iface; /* reset interface queues */
439 #define SLIC_RESET_IFACE 0x00f0
441 u32 slic_addr_upper; /* Bits 63-32 for host i/f addrs */
443 #define SLIC_ADDR_UPPER 0x00f8 /*Register is only written when it has changed*/
445 u32 slic_hbar64; /* 64 bit Header buffer address reg */
447 #define SLIC_HBAR64 0x0100
449 u32 slic_dbar64; /* 64 bit Data buffer handle & address reg */
451 #define SLIC_DBAR64 0x0108
453 u32 slic_cbar64; /* 64 bit Xmt Cmd buf addr regs. */
455 #define SLIC_CBAR64 0x0110
457 u32 slic_rbar64; /* 64 bit Response buffer address reg.*/
459 #define SLIC_RBAR64 0x0118
461 u32 slic_rcbar64; /* 64 bit Rcv Cmd buf addr reg*/
463 #define SLIC_RCBAR64 0x0120
465 u32 slic_stats64; /*read statistics (64 bit UPR)*/
467 #define SLIC_RSTAT64 0x0128
469 u32 slic_rcv_wcs; /*Download Gigabit RCV sequencer ucode*/
471 #define SLIC_RCV_WCS 0x0130
472 #define SLIC_RCVWCS_BEGIN 0x40000000
473 #define SLIC_RCVWCS_FINISH 0x80000000
475 u32 slic_wrvlanid; /* Write VlanId field */
477 #define SLIC_WRVLANID 0x0138
479 u32 slic_read_xf_info; /* Read Transformer info */
481 #define SLIC_READ_XF_INFO 0x0140
483 u32 slic_write_xf_info; /* Write Transformer info */
485 #define SLIC_WRITE_XF_INFO 0x0148
487 u32 RSVD1; /* TOE Only */
490 u32 RSVD2; /* TOE Only */
493 u32 RSVD3; /* TOE Only */
496 u32 RSVD4; /* TOE Only */
499 u32 slic_ticks_per_sec; /* Write card ticks per second */
501 #define SLIC_TICKS_PER_SEC 0x0170
518 struct inicpm_wakepattern {
520 unsigned char pattern[SLIC_PM_PATTERNSIZE];
521 unsigned char mask[SLIC_PM_PATTERNSIZE];
524 struct inicpm_state {
528 u32 wake_magicpacket;
529 u32 wake_framepattern;
530 struct inicpm_wakepattern wakepattern[SLIC_PM_MAXPATTERNS];
533 struct slicpm_packet_pattern {
542 enum slicpm_power_state {
543 slicpm_state_unspecified = 0,
551 struct slicpm_wakeup_capabilities {
552 enum slicpm_power_state min_magic_packet_wakeup;
553 enum slicpm_power_state min_pattern_wakeup;
554 enum slicpm_power_state min_link_change_wakeup;
557 struct slic_pnp_capabilities {
559 struct slicpm_wakeup_capabilities wakeup_capabilities;
568 u32 xmit_other_error;
569 u32 xmit_excess_collisions;
587 u64 xmit_other_error;
588 u64 xmit_excess_collisions;
603 struct xmt_stats xmt100;
604 struct rcv_stats rcv100;
607 struct xmt_statsgb xmtGB;
608 struct rcv_statsgb rcvGB;
613 #define xmit_tcp_segs100 u.stats_100.xmt100.xmit_tcp_segs
614 #define xmit_tcp_bytes100 u.stats_100.xmt100.xmit_tcp_bytes
615 #define xmit_bytes100 u.stats_100.xmt100.xmit_bytes
616 #define xmit_collisions100 u.stats_100.xmt100.xmit_collisions
617 #define xmit_unicasts100 u.stats_100.xmt100.xmit_unicasts
618 #define xmit_other_error100 u.stats_100.xmt100.xmit_other_error
619 #define xmit_excess_collisions100 u.stats_100.xmt100.xmit_excess_collisions
620 #define rcv_tcp_segs100 u.stats_100.rcv100.rcv_tcp_segs
621 #define rcv_tcp_bytes100 u.stats_100.rcv100.rcv_tcp_bytes
622 #define rcv_bytes100 u.stats_100.rcv100.rcv_bytes
623 #define rcv_unicasts100 u.stats_100.rcv100.rcv_unicasts
624 #define rcv_other_error100 u.stats_100.rcv100.rcv_other_error
625 #define rcv_drops100 u.stats_100.rcv100.rcv_drops
626 #define xmit_tcp_segs_gb u.stats_GB.xmtGB.xmit_tcp_segs
627 #define xmit_tcp_bytes_gb u.stats_GB.xmtGB.xmit_tcp_bytes
628 #define xmit_bytes_gb u.stats_GB.xmtGB.xmit_bytes
629 #define xmit_collisions_gb u.stats_GB.xmtGB.xmit_collisions
630 #define xmit_unicasts_gb u.stats_GB.xmtGB.xmit_unicasts
631 #define xmit_other_error_gb u.stats_GB.xmtGB.xmit_other_error
632 #define xmit_excess_collisions_gb u.stats_GB.xmtGB.xmit_excess_collisions
634 #define rcv_tcp_segs_gb u.stats_GB.rcvGB.rcv_tcp_segs
635 #define rcv_tcp_bytes_gb u.stats_GB.rcvGB.rcv_tcp_bytes
636 #define rcv_bytes_gb u.stats_GB.rcvGB.rcv_bytes
637 #define rcv_unicasts_gb u.stats_GB.rcvGB.rcv_unicasts
638 #define rcv_other_error_gb u.stats_GB.rcvGB.rcv_other_error
639 #define rcv_drops_gb u.stats_GB.rcvGB.rcv_drops
641 struct slic_config_mac {
642 unsigned char macaddrA[6];
645 #define ATK_FRU_FORMAT 0x00
646 #define VENDOR1_FRU_FORMAT 0x01
647 #define VENDOR2_FRU_FORMAT 0x02
648 #define VENDOR3_FRU_FORMAT 0x03
649 #define VENDOR4_FRU_FORMAT 0x04
650 #define NO_FRU_FORMAT 0xFF
653 unsigned char assembly[6];
654 unsigned char revision[2];
655 unsigned char serial[14];
656 unsigned char pad[3];
660 unsigned char commodity;
661 unsigned char assembly[4];
662 unsigned char revision[2];
663 unsigned char supplier[2];
664 unsigned char date[2];
665 unsigned char sequence[3];
666 unsigned char pad[13];
670 unsigned char part[8];
671 unsigned char supplier[5];
672 unsigned char date[3];
673 unsigned char sequence[4];
674 unsigned char pad[7];
678 unsigned char assembly[6];
679 unsigned char revision[2];
680 unsigned char serial[14];
681 unsigned char pad[3];
685 unsigned char number[8];
686 unsigned char part[8];
687 unsigned char version[8];
688 unsigned char pad[3];
692 struct vendor1_fru vendor1_fru;
693 struct vendor2_fru vendor2_fru;
694 struct vendor3_fru vendor3_fru;
695 struct vendor4_fru vendor4_fru;
699 SLIC EEPROM structure for Mojave
702 ushort Id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/
703 ushort EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
704 ushort FlashSize; /* 02 Flash size */
705 ushort EepromSize; /* 03 EEPROM Size */
706 ushort VendorId; /* 04 Vendor ID */
707 ushort DeviceId; /* 05 Device ID */
708 unsigned char RevisionId; /* 06 Revision ID */
709 unsigned char ClassCode[3]; /* 07 Class Code */
710 unsigned char DbgIntPin; /* 08 Debug Interrupt pin */
711 unsigned char NetIntPin0; /* Network Interrupt Pin */
712 unsigned char MinGrant; /* 09 Minimum grant */
713 unsigned char MaxLat; /* Maximum Latency */
714 ushort PciStatus; /* 10 PCI Status */
715 ushort SubSysVId; /* 11 Subsystem Vendor Id */
716 ushort SubSysId; /* 12 Subsystem ID */
717 ushort DbgDevId; /* 13 Debug Device Id */
718 ushort DramRomFn; /* 14 Dram/Rom function */
719 ushort DSize2Pci; /* 15 DRAM size to PCI (bytes * 64K) */
720 ushort RSize2Pci; /* 16 ROM extension size to PCI (bytes * 4k) */
721 unsigned char NetIntPin1;/* 17 Network Interface Pin 1
722 (simba/leone only) */
723 unsigned char NetIntPin2; /*Network Interface Pin 2 (simba/leone only)*/
725 unsigned char NetIntPin3;/*18 Network Interface Pin 3
727 unsigned char FreeTime;/*FreeTime setting (leone/mojave only) */
729 unsigned char TBIctl; /* 10-bit interface control (Mojave only) */
730 ushort DramSize; /* 19 DRAM size (bytes * 64k) */
733 /* Mac Interface Specific portions */
734 struct slic_config_mac MacInfo[SLIC_NBR_MACS];
735 } mac; /* MAC access for all boards */
737 /* use above struct for MAC access */
738 struct slic_config_mac pad[SLIC_NBR_MACS - 1];
739 ushort DeviceId2; /* Device ID for 2nd
741 unsigned char IntPin2; /* Interrupt pin for
743 unsigned char ClassCode2[3]; /* Class Code for 2nd
745 } mojave; /* 2nd function access for gigabit board */
747 ushort CfgByte6; /* Config Byte 6 */
748 ushort PMECapab; /* Power Mgment capabilities */
749 ushort NwClkCtrls; /* NetworkClockControls */
750 unsigned char FruFormat; /* Alacritech FRU format type */
751 struct atk_fru AtkFru; /* Alacritech FRU information */
752 unsigned char OemFruFormat; /* optional OEM FRU format type */
753 union oemfru OemFru; /* optional OEM FRU information */
754 unsigned char Pad[4]; /* Pad to 128 bytes - includes 2 cksum bytes
755 *(if OEM FRU info exists) and two unusable
756 * bytes at the end */
759 /* SLIC EEPROM structure for Oasis */
760 struct oslic_eeprom {
761 ushort Id; /* 00 EEPROM/FLASH Magic code 'A5A5' */
762 ushort EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
763 ushort FlashConfig0; /* 02 Flash Config for SPI device 0 */
764 ushort FlashConfig1; /* 03 Flash Config for SPI device 1 */
765 ushort VendorId; /* 04 Vendor ID */
766 ushort DeviceId; /* 05 Device ID (function 0) */
767 unsigned char RevisionId; /* 06 Revision ID */
768 unsigned char ClassCode[3]; /* 07 Class Code for PCI function 0 */
769 unsigned char IntPin1; /* 08 Interrupt pin for PCI function 1*/
770 unsigned char ClassCode2[3]; /* 09 Class Code for PCI function 1 */
771 unsigned char IntPin2; /* 10 Interrupt pin for PCI function 2*/
772 unsigned char IntPin0; /* Interrupt pin for PCI function 0*/
773 unsigned char MinGrant; /* 11 Minimum grant */
774 unsigned char MaxLat; /* Maximum Latency */
775 ushort SubSysVId; /* 12 Subsystem Vendor Id */
776 ushort SubSysId; /* 13 Subsystem ID */
777 ushort FlashSize; /* 14 Flash size (bytes / 4K) */
778 ushort DSize2Pci; /* 15 DRAM size to PCI (bytes / 64K) */
779 ushort RSize2Pci; /* 16 Flash (ROM extension) size to
781 ushort DeviceId1; /* 17 Device Id (function 1) */
782 ushort DeviceId2; /* 18 Device Id (function 2) */
783 ushort CfgByte6; /* 19 Device Status Config Bytes 6-7 */
784 ushort PMECapab; /* 20 Power Mgment capabilities */
785 unsigned char MSICapab; /* 21 MSI capabilities */
786 unsigned char ClockDivider; /* Clock divider */
787 ushort PciStatusLow; /* 22 PCI Status bits 15:0 */
788 ushort PciStatusHigh; /* 23 PCI Status bits 31:16 */
789 ushort DramConfigLow; /* 24 DRAM Configuration bits 15:0 */
790 ushort DramConfigHigh; /* 25 DRAM Configuration bits 31:16 */
791 ushort DramSize; /* 26 DRAM size (bytes / 64K) */
792 ushort GpioTbiCtl;/* 27 GPIO/TBI controls for functions 1/0 */
793 ushort EepromSize; /* 28 EEPROM Size */
794 struct slic_config_mac MacInfo[2]; /* 29 MAC addresses (2 ports) */
795 unsigned char FruFormat; /* 35 Alacritech FRU format type */
796 struct atk_fru AtkFru; /* Alacritech FRU information */
797 unsigned char OemFruFormat; /* optional OEM FRU format type */
798 union oemfru OemFru; /* optional OEM FRU information */
799 unsigned char Pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes
800 * (if OEM FRU info exists) and two unusable
805 #define MAX_EECODE_SIZE sizeof(struct slic_eeprom)
806 #define MIN_EECODE_SIZE 0x62 /* code size without optional OEM FRU stuff */
808 /* SLIC CONFIG structure
810 This structure lives in the CARD structure and is valid for all
811 board types. It is filled in from the appropriate EEPROM structure
812 by SlicGetConfigData().
815 bool EepromValid; /* Valid EEPROM flag (checksum good?) */
816 ushort DramSize; /* DRAM size (bytes / 64K) */
817 struct slic_config_mac MacInfo[SLIC_NBR_MACS]; /* MAC addresses */
818 unsigned char FruFormat; /* Alacritech FRU format type */
819 struct atk_fru AtkFru; /* Alacritech FRU information */
820 unsigned char OemFruFormat; /* optional OEM FRU format type */
822 struct vendor1_fru vendor1_fru;
823 struct vendor2_fru vendor2_fru;
824 struct vendor3_fru vendor3_fru;
825 struct vendor4_fru vendor4_fru;