Merge commit 'v2.6.27-rc3' into x86/urgent
[linux-2.6] / arch / sparc64 / kernel / pci_sabre.c
1 /* pci_sabre.c: Sabre specific PCI controller support.
2  *
3  * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
4  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
5  * Copyright (C) 1999 Jakub Jelinek   (jakub@redhat.com)
6  */
7
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14 #include <linux/of_device.h>
15
16 #include <asm/apb.h>
17 #include <asm/iommu.h>
18 #include <asm/irq.h>
19 #include <asm/smp.h>
20 #include <asm/oplib.h>
21 #include <asm/prom.h>
22
23 #include "pci_impl.h"
24 #include "iommu_common.h"
25
26 /* All SABRE registers are 64-bits.  The following accessor
27  * routines are how they are accessed.  The REG parameter
28  * is a physical address.
29  */
30 #define sabre_read(__reg) \
31 ({      u64 __ret; \
32         __asm__ __volatile__("ldxa [%1] %2, %0" \
33                              : "=r" (__ret) \
34                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
35                              : "memory"); \
36         __ret; \
37 })
38 #define sabre_write(__reg, __val) \
39         __asm__ __volatile__("stxa %0, [%1] %2" \
40                              : /* no outputs */ \
41                              : "r" (__val), "r" (__reg), \
42                                "i" (ASI_PHYS_BYPASS_EC_E) \
43                              : "memory")
44
45 /* SABRE PCI controller register offsets and definitions. */
46 #define SABRE_UE_AFSR           0x0030UL
47 #define  SABRE_UEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
48 #define  SABRE_UEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
49 #define  SABRE_UEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
50 #define  SABRE_UEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
51 #define  SABRE_UEAFSR_SDTE       0x0200000000000000UL   /* Secondary DMA Translation Error */
52 #define  SABRE_UEAFSR_PDTE       0x0100000000000000UL   /* Primary DMA Translation Error */
53 #define  SABRE_UEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
54 #define  SABRE_UEAFSR_OFF        0x00000000e0000000UL   /* Offset (AFAR bits [5:3] */
55 #define  SABRE_UEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
56 #define SABRE_UECE_AFAR         0x0038UL
57 #define SABRE_CE_AFSR           0x0040UL
58 #define  SABRE_CEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
59 #define  SABRE_CEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
60 #define  SABRE_CEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
61 #define  SABRE_CEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
62 #define  SABRE_CEAFSR_ESYND      0x00ff000000000000UL   /* ECC Syndrome */
63 #define  SABRE_CEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
64 #define  SABRE_CEAFSR_OFF        0x00000000e0000000UL   /* Offset */
65 #define  SABRE_CEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
66 #define SABRE_UECE_AFAR_ALIAS   0x0048UL        /* Aliases to 0x0038 */
67 #define SABRE_IOMMU_CONTROL     0x0200UL
68 #define  SABRE_IOMMUCTRL_ERRSTS  0x0000000006000000UL   /* Error status bits */
69 #define  SABRE_IOMMUCTRL_ERR     0x0000000001000000UL   /* Error present in IOTLB */
70 #define  SABRE_IOMMUCTRL_LCKEN   0x0000000000800000UL   /* IOTLB lock enable */
71 #define  SABRE_IOMMUCTRL_LCKPTR  0x0000000000780000UL   /* IOTLB lock pointer */
72 #define  SABRE_IOMMUCTRL_TSBSZ   0x0000000000070000UL   /* TSB Size */
73 #define  SABRE_IOMMU_TSBSZ_1K   0x0000000000000000
74 #define  SABRE_IOMMU_TSBSZ_2K   0x0000000000010000
75 #define  SABRE_IOMMU_TSBSZ_4K   0x0000000000020000
76 #define  SABRE_IOMMU_TSBSZ_8K   0x0000000000030000
77 #define  SABRE_IOMMU_TSBSZ_16K  0x0000000000040000
78 #define  SABRE_IOMMU_TSBSZ_32K  0x0000000000050000
79 #define  SABRE_IOMMU_TSBSZ_64K  0x0000000000060000
80 #define  SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
81 #define  SABRE_IOMMUCTRL_TBWSZ   0x0000000000000004UL   /* TSB assumed page size */
82 #define  SABRE_IOMMUCTRL_DENAB   0x0000000000000002UL   /* Diagnostic Mode Enable */
83 #define  SABRE_IOMMUCTRL_ENAB    0x0000000000000001UL   /* IOMMU Enable */
84 #define SABRE_IOMMU_TSBBASE     0x0208UL
85 #define SABRE_IOMMU_FLUSH       0x0210UL
86 #define SABRE_IMAP_A_SLOT0      0x0c00UL
87 #define SABRE_IMAP_B_SLOT0      0x0c20UL
88 #define SABRE_IMAP_SCSI         0x1000UL
89 #define SABRE_IMAP_ETH          0x1008UL
90 #define SABRE_IMAP_BPP          0x1010UL
91 #define SABRE_IMAP_AU_REC       0x1018UL
92 #define SABRE_IMAP_AU_PLAY      0x1020UL
93 #define SABRE_IMAP_PFAIL        0x1028UL
94 #define SABRE_IMAP_KMS          0x1030UL
95 #define SABRE_IMAP_FLPY         0x1038UL
96 #define SABRE_IMAP_SHW          0x1040UL
97 #define SABRE_IMAP_KBD          0x1048UL
98 #define SABRE_IMAP_MS           0x1050UL
99 #define SABRE_IMAP_SER          0x1058UL
100 #define SABRE_IMAP_UE           0x1070UL
101 #define SABRE_IMAP_CE           0x1078UL
102 #define SABRE_IMAP_PCIERR       0x1080UL
103 #define SABRE_IMAP_GFX          0x1098UL
104 #define SABRE_IMAP_EUPA         0x10a0UL
105 #define SABRE_ICLR_A_SLOT0      0x1400UL
106 #define SABRE_ICLR_B_SLOT0      0x1480UL
107 #define SABRE_ICLR_SCSI         0x1800UL
108 #define SABRE_ICLR_ETH          0x1808UL
109 #define SABRE_ICLR_BPP          0x1810UL
110 #define SABRE_ICLR_AU_REC       0x1818UL
111 #define SABRE_ICLR_AU_PLAY      0x1820UL
112 #define SABRE_ICLR_PFAIL        0x1828UL
113 #define SABRE_ICLR_KMS          0x1830UL
114 #define SABRE_ICLR_FLPY         0x1838UL
115 #define SABRE_ICLR_SHW          0x1840UL
116 #define SABRE_ICLR_KBD          0x1848UL
117 #define SABRE_ICLR_MS           0x1850UL
118 #define SABRE_ICLR_SER          0x1858UL
119 #define SABRE_ICLR_UE           0x1870UL
120 #define SABRE_ICLR_CE           0x1878UL
121 #define SABRE_ICLR_PCIERR       0x1880UL
122 #define SABRE_WRSYNC            0x1c20UL
123 #define SABRE_PCICTRL           0x2000UL
124 #define  SABRE_PCICTRL_MRLEN     0x0000001000000000UL   /* Use MemoryReadLine for block loads/stores */
125 #define  SABRE_PCICTRL_SERR      0x0000000400000000UL   /* Set when SERR asserted on PCI bus */
126 #define  SABRE_PCICTRL_ARBPARK   0x0000000000200000UL   /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
127 #define  SABRE_PCICTRL_CPUPRIO   0x0000000000100000UL   /* Ultra-IIi granted every other bus cycle */
128 #define  SABRE_PCICTRL_ARBPRIO   0x00000000000f0000UL   /* Slot which is granted every other bus cycle */
129 #define  SABRE_PCICTRL_ERREN     0x0000000000000100UL   /* PCI Error Interrupt Enable */
130 #define  SABRE_PCICTRL_RTRYWE    0x0000000000000080UL   /* DMA Flow Control 0=wait-if-possible 1=retry */
131 #define  SABRE_PCICTRL_AEN       0x000000000000000fUL   /* Slot PCI arbitration enables */
132 #define SABRE_PIOAFSR           0x2010UL
133 #define  SABRE_PIOAFSR_PMA       0x8000000000000000UL   /* Primary Master Abort */
134 #define  SABRE_PIOAFSR_PTA       0x4000000000000000UL   /* Primary Target Abort */
135 #define  SABRE_PIOAFSR_PRTRY     0x2000000000000000UL   /* Primary Excessive Retries */
136 #define  SABRE_PIOAFSR_PPERR     0x1000000000000000UL   /* Primary Parity Error */
137 #define  SABRE_PIOAFSR_SMA       0x0800000000000000UL   /* Secondary Master Abort */
138 #define  SABRE_PIOAFSR_STA       0x0400000000000000UL   /* Secondary Target Abort */
139 #define  SABRE_PIOAFSR_SRTRY     0x0200000000000000UL   /* Secondary Excessive Retries */
140 #define  SABRE_PIOAFSR_SPERR     0x0100000000000000UL   /* Secondary Parity Error */
141 #define  SABRE_PIOAFSR_BMSK      0x0000ffff00000000UL   /* Byte Mask */
142 #define  SABRE_PIOAFSR_BLK       0x0000000080000000UL   /* Was Block Operation */
143 #define SABRE_PIOAFAR           0x2018UL
144 #define SABRE_PCIDIAG           0x2020UL
145 #define  SABRE_PCIDIAG_DRTRY     0x0000000000000040UL   /* Disable PIO Retry Limit */
146 #define  SABRE_PCIDIAG_IPAPAR    0x0000000000000008UL   /* Invert PIO Address Parity */
147 #define  SABRE_PCIDIAG_IPDPAR    0x0000000000000004UL   /* Invert PIO Data Parity */
148 #define  SABRE_PCIDIAG_IDDPAR    0x0000000000000002UL   /* Invert DMA Data Parity */
149 #define  SABRE_PCIDIAG_ELPBK     0x0000000000000001UL   /* Loopback Enable - not supported */
150 #define SABRE_PCITASR           0x2028UL
151 #define  SABRE_PCITASR_EF        0x0000000000000080UL   /* Respond to 0xe0000000-0xffffffff */
152 #define  SABRE_PCITASR_CD        0x0000000000000040UL   /* Respond to 0xc0000000-0xdfffffff */
153 #define  SABRE_PCITASR_AB        0x0000000000000020UL   /* Respond to 0xa0000000-0xbfffffff */
154 #define  SABRE_PCITASR_89        0x0000000000000010UL   /* Respond to 0x80000000-0x9fffffff */
155 #define  SABRE_PCITASR_67        0x0000000000000008UL   /* Respond to 0x60000000-0x7fffffff */
156 #define  SABRE_PCITASR_45        0x0000000000000004UL   /* Respond to 0x40000000-0x5fffffff */
157 #define  SABRE_PCITASR_23        0x0000000000000002UL   /* Respond to 0x20000000-0x3fffffff */
158 #define  SABRE_PCITASR_01        0x0000000000000001UL   /* Respond to 0x00000000-0x1fffffff */
159 #define SABRE_PIOBUF_DIAG       0x5000UL
160 #define SABRE_DMABUF_DIAGLO     0x5100UL
161 #define SABRE_DMABUF_DIAGHI     0x51c0UL
162 #define SABRE_IMAP_GFX_ALIAS    0x6000UL        /* Aliases to 0x1098 */
163 #define SABRE_IMAP_EUPA_ALIAS   0x8000UL        /* Aliases to 0x10a0 */
164 #define SABRE_IOMMU_VADIAG      0xa400UL
165 #define SABRE_IOMMU_TCDIAG      0xa408UL
166 #define SABRE_IOMMU_TAG         0xa580UL
167 #define  SABRE_IOMMUTAG_ERRSTS   0x0000000001800000UL   /* Error status bits */
168 #define  SABRE_IOMMUTAG_ERR      0x0000000000400000UL   /* Error present */
169 #define  SABRE_IOMMUTAG_WRITE    0x0000000000200000UL   /* Page is writable */
170 #define  SABRE_IOMMUTAG_STREAM   0x0000000000100000UL   /* Streamable bit - unused */
171 #define  SABRE_IOMMUTAG_SIZE     0x0000000000080000UL   /* 0=8k 1=16k */
172 #define  SABRE_IOMMUTAG_VPN      0x000000000007ffffUL   /* Virtual Page Number [31:13] */
173 #define SABRE_IOMMU_DATA        0xa600UL
174 #define SABRE_IOMMUDATA_VALID    0x0000000040000000UL   /* Valid */
175 #define SABRE_IOMMUDATA_USED     0x0000000020000000UL   /* Used (for LRU algorithm) */
176 #define SABRE_IOMMUDATA_CACHE    0x0000000010000000UL   /* Cacheable */
177 #define SABRE_IOMMUDATA_PPN      0x00000000001fffffUL   /* Physical Page Number [33:13] */
178 #define SABRE_PCI_IRQSTATE      0xa800UL
179 #define SABRE_OBIO_IRQSTATE     0xa808UL
180 #define SABRE_FFBCFG            0xf000UL
181 #define  SABRE_FFBCFG_SPRQS      0x000000000f000000     /* Slave P_RQST queue size */
182 #define  SABRE_FFBCFG_ONEREAD    0x0000000000004000     /* Slave supports one outstanding read */
183 #define SABRE_MCCTRL0           0xf010UL
184 #define  SABRE_MCCTRL0_RENAB     0x0000000080000000     /* Refresh Enable */
185 #define  SABRE_MCCTRL0_EENAB     0x0000000010000000     /* Enable all ECC functions */
186 #define  SABRE_MCCTRL0_11BIT     0x0000000000001000     /* Enable 11-bit column addressing */
187 #define  SABRE_MCCTRL0_DPP       0x0000000000000f00     /* DIMM Pair Present Bits */
188 #define  SABRE_MCCTRL0_RINTVL    0x00000000000000ff     /* Refresh Interval */
189 #define SABRE_MCCTRL1           0xf018UL
190 #define  SABRE_MCCTRL1_AMDC      0x0000000038000000     /* Advance Memdata Clock */
191 #define  SABRE_MCCTRL1_ARDC      0x0000000007000000     /* Advance DRAM Read Data Clock */
192 #define  SABRE_MCCTRL1_CSR       0x0000000000e00000     /* CAS to RAS delay for CBR refresh */
193 #define  SABRE_MCCTRL1_CASRW     0x00000000001c0000     /* CAS length for read/write */
194 #define  SABRE_MCCTRL1_RCD       0x0000000000038000     /* RAS to CAS delay */
195 #define  SABRE_MCCTRL1_CP        0x0000000000007000     /* CAS Precharge */
196 #define  SABRE_MCCTRL1_RP        0x0000000000000e00     /* RAS Precharge */
197 #define  SABRE_MCCTRL1_RAS       0x00000000000001c0     /* Length of RAS for refresh */
198 #define  SABRE_MCCTRL1_CASRW2    0x0000000000000038     /* Must be same as CASRW */
199 #define  SABRE_MCCTRL1_RSC       0x0000000000000007     /* RAS after CAS hold time */
200 #define SABRE_RESETCTRL         0xf020UL
201
202 #define SABRE_CONFIGSPACE       0x001000000UL
203 #define SABRE_IOSPACE           0x002000000UL
204 #define SABRE_IOSPACE_SIZE      0x000ffffffUL
205 #define SABRE_MEMSPACE          0x100000000UL
206 #define SABRE_MEMSPACE_SIZE     0x07fffffffUL
207
208 static int hummingbird_p;
209 static struct pci_bus *sabre_root_bus;
210
211 /* SABRE error handling support. */
212 static void sabre_check_iommu_error(struct pci_pbm_info *pbm,
213                                     unsigned long afsr,
214                                     unsigned long afar)
215 {
216         struct iommu *iommu = pbm->iommu;
217         unsigned long iommu_tag[16];
218         unsigned long iommu_data[16];
219         unsigned long flags;
220         u64 control;
221         int i;
222
223         spin_lock_irqsave(&iommu->lock, flags);
224         control = sabre_read(iommu->iommu_control);
225         if (control & SABRE_IOMMUCTRL_ERR) {
226                 char *type_string;
227
228                 /* Clear the error encountered bit.
229                  * NOTE: On Sabre this is write 1 to clear,
230                  *       which is different from Psycho.
231                  */
232                 sabre_write(iommu->iommu_control, control);
233                 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
234                 case 1:
235                         type_string = "Invalid Error";
236                         break;
237                 case 3:
238                         type_string = "ECC Error";
239                         break;
240                 default:
241                         type_string = "Unknown";
242                         break;
243                 };
244                 printk("%s: IOMMU Error, type[%s]\n",
245                        pbm->name, type_string);
246
247                 /* Enter diagnostic mode and probe for error'd
248                  * entries in the IOTLB.
249                  */
250                 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
251                 sabre_write(iommu->iommu_control,
252                             (control | SABRE_IOMMUCTRL_DENAB));
253                 for (i = 0; i < 16; i++) {
254                         unsigned long base = pbm->controller_regs;
255
256                         iommu_tag[i] =
257                                 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
258                         iommu_data[i] =
259                                 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
260                         sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
261                         sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
262                 }
263                 sabre_write(iommu->iommu_control, control);
264
265                 for (i = 0; i < 16; i++) {
266                         unsigned long tag, data;
267
268                         tag = iommu_tag[i];
269                         if (!(tag & SABRE_IOMMUTAG_ERR))
270                                 continue;
271
272                         data = iommu_data[i];
273                         switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
274                         case 1:
275                                 type_string = "Invalid Error";
276                                 break;
277                         case 3:
278                                 type_string = "ECC Error";
279                                 break;
280                         default:
281                                 type_string = "Unknown";
282                                 break;
283                         };
284                         printk("%s: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
285                                pbm->name, i, tag, type_string,
286                                ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
287                                ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
288                                ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
289                         printk("%s: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
290                                pbm->name, i, data,
291                                ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
292                                ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
293                                ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
294                                ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
295                 }
296         }
297         spin_unlock_irqrestore(&iommu->lock, flags);
298 }
299
300 static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
301 {
302         struct pci_pbm_info *pbm = dev_id;
303         unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;
304         unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
305         unsigned long afsr, afar, error_bits;
306         int reported;
307
308         /* Latch uncorrectable error status. */
309         afar = sabre_read(afar_reg);
310         afsr = sabre_read(afsr_reg);
311
312         /* Clear the primary/secondary error status bits. */
313         error_bits = afsr &
314                 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
315                  SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
316                  SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
317         if (!error_bits)
318                 return IRQ_NONE;
319         sabre_write(afsr_reg, error_bits);
320
321         /* Log the error. */
322         printk("%s: Uncorrectable Error, primary error type[%s%s]\n",
323                pbm->name,
324                ((error_bits & SABRE_UEAFSR_PDRD) ?
325                 "DMA Read" :
326                 ((error_bits & SABRE_UEAFSR_PDWR) ?
327                  "DMA Write" : "???")),
328                ((error_bits & SABRE_UEAFSR_PDTE) ?
329                 ":Translation Error" : ""));
330         printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
331                pbm->name,
332                (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
333                (afsr & SABRE_UEAFSR_OFF) >> 29UL,
334                ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
335         printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
336         printk("%s: UE Secondary errors [", pbm->name);
337         reported = 0;
338         if (afsr & SABRE_UEAFSR_SDRD) {
339                 reported++;
340                 printk("(DMA Read)");
341         }
342         if (afsr & SABRE_UEAFSR_SDWR) {
343                 reported++;
344                 printk("(DMA Write)");
345         }
346         if (afsr & SABRE_UEAFSR_SDTE) {
347                 reported++;
348                 printk("(Translation Error)");
349         }
350         if (!reported)
351                 printk("(none)");
352         printk("]\n");
353
354         /* Interrogate IOMMU for error status. */
355         sabre_check_iommu_error(pbm, afsr, afar);
356
357         return IRQ_HANDLED;
358 }
359
360 static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
361 {
362         struct pci_pbm_info *pbm = dev_id;
363         unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;
364         unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
365         unsigned long afsr, afar, error_bits;
366         int reported;
367
368         /* Latch error status. */
369         afar = sabre_read(afar_reg);
370         afsr = sabre_read(afsr_reg);
371
372         /* Clear primary/secondary error status bits. */
373         error_bits = afsr &
374                 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
375                  SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
376         if (!error_bits)
377                 return IRQ_NONE;
378         sabre_write(afsr_reg, error_bits);
379
380         /* Log the error. */
381         printk("%s: Correctable Error, primary error type[%s]\n",
382                pbm->name,
383                ((error_bits & SABRE_CEAFSR_PDRD) ?
384                 "DMA Read" :
385                 ((error_bits & SABRE_CEAFSR_PDWR) ?
386                  "DMA Write" : "???")));
387
388         /* XXX Use syndrome and afar to print out module string just like
389          * XXX UDB CE trap handler does... -DaveM
390          */
391         printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
392                "was_block(%d)\n",
393                pbm->name,
394                (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
395                (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
396                (afsr & SABRE_CEAFSR_OFF) >> 29UL,
397                ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
398         printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
399         printk("%s: CE Secondary errors [", pbm->name);
400         reported = 0;
401         if (afsr & SABRE_CEAFSR_SDRD) {
402                 reported++;
403                 printk("(DMA Read)");
404         }
405         if (afsr & SABRE_CEAFSR_SDWR) {
406                 reported++;
407                 printk("(DMA Write)");
408         }
409         if (!reported)
410                 printk("(none)");
411         printk("]\n");
412
413         return IRQ_HANDLED;
414 }
415
416 static irqreturn_t sabre_pcierr_intr_other(struct pci_pbm_info *pbm)
417 {
418         unsigned long csr_reg, csr, csr_error_bits;
419         irqreturn_t ret = IRQ_NONE;
420         u16 stat;
421
422         csr_reg = pbm->controller_regs + SABRE_PCICTRL;
423         csr = sabre_read(csr_reg);
424         csr_error_bits =
425                 csr & SABRE_PCICTRL_SERR;
426         if (csr_error_bits) {
427                 /* Clear the errors.  */
428                 sabre_write(csr_reg, csr);
429
430                 /* Log 'em.  */
431                 if (csr_error_bits & SABRE_PCICTRL_SERR)
432                         printk("%s: PCI SERR signal asserted.\n",
433                                pbm->name);
434                 ret = IRQ_HANDLED;
435         }
436         pci_bus_read_config_word(sabre_root_bus, 0,
437                                  PCI_STATUS, &stat);
438         if (stat & (PCI_STATUS_PARITY |
439                     PCI_STATUS_SIG_TARGET_ABORT |
440                     PCI_STATUS_REC_TARGET_ABORT |
441                     PCI_STATUS_REC_MASTER_ABORT |
442                     PCI_STATUS_SIG_SYSTEM_ERROR)) {
443                 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
444                        pbm->name, stat);
445                 pci_bus_write_config_word(sabre_root_bus, 0,
446                                           PCI_STATUS, 0xffff);
447                 ret = IRQ_HANDLED;
448         }
449         return ret;
450 }
451
452 static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
453 {
454         struct pci_pbm_info *pbm = dev_id;
455         unsigned long afsr_reg, afar_reg;
456         unsigned long afsr, afar, error_bits;
457         int reported;
458
459         afsr_reg = pbm->controller_regs + SABRE_PIOAFSR;
460         afar_reg = pbm->controller_regs + SABRE_PIOAFAR;
461
462         /* Latch error status. */
463         afar = sabre_read(afar_reg);
464         afsr = sabre_read(afsr_reg);
465
466         /* Clear primary/secondary error status bits. */
467         error_bits = afsr &
468                 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
469                  SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
470                  SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
471                  SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
472         if (!error_bits)
473                 return sabre_pcierr_intr_other(pbm);
474         sabre_write(afsr_reg, error_bits);
475
476         /* Log the error. */
477         printk("%s: PCI Error, primary error type[%s]\n",
478                pbm->name,
479                (((error_bits & SABRE_PIOAFSR_PMA) ?
480                  "Master Abort" :
481                  ((error_bits & SABRE_PIOAFSR_PTA) ?
482                   "Target Abort" :
483                   ((error_bits & SABRE_PIOAFSR_PRTRY) ?
484                    "Excessive Retries" :
485                    ((error_bits & SABRE_PIOAFSR_PPERR) ?
486                     "Parity Error" : "???"))))));
487         printk("%s: bytemask[%04lx] was_block(%d)\n",
488                pbm->name,
489                (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
490                (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
491         printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
492         printk("%s: PCI Secondary errors [", pbm->name);
493         reported = 0;
494         if (afsr & SABRE_PIOAFSR_SMA) {
495                 reported++;
496                 printk("(Master Abort)");
497         }
498         if (afsr & SABRE_PIOAFSR_STA) {
499                 reported++;
500                 printk("(Target Abort)");
501         }
502         if (afsr & SABRE_PIOAFSR_SRTRY) {
503                 reported++;
504                 printk("(Excessive Retries)");
505         }
506         if (afsr & SABRE_PIOAFSR_SPERR) {
507                 reported++;
508                 printk("(Parity Error)");
509         }
510         if (!reported)
511                 printk("(none)");
512         printk("]\n");
513
514         /* For the error types shown, scan both PCI buses for devices
515          * which have logged that error type.
516          */
517
518         /* If we see a Target Abort, this could be the result of an
519          * IOMMU translation error of some sort.  It is extremely
520          * useful to log this information as usually it indicates
521          * a bug in the IOMMU support code or a PCI device driver.
522          */
523         if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
524                 sabre_check_iommu_error(pbm, afsr, afar);
525                 pci_scan_for_target_abort(pbm, pbm->pci_bus);
526         }
527         if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA))
528                 pci_scan_for_master_abort(pbm, pbm->pci_bus);
529
530         /* For excessive retries, SABRE/PBM will abort the device
531          * and there is no way to specifically check for excessive
532          * retries in the config space status registers.  So what
533          * we hope is that we'll catch it via the master/target
534          * abort events.
535          */
536
537         if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR))
538                 pci_scan_for_parity_error(pbm, pbm->pci_bus);
539
540         return IRQ_HANDLED;
541 }
542
543 static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
544 {
545         struct device_node *dp = pbm->prom_node;
546         struct of_device *op;
547         unsigned long base = pbm->controller_regs;
548         u64 tmp;
549         int err;
550
551         if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
552                 dp = dp->parent;
553
554         op = of_find_device_by_node(dp);
555         if (!op)
556                 return;
557
558         /* Sabre/Hummingbird IRQ property layout is:
559          * 0: PCI ERR
560          * 1: UE ERR
561          * 2: CE ERR
562          * 3: POWER FAIL
563          */
564         if (op->num_irqs < 4)
565                 return;
566
567         /* We clear the error bits in the appropriate AFSR before
568          * registering the handler so that we don't get spurious
569          * interrupts.
570          */
571         sabre_write(base + SABRE_UE_AFSR,
572                     (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
573                      SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
574                      SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
575
576         err = request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
577         if (err)
578                 printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n",
579                        pbm->name, err);
580
581         sabre_write(base + SABRE_CE_AFSR,
582                     (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
583                      SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
584
585         err = request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
586         if (err)
587                 printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n",
588                        pbm->name, err);
589         err = request_irq(op->irqs[0], sabre_pcierr_intr, 0,
590                           "SABRE_PCIERR", pbm);
591         if (err)
592                 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n",
593                        pbm->name, err);
594
595         tmp = sabre_read(base + SABRE_PCICTRL);
596         tmp |= SABRE_PCICTRL_ERREN;
597         sabre_write(base + SABRE_PCICTRL, tmp);
598 }
599
600 static void apb_init(struct pci_bus *sabre_bus)
601 {
602         struct pci_dev *pdev;
603
604         list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
605                 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
606                     pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
607                         u16 word16;
608
609                         pci_read_config_word(pdev, PCI_COMMAND, &word16);
610                         word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
611                                 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
612                                 PCI_COMMAND_IO;
613                         pci_write_config_word(pdev, PCI_COMMAND, word16);
614
615                         /* Status register bits are "write 1 to clear". */
616                         pci_write_config_word(pdev, PCI_STATUS, 0xffff);
617                         pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
618
619                         /* Use a primary/seconday latency timer value
620                          * of 64.
621                          */
622                         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
623                         pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
624
625                         /* Enable reporting/forwarding of master aborts,
626                          * parity, and SERR.
627                          */
628                         pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
629                                               (PCI_BRIDGE_CTL_PARITY |
630                                                PCI_BRIDGE_CTL_SERR |
631                                                PCI_BRIDGE_CTL_MASTER_ABORT));
632                 }
633         }
634 }
635
636 static void __init sabre_scan_bus(struct pci_pbm_info *pbm)
637 {
638         static int once;
639
640         /* The APB bridge speaks to the Sabre host PCI bridge
641          * at 66Mhz, but the front side of APB runs at 33Mhz
642          * for both segments.
643          *
644          * Hummingbird systems do not use APB, so they run
645          * at 66MHZ.
646          */
647         if (hummingbird_p)
648                 pbm->is_66mhz_capable = 1;
649         else
650                 pbm->is_66mhz_capable = 0;
651
652         /* This driver has not been verified to handle
653          * multiple SABREs yet, so trap this.
654          *
655          * Also note that the SABRE host bridge is hardwired
656          * to live at bus 0.
657          */
658         if (once != 0) {
659                 prom_printf("SABRE: Multiple controllers unsupported.\n");
660                 prom_halt();
661         }
662         once++;
663
664         pbm->pci_bus = pci_scan_one_pbm(pbm);
665         if (!pbm->pci_bus)
666                 return;
667
668         sabre_root_bus = pbm->pci_bus;
669
670         apb_init(pbm->pci_bus);
671
672         sabre_register_error_handlers(pbm);
673 }
674
675 static int sabre_iommu_init(struct pci_pbm_info *pbm,
676                             int tsbsize, unsigned long dvma_offset,
677                             u32 dma_mask)
678 {
679         struct iommu *iommu = pbm->iommu;
680         unsigned long i;
681         u64 control;
682         int err;
683
684         /* Register addresses. */
685         iommu->iommu_control  = pbm->controller_regs + SABRE_IOMMU_CONTROL;
686         iommu->iommu_tsbbase  = pbm->controller_regs + SABRE_IOMMU_TSBBASE;
687         iommu->iommu_flush    = pbm->controller_regs + SABRE_IOMMU_FLUSH;
688         iommu->iommu_tags     = iommu->iommu_flush + (0xa580UL - 0x0210UL);
689         iommu->write_complete_reg = pbm->controller_regs + SABRE_WRSYNC;
690         /* Sabre's IOMMU lacks ctx flushing. */
691         iommu->iommu_ctxflush = 0;
692                                         
693         /* Invalidate TLB Entries. */
694         control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);
695         control |= SABRE_IOMMUCTRL_DENAB;
696         sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);
697
698         for(i = 0; i < 16; i++) {
699                 sabre_write(pbm->controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
700                 sabre_write(pbm->controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
701         }
702
703         /* Leave diag mode enabled for full-flushing done
704          * in pci_iommu.c
705          */
706         err = iommu_table_init(iommu, tsbsize * 1024 * 8,
707                                dvma_offset, dma_mask, pbm->numa_node);
708         if (err)
709                 return err;
710
711         sabre_write(pbm->controller_regs + SABRE_IOMMU_TSBBASE,
712                     __pa(iommu->page_table));
713
714         control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);
715         control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
716         control |= SABRE_IOMMUCTRL_ENAB;
717         switch(tsbsize) {
718         case 64:
719                 control |= SABRE_IOMMU_TSBSZ_64K;
720                 break;
721         case 128:
722                 control |= SABRE_IOMMU_TSBSZ_128K;
723                 break;
724         default:
725                 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
726                 prom_halt();
727                 break;
728         }
729         sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);
730
731         return 0;
732 }
733
734 static void __init sabre_pbm_init(struct pci_controller_info *p,
735                                   struct pci_pbm_info *pbm, struct device_node *dp)
736 {
737         pbm->name = dp->full_name;
738         printk("%s: SABRE PCI Bus Module\n", pbm->name);
739
740         pbm->numa_node = -1;
741
742         pbm->scan_bus = sabre_scan_bus;
743         pbm->pci_ops = &sun4u_pci_ops;
744         pbm->config_space_reg_bits = 8;
745
746         pbm->index = pci_num_pbms++;
747
748         pbm->chip_type = PBM_CHIP_TYPE_SABRE;
749         pbm->parent = p;
750         pbm->prom_node = dp;
751         pci_get_pbm_props(pbm);
752
753         pci_determine_mem_io_space(pbm);
754 }
755
756 void __init sabre_init(struct device_node *dp, char *model_name)
757 {
758         const struct linux_prom64_registers *pr_regs;
759         struct pci_controller_info *p;
760         struct pci_pbm_info *pbm;
761         struct iommu *iommu;
762         int tsbsize;
763         const u32 *vdma;
764         u32 upa_portid, dma_mask;
765         u64 clear_irq;
766
767         hummingbird_p = 0;
768         if (!strcmp(model_name, "pci108e,a001"))
769                 hummingbird_p = 1;
770         else if (!strcmp(model_name, "SUNW,sabre")) {
771                 const char *compat = of_get_property(dp, "compatible", NULL);
772                 if (compat && !strcmp(compat, "pci108e,a001"))
773                         hummingbird_p = 1;
774                 if (!hummingbird_p) {
775                         struct device_node *dp;
776
777                         /* Of course, Sun has to encode things a thousand
778                          * different ways, inconsistently.
779                          */
780                         for_each_node_by_type(dp, "cpu") {
781                                 if (!strcmp(dp->name, "SUNW,UltraSPARC-IIe"))
782                                         hummingbird_p = 1;
783                         }
784                 }
785         }
786
787         p = kzalloc(sizeof(*p), GFP_ATOMIC);
788         if (!p)
789                 goto fatal_memory_error;
790
791         iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
792         if (!iommu)
793                 goto fatal_memory_error;
794         pbm = &p->pbm_A;
795         pbm->iommu = iommu;
796
797         upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
798
799         pbm->next = pci_pbm_root;
800         pci_pbm_root = pbm;
801
802         pbm->portid = upa_portid;
803
804         /*
805          * Map in SABRE register set and report the presence of this SABRE.
806          */
807         
808         pr_regs = of_get_property(dp, "reg", NULL);
809
810         /*
811          * First REG in property is base of entire SABRE register space.
812          */
813         pbm->controller_regs = pr_regs[0].phys_addr;
814
815         /* Clear interrupts */
816
817         /* PCI first */
818         for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
819                 sabre_write(pbm->controller_regs + clear_irq, 0x0UL);
820
821         /* Then OBIO */
822         for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
823                 sabre_write(pbm->controller_regs + clear_irq, 0x0UL);
824
825         /* Error interrupts are enabled later after the bus scan. */
826         sabre_write(pbm->controller_regs + SABRE_PCICTRL,
827                     (SABRE_PCICTRL_MRLEN   | SABRE_PCICTRL_SERR |
828                      SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
829
830         /* Now map in PCI config space for entire SABRE. */
831         pbm->config_space =
832                 (pbm->controller_regs + SABRE_CONFIGSPACE);
833
834         vdma = of_get_property(dp, "virtual-dma", NULL);
835
836         dma_mask = vdma[0];
837         switch(vdma[1]) {
838                 case 0x20000000:
839                         dma_mask |= 0x1fffffff;
840                         tsbsize = 64;
841                         break;
842                 case 0x40000000:
843                         dma_mask |= 0x3fffffff;
844                         tsbsize = 128;
845                         break;
846
847                 case 0x80000000:
848                         dma_mask |= 0x7fffffff;
849                         tsbsize = 128;
850                         break;
851                 default:
852                         prom_printf("SABRE: strange virtual-dma size.\n");
853                         prom_halt();
854         }
855
856         if (sabre_iommu_init(pbm, tsbsize, vdma[0], dma_mask))
857                 goto fatal_memory_error;
858
859         /*
860          * Look for APB underneath.
861          */
862         sabre_pbm_init(p, pbm, dp);
863         return;
864
865 fatal_memory_error:
866         prom_printf("SABRE: Fatal memory allocation error.\n");
867         prom_halt();
868 }