Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland...
[linux-2.6] / arch / sparc64 / kernel / pci_fire.c
1 /* pci_fire.c: Sun4u platform PCI-E controller support.
2  *
3  * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4  */
5 #include <linux/kernel.h>
6 #include <linux/pci.h>
7 #include <linux/slab.h>
8 #include <linux/init.h>
9 #include <linux/msi.h>
10 #include <linux/irq.h>
11
12 #include <asm/oplib.h>
13 #include <asm/prom.h>
14 #include <asm/irq.h>
15
16 #include "pci_impl.h"
17
18 #define fire_read(__reg) \
19 ({      u64 __ret; \
20         __asm__ __volatile__("ldxa [%1] %2, %0" \
21                              : "=r" (__ret) \
22                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
23                              : "memory"); \
24         __ret; \
25 })
26 #define fire_write(__reg, __val) \
27         __asm__ __volatile__("stxa %0, [%1] %2" \
28                              : /* no outputs */ \
29                              : "r" (__val), "r" (__reg), \
30                                "i" (ASI_PHYS_BYPASS_EC_E) \
31                              : "memory")
32
33 static void __init pci_fire_scan_bus(struct pci_pbm_info *pbm)
34 {
35         pbm->pci_bus = pci_scan_one_pbm(pbm);
36
37         /* XXX register error interrupt handlers XXX */
38 }
39
40 #define FIRE_IOMMU_CONTROL      0x40000UL
41 #define FIRE_IOMMU_TSBBASE      0x40008UL
42 #define FIRE_IOMMU_FLUSH        0x40100UL
43 #define FIRE_IOMMU_FLUSHINV     0x40108UL
44
45 static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
46 {
47         struct iommu *iommu = pbm->iommu;
48         u32 vdma[2], dma_mask;
49         u64 control;
50         int tsbsize, err;
51
52         /* No virtual-dma property on these guys, use largest size.  */
53         vdma[0] = 0xc0000000; /* base */
54         vdma[1] = 0x40000000; /* size */
55         dma_mask = 0xffffffff;
56         tsbsize = 128;
57
58         /* Register addresses. */
59         iommu->iommu_control  = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
60         iommu->iommu_tsbbase  = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
61         iommu->iommu_flush    = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
62         iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
63
64         /* We use the main control/status register of FIRE as the write
65          * completion register.
66          */
67         iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
68
69         /*
70          * Invalidate TLB Entries.
71          */
72         fire_write(iommu->iommu_flushinv, ~(u64)0);
73
74         err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
75                                pbm->numa_node);
76         if (err)
77                 return err;
78
79         fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL);
80
81         control = fire_read(iommu->iommu_control);
82         control |= (0x00000400 /* TSB cache snoop enable */     |
83                     0x00000300 /* Cache mode */                 |
84                     0x00000002 /* Bypass enable */              |
85                     0x00000001 /* Translation enable */);
86         fire_write(iommu->iommu_control, control);
87
88         return 0;
89 }
90
91 #ifdef CONFIG_PCI_MSI
92 struct pci_msiq_entry {
93         u64             word0;
94 #define MSIQ_WORD0_RESV                 0x8000000000000000UL
95 #define MSIQ_WORD0_FMT_TYPE             0x7f00000000000000UL
96 #define MSIQ_WORD0_FMT_TYPE_SHIFT       56
97 #define MSIQ_WORD0_LEN                  0x00ffc00000000000UL
98 #define MSIQ_WORD0_LEN_SHIFT            46
99 #define MSIQ_WORD0_ADDR0                0x00003fff00000000UL
100 #define MSIQ_WORD0_ADDR0_SHIFT          32
101 #define MSIQ_WORD0_RID                  0x00000000ffff0000UL
102 #define MSIQ_WORD0_RID_SHIFT            16
103 #define MSIQ_WORD0_DATA0                0x000000000000ffffUL
104 #define MSIQ_WORD0_DATA0_SHIFT          0
105
106 #define MSIQ_TYPE_MSG                   0x6
107 #define MSIQ_TYPE_MSI32                 0xb
108 #define MSIQ_TYPE_MSI64                 0xf
109
110         u64             word1;
111 #define MSIQ_WORD1_ADDR1                0xffffffffffff0000UL
112 #define MSIQ_WORD1_ADDR1_SHIFT          16
113 #define MSIQ_WORD1_DATA1                0x000000000000ffffUL
114 #define MSIQ_WORD1_DATA1_SHIFT          0
115
116         u64             resv[6];
117 };
118
119 /* All MSI registers are offset from pbm->pbm_regs */
120 #define EVENT_QUEUE_BASE_ADDR_REG       0x010000UL
121 #define  EVENT_QUEUE_BASE_ADDR_ALL_ONES 0xfffc000000000000UL
122
123 #define EVENT_QUEUE_CONTROL_SET(EQ)     (0x011000UL + (EQ) * 0x8UL)
124 #define  EVENT_QUEUE_CONTROL_SET_OFLOW  0x0200000000000000UL
125 #define  EVENT_QUEUE_CONTROL_SET_EN     0x0000100000000000UL
126
127 #define EVENT_QUEUE_CONTROL_CLEAR(EQ)   (0x011200UL + (EQ) * 0x8UL)
128 #define  EVENT_QUEUE_CONTROL_CLEAR_OF   0x0200000000000000UL
129 #define  EVENT_QUEUE_CONTROL_CLEAR_E2I  0x0000800000000000UL
130 #define  EVENT_QUEUE_CONTROL_CLEAR_DIS  0x0000100000000000UL
131
132 #define EVENT_QUEUE_STATE(EQ)           (0x011400UL + (EQ) * 0x8UL)
133 #define  EVENT_QUEUE_STATE_MASK         0x0000000000000007UL
134 #define  EVENT_QUEUE_STATE_IDLE         0x0000000000000001UL
135 #define  EVENT_QUEUE_STATE_ACTIVE       0x0000000000000002UL
136 #define  EVENT_QUEUE_STATE_ERROR        0x0000000000000004UL
137
138 #define EVENT_QUEUE_TAIL(EQ)            (0x011600UL + (EQ) * 0x8UL)
139 #define  EVENT_QUEUE_TAIL_OFLOW         0x0200000000000000UL
140 #define  EVENT_QUEUE_TAIL_VAL           0x000000000000007fUL
141
142 #define EVENT_QUEUE_HEAD(EQ)            (0x011800UL + (EQ) * 0x8UL)
143 #define  EVENT_QUEUE_HEAD_VAL           0x000000000000007fUL
144
145 #define MSI_MAP(MSI)                    (0x020000UL + (MSI) * 0x8UL)
146 #define  MSI_MAP_VALID                  0x8000000000000000UL
147 #define  MSI_MAP_EQWR_N                 0x4000000000000000UL
148 #define  MSI_MAP_EQNUM                  0x000000000000003fUL
149
150 #define MSI_CLEAR(MSI)                  (0x028000UL + (MSI) * 0x8UL)
151 #define  MSI_CLEAR_EQWR_N               0x4000000000000000UL
152
153 #define IMONDO_DATA0                    0x02C000UL
154 #define  IMONDO_DATA0_DATA              0xffffffffffffffc0UL
155
156 #define IMONDO_DATA1                    0x02C008UL
157 #define  IMONDO_DATA1_DATA              0xffffffffffffffffUL
158
159 #define MSI_32BIT_ADDR                  0x034000UL
160 #define  MSI_32BIT_ADDR_VAL             0x00000000ffff0000UL
161
162 #define MSI_64BIT_ADDR                  0x034008UL
163 #define  MSI_64BIT_ADDR_VAL             0xffffffffffff0000UL
164
165 static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
166                              unsigned long *head)
167 {
168         *head = fire_read(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
169         return 0;
170 }
171
172 static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
173                                 unsigned long *head, unsigned long *msi)
174 {
175         unsigned long type_fmt, type, msi_num;
176         struct pci_msiq_entry *base, *ep;
177
178         base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192));
179         ep = &base[*head];
180
181         if ((ep->word0 & MSIQ_WORD0_FMT_TYPE) == 0)
182                 return 0;
183
184         type_fmt = ((ep->word0 & MSIQ_WORD0_FMT_TYPE) >>
185                     MSIQ_WORD0_FMT_TYPE_SHIFT);
186         type = (type_fmt >> 3);
187         if (unlikely(type != MSIQ_TYPE_MSI32 &&
188                      type != MSIQ_TYPE_MSI64))
189                 return -EINVAL;
190
191         *msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>
192                           MSIQ_WORD0_DATA0_SHIFT);
193
194         fire_write(pbm->pbm_regs + MSI_CLEAR(msi_num),
195                    MSI_CLEAR_EQWR_N);
196
197         /* Clear the entry.  */
198         ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;
199
200         /* Go to next entry in ring.  */
201         (*head)++;
202         if (*head >= pbm->msiq_ent_count)
203                 *head = 0;
204
205         return 1;
206 }
207
208 static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
209                              unsigned long head)
210 {
211         fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid), head);
212         return 0;
213 }
214
215 static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
216                               unsigned long msi, int is_msi64)
217 {
218         u64 val;
219
220         val = fire_read(pbm->pbm_regs + MSI_MAP(msi));
221         val &= ~(MSI_MAP_EQNUM);
222         val |= msiqid;
223         fire_write(pbm->pbm_regs + MSI_MAP(msi), val);
224
225         fire_write(pbm->pbm_regs + MSI_CLEAR(msi),
226                    MSI_CLEAR_EQWR_N);
227
228         val = fire_read(pbm->pbm_regs + MSI_MAP(msi));
229         val |= MSI_MAP_VALID;
230         fire_write(pbm->pbm_regs + MSI_MAP(msi), val);
231
232         return 0;
233 }
234
235 static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
236 {
237         unsigned long msiqid;
238         u64 val;
239
240         val = fire_read(pbm->pbm_regs + MSI_MAP(msi));
241         msiqid = (val & MSI_MAP_EQNUM);
242
243         val &= ~MSI_MAP_VALID;
244
245         fire_write(pbm->pbm_regs + MSI_MAP(msi), val);
246
247         return 0;
248 }
249
250 static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm)
251 {
252         unsigned long pages, order, i;
253
254         order = get_order(512 * 1024);
255         pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
256         if (pages == 0UL) {
257                 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
258                        order);
259                 return -ENOMEM;
260         }
261         memset((char *)pages, 0, PAGE_SIZE << order);
262         pbm->msi_queues = (void *) pages;
263
264         fire_write(pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG,
265                    (EVENT_QUEUE_BASE_ADDR_ALL_ONES |
266                     __pa(pbm->msi_queues)));
267
268         fire_write(pbm->pbm_regs + IMONDO_DATA0,
269                    pbm->portid << 6);
270         fire_write(pbm->pbm_regs + IMONDO_DATA1, 0);
271
272         fire_write(pbm->pbm_regs + MSI_32BIT_ADDR,
273                    pbm->msi32_start);
274         fire_write(pbm->pbm_regs + MSI_64BIT_ADDR,
275                    pbm->msi64_start);
276
277         for (i = 0; i < pbm->msiq_num; i++) {
278                 fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(i), 0);
279                 fire_write(pbm->pbm_regs + EVENT_QUEUE_TAIL(i), 0);
280         }
281
282         return 0;
283 }
284
285 static void pci_fire_msiq_free(struct pci_pbm_info *pbm)
286 {
287         unsigned long pages, order;
288
289         order = get_order(512 * 1024);
290         pages = (unsigned long) pbm->msi_queues;
291
292         free_pages(pages, order);
293
294         pbm->msi_queues = NULL;
295 }
296
297 static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
298                                    unsigned long msiqid,
299                                    unsigned long devino)
300 {
301         unsigned long cregs = (unsigned long) pbm->pbm_regs;
302         unsigned long imap_reg, iclr_reg, int_ctrlr;
303         unsigned int virt_irq;
304         int fixup;
305         u64 val;
306
307         imap_reg = cregs + (0x001000UL + (devino * 0x08UL));
308         iclr_reg = cregs + (0x001400UL + (devino * 0x08UL));
309
310         /* XXX iterate amongst the 4 IRQ controllers XXX */
311         int_ctrlr = (1UL << 6);
312
313         val = fire_read(imap_reg);
314         val |= (1UL << 63) | int_ctrlr;
315         fire_write(imap_reg, val);
316
317         fixup = ((pbm->portid << 6) | devino) - int_ctrlr;
318
319         virt_irq = build_irq(fixup, iclr_reg, imap_reg);
320         if (!virt_irq)
321                 return -ENOMEM;
322
323         fire_write(pbm->pbm_regs +
324                    EVENT_QUEUE_CONTROL_SET(msiqid),
325                    EVENT_QUEUE_CONTROL_SET_EN);
326
327         return virt_irq;
328 }
329
330 static const struct sparc64_msiq_ops pci_fire_msiq_ops = {
331         .get_head       =       pci_fire_get_head,
332         .dequeue_msi    =       pci_fire_dequeue_msi,
333         .set_head       =       pci_fire_set_head,
334         .msi_setup      =       pci_fire_msi_setup,
335         .msi_teardown   =       pci_fire_msi_teardown,
336         .msiq_alloc     =       pci_fire_msiq_alloc,
337         .msiq_free      =       pci_fire_msiq_free,
338         .msiq_build_irq =       pci_fire_msiq_build_irq,
339 };
340
341 static void pci_fire_msi_init(struct pci_pbm_info *pbm)
342 {
343         sparc64_pbm_msi_init(pbm, &pci_fire_msiq_ops);
344 }
345 #else /* CONFIG_PCI_MSI */
346 static void pci_fire_msi_init(struct pci_pbm_info *pbm)
347 {
348 }
349 #endif /* !(CONFIG_PCI_MSI) */
350
351 /* Based at pbm->controller_regs */
352 #define FIRE_PARITY_CONTROL     0x470010UL
353 #define  FIRE_PARITY_ENAB       0x8000000000000000UL
354 #define FIRE_FATAL_RESET_CTL    0x471028UL
355 #define  FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
356 #define  FIRE_FATAL_RESET_MB    0x0000000002000000UL
357 #define  FIRE_FATAL_RESET_CPE   0x0000000000008000UL
358 #define  FIRE_FATAL_RESET_APE   0x0000000000004000UL
359 #define  FIRE_FATAL_RESET_PIO   0x0000000000000040UL
360 #define  FIRE_FATAL_RESET_JW    0x0000000000000004UL
361 #define  FIRE_FATAL_RESET_JI    0x0000000000000002UL
362 #define  FIRE_FATAL_RESET_JR    0x0000000000000001UL
363 #define FIRE_CORE_INTR_ENABLE   0x471800UL
364
365 /* Based at pbm->pbm_regs */
366 #define FIRE_TLU_CTRL           0x80000UL
367 #define  FIRE_TLU_CTRL_TIM      0x00000000da000000UL
368 #define  FIRE_TLU_CTRL_QDET     0x0000000000000100UL
369 #define  FIRE_TLU_CTRL_CFG      0x0000000000000001UL
370 #define FIRE_TLU_DEV_CTRL       0x90008UL
371 #define FIRE_TLU_LINK_CTRL      0x90020UL
372 #define FIRE_TLU_LINK_CTRL_CLK  0x0000000000000040UL
373 #define FIRE_LPU_RESET          0xe2008UL
374 #define FIRE_LPU_LLCFG          0xe2200UL
375 #define  FIRE_LPU_LLCFG_VC0     0x0000000000000100UL
376 #define FIRE_LPU_FCTRL_UCTRL    0xe2240UL
377 #define  FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
378 #define  FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
379 #define FIRE_LPU_TXL_FIFOP      0xe2430UL
380 #define FIRE_LPU_LTSSM_CFG2     0xe2788UL
381 #define FIRE_LPU_LTSSM_CFG3     0xe2790UL
382 #define FIRE_LPU_LTSSM_CFG4     0xe2798UL
383 #define FIRE_LPU_LTSSM_CFG5     0xe27a0UL
384 #define FIRE_DMC_IENAB          0x31800UL
385 #define FIRE_DMC_DBG_SEL_A      0x53000UL
386 #define FIRE_DMC_DBG_SEL_B      0x53008UL
387 #define FIRE_PEC_IENAB          0x51800UL
388
389 static void pci_fire_hw_init(struct pci_pbm_info *pbm)
390 {
391         u64 val;
392
393         fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL,
394                    FIRE_PARITY_ENAB);
395
396         fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL,
397                    (FIRE_FATAL_RESET_SPARE |
398                     FIRE_FATAL_RESET_MB |
399                     FIRE_FATAL_RESET_CPE |
400                     FIRE_FATAL_RESET_APE |
401                     FIRE_FATAL_RESET_PIO |
402                     FIRE_FATAL_RESET_JW |
403                     FIRE_FATAL_RESET_JI |
404                     FIRE_FATAL_RESET_JR));
405
406         fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0);
407
408         val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL);
409         val |= (FIRE_TLU_CTRL_TIM |
410                 FIRE_TLU_CTRL_QDET |
411                 FIRE_TLU_CTRL_CFG);
412         fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val);
413         fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0);
414         fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL,
415                    FIRE_TLU_LINK_CTRL_CLK);
416
417         fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0);
418         fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG,
419                    FIRE_LPU_LLCFG_VC0);
420         fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL,
421                    (FIRE_LPU_FCTRL_UCTRL_N |
422                     FIRE_LPU_FCTRL_UCTRL_P));
423         fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP,
424                    ((0xffff << 16) | (0x0000 << 0)));
425         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000);
426         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000);
427         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4,
428                    (2 << 16) | (140 << 8));
429         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0);
430
431         fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0);
432         fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0);
433         fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0);
434
435         fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
436 }
437
438 static int __init pci_fire_pbm_init(struct pci_controller_info *p,
439                                     struct device_node *dp, u32 portid)
440 {
441         const struct linux_prom64_registers *regs;
442         struct pci_pbm_info *pbm;
443         int err;
444
445         if ((portid & 1) == 0)
446                 pbm = &p->pbm_A;
447         else
448                 pbm = &p->pbm_B;
449
450         pbm->next = pci_pbm_root;
451         pci_pbm_root = pbm;
452
453         pbm->numa_node = -1;
454
455         pbm->scan_bus = pci_fire_scan_bus;
456         pbm->pci_ops = &sun4u_pci_ops;
457         pbm->config_space_reg_bits = 12;
458
459         pbm->index = pci_num_pbms++;
460
461         pbm->portid = portid;
462         pbm->parent = p;
463         pbm->prom_node = dp;
464         pbm->name = dp->full_name;
465
466         regs = of_get_property(dp, "reg", NULL);
467         pbm->pbm_regs = regs[0].phys_addr;
468         pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
469
470         printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
471
472         pci_determine_mem_io_space(pbm);
473
474         pci_get_pbm_props(pbm);
475
476         pci_fire_hw_init(pbm);
477
478         err = pci_fire_pbm_iommu_init(pbm);
479         if (err)
480                 return err;
481
482         pci_fire_msi_init(pbm);
483
484         return 0;
485 }
486
487 static inline int portid_compare(u32 x, u32 y)
488 {
489         if (x == (y ^ 1))
490                 return 1;
491         return 0;
492 }
493
494 void __init fire_pci_init(struct device_node *dp, const char *model_name)
495 {
496         struct pci_controller_info *p;
497         u32 portid = of_getintprop_default(dp, "portid", 0xff);
498         struct iommu *iommu;
499         struct pci_pbm_info *pbm;
500
501         for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
502                 if (portid_compare(pbm->portid, portid)) {
503                         if (pci_fire_pbm_init(pbm->parent, dp, portid))
504                                 goto fatal_memory_error;
505                         return;
506                 }
507         }
508
509         p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
510         if (!p)
511                 goto fatal_memory_error;
512
513         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
514         if (!iommu)
515                 goto fatal_memory_error;
516
517         p->pbm_A.iommu = iommu;
518
519         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
520         if (!iommu)
521                 goto fatal_memory_error;
522
523         p->pbm_B.iommu = iommu;
524
525         if (pci_fire_pbm_init(p, dp, portid))
526                 goto fatal_memory_error;
527
528         return;
529
530 fatal_memory_error:
531         prom_printf("PCI_FIRE: Fatal memory allocation error.\n");
532         prom_halt();
533 }