2 * arch/powerpc/sysdev/qe_lib/qe_ic.c
4 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
6 * Author: Li Yang <leoli@freescale.com>
7 * Based on code from Shlomi Gridish <gridish@freescale.com>
9 * QUICC ENGINE Interrupt Controller
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/slab.h>
22 #include <linux/stddef.h>
23 #include <linux/sched.h>
24 #include <linux/signal.h>
25 #include <linux/sysdev.h>
26 #include <linux/device.h>
27 #include <linux/bootmem.h>
28 #include <linux/spinlock.h>
32 #include <asm/qe_ic.h>
36 static DEFINE_SPINLOCK(qe_ic_lock);
38 static struct qe_ic_info qe_ic_info[] = {
41 .mask_reg = QEIC_CIMR,
43 .pri_reg = QEIC_CIPWCC,
47 .mask_reg = QEIC_CIMR,
49 .pri_reg = QEIC_CIPWCC,
53 .mask_reg = QEIC_CIMR,
55 .pri_reg = QEIC_CIPWCC,
59 .mask_reg = QEIC_CIMR,
61 .pri_reg = QEIC_CIPZCC,
65 .mask_reg = QEIC_CIMR,
67 .pri_reg = QEIC_CIPZCC,
71 .mask_reg = QEIC_CIMR,
73 .pri_reg = QEIC_CIPZCC,
77 .mask_reg = QEIC_CIMR,
79 .pri_reg = QEIC_CIPZCC,
83 .mask_reg = QEIC_CIMR,
85 .pri_reg = QEIC_CIPZCC,
89 .mask_reg = QEIC_CIMR,
91 .pri_reg = QEIC_CIPZCC,
95 .mask_reg = QEIC_CRIMR,
97 .pri_reg = QEIC_CIPRTA,
101 .mask_reg = QEIC_CRIMR,
103 .pri_reg = QEIC_CIPRTB,
107 .mask_reg = QEIC_CRIMR,
109 .pri_reg = QEIC_CIPRTB,
113 .mask_reg = QEIC_CRIMR,
115 .pri_reg = QEIC_CIPRTB,
119 .mask_reg = QEIC_CRIMR,
121 .pri_reg = QEIC_CIPRTB,
125 .mask_reg = QEIC_CIMR,
127 .pri_reg = QEIC_CIPXCC,
131 .mask_reg = QEIC_CIMR,
133 .pri_reg = QEIC_CIPXCC,
137 .mask_reg = QEIC_CIMR,
139 .pri_reg = QEIC_CIPXCC,
143 .mask_reg = QEIC_CIMR,
145 .pri_reg = QEIC_CIPXCC,
149 .mask_reg = QEIC_CIMR,
151 .pri_reg = QEIC_CIPXCC,
155 .mask_reg = QEIC_CIMR,
157 .pri_reg = QEIC_CIPYCC,
161 .mask_reg = QEIC_CIMR,
163 .pri_reg = QEIC_CIPYCC,
167 .mask_reg = QEIC_CIMR,
169 .pri_reg = QEIC_CIPYCC,
173 .mask_reg = QEIC_CIMR,
175 .pri_reg = QEIC_CIPYCC,
179 static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
181 return in_be32(base + (reg >> 2));
184 static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
187 out_be32(base + (reg >> 2), value);
190 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
192 return irq_desc[virq].chip_data;
195 #define virq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
197 static void qe_ic_unmask_irq(unsigned int virq)
199 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
200 unsigned int src = virq_to_hw(virq);
204 spin_lock_irqsave(&qe_ic_lock, flags);
206 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
207 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
208 temp | qe_ic_info[src].mask);
210 spin_unlock_irqrestore(&qe_ic_lock, flags);
213 static void qe_ic_mask_irq(unsigned int virq)
215 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
216 unsigned int src = virq_to_hw(virq);
220 spin_lock_irqsave(&qe_ic_lock, flags);
222 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
223 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
224 temp & ~qe_ic_info[src].mask);
226 /* Flush the above write before enabling interrupts; otherwise,
227 * spurious interrupts will sometimes happen. To be 100% sure
228 * that the write has reached the device before interrupts are
229 * enabled, the mask register would have to be read back; however,
230 * this is not required for correctness, only to avoid wasting
231 * time on a large number of spurious interrupts. In testing,
232 * a sync reduced the observed spurious interrupts to zero.
236 spin_unlock_irqrestore(&qe_ic_lock, flags);
239 static struct irq_chip qe_ic_irq_chip = {
240 .typename = " QEIC ",
241 .unmask = qe_ic_unmask_irq,
242 .mask = qe_ic_mask_irq,
243 .mask_ack = qe_ic_mask_irq,
246 static int qe_ic_host_match(struct irq_host *h, struct device_node *node)
248 struct qe_ic *qe_ic = h->host_data;
250 /* Exact match, unless qe_ic node is NULL */
251 return qe_ic->of_node == NULL || qe_ic->of_node == node;
254 static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
257 struct qe_ic *qe_ic = h->host_data;
258 struct irq_chip *chip;
260 if (qe_ic_info[hw].mask == 0) {
261 printk(KERN_ERR "Can't map reserved IRQ \n");
265 chip = &qe_ic->hc_irq;
267 set_irq_chip_data(virq, qe_ic);
268 get_irq_desc(virq)->status |= IRQ_LEVEL;
270 set_irq_chip_and_handler(virq, chip, handle_level_irq);
275 static int qe_ic_host_xlate(struct irq_host *h, struct device_node *ct,
276 u32 * intspec, unsigned int intsize,
277 irq_hw_number_t * out_hwirq,
278 unsigned int *out_flags)
280 *out_hwirq = intspec[0];
282 *out_flags = intspec[1];
284 *out_flags = IRQ_TYPE_NONE;
288 static struct irq_host_ops qe_ic_host_ops = {
289 .match = qe_ic_host_match,
290 .map = qe_ic_host_map,
291 .xlate = qe_ic_host_xlate,
294 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
295 unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
299 BUG_ON(qe_ic == NULL);
301 /* get the interrupt source vector. */
302 irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
307 return irq_linear_revmap(qe_ic->irqhost, irq);
310 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
311 unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
315 BUG_ON(qe_ic == NULL);
317 /* get the interrupt source vector. */
318 irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
323 return irq_linear_revmap(qe_ic->irqhost, irq);
326 void fastcall qe_ic_cascade_low(unsigned int irq, struct irq_desc *desc)
328 struct qe_ic *qe_ic = desc->handler_data;
329 unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
331 if (cascade_irq != NO_IRQ)
332 generic_handle_irq(cascade_irq);
335 void fastcall qe_ic_cascade_high(unsigned int irq, struct irq_desc *desc)
337 struct qe_ic *qe_ic = desc->handler_data;
338 unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
340 if (cascade_irq != NO_IRQ)
341 generic_handle_irq(cascade_irq);
344 void __init qe_ic_init(struct device_node *node, unsigned int flags)
348 u32 temp = 0, ret, high_active = 0;
350 qe_ic = alloc_bootmem(sizeof(struct qe_ic));
354 memset(qe_ic, 0, sizeof(struct qe_ic));
355 qe_ic->of_node = of_node_get(node);
357 qe_ic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR,
358 NR_QE_IC_INTS, &qe_ic_host_ops, 0);
359 if (qe_ic->irqhost == NULL) {
364 ret = of_address_to_resource(node, 0, &res);
368 qe_ic->regs = ioremap(res.start, res.end - res.start + 1);
370 qe_ic->irqhost->host_data = qe_ic;
371 qe_ic->hc_irq = qe_ic_irq_chip;
373 qe_ic->virq_high = irq_of_parse_and_map(node, 0);
374 qe_ic->virq_low = irq_of_parse_and_map(node, 1);
376 if (qe_ic->virq_low == NO_IRQ) {
377 printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
381 /* default priority scheme is grouped. If spread mode is */
382 /* required, configure cicr accordingly. */
383 if (flags & QE_IC_SPREADMODE_GRP_W)
385 if (flags & QE_IC_SPREADMODE_GRP_X)
387 if (flags & QE_IC_SPREADMODE_GRP_Y)
389 if (flags & QE_IC_SPREADMODE_GRP_Z)
391 if (flags & QE_IC_SPREADMODE_GRP_RISCA)
393 if (flags & QE_IC_SPREADMODE_GRP_RISCB)
396 /* choose destination signal for highest priority interrupt */
397 if (flags & QE_IC_HIGH_SIGNAL) {
398 temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
402 qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
404 set_irq_data(qe_ic->virq_low, qe_ic);
405 set_irq_chained_handler(qe_ic->virq_low, qe_ic_cascade_low);
407 if (qe_ic->virq_high != NO_IRQ) {
408 set_irq_data(qe_ic->virq_high, qe_ic);
409 set_irq_chained_handler(qe_ic->virq_high, qe_ic_cascade_high);
412 printk("QEIC (%d IRQ sources) at %p\n", NR_QE_IC_INTS, qe_ic->regs);
415 void qe_ic_set_highest_priority(unsigned int virq, int high)
417 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
418 unsigned int src = virq_to_hw(virq);
421 temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
423 temp &= ~CICR_HP_MASK;
424 temp |= src << CICR_HP_SHIFT;
426 temp &= ~CICR_HPIT_MASK;
427 temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
429 qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
432 /* Set Priority level within its group, from 1 to 8 */
433 int qe_ic_set_priority(unsigned int virq, unsigned int priority)
435 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
436 unsigned int src = virq_to_hw(virq);
439 if (priority > 8 || priority == 0)
443 if (qe_ic_info[src].pri_reg == 0)
446 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
449 temp &= ~(0x7 << (32 - priority * 3));
450 temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
452 temp &= ~(0x7 << (24 - priority * 3));
453 temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
456 qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
461 /* Set a QE priority to use high irq, only priority 1~2 can use high irq */
462 int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
464 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
465 unsigned int src = virq_to_hw(virq);
466 u32 temp, control_reg = QEIC_CICNR, shift = 0;
468 if (priority > 2 || priority == 0)
471 switch (qe_ic_info[src].pri_reg) {
473 shift = CICNR_ZCC1T_SHIFT;
476 shift = CICNR_WCC1T_SHIFT;
479 shift = CICNR_YCC1T_SHIFT;
482 shift = CICNR_XCC1T_SHIFT;
485 shift = CRICR_RTA1T_SHIFT;
486 control_reg = QEIC_CRICR;
489 shift = CRICR_RTB1T_SHIFT;
490 control_reg = QEIC_CRICR;
496 shift += (2 - priority) * 2;
497 temp = qe_ic_read(qe_ic->regs, control_reg);
498 temp &= ~(SIGNAL_MASK << shift);
499 temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
500 qe_ic_write(qe_ic->regs, control_reg, temp);
505 static struct sysdev_class qe_ic_sysclass = {
506 set_kset_name("qe_ic"),
509 static struct sys_device device_qe_ic = {
511 .cls = &qe_ic_sysclass,
514 static int __init init_qe_ic_sysfs(void)
518 printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
520 rc = sysdev_class_register(&qe_ic_sysclass);
522 printk(KERN_ERR "Failed registering qe_ic sys class\n");
525 rc = sysdev_register(&device_qe_ic);
527 printk(KERN_ERR "Failed registering qe_ic sys device\n");
533 subsys_initcall(init_qe_ic_sysfs);