Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6] / arch / powerpc / boot / dts / mpc8548cds.dts
1 /*
2  * MPC8548 CDS Device Tree Source
3  *
4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13
14 / {
15         model = "MPC8548CDS";
16         compatible = "MPC8548CDS", "MPC85xxCDS";
17         #address-cells = <1>;
18         #size-cells = <1>;
19
20         aliases {
21                 ethernet0 = &enet0;
22                 ethernet1 = &enet1;
23 /*
24                 ethernet2 = &enet2;
25                 ethernet3 = &enet3;
26 */
27                 serial0 = &serial0;
28                 serial1 = &serial1;
29                 pci0 = &pci0;
30                 pci1 = &pci1;
31                 pci2 = &pci2;
32         };
33
34         cpus {
35                 #address-cells = <1>;
36                 #size-cells = <0>;
37
38                 PowerPC,8548@0 {
39                         device_type = "cpu";
40                         reg = <0x0>;
41                         d-cache-line-size = <32>;       // 32 bytes
42                         i-cache-line-size = <32>;       // 32 bytes
43                         d-cache-size = <0x8000>;                // L1, 32K
44                         i-cache-size = <0x8000>;                // L1, 32K
45                         timebase-frequency = <0>;       //  33 MHz, from uboot
46                         bus-frequency = <0>;    // 166 MHz
47                         clock-frequency = <0>;  // 825 MHz, from uboot
48                 };
49         };
50
51         memory {
52                 device_type = "memory";
53                 reg = <0x0 0x8000000>;  // 128M at 0x0
54         };
55
56         soc8548@e0000000 {
57                 #address-cells = <1>;
58                 #size-cells = <1>;
59                 device_type = "soc";
60                 ranges = <0x0 0xe0000000 0x100000>;
61                 reg = <0xe0000000 0x1000>;      // CCSRBAR
62                 bus-frequency = <0>;
63
64                 memory-controller@2000 {
65                         compatible = "fsl,8548-memory-controller";
66                         reg = <0x2000 0x1000>;
67                         interrupt-parent = <&mpic>;
68                         interrupts = <18 2>;
69                 };
70
71                 l2-cache-controller@20000 {
72                         compatible = "fsl,8548-l2-cache-controller";
73                         reg = <0x20000 0x1000>;
74                         cache-line-size = <32>; // 32 bytes
75                         cache-size = <0x80000>; // L2, 512K
76                         interrupt-parent = <&mpic>;
77                         interrupts = <16 2>;
78                 };
79
80                 i2c@3000 {
81                         #address-cells = <1>;
82                         #size-cells = <0>;
83                         cell-index = <0>;
84                         compatible = "fsl-i2c";
85                         reg = <0x3000 0x100>;
86                         interrupts = <43 2>;
87                         interrupt-parent = <&mpic>;
88                         dfsrr;
89                 };
90
91                 i2c@3100 {
92                         #address-cells = <1>;
93                         #size-cells = <0>;
94                         cell-index = <1>;
95                         compatible = "fsl-i2c";
96                         reg = <0x3100 0x100>;
97                         interrupts = <43 2>;
98                         interrupt-parent = <&mpic>;
99                         dfsrr;
100                 };
101
102                 mdio@24520 {
103                         #address-cells = <1>;
104                         #size-cells = <0>;
105                         compatible = "fsl,gianfar-mdio";
106                         reg = <0x24520 0x20>;
107
108                         phy0: ethernet-phy@0 {
109                                 interrupt-parent = <&mpic>;
110                                 interrupts = <5 1>;
111                                 reg = <0x0>;
112                                 device_type = "ethernet-phy";
113                         };
114                         phy1: ethernet-phy@1 {
115                                 interrupt-parent = <&mpic>;
116                                 interrupts = <5 1>;
117                                 reg = <0x1>;
118                                 device_type = "ethernet-phy";
119                         };
120                         phy2: ethernet-phy@2 {
121                                 interrupt-parent = <&mpic>;
122                                 interrupts = <5 1>;
123                                 reg = <0x2>;
124                                 device_type = "ethernet-phy";
125                         };
126                         phy3: ethernet-phy@3 {
127                                 interrupt-parent = <&mpic>;
128                                 interrupts = <5 1>;
129                                 reg = <0x3>;
130                                 device_type = "ethernet-phy";
131                         };
132                 };
133
134                 enet0: ethernet@24000 {
135                         cell-index = <0>;
136                         device_type = "network";
137                         model = "eTSEC";
138                         compatible = "gianfar";
139                         reg = <0x24000 0x1000>;
140                         local-mac-address = [ 00 00 00 00 00 00 ];
141                         interrupts = <29 2 30 2 34 2>;
142                         interrupt-parent = <&mpic>;
143                         phy-handle = <&phy0>;
144                 };
145
146                 enet1: ethernet@25000 {
147                         cell-index = <1>;
148                         device_type = "network";
149                         model = "eTSEC";
150                         compatible = "gianfar";
151                         reg = <0x25000 0x1000>;
152                         local-mac-address = [ 00 00 00 00 00 00 ];
153                         interrupts = <35 2 36 2 40 2>;
154                         interrupt-parent = <&mpic>;
155                         phy-handle = <&phy1>;
156                 };
157
158 /* eTSEC 3/4 are currently broken
159                 enet2: ethernet@26000 {
160                         cell-index = <2>;
161                         device_type = "network";
162                         model = "eTSEC";
163                         compatible = "gianfar";
164                         reg = <0x26000 0x1000>;
165                         local-mac-address = [ 00 00 00 00 00 00 ];
166                         interrupts = <31 2 32 2 33 2>;
167                         interrupt-parent = <&mpic>;
168                         phy-handle = <&phy2>;
169                 };
170
171                 enet3: ethernet@27000 {
172                         cell-index = <3>;
173                         device_type = "network";
174                         model = "eTSEC";
175                         compatible = "gianfar";
176                         reg = <0x27000 0x1000>;
177                         local-mac-address = [ 00 00 00 00 00 00 ];
178                         interrupts = <37 2 38 2 39 2>;
179                         interrupt-parent = <&mpic>;
180                         phy-handle = <&phy3>;
181                 };
182  */
183
184                 serial0: serial@4500 {
185                         cell-index = <0>;
186                         device_type = "serial";
187                         compatible = "ns16550";
188                         reg = <0x4500 0x100>;   // reg base, size
189                         clock-frequency = <0>;  // should we fill in in uboot?
190                         interrupts = <42 2>;
191                         interrupt-parent = <&mpic>;
192                 };
193
194                 serial1: serial@4600 {
195                         cell-index = <1>;
196                         device_type = "serial";
197                         compatible = "ns16550";
198                         reg = <0x4600 0x100>;   // reg base, size
199                         clock-frequency = <0>;  // should we fill in in uboot?
200                         interrupts = <42 2>;
201                         interrupt-parent = <&mpic>;
202                 };
203
204                 global-utilities@e0000 {        //global utilities reg
205                         compatible = "fsl,mpc8548-guts";
206                         reg = <0xe0000 0x1000>;
207                         fsl,has-rstcr;
208                 };
209
210                 mpic: pic@40000 {
211                         clock-frequency = <0>;
212                         interrupt-controller;
213                         #address-cells = <0>;
214                         #interrupt-cells = <2>;
215                         reg = <0x40000 0x40000>;
216                         compatible = "chrp,open-pic";
217                         device_type = "open-pic";
218                         big-endian;
219                 };
220         };
221
222         pci0: pci@e0008000 {
223                 cell-index = <0>;
224                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
225                 interrupt-map = <
226                         /* IDSEL 0x4 (PCIX Slot 2) */
227                         0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
228                         0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
229                         0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
230                         0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
231
232                         /* IDSEL 0x5 (PCIX Slot 3) */
233                         0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
234                         0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
235                         0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
236                         0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
237
238                         /* IDSEL 0x6 (PCIX Slot 4) */
239                         0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
240                         0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
241                         0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
242                         0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
243
244                         /* IDSEL 0x8 (PCIX Slot 5) */
245                         0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
246                         0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
247                         0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
248                         0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
249
250                         /* IDSEL 0xC (Tsi310 bridge) */
251                         0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
252                         0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
253                         0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
254                         0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
255
256                         /* IDSEL 0x14 (Slot 2) */
257                         0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
258                         0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
259                         0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
260                         0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
261
262                         /* IDSEL 0x15 (Slot 3) */
263                         0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
264                         0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
265                         0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
266                         0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
267
268                         /* IDSEL 0x16 (Slot 4) */
269                         0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
270                         0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
271                         0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
272                         0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
273
274                         /* IDSEL 0x18 (Slot 5) */
275                         0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
276                         0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
277                         0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
278                         0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
279
280                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
281                         0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
282                         0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
283                         0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
284                         0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
285
286                 interrupt-parent = <&mpic>;
287                 interrupts = <24 2>;
288                 bus-range = <0 0>;
289                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
290                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
291                 clock-frequency = <66666666>;
292                 #interrupt-cells = <1>;
293                 #size-cells = <2>;
294                 #address-cells = <3>;
295                 reg = <0xe0008000 0x1000>;
296                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
297                 device_type = "pci";
298
299                 pci_bridge@1c {
300                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
301                         interrupt-map = <
302
303                                 /* IDSEL 0x00 (PrPMC Site) */
304                                 0000 0x0 0x0 0x1 &mpic 0x0 0x1
305                                 0000 0x0 0x0 0x2 &mpic 0x1 0x1
306                                 0000 0x0 0x0 0x3 &mpic 0x2 0x1
307                                 0000 0x0 0x0 0x4 &mpic 0x3 0x1
308
309                                 /* IDSEL 0x04 (VIA chip) */
310                                 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
311                                 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
312                                 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
313                                 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
314
315                                 /* IDSEL 0x05 (8139) */
316                                 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
317
318                                 /* IDSEL 0x06 (Slot 6) */
319                                 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
320                                 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
321                                 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
322                                 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
323
324                                 /* IDESL 0x07 (Slot 7) */
325                                 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
326                                 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
327                                 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
328                                 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
329
330                         reg = <0xe000 0x0 0x0 0x0 0x0>;
331                         #interrupt-cells = <1>;
332                         #size-cells = <2>;
333                         #address-cells = <3>;
334                         ranges = <0x2000000 0x0 0x80000000
335                                   0x2000000 0x0 0x80000000
336                                   0x0 0x20000000
337                                   0x1000000 0x0 0x0
338                                   0x1000000 0x0 0x0
339                                   0x0 0x80000>;
340                         clock-frequency = <33333333>;
341
342                         isa@4 {
343                                 device_type = "isa";
344                                 #interrupt-cells = <2>;
345                                 #size-cells = <1>;
346                                 #address-cells = <2>;
347                                 reg = <0x2000 0x0 0x0 0x0 0x0>;
348                                 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
349                                 interrupt-parent = <&i8259>;
350
351                                 i8259: interrupt-controller@20 {
352                                         interrupt-controller;
353                                         device_type = "interrupt-controller";
354                                         reg = <0x1 0x20 0x2
355                                                0x1 0xa0 0x2
356                                                0x1 0x4d0 0x2>;
357                                         #address-cells = <0>;
358                                         #interrupt-cells = <2>;
359                                         compatible = "chrp,iic";
360                                         interrupts = <0 1>;
361                                         interrupt-parent = <&mpic>;
362                                 };
363
364                                 rtc@70 {
365                                         compatible = "pnpPNP,b00";
366                                         reg = <0x1 0x70 0x2>;
367                                 };
368                         };
369                 };
370         };
371
372         pci1: pci@e0009000 {
373                 cell-index = <1>;
374                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
375                 interrupt-map = <
376
377                         /* IDSEL 0x15 */
378                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
379                         0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
380                         0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
381                         0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
382
383                 interrupt-parent = <&mpic>;
384                 interrupts = <25 2>;
385                 bus-range = <0 0>;
386                 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
387                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
388                 clock-frequency = <66666666>;
389                 #interrupt-cells = <1>;
390                 #size-cells = <2>;
391                 #address-cells = <3>;
392                 reg = <0xe0009000 0x1000>;
393                 compatible = "fsl,mpc8540-pci";
394                 device_type = "pci";
395         };
396
397         pci2: pcie@e000a000 {
398                 cell-index = <2>;
399                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
400                 interrupt-map = <
401
402                         /* IDSEL 0x0 (PEX) */
403                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
404                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
405                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
406                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
407
408                 interrupt-parent = <&mpic>;
409                 interrupts = <26 2>;
410                 bus-range = <0 255>;
411                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
412                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
413                 clock-frequency = <33333333>;
414                 #interrupt-cells = <1>;
415                 #size-cells = <2>;
416                 #address-cells = <3>;
417                 reg = <0xe000a000 0x1000>;
418                 compatible = "fsl,mpc8548-pcie";
419                 device_type = "pci";
420                 pcie@0 {
421                         reg = <0x0 0x0 0x0 0x0 0x0>;
422                         #size-cells = <2>;
423                         #address-cells = <3>;
424                         device_type = "pci";
425                         ranges = <0x2000000 0x0 0xa0000000
426                                   0x2000000 0x0 0xa0000000
427                                   0x0 0x20000000
428
429                                   0x1000000 0x0 0x0
430                                   0x1000000 0x0 0x0
431                                   0x0 0x100000>;
432                 };
433         };
434 };