git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/platforms/iseries/exception.S

   1 /*
   2  *  Low level routines for legacy iSeries support.
   3  *
   4  *  Extracted from head_64.S
   5  *
   6  *  PowerPC version
   7  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   8  *
   9  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
  10  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  11  *  Adapted for Power Macintosh by Paul Mackerras.
  12  *  Low-level exception handlers and MMU support
  13  *  rewritten by Paul Mackerras.
  14  *    Copyright (C) 1996 Paul Mackerras.
  15  *
  16  *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
  17  *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
  18  *
  19  *  This file contains the low-level support and setup for the
  20  *  PowerPC-64 platform, including trap and interrupt dispatch.
  21  *
  22  *  This program is free software; you can redistribute it and/or
  23  *  modify it under the terms of the GNU General Public License
  24  *  as published by the Free Software Foundation; either version
  25  *  2 of the License, or (at your option) any later version.
  26  */
  27
  28 #include <asm/reg.h>
  29 #include <asm/ppc_asm.h>
  30 #include <asm/asm-offsets.h>
  31 #include <asm/thread_info.h>
  32 #include <asm/ptrace.h>
  33 #include <asm/cputable.h>
  34
  35 #include "exception.h"
  36
  37         .text
  38
  39         .globl system_reset_iSeries
  40 system_reset_iSeries:
  41         mfspr   r13,SPRN_SPRG3          /* Get alpaca address */
  42         LOAD_REG_IMMEDIATE(r23, alpaca)
  43         li      r0,ALPACA_SIZE
  44         sub     r23,r13,r23
  45         divdu   r23,r23,r0              /* r23 has cpu number */
  46         LOAD_REG_IMMEDIATE(r13, paca)
  47         mulli   r0,r23,PACA_SIZE
  48         add     r13,r13,r0
  49         mtspr   SPRN_SPRG3,r13          /* Save it away for the future */
  50         mfmsr   r24
  51         ori     r24,r24,MSR_RI
  52         mtmsrd  r24                     /* RI on */
  53         mr      r24,r23
  54         cmpwi   0,r24,0                 /* Are we processor 0? */
  55         bne     1f
  56         b       .__start_initialization_iSeries /* Start up the first processor */
  57 1:      mfspr   r4,SPRN_CTRLF
  58         li      r5,CTRL_RUNLATCH        /* Turn off the run light */
  59         andc    r4,r4,r5
  60         mtspr   SPRN_CTRLT,r4
  61
  62 /* Spin on __secondary_hold_spinloop until it is updated by the boot cpu. */
  63 /* In the UP case we'll yeild() later, and we will not access the paca anyway */
  64 #ifdef CONFIG_SMP
  65 1:
  66         HMT_LOW
  67         LOAD_REG_IMMEDIATE(r23, __secondary_hold_spinloop)
  68         ld      r23,0(r23)
  69         sync
  70         LOAD_REG_IMMEDIATE(r3,current_set)
  71         sldi    r28,r24,3               /* get current_set[cpu#] */
  72         ldx     r3,r3,r28
  73         addi    r1,r3,THREAD_SIZE
  74         subi    r1,r1,STACK_FRAME_OVERHEAD
  75
  76         cmpwi   0,r23,0                 /* Keep poking the Hypervisor until */
  77         bne     2f                      /* we're released */
  78         /* Let the Hypervisor know we are alive */
  79         /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
  80         lis     r3,0x8002
  81         rldicr  r3,r3,32,15             /* r0 = (r3 << 32) & 0xffff000000000000 */
  82         li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
  83         sc                              /* Invoke the hypervisor via a system call */
  84         b       1b
  85 #endif
  86
  87 2:
  88         HMT_LOW
  89 #ifdef CONFIG_SMP
  90         lbz     r23,PACAPROCSTART(r13)  /* Test if this processor
  91                                          * should start */
  92         sync
  93         LOAD_REG_IMMEDIATE(r3,current_set)
  94         sldi    r28,r24,3               /* get current_set[cpu#] */
  95         ldx     r3,r3,r28
  96         addi    r1,r3,THREAD_SIZE
  97         subi    r1,r1,STACK_FRAME_OVERHEAD
  98
  99         cmpwi   0,r23,0
 100         beq     iSeries_secondary_smp_loop      /* Loop until told to go */
 101         b       __secondary_start               /* Loop until told to go */
 102 iSeries_secondary_smp_loop:
 103         /* Let the Hypervisor know we are alive */
 104         /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
 105         lis     r3,0x8002
 106         rldicr  r3,r3,32,15             /* r0 = (r3 << 32) & 0xffff000000000000 */
 107 #else /* CONFIG_SMP */
 108         /* Yield the processor.  This is required for non-SMP kernels
 109                 which are running on multi-threaded machines. */
 110         lis     r3,0x8000
 111         rldicr  r3,r3,32,15             /* r3 = (r3 << 32) & 0xffff000000000000 */
 112         addi    r3,r3,18                /* r3 = 0x8000000000000012 which is "yield" */
 113         li      r4,0                    /* "yield timed" */
 114         li      r5,-1                   /* "yield forever" */
 115 #endif /* CONFIG_SMP */
 116         li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
 117         sc                              /* Invoke the hypervisor via a system call */
 118         mfspr   r13,SPRN_SPRG3          /* Put r13 back ???? */
 119         b       2b                      /* If SMP not configured, secondaries
 120                                          * loop forever */
 121
 122 /***  ISeries-LPAR interrupt handlers ***/
 123
 124         STD_EXCEPTION_ISERIES(machine_check, PACA_EXMC)
 125
 126         .globl data_access_iSeries
 127 data_access_iSeries:
 128         mtspr   SPRN_SPRG1,r13
 129 BEGIN_FTR_SECTION
 130         mtspr   SPRN_SPRG2,r12
 131         mfspr   r13,SPRN_DAR
 132         mfspr   r12,SPRN_DSISR
 133         srdi    r13,r13,60
 134         rlwimi  r13,r12,16,0x20
 135         mfcr    r12
 136         cmpwi   r13,0x2c
 137         beq     .do_stab_bolted_iSeries
 138         mtcrf   0x80,r12
 139         mfspr   r12,SPRN_SPRG2
 140 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
 141         EXCEPTION_PROLOG_1(PACA_EXGEN)
 142         EXCEPTION_PROLOG_ISERIES_1
 143         b       data_access_common
 144
 145 .do_stab_bolted_iSeries:
 146         mtcrf   0x80,r12
 147         mfspr   r12,SPRN_SPRG2
 148         EXCEPTION_PROLOG_1(PACA_EXSLB)
 149         EXCEPTION_PROLOG_ISERIES_1
 150         b       .do_stab_bolted
 151
 152         .globl  data_access_slb_iSeries
 153 data_access_slb_iSeries:
 154         mtspr   SPRN_SPRG1,r13          /* save r13 */
 155         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 156         std     r3,PACA_EXSLB+EX_R3(r13)
 157         mfspr   r3,SPRN_DAR
 158         std     r9,PACA_EXSLB+EX_R9(r13)
 159         mfcr    r9
 160 #ifdef __DISABLED__
 161         cmpdi   r3,0
 162         bge     slb_miss_user_iseries
 163 #endif
 164         std     r10,PACA_EXSLB+EX_R10(r13)
 165         std     r11,PACA_EXSLB+EX_R11(r13)
 166         std     r12,PACA_EXSLB+EX_R12(r13)
 167         mfspr   r10,SPRN_SPRG1
 168         std     r10,PACA_EXSLB+EX_R13(r13)
 169         ld      r12,PACALPPACAPTR(r13)
 170         ld      r12,LPPACASRR1(r12)
 171         b       .slb_miss_realmode
 172
 173         STD_EXCEPTION_ISERIES(instruction_access, PACA_EXGEN)
 174
 175         .globl  instruction_access_slb_iSeries
 176 instruction_access_slb_iSeries:
 177         mtspr   SPRN_SPRG1,r13          /* save r13 */
 178         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 179         std     r3,PACA_EXSLB+EX_R3(r13)
 180         ld      r3,PACALPPACAPTR(r13)
 181         ld      r3,LPPACASRR0(r3)       /* get SRR0 value */
 182         std     r9,PACA_EXSLB+EX_R9(r13)
 183         mfcr    r9
 184 #ifdef __DISABLED__
 185         cmpdi   r3,0
 186         bge     slb_miss_user_iseries
 187 #endif
 188         std     r10,PACA_EXSLB+EX_R10(r13)
 189         std     r11,PACA_EXSLB+EX_R11(r13)
 190         std     r12,PACA_EXSLB+EX_R12(r13)
 191         mfspr   r10,SPRN_SPRG1
 192         std     r10,PACA_EXSLB+EX_R13(r13)
 193         ld      r12,PACALPPACAPTR(r13)
 194         ld      r12,LPPACASRR1(r12)
 195         b       .slb_miss_realmode
 196
 197 #ifdef __DISABLED__
 198 slb_miss_user_iseries:
 199         std     r10,PACA_EXGEN+EX_R10(r13)
 200         std     r11,PACA_EXGEN+EX_R11(r13)
 201         std     r12,PACA_EXGEN+EX_R12(r13)
 202         mfspr   r10,SPRG1
 203         ld      r11,PACA_EXSLB+EX_R9(r13)
 204         ld      r12,PACA_EXSLB+EX_R3(r13)
 205         std     r10,PACA_EXGEN+EX_R13(r13)
 206         std     r11,PACA_EXGEN+EX_R9(r13)
 207         std     r12,PACA_EXGEN+EX_R3(r13)
 208         EXCEPTION_PROLOG_ISERIES_1
 209         b       slb_miss_user_common
 210 #endif
 211
 212         MASKABLE_EXCEPTION_ISERIES(hardware_interrupt)
 213         STD_EXCEPTION_ISERIES(alignment, PACA_EXGEN)
 214         STD_EXCEPTION_ISERIES(program_check, PACA_EXGEN)
 215         STD_EXCEPTION_ISERIES(fp_unavailable, PACA_EXGEN)
 216         MASKABLE_EXCEPTION_ISERIES(decrementer)
 217         STD_EXCEPTION_ISERIES(trap_0a, PACA_EXGEN)
 218         STD_EXCEPTION_ISERIES(trap_0b, PACA_EXGEN)
 219
 220         .globl  system_call_iSeries
 221 system_call_iSeries:
 222         mr      r9,r13
 223         mfspr   r13,SPRN_SPRG3
 224         EXCEPTION_PROLOG_ISERIES_1
 225         b       system_call_common
 226
 227         STD_EXCEPTION_ISERIES(single_step, PACA_EXGEN)
 228         STD_EXCEPTION_ISERIES(trap_0e, PACA_EXGEN)
 229         STD_EXCEPTION_ISERIES(performance_monitor, PACA_EXGEN)
 230
 231 decrementer_iSeries_masked:
 232         /* We may not have a valid TOC pointer in here. */
 233         li      r11,1
 234         ld      r12,PACALPPACAPTR(r13)
 235         stb     r11,LPPACADECRINT(r12)
 236         LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
 237         lwz     r12,0(r12)
 238         mtspr   SPRN_DEC,r12
 239         /* fall through */
 240
 241 hardware_interrupt_iSeries_masked:
 242         mtcrf   0x80,r9         /* Restore regs */
 243         ld      r12,PACALPPACAPTR(r13)
 244         ld      r11,LPPACASRR0(r12)
 245         ld      r12,LPPACASRR1(r12)
 246         mtspr   SPRN_SRR0,r11
 247         mtspr   SPRN_SRR1,r12
 248         ld      r9,PACA_EXGEN+EX_R9(r13)
 249         ld      r10,PACA_EXGEN+EX_R10(r13)
 250         ld      r11,PACA_EXGEN+EX_R11(r13)
 251         ld      r12,PACA_EXGEN+EX_R12(r13)
 252         ld      r13,PACA_EXGEN+EX_R13(r13)
 253         rfid
 254         b       .       /* prevent speculative execution */
 255
 256 _INIT_STATIC(__start_initialization_iSeries)
 257         /* Clear out the BSS */
 258         LOAD_REG_IMMEDIATE(r11,__bss_stop)
 259         LOAD_REG_IMMEDIATE(r8,__bss_start)
 260         sub     r11,r11,r8              /* bss size                     */
 261         addi    r11,r11,7               /* round up to an even double word */
 262         rldicl. r11,r11,61,3            /* shift right by 3             */
 263         beq     4f
 264         addi    r8,r8,-8
 265         li      r0,0
 266         mtctr   r11                     /* zero this many doublewords   */
 267 3:      stdu    r0,8(r8)
 268         bdnz    3b
 269 4:
 270         LOAD_REG_IMMEDIATE(r1,init_thread_union)
 271         addi    r1,r1,THREAD_SIZE
 272         li      r0,0
 273         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
 274
 275         LOAD_REG_IMMEDIATE(r2,__toc_start)
 276         addi    r2,r2,0x4000
 277         addi    r2,r2,0x4000
 278
 279         bl      .iSeries_early_setup
 280         bl      .early_setup
 281
 282         /* relocation is on at this point */
 283
 284         b       .start_here_common