Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/agpgart
[linux-2.6] / arch / sparc64 / kernel / irq.c
1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
2  * irq.c: UltraSparc IRQ handling/init/registry.
3  *
4  * Copyright (C) 1997  David S. Miller  (davem@caip.rutgers.edu)
5  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
6  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
7  */
8
9 #include <linux/module.h>
10 #include <linux/sched.h>
11 #include <linux/ptrace.h>
12 #include <linux/errno.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/signal.h>
15 #include <linux/mm.h>
16 #include <linux/interrupt.h>
17 #include <linux/slab.h>
18 #include <linux/random.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/proc_fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/bootmem.h>
24 #include <linux/irq.h>
25 #include <linux/msi.h>
26
27 #include <asm/ptrace.h>
28 #include <asm/processor.h>
29 #include <asm/atomic.h>
30 #include <asm/system.h>
31 #include <asm/irq.h>
32 #include <asm/io.h>
33 #include <asm/sbus.h>
34 #include <asm/iommu.h>
35 #include <asm/upa.h>
36 #include <asm/oplib.h>
37 #include <asm/prom.h>
38 #include <asm/timer.h>
39 #include <asm/smp.h>
40 #include <asm/starfire.h>
41 #include <asm/uaccess.h>
42 #include <asm/cache.h>
43 #include <asm/cpudata.h>
44 #include <asm/auxio.h>
45 #include <asm/head.h>
46
47 /* UPA nodes send interrupt packet to UltraSparc with first data reg
48  * value low 5 (7 on Starfire) bits holding the IRQ identifier being
49  * delivered.  We must translate this into a non-vector IRQ so we can
50  * set the softint on this cpu.
51  *
52  * To make processing these packets efficient and race free we use
53  * an array of irq buckets below.  The interrupt vector handler in
54  * entry.S feeds incoming packets into per-cpu pil-indexed lists.
55  * The IVEC handler does not need to act atomically, the PIL dispatch
56  * code uses CAS to get an atomic snapshot of the list and clear it
57  * at the same time.
58  *
59  * If you make changes to ino_bucket, please update hand coded assembler
60  * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
61  */
62 struct ino_bucket {
63         /* Next handler in per-CPU IRQ worklist.  We know that
64          * bucket pointers have the high 32-bits clear, so to
65          * save space we only store the bits we need.
66          */
67 /*0x00*/unsigned int irq_chain;
68
69         /* Virtual interrupt number assigned to this INO.  */
70 /*0x04*/unsigned int virt_irq;
71 };
72
73 #define NUM_IVECS       (IMAP_INR + 1)
74 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
75
76 #define __irq_ino(irq) \
77         (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
78 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
79 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
80
81 /* This has to be in the main kernel image, it cannot be
82  * turned into per-cpu data.  The reason is that the main
83  * kernel image is locked into the TLB and this structure
84  * is accessed from the vectored interrupt trap handler.  If
85  * access to this structure takes a TLB miss it could cause
86  * the 5-level sparc v9 trap stack to overflow.
87  */
88 #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
89
90 static unsigned int virt_to_real_irq_table[NR_IRQS];
91
92 static unsigned char virt_irq_alloc(unsigned int real_irq)
93 {
94         unsigned char ent;
95
96         BUILD_BUG_ON(NR_IRQS >= 256);
97
98         for (ent = 1; ent < NR_IRQS; ent++) {
99                 if (!virt_to_real_irq_table[ent])
100                         break;
101         }
102         if (ent >= NR_IRQS) {
103                 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
104                 return 0;
105         }
106
107         virt_to_real_irq_table[ent] = real_irq;
108
109         return ent;
110 }
111
112 static void virt_irq_free(unsigned int virt_irq)
113 {
114         unsigned int real_irq;
115
116         if (virt_irq >= NR_IRQS)
117                 return;
118
119         real_irq = virt_to_real_irq_table[virt_irq];
120         virt_to_real_irq_table[virt_irq] = 0;
121
122         __bucket(real_irq)->virt_irq = 0;
123 }
124
125 static unsigned int virt_to_real_irq(unsigned char virt_irq)
126 {
127         return virt_to_real_irq_table[virt_irq];
128 }
129
130 /*
131  * /proc/interrupts printing:
132  */
133
134 int show_interrupts(struct seq_file *p, void *v)
135 {
136         int i = *(loff_t *) v, j;
137         struct irqaction * action;
138         unsigned long flags;
139
140         if (i == 0) {
141                 seq_printf(p, "           ");
142                 for_each_online_cpu(j)
143                         seq_printf(p, "CPU%d       ",j);
144                 seq_putc(p, '\n');
145         }
146
147         if (i < NR_IRQS) {
148                 spin_lock_irqsave(&irq_desc[i].lock, flags);
149                 action = irq_desc[i].action;
150                 if (!action)
151                         goto skip;
152                 seq_printf(p, "%3d: ",i);
153 #ifndef CONFIG_SMP
154                 seq_printf(p, "%10u ", kstat_irqs(i));
155 #else
156                 for_each_online_cpu(j)
157                         seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
158 #endif
159                 seq_printf(p, " %9s", irq_desc[i].chip->typename);
160                 seq_printf(p, "  %s", action->name);
161
162                 for (action=action->next; action; action = action->next)
163                         seq_printf(p, ", %s", action->name);
164
165                 seq_putc(p, '\n');
166 skip:
167                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
168         }
169         return 0;
170 }
171
172 extern unsigned long real_hard_smp_processor_id(void);
173
174 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
175 {
176         unsigned int tid;
177
178         if (this_is_starfire) {
179                 tid = starfire_translate(imap, cpuid);
180                 tid <<= IMAP_TID_SHIFT;
181                 tid &= IMAP_TID_UPA;
182         } else {
183                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
184                         unsigned long ver;
185
186                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
187                         if ((ver >> 32UL) == __JALAPENO_ID ||
188                             (ver >> 32UL) == __SERRANO_ID) {
189                                 tid = cpuid << IMAP_TID_SHIFT;
190                                 tid &= IMAP_TID_JBUS;
191                         } else {
192                                 unsigned int a = cpuid & 0x1f;
193                                 unsigned int n = (cpuid >> 5) & 0x1f;
194
195                                 tid = ((a << IMAP_AID_SHIFT) |
196                                        (n << IMAP_NID_SHIFT));
197                                 tid &= (IMAP_AID_SAFARI |
198                                         IMAP_NID_SAFARI);;
199                         }
200                 } else {
201                         tid = cpuid << IMAP_TID_SHIFT;
202                         tid &= IMAP_TID_UPA;
203                 }
204         }
205
206         return tid;
207 }
208
209 struct irq_handler_data {
210         unsigned long   iclr;
211         unsigned long   imap;
212
213         void            (*pre_handler)(unsigned int, void *, void *);
214         void            *pre_handler_arg1;
215         void            *pre_handler_arg2;
216 };
217
218 static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq)
219 {
220         unsigned int real_irq = virt_to_real_irq(virt_irq);
221         struct ino_bucket *bucket = NULL;
222
223         if (likely(real_irq))
224                 bucket = __bucket(real_irq);
225
226         return bucket;
227 }
228
229 #ifdef CONFIG_SMP
230 static int irq_choose_cpu(unsigned int virt_irq)
231 {
232         cpumask_t mask = irq_desc[virt_irq].affinity;
233         int cpuid;
234
235         if (cpus_equal(mask, CPU_MASK_ALL)) {
236                 static int irq_rover;
237                 static DEFINE_SPINLOCK(irq_rover_lock);
238                 unsigned long flags;
239
240                 /* Round-robin distribution... */
241         do_round_robin:
242                 spin_lock_irqsave(&irq_rover_lock, flags);
243
244                 while (!cpu_online(irq_rover)) {
245                         if (++irq_rover >= NR_CPUS)
246                                 irq_rover = 0;
247                 }
248                 cpuid = irq_rover;
249                 do {
250                         if (++irq_rover >= NR_CPUS)
251                                 irq_rover = 0;
252                 } while (!cpu_online(irq_rover));
253
254                 spin_unlock_irqrestore(&irq_rover_lock, flags);
255         } else {
256                 cpumask_t tmp;
257
258                 cpus_and(tmp, cpu_online_map, mask);
259
260                 if (cpus_empty(tmp))
261                         goto do_round_robin;
262
263                 cpuid = first_cpu(tmp);
264         }
265
266         return cpuid;
267 }
268 #else
269 static int irq_choose_cpu(unsigned int virt_irq)
270 {
271         return real_hard_smp_processor_id();
272 }
273 #endif
274
275 static void sun4u_irq_enable(unsigned int virt_irq)
276 {
277         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
278
279         if (likely(data)) {
280                 unsigned long cpuid, imap;
281                 unsigned int tid;
282
283                 cpuid = irq_choose_cpu(virt_irq);
284                 imap = data->imap;
285
286                 tid = sun4u_compute_tid(imap, cpuid);
287
288                 upa_writel(tid | IMAP_VALID, imap);
289         }
290 }
291
292 static void sun4u_irq_disable(unsigned int virt_irq)
293 {
294         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
295
296         if (likely(data)) {
297                 unsigned long imap = data->imap;
298                 u32 tmp = upa_readl(imap);
299
300                 tmp &= ~IMAP_VALID;
301                 upa_writel(tmp, imap);
302         }
303 }
304
305 static void sun4u_irq_end(unsigned int virt_irq)
306 {
307         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
308
309         if (likely(data))
310                 upa_writel(ICLR_IDLE, data->iclr);
311 }
312
313 static void sun4v_irq_enable(unsigned int virt_irq)
314 {
315         struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
316         unsigned int ino = bucket - &ivector_table[0];
317
318         if (likely(bucket)) {
319                 unsigned long cpuid;
320                 int err;
321
322                 cpuid = irq_choose_cpu(virt_irq);
323
324                 err = sun4v_intr_settarget(ino, cpuid);
325                 if (err != HV_EOK)
326                         printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
327                                ino, cpuid, err);
328                 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
329                 if (err != HV_EOK)
330                         printk("sun4v_intr_setenabled(%x): err(%d)\n",
331                                ino, err);
332         }
333 }
334
335 static void sun4v_irq_disable(unsigned int virt_irq)
336 {
337         struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
338         unsigned int ino = bucket - &ivector_table[0];
339
340         if (likely(bucket)) {
341                 int err;
342
343                 err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
344                 if (err != HV_EOK)
345                         printk("sun4v_intr_setenabled(%x): "
346                                "err(%d)\n", ino, err);
347         }
348 }
349
350 #ifdef CONFIG_PCI_MSI
351 static void sun4v_msi_enable(unsigned int virt_irq)
352 {
353         sun4v_irq_enable(virt_irq);
354         unmask_msi_irq(virt_irq);
355 }
356
357 static void sun4v_msi_disable(unsigned int virt_irq)
358 {
359         mask_msi_irq(virt_irq);
360         sun4v_irq_disable(virt_irq);
361 }
362 #endif
363
364 static void sun4v_irq_end(unsigned int virt_irq)
365 {
366         struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
367         unsigned int ino = bucket - &ivector_table[0];
368
369         if (likely(bucket)) {
370                 int err;
371
372                 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
373                 if (err != HV_EOK)
374                         printk("sun4v_intr_setstate(%x): "
375                                "err(%d)\n", ino, err);
376         }
377 }
378
379 static void run_pre_handler(unsigned int virt_irq)
380 {
381         struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
382         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
383
384         if (likely(data->pre_handler)) {
385                 data->pre_handler(__irq_ino(__irq(bucket)),
386                                   data->pre_handler_arg1,
387                                   data->pre_handler_arg2);
388         }
389 }
390
391 static struct irq_chip sun4u_irq = {
392         .typename       = "sun4u",
393         .enable         = sun4u_irq_enable,
394         .disable        = sun4u_irq_disable,
395         .end            = sun4u_irq_end,
396 };
397
398 static struct irq_chip sun4u_irq_ack = {
399         .typename       = "sun4u+ack",
400         .enable         = sun4u_irq_enable,
401         .disable        = sun4u_irq_disable,
402         .ack            = run_pre_handler,
403         .end            = sun4u_irq_end,
404 };
405
406 static struct irq_chip sun4v_irq = {
407         .typename       = "sun4v",
408         .enable         = sun4v_irq_enable,
409         .disable        = sun4v_irq_disable,
410         .end            = sun4v_irq_end,
411 };
412
413 static struct irq_chip sun4v_irq_ack = {
414         .typename       = "sun4v+ack",
415         .enable         = sun4v_irq_enable,
416         .disable        = sun4v_irq_disable,
417         .ack            = run_pre_handler,
418         .end            = sun4v_irq_end,
419 };
420
421 #ifdef CONFIG_PCI_MSI
422 static struct irq_chip sun4v_msi = {
423         .typename       = "sun4v+msi",
424         .mask           = mask_msi_irq,
425         .unmask         = unmask_msi_irq,
426         .enable         = sun4v_msi_enable,
427         .disable        = sun4v_msi_disable,
428         .ack            = run_pre_handler,
429         .end            = sun4v_irq_end,
430 };
431 #endif
432
433 void irq_install_pre_handler(int virt_irq,
434                              void (*func)(unsigned int, void *, void *),
435                              void *arg1, void *arg2)
436 {
437         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
438         struct irq_chip *chip;
439
440         data->pre_handler = func;
441         data->pre_handler_arg1 = arg1;
442         data->pre_handler_arg2 = arg2;
443
444         chip = get_irq_chip(virt_irq);
445         if (chip == &sun4u_irq_ack ||
446             chip == &sun4v_irq_ack
447 #ifdef CONFIG_PCI_MSI
448             || chip == &sun4v_msi
449 #endif
450             )
451                 return;
452
453         chip = (chip == &sun4u_irq ?
454                 &sun4u_irq_ack : &sun4v_irq_ack);
455         set_irq_chip(virt_irq, chip);
456 }
457
458 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
459 {
460         struct ino_bucket *bucket;
461         struct irq_handler_data *data;
462         int ino;
463
464         BUG_ON(tlb_type == hypervisor);
465
466         ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
467         bucket = &ivector_table[ino];
468         if (!bucket->virt_irq) {
469                 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
470                 set_irq_chip(bucket->virt_irq, &sun4u_irq);
471         }
472
473         data = get_irq_chip_data(bucket->virt_irq);
474         if (unlikely(data))
475                 goto out;
476
477         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
478         if (unlikely(!data)) {
479                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
480                 prom_halt();
481         }
482         set_irq_chip_data(bucket->virt_irq, data);
483
484         data->imap  = imap;
485         data->iclr  = iclr;
486
487 out:
488         return bucket->virt_irq;
489 }
490
491 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
492 {
493         struct ino_bucket *bucket;
494         struct irq_handler_data *data;
495         unsigned long sysino;
496
497         BUG_ON(tlb_type != hypervisor);
498
499         sysino = sun4v_devino_to_sysino(devhandle, devino);
500         bucket = &ivector_table[sysino];
501         if (!bucket->virt_irq) {
502                 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
503                 set_irq_chip(bucket->virt_irq, &sun4v_irq);
504         }
505
506         data = get_irq_chip_data(bucket->virt_irq);
507         if (unlikely(data))
508                 goto out;
509
510         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
511         if (unlikely(!data)) {
512                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
513                 prom_halt();
514         }
515         set_irq_chip_data(bucket->virt_irq, data);
516
517         /* Catch accidental accesses to these things.  IMAP/ICLR handling
518          * is done by hypervisor calls on sun4v platforms, not by direct
519          * register accesses.
520          */
521         data->imap = ~0UL;
522         data->iclr = ~0UL;
523
524 out:
525         return bucket->virt_irq;
526 }
527
528 #ifdef CONFIG_PCI_MSI
529 unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
530                              unsigned int msi_start, unsigned int msi_end)
531 {
532         struct ino_bucket *bucket;
533         struct irq_handler_data *data;
534         unsigned long sysino;
535         unsigned int devino;
536
537         BUG_ON(tlb_type != hypervisor);
538
539         /* Find a free devino in the given range.  */
540         for (devino = msi_start; devino < msi_end; devino++) {
541                 sysino = sun4v_devino_to_sysino(devhandle, devino);
542                 bucket = &ivector_table[sysino];
543                 if (!bucket->virt_irq)
544                         break;
545         }
546         if (devino >= msi_end)
547                 return 0;
548
549         sysino = sun4v_devino_to_sysino(devhandle, devino);
550         bucket = &ivector_table[sysino];
551         bucket->virt_irq = virt_irq_alloc(__irq(bucket));
552         *virt_irq_p = bucket->virt_irq;
553         set_irq_chip(bucket->virt_irq, &sun4v_msi);
554
555         data = get_irq_chip_data(bucket->virt_irq);
556         if (unlikely(data))
557                 return devino;
558
559         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
560         if (unlikely(!data)) {
561                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
562                 prom_halt();
563         }
564         set_irq_chip_data(bucket->virt_irq, data);
565
566         data->imap = ~0UL;
567         data->iclr = ~0UL;
568
569         return devino;
570 }
571
572 void sun4v_destroy_msi(unsigned int virt_irq)
573 {
574         virt_irq_free(virt_irq);
575 }
576 #endif
577
578 void ack_bad_irq(unsigned int virt_irq)
579 {
580         struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
581         unsigned int ino = 0xdeadbeef;
582
583         if (bucket)
584                 ino = bucket - &ivector_table[0];
585
586         printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
587                ino, virt_irq);
588 }
589
590 #ifndef CONFIG_SMP
591 extern irqreturn_t timer_interrupt(int, void *);
592
593 void timer_irq(int irq, struct pt_regs *regs)
594 {
595         unsigned long clr_mask = 1 << irq;
596         unsigned long tick_mask = tick_ops->softint_mask;
597         struct pt_regs *old_regs;
598
599         if (get_softint() & tick_mask) {
600                 irq = 0;
601                 clr_mask = tick_mask;
602         }
603         clear_softint(clr_mask);
604
605         old_regs = set_irq_regs(regs);
606         irq_enter();
607
608         kstat_this_cpu.irqs[0]++;
609         timer_interrupt(irq, NULL);
610
611         irq_exit();
612         set_irq_regs(old_regs);
613 }
614 #endif
615
616 void handler_irq(int irq, struct pt_regs *regs)
617 {
618         struct ino_bucket *bucket;
619         struct pt_regs *old_regs;
620
621         clear_softint(1 << irq);
622
623         old_regs = set_irq_regs(regs);
624         irq_enter();
625
626         /* Sliiiick... */
627         bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0));
628         while (bucket) {
629                 struct ino_bucket *next = __bucket(bucket->irq_chain);
630
631                 bucket->irq_chain = 0;
632                 __do_IRQ(bucket->virt_irq);
633
634                 bucket = next;
635         }
636
637         irq_exit();
638         set_irq_regs(old_regs);
639 }
640
641 struct sun5_timer {
642         u64     count0;
643         u64     limit0;
644         u64     count1;
645         u64     limit1;
646 };
647
648 static struct sun5_timer *prom_timers;
649 static u64 prom_limit0, prom_limit1;
650
651 static void map_prom_timers(void)
652 {
653         struct device_node *dp;
654         unsigned int *addr;
655
656         /* PROM timer node hangs out in the top level of device siblings... */
657         dp = of_find_node_by_path("/");
658         dp = dp->child;
659         while (dp) {
660                 if (!strcmp(dp->name, "counter-timer"))
661                         break;
662                 dp = dp->sibling;
663         }
664
665         /* Assume if node is not present, PROM uses different tick mechanism
666          * which we should not care about.
667          */
668         if (!dp) {
669                 prom_timers = (struct sun5_timer *) 0;
670                 return;
671         }
672
673         /* If PROM is really using this, it must be mapped by him. */
674         addr = of_get_property(dp, "address", NULL);
675         if (!addr) {
676                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
677                 prom_timers = (struct sun5_timer *) 0;
678                 return;
679         }
680         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
681 }
682
683 static void kill_prom_timer(void)
684 {
685         if (!prom_timers)
686                 return;
687
688         /* Save them away for later. */
689         prom_limit0 = prom_timers->limit0;
690         prom_limit1 = prom_timers->limit1;
691
692         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
693          * We turn both off here just to be paranoid.
694          */
695         prom_timers->limit0 = 0;
696         prom_timers->limit1 = 0;
697
698         /* Wheee, eat the interrupt packet too... */
699         __asm__ __volatile__(
700 "       mov     0x40, %%g2\n"
701 "       ldxa    [%%g0] %0, %%g1\n"
702 "       ldxa    [%%g2] %1, %%g1\n"
703 "       stxa    %%g0, [%%g0] %0\n"
704 "       membar  #Sync\n"
705         : /* no outputs */
706         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
707         : "g1", "g2");
708 }
709
710 void init_irqwork_curcpu(void)
711 {
712         int cpu = hard_smp_processor_id();
713
714         trap_block[cpu].irq_worklist = 0;
715 }
716
717 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
718 {
719         unsigned long num_entries = 128;
720         unsigned long status;
721
722         status = sun4v_cpu_qconf(type, paddr, num_entries);
723         if (status != HV_EOK) {
724                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
725                             "err %lu\n", type, paddr, num_entries, status);
726                 prom_halt();
727         }
728 }
729
730 static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
731 {
732         struct trap_per_cpu *tb = &trap_block[this_cpu];
733
734         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
735         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
736         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
737         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
738 }
739
740 static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
741 {
742         void *page;
743
744         if (use_bootmem)
745                 page = alloc_bootmem_low_pages(PAGE_SIZE);
746         else
747                 page = (void *) get_zeroed_page(GFP_ATOMIC);
748
749         if (!page) {
750                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
751                 prom_halt();
752         }
753
754         *pa_ptr = __pa(page);
755 }
756
757 static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
758 {
759         void *page;
760
761         if (use_bootmem)
762                 page = alloc_bootmem_low_pages(PAGE_SIZE);
763         else
764                 page = (void *) get_zeroed_page(GFP_ATOMIC);
765
766         if (!page) {
767                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
768                 prom_halt();
769         }
770
771         *pa_ptr = __pa(page);
772 }
773
774 static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
775 {
776 #ifdef CONFIG_SMP
777         void *page;
778
779         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
780
781         if (use_bootmem)
782                 page = alloc_bootmem_low_pages(PAGE_SIZE);
783         else
784                 page = (void *) get_zeroed_page(GFP_ATOMIC);
785
786         if (!page) {
787                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
788                 prom_halt();
789         }
790
791         tb->cpu_mondo_block_pa = __pa(page);
792         tb->cpu_list_pa = __pa(page + 64);
793 #endif
794 }
795
796 /* Allocate and register the mondo and error queues for this cpu.  */
797 void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load)
798 {
799         struct trap_per_cpu *tb = &trap_block[cpu];
800
801         if (alloc) {
802                 alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
803                 alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
804                 alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
805                 alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
806                 alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
807                 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
808
809                 init_cpu_send_mondo_info(tb, use_bootmem);
810         }
811
812         if (load) {
813                 if (cpu != hard_smp_processor_id()) {
814                         prom_printf("SUN4V: init mondo on cpu %d not %d\n",
815                                     cpu, hard_smp_processor_id());
816                         prom_halt();
817                 }
818                 sun4v_register_mondo_queues(cpu);
819         }
820 }
821
822 static struct irqaction timer_irq_action = {
823         .name = "timer",
824 };
825
826 /* Only invoked on boot processor. */
827 void __init init_IRQ(void)
828 {
829         map_prom_timers();
830         kill_prom_timer();
831         memset(&ivector_table[0], 0, sizeof(ivector_table));
832
833         if (tlb_type == hypervisor)
834                 sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
835
836         /* We need to clear any IRQ's pending in the soft interrupt
837          * registers, a spurious one could be left around from the
838          * PROM timer which we just disabled.
839          */
840         clear_softint(get_softint());
841
842         /* Now that ivector table is initialized, it is safe
843          * to receive IRQ vector traps.  We will normally take
844          * one or two right now, in case some device PROM used
845          * to boot us wants to speak to us.  We just ignore them.
846          */
847         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
848                              "or        %%g1, %0, %%g1\n\t"
849                              "wrpr      %%g1, 0x0, %%pstate"
850                              : /* No outputs */
851                              : "i" (PSTATE_IE)
852                              : "g1");
853
854         irq_desc[0].action = &timer_irq_action;
855 }