2 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
4 * Author Andreas Eversberg (jolly@eversberg.eu)
5 * ported to mqueue mechanism:
6 * Peter Sprenger (sprengermoving-bytes.de)
8 * inspired by existing hfc-pci driver:
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil (kkeil@suse.de)
11 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu)
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * Thanks to Cologne Chip AG for this great controller!
34 * By default (0), the card is automatically detected.
35 * Or use the following combinations:
36 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
37 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
38 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
39 * Bit 8 = 0x00100 = uLaw (instead of aLaw)
40 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
42 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
43 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
45 * Bit 14 = 0x04000 = Use external ram (128K)
46 * Bit 15 = 0x08000 = Use external ram (512K)
47 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32
48 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else
50 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
51 * (all other bits are reserved and shall be 0)
52 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
55 * port: (optional or required for all ports on all installed cards)
56 * HFC-4S/HFC-8S only bits:
57 * Bit 0 = 0x001 = Use master clock for this S/T interface
58 * (ony once per chip).
59 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode)
60 * Don't use this unless you know what you are doing!
61 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing)
62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
63 * received from port 1
66 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical
67 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode)
68 * Bit 2 = 0x0004 = Report LOS
69 * Bit 3 = 0x0008 = Report AIS
70 * Bit 4 = 0x0010 = Report SLIP
71 * Bit 5 = 0x0020 = Report RDI
72 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode.
75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode.
76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
78 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
80 * (all other bits are reserved and shall be 0)
83 * NOTE: only one debug value must be given for all cards
84 * enable debugging (see hfc_multi.h for debug options)
87 * NOTE: only one poll value must be given for all cards
88 * Give the number of samples for each fifo process.
89 * By default 128 is used. Decrease to reduce delay, increase to
90 * reduce cpu load. If unsure, don't mess with it!
91 * Valid is 8, 16, 32, 64, 128, 256.
94 * NOTE: only one pcm value must be given for every card.
95 * The PCM bus id tells the mISDNdsp module about the connected PCM bus.
96 * By default (0), the PCM bus id is 100 for the card that is PCM master.
97 * If multiple cards are PCM master (because they are not interconnected),
98 * each card with PCM master will have increasing PCM id.
99 * All PCM busses with the same ID are expected to be connected and have
100 * common time slots slots.
101 * Only one chip of the PCM bus must be master, the others slave.
102 * -1 means no support of PCM bus not even.
103 * Omit this value, if all cards are interconnected or none is connected.
104 * If unsure, don't give this parameter.
107 * NOTE: only one poll value must be given for every card.
108 * Also this value must be given for non-E1 cards. If omitted, the E1
109 * card has D-channel on time slot 16, which is default.
110 * If 1..15 or 17..31, an alternate time slot is used for D-channel.
111 * In this case, the application must be able to handle this.
112 * If -1 is given, the D-channel is disabled and all 31 slots can be used
113 * for B-channel. (only for specific applications)
114 * If you don't know how to use it, you don't need it!
117 * NOTE: only one mode value must be given for every card.
118 * -> See hfc_multi.h for HFC_IO_MODE_* values
119 * By default, the IO mode is pci memory IO (MEMIO).
120 * Some cards requre specific IO mode, so it cannot be changed.
121 * It may be usefull to set IO mode to register io (REGIO) to solve
122 * PCI bridge problems.
123 * If unsure, don't give this parameter.
126 * NOTE: only one clockdelay_nt value must be given once for all cards.
127 * Give the value of the clock control register (A_ST_CLK_DLY)
128 * of the S/T interfaces in NT mode.
129 * This register is needed for the TBR3 certification, so don't change it.
132 * NOTE: only one clockdelay_te value must be given once
133 * Give the value of the clock control register (A_ST_CLK_DLY)
134 * of the S/T interfaces in TE mode.
135 * This register is needed for the TBR3 certification, so don't change it.
138 * NOTE: only one clock value must be given once
139 * Selects interface with clock source for mISDN and applications.
140 * Set to card number starting with 1. Set to -1 to disable.
141 * By default, the first card is used as clock source.
145 * debug register access (never use this, it will flood your system log)
146 * #define HFC_REGISTER_DEBUG
149 #define HFC_MULTI_VERSION "2.03"
151 #include <linux/module.h>
152 #include <linux/pci.h>
153 #include <linux/delay.h>
154 #include <linux/mISDNhw.h>
155 #include <linux/mISDNdsp.h>
158 #define IRQCOUNT_DEBUG
162 #include "hfc_multi.h"
168 #define MAX_PORTS (8 * MAX_CARDS)
170 static LIST_HEAD(HFClist);
171 static spinlock_t HFClock; /* global hfc list lock */
173 static void ph_state_change(struct dchannel *);
175 static struct hfc_multi *syncmaster;
176 static int plxsd_master; /* if we have a master card (yet) */
177 static spinlock_t plx_lock; /* may not acquire other lock inside */
183 static int poll_timer = 6; /* default = 128 samples = 16ms */
184 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
185 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 };
186 #define CLKDEL_TE 0x0f /* CLKDEL in TE mode */
187 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode
188 (0x60 MUST be included!) */
190 #define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */
191 #define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */
192 #define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */
198 static uint type[MAX_CARDS];
199 static int pcm[MAX_CARDS];
200 static int dslot[MAX_CARDS];
201 static uint iomode[MAX_CARDS];
202 static uint port[MAX_PORTS];
207 static uint clockdelay_te = CLKDEL_TE;
208 static uint clockdelay_nt = CLKDEL_NT;
210 static int HFC_cnt, Port_cnt, PCM_cnt = 99;
212 MODULE_AUTHOR("Andreas Eversberg");
213 MODULE_LICENSE("GPL");
214 MODULE_VERSION(HFC_MULTI_VERSION);
215 module_param(debug, uint, S_IRUGO | S_IWUSR);
216 module_param(poll, uint, S_IRUGO | S_IWUSR);
217 module_param(clock, int, S_IRUGO | S_IWUSR);
218 module_param(timer, uint, S_IRUGO | S_IWUSR);
219 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
220 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
221 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
222 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
223 module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR);
224 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
225 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
227 #ifdef HFC_REGISTER_DEBUG
228 #define HFC_outb(hc, reg, val) \
229 (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
230 #define HFC_outb_nodebug(hc, reg, val) \
231 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
232 #define HFC_inb(hc, reg) \
233 (hc->HFC_inb(hc, reg, __func__, __LINE__))
234 #define HFC_inb_nodebug(hc, reg) \
235 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
236 #define HFC_inw(hc, reg) \
237 (hc->HFC_inw(hc, reg, __func__, __LINE__))
238 #define HFC_inw_nodebug(hc, reg) \
239 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
240 #define HFC_wait(hc) \
241 (hc->HFC_wait(hc, __func__, __LINE__))
242 #define HFC_wait_nodebug(hc) \
243 (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
245 #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val))
246 #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val))
247 #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg))
248 #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg))
249 #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg))
250 #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg))
251 #define HFC_wait(hc) (hc->HFC_wait(hc))
252 #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
255 /* HFC_IO_MODE_PCIMEM */
257 #ifdef HFC_REGISTER_DEBUG
258 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
259 const char *function, int line)
261 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
264 writeb(val, (hc->pci_membase)+reg);
267 #ifdef HFC_REGISTER_DEBUG
268 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
270 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
273 return readb((hc->pci_membase)+reg);
276 #ifdef HFC_REGISTER_DEBUG
277 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
279 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
282 return readw((hc->pci_membase)+reg);
285 #ifdef HFC_REGISTER_DEBUG
286 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
288 HFC_wait_pcimem(struct hfc_multi *hc)
291 while (readb((hc->pci_membase)+R_STATUS) & V_BUSY);
294 /* HFC_IO_MODE_REGIO */
296 #ifdef HFC_REGISTER_DEBUG
297 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
298 const char *function, int line)
300 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
303 outb(reg, (hc->pci_iobase)+4);
304 outb(val, hc->pci_iobase);
307 #ifdef HFC_REGISTER_DEBUG
308 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
310 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
313 outb(reg, (hc->pci_iobase)+4);
314 return inb(hc->pci_iobase);
317 #ifdef HFC_REGISTER_DEBUG
318 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
320 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
323 outb(reg, (hc->pci_iobase)+4);
324 return inw(hc->pci_iobase);
327 #ifdef HFC_REGISTER_DEBUG
328 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
330 HFC_wait_regio(struct hfc_multi *hc)
333 outb(R_STATUS, (hc->pci_iobase)+4);
334 while (inb(hc->pci_iobase) & V_BUSY);
337 #ifdef HFC_REGISTER_DEBUG
339 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
340 const char *function, int line)
342 char regname[256] = "", bits[9] = "xxxxxxxx";
346 while (hfc_register_names[++i].name) {
347 if (hfc_register_names[i].reg == reg)
348 strcat(regname, hfc_register_names[i].name);
350 if (regname[0] == '\0')
351 strcpy(regname, "register");
353 bits[7] = '0'+(!!(val&1));
354 bits[6] = '0'+(!!(val&2));
355 bits[5] = '0'+(!!(val&4));
356 bits[4] = '0'+(!!(val&8));
357 bits[3] = '0'+(!!(val&16));
358 bits[2] = '0'+(!!(val&32));
359 bits[1] = '0'+(!!(val&64));
360 bits[0] = '0'+(!!(val&128));
362 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
363 hc->id, reg, regname, val, bits, function, line);
364 HFC_outb_nodebug(hc, reg, val);
367 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
369 char regname[256] = "", bits[9] = "xxxxxxxx";
370 u_char val = HFC_inb_nodebug(hc, reg);
374 while (hfc_register_names[i++].name)
376 while (hfc_register_names[++i].name) {
377 if (hfc_register_names[i].reg == reg)
378 strcat(regname, hfc_register_names[i].name);
380 if (regname[0] == '\0')
381 strcpy(regname, "register");
383 bits[7] = '0'+(!!(val&1));
384 bits[6] = '0'+(!!(val&2));
385 bits[5] = '0'+(!!(val&4));
386 bits[4] = '0'+(!!(val&8));
387 bits[3] = '0'+(!!(val&16));
388 bits[2] = '0'+(!!(val&32));
389 bits[1] = '0'+(!!(val&64));
390 bits[0] = '0'+(!!(val&128));
392 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
393 hc->id, reg, regname, val, bits, function, line);
397 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
399 char regname[256] = "";
400 u_short val = HFC_inw_nodebug(hc, reg);
404 while (hfc_register_names[i++].name)
406 while (hfc_register_names[++i].name) {
407 if (hfc_register_names[i].reg == reg)
408 strcat(regname, hfc_register_names[i].name);
410 if (regname[0] == '\0')
411 strcpy(regname, "register");
414 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
415 hc->id, reg, regname, val, function, line);
419 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
421 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
422 hc->id, function, line);
423 HFC_wait_nodebug(hc);
427 /* write fifo data (REGIO) */
429 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
431 outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
433 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
438 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
443 outb(*data, hc->pci_iobase);
448 /* write fifo data (PCIMEM) */
450 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
453 writel(cpu_to_le32(*(u32 *)data),
454 hc->pci_membase + A_FIFO_DATA0);
459 writew(cpu_to_le16(*(u16 *)data),
460 hc->pci_membase + A_FIFO_DATA0);
465 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
470 /* read fifo data (REGIO) */
472 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
474 outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
476 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
481 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
486 *data = inb(hc->pci_iobase);
492 /* read fifo data (PCIMEM) */
494 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
498 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
504 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
509 *data = readb(hc->pci_membase + A_FIFO_DATA0);
517 enable_hwirq(struct hfc_multi *hc)
519 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
520 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
524 disable_hwirq(struct hfc_multi *hc)
526 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
527 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
531 #define MAX_TDM_CHAN 32
535 enablepcibridge(struct hfc_multi *c)
537 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
541 disablepcibridge(struct hfc_multi *c)
543 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
547 readpcibridge(struct hfc_multi *hc, unsigned char address)
555 /* slow down a PCI read access by 1 PCI clock cycle */
556 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
563 /* select local bridge port address by writing to CIP port */
564 /* data = HFC_inb(c, cipv); * was _io before */
565 outw(cipv, hc->pci_iobase + 4);
566 data = inb(hc->pci_iobase);
568 /* restore R_CTRL for normal PCI read cycle speed */
569 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
575 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
588 /* select local bridge port address by writing to CIP port */
589 outw(cipv, hc->pci_iobase + 4);
590 /* define a 32 bit dword with 4 identical bytes for write sequence */
591 datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
592 ((__u32) data << 24);
595 * write this 32 bit dword to the bridge data port
596 * this will initiate a write sequence of up to 4 writes to the same
597 * address on the local bus interface the number of write accesses
598 * is undefined but >=1 and depends on the next PCI transaction
599 * during write sequence on the local bus
601 outl(datav, hc->pci_iobase);
605 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
607 /* Do data pin read low byte */
608 HFC_outb(hc, R_GPIO_OUT1, reg);
612 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
614 cpld_set_reg(hc, reg);
617 writepcibridge(hc, 1, val);
618 disablepcibridge(hc);
624 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
626 unsigned char bytein;
628 cpld_set_reg(hc, reg);
630 /* Do data pin read low byte */
631 HFC_outb(hc, R_GPIO_OUT1, reg);
634 bytein = readpcibridge(hc, 1);
635 disablepcibridge(hc);
641 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
643 cpld_write_reg(hc, 0, 0xff & addr);
644 cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
647 inline unsigned short
648 vpm_read_address(struct hfc_multi *c)
651 unsigned short highbit;
653 addr = cpld_read_reg(c, 0);
654 highbit = cpld_read_reg(c, 1);
656 addr = addr | (highbit << 8);
662 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
666 vpm_write_address(c, addr);
674 res = readpcibridge(c, 1);
683 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
686 vpm_write_address(c, addr);
695 writepcibridge(c, 1, data);
703 regin = vpm_in(c, which, addr);
705 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
706 "0x%x\n", data, addr, regin);
713 vpm_init(struct hfc_multi *wc)
717 unsigned int i, x, y;
720 for (x = 0; x < NUM_EC; x++) {
723 ver = vpm_in(wc, x, 0x1a0);
724 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
727 for (y = 0; y < 4; y++) {
728 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
729 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
730 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
733 /* Setup TDM path - sets fsync and tdm_clk as inputs */
734 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
735 vpm_out(wc, x, 0x1a3, reg & ~2);
737 /* Setup Echo length (256 taps) */
738 vpm_out(wc, x, 0x022, 1);
739 vpm_out(wc, x, 0x023, 0xff);
741 /* Setup timeslots */
742 vpm_out(wc, x, 0x02f, 0x00);
743 mask = 0x02020202 << (x * 4);
745 /* Setup the tdm channel masks for all chips */
746 for (i = 0; i < 4; i++)
747 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
749 /* Setup convergence rate */
750 printk(KERN_DEBUG "VPM: A-law mode\n");
751 reg = 0x00 | 0x10 | 0x01;
752 vpm_out(wc, x, 0x20, reg);
753 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
754 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
756 vpm_out(wc, x, 0x24, 0x02);
757 reg = vpm_in(wc, x, 0x24);
758 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
760 /* Initialize echo cans */
761 for (i = 0; i < MAX_TDM_CHAN; i++) {
762 if (mask & (0x00000001 << i))
763 vpm_out(wc, x, i, 0x00);
767 * ARM arch at least disallows a udelay of
768 * more than 2ms... it gives a fake "__bad_udelay"
769 * reference at link-time.
770 * long delays in kernel code are pretty sucky anyway
771 * for now work around it using 5 x 2ms instead of 1 x 10ms
780 /* Put in bypass mode */
781 for (i = 0; i < MAX_TDM_CHAN; i++) {
782 if (mask & (0x00000001 << i))
783 vpm_out(wc, x, i, 0x01);
787 for (i = 0; i < MAX_TDM_CHAN; i++) {
788 if (mask & (0x00000001 << i))
789 vpm_out(wc, x, 0x78 + i, 0x01);
797 vpm_check(struct hfc_multi *hctmp)
801 gpi2 = HFC_inb(hctmp, R_GPI_IN2);
803 if ((gpi2 & 0x3) != 0x3)
804 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
810 * Interface to enable/disable the HW Echocan
812 * these functions are called within a spin_lock_irqsave on
813 * the channel instance lock, so we are not disturbed by irqs
815 * we can later easily change the interface to make other
816 * things configurable, for now we configure the taps
821 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
823 unsigned int timeslot;
825 struct bchannel *bch = hc->chan[ch].bch;
830 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
837 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
838 sizeof(int), &txadj, GFP_ATOMIC);
840 recv_Bchannel_skb(bch, skb);
843 timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
846 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
849 vpm_out(hc, unit, timeslot, 0x7e);
853 vpm_echocan_off(struct hfc_multi *hc, int ch)
855 unsigned int timeslot;
857 struct bchannel *bch = hc->chan[ch].bch;
863 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
870 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
871 sizeof(int), &txadj, GFP_ATOMIC);
873 recv_Bchannel_skb(bch, skb);
876 timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
879 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
882 vpm_out(hc, unit, timeslot, 0x01);
887 * Speech Design resync feature
888 * NOTE: This is called sometimes outside interrupt handler.
889 * We must lock irqsave, so no other interrupt (other card) will occurr!
890 * Also multiple interrupts may nest, so must lock each access (lists, card)!
893 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
895 struct hfc_multi *hc, *next, *pcmmaster = NULL;
896 void __iomem *plx_acc_32;
900 spin_lock_irqsave(&HFClock, flags);
901 spin_lock(&plx_lock); /* must be locked inside other locks */
903 if (debug & DEBUG_HFCMULTI_PLXSD)
904 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
905 __func__, syncmaster);
907 /* select new master */
909 if (debug & DEBUG_HFCMULTI_PLXSD)
910 printk(KERN_DEBUG "using provided controller\n");
912 list_for_each_entry_safe(hc, next, &HFClist, list) {
913 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
914 if (hc->syncronized) {
922 /* Disable sync of all cards */
923 list_for_each_entry_safe(hc, next, &HFClist, list) {
924 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
925 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
926 pv = readl(plx_acc_32);
927 pv &= ~PLX_SYNC_O_EN;
928 writel(pv, plx_acc_32);
929 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
932 if (debug & DEBUG_HFCMULTI_PLXSD)
934 "Schedule SYNC_I\n");
935 hc->e1_resync |= 1; /* get SYNC_I */
943 if (debug & DEBUG_HFCMULTI_PLXSD)
944 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
945 "interface.\n", hc->id, hc);
946 /* Enable new sync master */
947 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
948 pv = readl(plx_acc_32);
950 writel(pv, plx_acc_32);
951 /* switch to jatt PLL, if not disabled by RX_SYNC */
952 if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
953 if (debug & DEBUG_HFCMULTI_PLXSD)
954 printk(KERN_DEBUG "Schedule jatt PLL\n");
955 hc->e1_resync |= 2; /* switch to jatt */
960 if (debug & DEBUG_HFCMULTI_PLXSD)
962 "id=%d (0x%p) = PCM master syncronized "
963 "with QUARTZ\n", hc->id, hc);
965 /* Use the crystal clock for the PCM
967 if (debug & DEBUG_HFCMULTI_PLXSD)
969 "Schedule QUARTZ for HFC-E1\n");
970 hc->e1_resync |= 4; /* switch quartz */
972 if (debug & DEBUG_HFCMULTI_PLXSD)
974 "QUARTZ is automatically "
975 "enabled by HFC-%dS\n", hc->type);
977 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
978 pv = readl(plx_acc_32);
980 writel(pv, plx_acc_32);
983 printk(KERN_ERR "%s no pcm master, this MUST "
984 "not happen!\n", __func__);
986 syncmaster = newmaster;
988 spin_unlock(&plx_lock);
989 spin_unlock_irqrestore(&HFClock, flags);
992 /* This must be called AND hc must be locked irqsave!!! */
994 plxsd_checksync(struct hfc_multi *hc, int rm)
996 if (hc->syncronized) {
997 if (syncmaster == NULL) {
998 if (debug & DEBUG_HFCMULTI_PLXSD)
999 printk(KERN_WARNING "%s: GOT sync on card %d"
1000 " (id=%d)\n", __func__, hc->id + 1,
1002 hfcmulti_resync(hc, hc, rm);
1005 if (syncmaster == hc) {
1006 if (debug & DEBUG_HFCMULTI_PLXSD)
1007 printk(KERN_WARNING "%s: LOST sync on card %d"
1008 " (id=%d)\n", __func__, hc->id + 1,
1010 hfcmulti_resync(hc, NULL, rm);
1017 * free hardware resources used by driver
1020 release_io_hfcmulti(struct hfc_multi *hc)
1022 void __iomem *plx_acc_32;
1026 if (debug & DEBUG_HFCMULTI_INIT)
1027 printk(KERN_DEBUG "%s: entered\n", __func__);
1029 /* soft reset also masks all interrupts */
1030 hc->hw.r_cirm |= V_SRES;
1031 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1033 hc->hw.r_cirm &= ~V_SRES;
1034 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1035 udelay(1000); /* instead of 'wait' that may cause locking */
1037 /* release Speech Design card, if PLX was initialized */
1038 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1039 if (debug & DEBUG_HFCMULTI_PLXSD)
1040 printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1041 __func__, hc->id + 1);
1042 spin_lock_irqsave(&plx_lock, plx_flags);
1043 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1044 writel(PLX_GPIOC_INIT, plx_acc_32);
1045 pv = readl(plx_acc_32);
1046 /* Termination off */
1048 /* Disconnect the PCM */
1049 pv |= PLX_SLAVE_EN_N;
1050 pv &= ~PLX_MASTER_EN;
1051 pv &= ~PLX_SYNC_O_EN;
1052 /* Put the DSP in Reset */
1053 pv &= ~PLX_DSP_RES_N;
1054 writel(pv, plx_acc_32);
1055 if (debug & DEBUG_HFCMULTI_INIT)
1056 printk(KERN_WARNING "%s: PCM off: PLX_GPIO=%x\n",
1058 spin_unlock_irqrestore(&plx_lock, plx_flags);
1061 /* disable memory mapped ports / io ports */
1062 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1063 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1064 if (hc->pci_membase)
1065 iounmap(hc->pci_membase);
1066 if (hc->plx_membase)
1067 iounmap(hc->plx_membase);
1069 release_region(hc->pci_iobase, 8);
1072 pci_disable_device(hc->pci_dev);
1073 pci_set_drvdata(hc->pci_dev, NULL);
1075 if (debug & DEBUG_HFCMULTI_INIT)
1076 printk(KERN_DEBUG "%s: done\n", __func__);
1080 * function called to reset the HFC chip. A complete software reset of chip
1081 * and fifos is done. All configuration of the chip is done.
1085 init_chip(struct hfc_multi *hc)
1087 u_long flags, val, val2 = 0, rev;
1089 u_char r_conf_en, rval;
1090 void __iomem *plx_acc_32;
1092 u_long plx_flags, hfc_flags;
1094 struct hfc_multi *pos, *next, *plx_last_hc;
1096 spin_lock_irqsave(&hc->lock, flags);
1097 /* reset all registers */
1098 memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1100 /* revision check */
1101 if (debug & DEBUG_HFCMULTI_INIT)
1102 printk(KERN_DEBUG "%s: entered\n", __func__);
1103 val = HFC_inb(hc, R_CHIP_ID)>>4;
1104 if (val != 0x8 && val != 0xc && val != 0xe) {
1105 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1109 rev = HFC_inb(hc, R_CHIP_RV);
1111 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1112 val, rev, (rev == 0) ? " (old FIFO handling)" : "");
1114 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1116 "HFC_multi: NOTE: Your chip is revision 0, "
1117 "ask Cologne Chip for update. Newer chips "
1118 "have a better FIFO handling. Old chips "
1119 "still work but may have slightly lower "
1120 "HDLC transmit performance.\n");
1123 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1124 "consider chip revision = %ld. The chip / "
1125 "bridge may not work.\n", rev);
1128 /* set s-ram size */
1132 hc->DTMFbase = 0x1000;
1133 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1134 if (debug & DEBUG_HFCMULTI_INIT)
1135 printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1137 hc->hw.r_ctrl |= V_EXT_RAM;
1138 hc->hw.r_ram_sz = 1;
1142 hc->DTMFbase = 0x2000;
1144 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1145 if (debug & DEBUG_HFCMULTI_INIT)
1146 printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1148 hc->hw.r_ctrl |= V_EXT_RAM;
1149 hc->hw.r_ram_sz = 2;
1153 hc->DTMFbase = 0x2000;
1155 hc->max_trans = poll << 1;
1156 if (hc->max_trans > hc->Zlen)
1157 hc->max_trans = hc->Zlen;
1159 /* Speech Design PLX bridge */
1160 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1161 if (debug & DEBUG_HFCMULTI_PLXSD)
1162 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1163 __func__, hc->id + 1);
1164 spin_lock_irqsave(&plx_lock, plx_flags);
1165 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1166 writel(PLX_GPIOC_INIT, plx_acc_32);
1167 pv = readl(plx_acc_32);
1168 /* The first and the last cards are terminating the PCM bus */
1169 pv |= PLX_TERM_ON; /* hc is currently the last */
1170 /* Disconnect the PCM */
1171 pv |= PLX_SLAVE_EN_N;
1172 pv &= ~PLX_MASTER_EN;
1173 pv &= ~PLX_SYNC_O_EN;
1174 /* Put the DSP in Reset */
1175 pv &= ~PLX_DSP_RES_N;
1176 writel(pv, plx_acc_32);
1177 spin_unlock_irqrestore(&plx_lock, plx_flags);
1178 if (debug & DEBUG_HFCMULTI_INIT)
1179 printk(KERN_WARNING "%s: slave/term: PLX_GPIO=%x\n",
1182 * If we are the 3rd PLXSD card or higher, we must turn
1183 * termination of last PLXSD card off.
1185 spin_lock_irqsave(&HFClock, hfc_flags);
1188 list_for_each_entry_safe(pos, next, &HFClist, list) {
1189 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1195 if (plx_count >= 3) {
1196 if (debug & DEBUG_HFCMULTI_PLXSD)
1197 printk(KERN_DEBUG "%s: card %d is between, so "
1198 "we disable termination\n",
1199 __func__, plx_last_hc->id + 1);
1200 spin_lock_irqsave(&plx_lock, plx_flags);
1201 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1202 pv = readl(plx_acc_32);
1204 writel(pv, plx_acc_32);
1205 spin_unlock_irqrestore(&plx_lock, plx_flags);
1206 if (debug & DEBUG_HFCMULTI_INIT)
1207 printk(KERN_WARNING "%s: term off: PLX_GPIO=%x\n",
1210 spin_unlock_irqrestore(&HFClock, hfc_flags);
1211 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1214 /* we only want the real Z2 read-pointer for revision > 0 */
1215 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1216 hc->hw.r_ram_sz |= V_FZ_MD;
1218 /* select pcm mode */
1219 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1220 if (debug & DEBUG_HFCMULTI_INIT)
1221 printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1224 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1225 if (debug & DEBUG_HFCMULTI_INIT)
1226 printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1228 hc->hw.r_pcm_md0 |= V_PCM_MD;
1230 if (debug & DEBUG_HFCMULTI_INIT)
1231 printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1236 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1237 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1238 HFC_outb(hc, R_FIFO_MD, 0);
1239 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR;
1240 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1243 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1245 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1247 /* Speech Design PLX bridge pcm and sync mode */
1248 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1249 spin_lock_irqsave(&plx_lock, plx_flags);
1250 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1251 pv = readl(plx_acc_32);
1253 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1254 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1255 pv |= PLX_SYNC_O_EN;
1256 if (debug & DEBUG_HFCMULTI_INIT)
1257 printk(KERN_WARNING "%s: master: PLX_GPIO=%x\n",
1260 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1261 pv &= ~PLX_SYNC_O_EN;
1262 if (debug & DEBUG_HFCMULTI_INIT)
1263 printk(KERN_WARNING "%s: slave: PLX_GPIO=%x\n",
1266 writel(pv, plx_acc_32);
1267 spin_unlock_irqrestore(&plx_lock, plx_flags);
1271 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1272 if (hc->slots == 32)
1273 HFC_outb(hc, R_PCM_MD1, 0x00);
1274 if (hc->slots == 64)
1275 HFC_outb(hc, R_PCM_MD1, 0x10);
1276 if (hc->slots == 128)
1277 HFC_outb(hc, R_PCM_MD1, 0x20);
1278 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1279 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1280 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1282 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1283 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1284 for (i = 0; i < 256; i++) {
1285 HFC_outb_nodebug(hc, R_SLOT, i);
1286 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1287 HFC_outb_nodebug(hc, A_CONF, 0);
1288 hc->slot_owner[i] = -1;
1291 /* set clock speed */
1292 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1293 if (debug & DEBUG_HFCMULTI_INIT)
1295 "%s: setting double clock\n", __func__);
1296 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1300 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1301 printk(KERN_NOTICE "Setting GPIOs\n");
1302 HFC_outb(hc, R_GPIO_SEL, 0x30);
1303 HFC_outb(hc, R_GPIO_EN1, 0x3);
1305 printk(KERN_NOTICE "calling vpm_init\n");
1309 /* check if R_F0_CNT counts (8 kHz frame count) */
1310 val = HFC_inb(hc, R_F0_CNTL);
1311 val += HFC_inb(hc, R_F0_CNTH) << 8;
1312 if (debug & DEBUG_HFCMULTI_INIT)
1314 "HFC_multi F0_CNT %ld after reset\n", val);
1315 spin_unlock_irqrestore(&hc->lock, flags);
1316 set_current_state(TASK_UNINTERRUPTIBLE);
1317 schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */
1318 spin_lock_irqsave(&hc->lock, flags);
1319 val2 = HFC_inb(hc, R_F0_CNTL);
1320 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1321 if (debug & DEBUG_HFCMULTI_INIT)
1323 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1325 if (val2 >= val+8) { /* 1 ms */
1326 /* it counts, so we keep the pcm mode */
1327 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1328 printk(KERN_INFO "controller is PCM bus MASTER\n");
1330 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1331 printk(KERN_INFO "controller is PCM bus SLAVE\n");
1333 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1334 printk(KERN_INFO "controller is PCM bus SLAVE "
1335 "(auto detected)\n");
1338 /* does not count */
1339 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1341 printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1342 "pulse. Seems that controller fails.\n");
1346 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1347 printk(KERN_INFO "controller is PCM bus SLAVE "
1348 "(ignoring missing PCM clock)\n");
1350 /* only one pcm master */
1351 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1353 printk(KERN_ERR "HFC_multi ERROR, no clock "
1354 "on another Speech Design card found. "
1355 "Please be sure to connect PCM cable.\n");
1359 /* retry with master clock */
1360 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1361 spin_lock_irqsave(&plx_lock, plx_flags);
1362 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1363 pv = readl(plx_acc_32);
1364 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1365 pv |= PLX_SYNC_O_EN;
1366 writel(pv, plx_acc_32);
1367 spin_unlock_irqrestore(&plx_lock, plx_flags);
1368 if (debug & DEBUG_HFCMULTI_INIT)
1369 printk(KERN_WARNING "%s: master: PLX_GPIO"
1370 "=%x\n", __func__, pv);
1372 hc->hw.r_pcm_md0 |= V_PCM_MD;
1373 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1374 spin_unlock_irqrestore(&hc->lock, flags);
1375 set_current_state(TASK_UNINTERRUPTIBLE);
1376 schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */
1377 spin_lock_irqsave(&hc->lock, flags);
1378 val2 = HFC_inb(hc, R_F0_CNTL);
1379 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1380 if (debug & DEBUG_HFCMULTI_INIT)
1381 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1382 "10 ms (2nd try)\n", val2);
1383 if (val2 >= val+8) { /* 1 ms */
1384 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1386 printk(KERN_INFO "controller is PCM bus MASTER "
1387 "(auto detected)\n");
1389 goto controller_fail;
1393 /* Release the DSP Reset */
1394 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1395 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1397 spin_lock_irqsave(&plx_lock, plx_flags);
1398 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1399 pv = readl(plx_acc_32);
1400 pv |= PLX_DSP_RES_N;
1401 writel(pv, plx_acc_32);
1402 spin_unlock_irqrestore(&plx_lock, plx_flags);
1403 if (debug & DEBUG_HFCMULTI_INIT)
1404 printk(KERN_WARNING "%s: reset off: PLX_GPIO=%x\n",
1410 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1413 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1414 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1415 PCM_cnt++; /* SD has proprietary bridging */
1418 printk(KERN_INFO "controller has PCM BUS ID %d "
1419 "(auto selected)\n", hc->pcm);
1423 HFC_outb(hc, R_TI_WD, poll_timer);
1424 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1426 /* set E1 state machine IRQ */
1428 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1430 /* set DTMF detection */
1431 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1432 if (debug & DEBUG_HFCMULTI_INIT)
1433 printk(KERN_DEBUG "%s: enabling DTMF detection "
1434 "for all B-channel\n", __func__);
1435 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1436 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1437 hc->hw.r_dtmf |= V_ULAW_SEL;
1438 HFC_outb(hc, R_DTMF_N, 102 - 1);
1439 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1442 /* conference engine */
1443 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1444 r_conf_en = V_CONF_EN | V_ULAW;
1446 r_conf_en = V_CONF_EN;
1447 HFC_outb(hc, R_CONF_EN, r_conf_en);
1451 case 1: /* HFC-E1 OEM */
1452 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1453 HFC_outb(hc, R_GPIO_SEL, 0x32);
1455 HFC_outb(hc, R_GPIO_SEL, 0x30);
1457 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1458 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1460 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1463 case 2: /* HFC-4S OEM */
1465 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1466 HFC_outb(hc, R_GPIO_EN1, 0xff);
1467 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1471 /* set master clock */
1472 if (hc->masterclk >= 0) {
1473 if (debug & DEBUG_HFCMULTI_INIT)
1474 printk(KERN_DEBUG "%s: setting ST master clock "
1475 "to port %d (0..%d)\n",
1476 __func__, hc->masterclk, hc->ports-1);
1477 hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC;
1478 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1481 /* setting misc irq */
1482 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1483 if (debug & DEBUG_HFCMULTI_INIT)
1484 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1485 hc->hw.r_irqmsk_misc);
1487 /* RAM access test */
1488 HFC_outb(hc, R_RAM_ADDR0, 0);
1489 HFC_outb(hc, R_RAM_ADDR1, 0);
1490 HFC_outb(hc, R_RAM_ADDR2, 0);
1491 for (i = 0; i < 256; i++) {
1492 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1493 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff));
1495 for (i = 0; i < 256; i++) {
1496 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1497 HFC_inb_nodebug(hc, R_RAM_DATA);
1498 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1499 if (rval != ((i * 3) & 0xff)) {
1501 "addr:%x val:%x should:%x\n", i, rval,
1507 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1512 if (debug & DEBUG_HFCMULTI_INIT)
1513 printk(KERN_DEBUG "%s: done\n", __func__);
1515 spin_unlock_irqrestore(&hc->lock, flags);
1521 * control the watchdog
1524 hfcmulti_watchdog(struct hfc_multi *hc)
1528 if (hc->wdcount > 10) {
1530 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1531 V_GPIO_OUT3 : V_GPIO_OUT2;
1533 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1534 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1535 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1545 hfcmulti_leds(struct hfc_multi *hc)
1548 unsigned long leddw;
1549 int i, state, active, leds;
1550 struct dchannel *dch;
1553 hc->ledcount += poll;
1554 if (hc->ledcount > 4096) {
1555 hc->ledcount -= 4096;
1556 hc->ledstate = 0xAFFEAFFE;
1560 case 1: /* HFC-E1 OEM */
1561 /* 2 red blinking: NT mode deactivate
1562 * 2 red steady: TE mode deactivate
1563 * left green: L1 active
1564 * left red: frame sync, but no L1
1565 * right green: L2 active
1567 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
1568 if (hc->chan[hc->dslot].dch->dev.D.protocol
1572 } else if (hc->ledcount>>11) {
1581 } else { /* with frame sync */
1582 /* TODO make it work */
1588 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1589 /* leds are inverted */
1590 if (leds != (int)hc->ledstate) {
1591 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1592 hc->ledstate = leds;
1596 case 2: /* HFC-4S OEM */
1597 /* red blinking = PH_DEACTIVATE NT Mode
1598 * red steady = PH_DEACTIVATE TE Mode
1599 * green steady = PH_ACTIVATE
1601 for (i = 0; i < 4; i++) {
1604 dch = hc->chan[(i << 2) | 2].dch;
1607 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1613 if (state == active) {
1614 led[i] = 1; /* led green */
1616 if (dch->dev.D.protocol == ISDN_P_TE_S0)
1617 /* TE mode: led red */
1620 if (hc->ledcount>>11)
1627 led[i] = 0; /* led off */
1629 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1631 for (i = 0; i < 4; i++) {
1634 leds |= (0x2 << (i * 2));
1635 } else if (led[i] == 2) {
1637 leds |= (0x1 << (i * 2));
1640 if (leds != (int)hc->ledstate) {
1641 vpm_out(hc, 0, 0x1a8 + 3, leds);
1642 hc->ledstate = leds;
1645 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1646 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1647 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1648 ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1649 if (leds != (int)hc->ledstate) {
1650 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1651 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1652 hc->ledstate = leds;
1657 case 3: /* HFC 1S/2S Beronet */
1658 /* red blinking = PH_DEACTIVATE NT Mode
1659 * red steady = PH_DEACTIVATE TE Mode
1660 * green steady = PH_ACTIVATE
1662 for (i = 0; i < 2; i++) {
1665 dch = hc->chan[(i << 2) | 2].dch;
1668 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1674 if (state == active) {
1675 led[i] = 1; /* led green */
1677 if (dch->dev.D.protocol == ISDN_P_TE_S0)
1678 /* TE mode: led red */
1681 if (hc->ledcount >> 11)
1688 led[i] = 0; /* led off */
1692 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2)
1694 if (leds != (int)hc->ledstate) {
1695 HFC_outb_nodebug(hc, R_GPIO_EN1,
1696 ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1697 HFC_outb_nodebug(hc, R_GPIO_OUT1,
1698 ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1699 hc->ledstate = leds;
1702 case 8: /* HFC 8S+ Beronet */
1705 for (i = 0; i < 8; i++) {
1708 dch = hc->chan[(i << 2) | 2].dch;
1711 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1717 if (state == active) {
1720 if (hc->ledcount >> 11)
1727 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1728 if (leddw != hc->ledstate) {
1729 /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1730 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1731 /* was _io before */
1732 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1733 outw(0x4000, hc->pci_iobase + 4);
1734 outl(leddw, hc->pci_iobase);
1735 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1736 hc->ledstate = leddw;
1742 * read dtmf coefficients
1746 hfcmulti_dtmf(struct hfc_multi *hc)
1751 struct bchannel *bch = NULL;
1756 struct sk_buff *skb;
1757 struct mISDNhead *hh;
1759 if (debug & DEBUG_HFCMULTI_DTMF)
1760 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1761 for (ch = 0; ch <= 31; ch++) {
1762 /* only process enabled B-channels */
1763 bch = hc->chan[ch].bch;
1766 if (!hc->created[hc->chan[ch].port])
1768 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1770 if (debug & DEBUG_HFCMULTI_DTMF)
1771 printk(KERN_DEBUG "%s: dtmf channel %d:",
1773 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1775 for (co = 0; co < 8; co++) {
1776 /* read W(n-1) coefficient */
1777 addr = hc->DTMFbase + ((co<<7) | (ch<<2));
1778 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1779 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8);
1780 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16)
1782 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1783 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1784 if (debug & DEBUG_HFCMULTI_DTMF)
1785 printk(" %04x", w_float);
1787 /* decode float (see chip doc) */
1788 mantissa = w_float & 0x0fff;
1789 if (w_float & 0x8000)
1790 mantissa |= 0xfffff000;
1791 exponent = (w_float>>12) & 0x7;
1794 mantissa <<= (exponent-1);
1797 /* store coefficient */
1798 coeff[co<<1] = mantissa;
1800 /* read W(n) coefficient */
1801 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1802 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1803 if (debug & DEBUG_HFCMULTI_DTMF)
1804 printk(" %04x", w_float);
1806 /* decode float (see chip doc) */
1807 mantissa = w_float & 0x0fff;
1808 if (w_float & 0x8000)
1809 mantissa |= 0xfffff000;
1810 exponent = (w_float>>12) & 0x7;
1813 mantissa <<= (exponent-1);
1816 /* store coefficient */
1817 coeff[(co<<1)|1] = mantissa;
1819 if (debug & DEBUG_HFCMULTI_DTMF)
1820 printk("%s: DTMF ready %08x %08x %08x %08x "
1821 "%08x %08x %08x %08x\n", __func__,
1822 coeff[0], coeff[1], coeff[2], coeff[3],
1823 coeff[4], coeff[5], coeff[6], coeff[7]);
1824 hc->chan[ch].coeff_count++;
1825 if (hc->chan[ch].coeff_count == 8) {
1826 hc->chan[ch].coeff_count = 0;
1827 skb = mI_alloc_skb(512, GFP_ATOMIC);
1829 printk(KERN_WARNING "%s: No memory for skb\n",
1833 hh = mISDN_HEAD_P(skb);
1834 hh->prim = PH_CONTROL_IND;
1835 hh->id = DTMF_HFC_COEF;
1836 memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1837 recv_Bchannel_skb(bch, skb);
1841 /* restart DTMF processing */
1844 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1849 * fill fifo as much as possible
1853 hfcmulti_tx(struct hfc_multi *hc, int ch)
1855 int i, ii, temp, len = 0;
1856 int Zspace, z1, z2; /* must be int for calculation */
1859 int *txpending, slot_tx;
1860 struct bchannel *bch;
1861 struct dchannel *dch;
1862 struct sk_buff **sp = NULL;
1865 bch = hc->chan[ch].bch;
1866 dch = hc->chan[ch].dch;
1867 if ((!dch) && (!bch))
1870 txpending = &hc->chan[ch].txpending;
1871 slot_tx = hc->chan[ch].slot_tx;
1873 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1876 idxp = &dch->tx_idx;
1878 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1881 idxp = &bch->tx_idx;
1886 if ((!len) && *txpending != 1)
1887 return; /* no data */
1889 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1890 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1891 (hc->chan[ch].slot_rx < 0) &&
1892 (hc->chan[ch].slot_tx < 0))
1893 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1895 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1896 HFC_wait_nodebug(hc);
1898 if (*txpending == 2) {
1900 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1901 HFC_wait_nodebug(hc);
1902 HFC_outb(hc, A_SUBCH_CFG, 0);
1906 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1907 f1 = HFC_inb_nodebug(hc, A_F1);
1908 f2 = HFC_inb_nodebug(hc, A_F2);
1909 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1910 if (debug & DEBUG_HFCMULTI_FIFO)
1912 "%s(card %d): reread f2 because %d!=%d\n",
1913 __func__, hc->id + 1, temp, f2);
1914 f2 = temp; /* repeat until F2 is equal */
1916 Fspace = f2 - f1 - 1;
1920 * Old FIFO handling doesn't give us the current Z2 read
1921 * pointer, so we cannot send the next frame before the fifo
1922 * is empty. It makes no difference except for a slightly
1923 * lower performance.
1925 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1931 /* one frame only for ST D-channels, to allow resending */
1932 if (hc->type != 1 && dch) {
1936 /* F-counter full condition */
1940 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1941 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1942 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1943 if (debug & DEBUG_HFCMULTI_FIFO)
1944 printk(KERN_DEBUG "%s(card %d): reread z2 because "
1945 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
1946 z2 = temp; /* repeat unti Z2 is equal */
1951 Zspace -= 4; /* keep not too full, so pointers will not overrun */
1952 /* fill transparent data only to maxinum transparent load (minus 4) */
1953 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
1954 Zspace = Zspace - hc->Zlen + hc->max_trans;
1955 if (Zspace <= 0) /* no space of 4 bytes */
1960 if (z1 == z2) { /* empty */
1961 /* if done with FIFO audio data during PCM connection */
1962 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
1963 *txpending && slot_tx >= 0) {
1964 if (debug & DEBUG_HFCMULTI_MODE)
1966 "%s: reconnecting PCM due to no "
1967 "more FIFO data: channel %d "
1969 __func__, ch, slot_tx);
1971 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1972 V_HDLC_TRP | V_IFF);
1973 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
1974 HFC_wait_nodebug(hc);
1975 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1976 V_HDLC_TRP | V_IFF);
1977 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
1978 HFC_wait_nodebug(hc);
1982 return; /* no data */
1985 /* "fill fifo if empty" feature */
1986 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
1987 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
1988 if (debug & DEBUG_HFCMULTI_FILL)
1989 printk(KERN_DEBUG "%s: buffer empty, so we have "
1990 "underrun\n", __func__);
1991 /* fill buffer, to prevent future underrun */
1992 hc->write_fifo(hc, hc->silence_data, poll >> 1);
1993 Zspace -= (poll >> 1);
1996 /* if audio data and connected slot */
1997 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
1999 if (debug & DEBUG_HFCMULTI_MODE)
2000 printk(KERN_DEBUG "%s: disconnecting PCM due to "
2001 "FIFO data: channel %d slot_tx %d\n",
2002 __func__, ch, slot_tx);
2003 /* disconnect slot */
2004 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2005 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
2006 HFC_wait_nodebug(hc);
2007 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2008 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2009 HFC_wait_nodebug(hc);
2014 hc->activity[hc->chan[ch].port] = 1;
2016 /* fill fifo to what we have left */
2018 if (dch || test_bit(FLG_HDLC, &bch->Flags))
2023 d = (*sp)->data + i;
2024 if (ii - i > Zspace)
2026 if (debug & DEBUG_HFCMULTI_FIFO)
2027 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2028 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2029 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2030 temp ? "HDLC":"TRANS");
2032 /* Have to prep the audio data */
2033 hc->write_fifo(hc, d, ii - i);
2036 /* if not all data has been written */
2038 /* NOTE: fifo is started by the calling function */
2042 /* if all data has been written, terminate frame */
2043 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2044 /* increment f-counter */
2045 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2046 HFC_wait_nodebug(hc);
2049 /* send confirm, since get_net_bframe will not do it with trans */
2050 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2053 /* check for next frame */
2055 if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2059 if (dch && get_next_dframe(dch)) {
2065 * now we have no more data, so in case of transparent,
2066 * we set the last byte in fifo to 'silence' in case we will get
2067 * no more data at all. this prevents sending an undefined value.
2069 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2070 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2074 /* NOTE: only called if E1 card is in active state */
2076 hfcmulti_rx(struct hfc_multi *hc, int ch)
2079 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2080 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2082 struct bchannel *bch;
2083 struct dchannel *dch;
2084 struct sk_buff *skb, **sp = NULL;
2087 bch = hc->chan[ch].bch;
2088 dch = hc->chan[ch].dch;
2089 if ((!dch) && (!bch))
2092 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2095 maxlen = dch->maxlen;
2097 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2100 maxlen = bch->maxlen;
2103 /* on first AND before getting next valid frame, R_FIFO must be written
2105 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2106 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2107 (hc->chan[ch].slot_rx < 0) &&
2108 (hc->chan[ch].slot_tx < 0))
2109 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1);
2111 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1);
2112 HFC_wait_nodebug(hc);
2114 /* ignore if rx is off BUT change fifo (above) to start pending TX */
2115 if (hc->chan[ch].rx_off)
2118 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2119 f1 = HFC_inb_nodebug(hc, A_F1);
2120 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2121 if (debug & DEBUG_HFCMULTI_FIFO)
2123 "%s(card %d): reread f1 because %d!=%d\n",
2124 __func__, hc->id + 1, temp, f1);
2125 f1 = temp; /* repeat until F1 is equal */
2127 f2 = HFC_inb_nodebug(hc, A_F2);
2129 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2130 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2131 if (debug & DEBUG_HFCMULTI_FIFO)
2132 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2133 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2134 z1 = temp; /* repeat until Z1 is equal */
2136 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2138 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2139 /* complete hdlc frame */
2143 /* if buffer is empty */
2148 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2150 printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2156 hc->activity[hc->chan[ch].port] = 1;
2158 /* empty fifo with what we have */
2159 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2160 if (debug & DEBUG_HFCMULTI_FIFO)
2161 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2162 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2163 "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2164 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2165 f1, f2, Zsize + (*sp)->len, again);
2167 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2168 if (debug & DEBUG_HFCMULTI_FIFO)
2170 "%s(card %d): hdlc-frame too large.\n",
2171 __func__, hc->id + 1);
2173 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2174 HFC_wait_nodebug(hc);
2178 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2181 /* increment Z2,F2-counter */
2182 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2183 HFC_wait_nodebug(hc);
2185 if ((*sp)->len < 4) {
2186 if (debug & DEBUG_HFCMULTI_FIFO)
2188 "%s(card %d): Frame below minimum "
2189 "size\n", __func__, hc->id + 1);
2193 /* there is at least one complete frame, check crc */
2194 if ((*sp)->data[(*sp)->len - 1]) {
2195 if (debug & DEBUG_HFCMULTI_CRC)
2197 "%s: CRC-error\n", __func__);
2201 skb_trim(*sp, (*sp)->len - 3);
2202 if ((*sp)->len < MISDN_COPY_SIZE) {
2204 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2206 memcpy(skb_put(*sp, skb->len),
2207 skb->data, skb->len);
2210 printk(KERN_DEBUG "%s: No mem\n",
2218 if (debug & DEBUG_HFCMULTI_FIFO) {
2219 printk(KERN_DEBUG "%s(card %d):",
2220 __func__, hc->id + 1);
2222 while (temp < (*sp)->len)
2223 printk(" %02x", (*sp)->data[temp++]);
2234 /* there is an incomplete frame */
2237 if (Zsize > skb_tailroom(*sp))
2238 Zsize = skb_tailroom(*sp);
2239 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2240 if (((*sp)->len) < MISDN_COPY_SIZE) {
2242 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2244 memcpy(skb_put(*sp, skb->len),
2245 skb->data, skb->len);
2248 printk(KERN_DEBUG "%s: No mem\n", __func__);
2255 if (debug & DEBUG_HFCMULTI_FIFO)
2257 "%s(card %d): fifo(%d) reading %d bytes "
2258 "(z1=%04x, z2=%04x) TRANS\n",
2259 __func__, hc->id + 1, ch, Zsize, z1, z2);
2260 /* only bch is transparent */
2271 signal_state_up(struct dchannel *dch, int info, char *msg)
2273 struct sk_buff *skb;
2274 int id, data = info;
2276 if (debug & DEBUG_HFCMULTI_STATE)
2277 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2279 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2281 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2285 recv_Dchannel_skb(dch, skb);
2289 handle_timer_irq(struct hfc_multi *hc)
2292 struct dchannel *dch;
2295 /* process queued resync jobs */
2296 if (hc->e1_resync) {
2297 /* lock, so e1_resync gets not changed */
2298 spin_lock_irqsave(&HFClock, flags);
2299 if (hc->e1_resync & 1) {
2300 if (debug & DEBUG_HFCMULTI_PLXSD)
2301 printk(KERN_DEBUG "Enable SYNC_I\n");
2302 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2303 /* disable JATT, if RX_SYNC is set */
2304 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2305 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2307 if (hc->e1_resync & 2) {
2308 if (debug & DEBUG_HFCMULTI_PLXSD)
2309 printk(KERN_DEBUG "Enable jatt PLL\n");
2310 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2312 if (hc->e1_resync & 4) {
2313 if (debug & DEBUG_HFCMULTI_PLXSD)
2315 "Enable QUARTZ for HFC-E1\n");
2316 /* set jatt to quartz */
2317 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2319 /* switch to JATT, in case it is not already */
2320 HFC_outb(hc, R_SYNC_OUT, 0);
2323 spin_unlock_irqrestore(&HFClock, flags);
2326 if (hc->type != 1 || hc->e1_state == 1)
2327 for (ch = 0; ch <= 31; ch++) {
2328 if (hc->created[hc->chan[ch].port]) {
2329 hfcmulti_tx(hc, ch);
2330 /* fifo is started when switching to rx-fifo */
2331 hfcmulti_rx(hc, ch);
2332 if (hc->chan[ch].dch &&
2333 hc->chan[ch].nt_timer > -1) {
2334 dch = hc->chan[ch].dch;
2335 if (!(--hc->chan[ch].nt_timer)) {
2339 DEBUG_HFCMULTI_STATE)
2349 if (hc->type == 1 && hc->created[0]) {
2350 dch = hc->chan[hc->dslot].dch;
2351 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2353 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2354 if (!temp && hc->chan[hc->dslot].los)
2355 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2357 if (temp && !hc->chan[hc->dslot].los)
2358 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2360 hc->chan[hc->dslot].los = temp;
2362 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2364 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2365 if (!temp && hc->chan[hc->dslot].ais)
2366 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2368 if (temp && !hc->chan[hc->dslot].ais)
2369 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2371 hc->chan[hc->dslot].ais = temp;
2373 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2375 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2376 if (!temp && hc->chan[hc->dslot].slip_rx)
2377 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2378 " bit SLIP detected RX");
2379 hc->chan[hc->dslot].slip_rx = temp;
2380 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2381 if (!temp && hc->chan[hc->dslot].slip_tx)
2382 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2383 " bit SLIP detected TX");
2384 hc->chan[hc->dslot].slip_tx = temp;
2386 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2388 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2389 if (!temp && hc->chan[hc->dslot].rdi)
2390 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2392 if (temp && !hc->chan[hc->dslot].rdi)
2393 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2395 hc->chan[hc->dslot].rdi = temp;
2397 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2398 switch (hc->chan[hc->dslot].sync) {
2400 if ((temp & 0x60) == 0x60) {
2401 if (debug & DEBUG_HFCMULTI_SYNC)
2403 "%s: (id=%d) E1 now "
2406 HFC_outb(hc, R_RX_OFF,
2407 hc->chan[hc->dslot].jitter | V_RX_INIT);
2408 HFC_outb(hc, R_TX_OFF,
2409 hc->chan[hc->dslot].jitter | V_RX_INIT);
2410 hc->chan[hc->dslot].sync = 1;
2411 goto check_framesync;
2415 if ((temp & 0x60) != 0x60) {
2416 if (debug & DEBUG_HFCMULTI_SYNC)
2419 "lost clock sync\n",
2421 hc->chan[hc->dslot].sync = 0;
2425 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2427 if (debug & DEBUG_HFCMULTI_SYNC)
2430 "now in frame sync\n",
2432 hc->chan[hc->dslot].sync = 2;
2436 if ((temp & 0x60) != 0x60) {
2437 if (debug & DEBUG_HFCMULTI_SYNC)
2439 "%s: (id=%d) E1 lost "
2440 "clock & frame sync\n",
2442 hc->chan[hc->dslot].sync = 0;
2445 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2447 if (debug & DEBUG_HFCMULTI_SYNC)
2450 "lost frame sync\n",
2452 hc->chan[hc->dslot].sync = 1;
2458 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2459 hfcmulti_watchdog(hc);
2466 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2468 struct dchannel *dch;
2471 u_char st_status, temp;
2474 for (ch = 0; ch <= 31; ch++) {
2475 if (hc->chan[ch].dch) {
2476 dch = hc->chan[ch].dch;
2477 if (r_irq_statech & 1) {
2478 HFC_outb_nodebug(hc, R_ST_SEL,
2480 /* undocumented: delay after R_ST_SEL */
2482 /* undocumented: status changes during read */
2483 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2484 while (st_status != (temp =
2485 HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2486 if (debug & DEBUG_HFCMULTI_STATE)
2487 printk(KERN_DEBUG "%s: reread "
2488 "STATE because %d!=%d\n",
2491 st_status = temp; /* repeat */
2494 /* Speech Design TE-sync indication */
2495 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2496 dch->dev.D.protocol == ISDN_P_TE_S0) {
2497 if (st_status & V_FR_SYNC_ST)
2499 (1 << hc->chan[ch].port);
2502 ~(1 << hc->chan[ch].port);
2504 dch->state = st_status & 0x0f;
2505 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2509 if (dch->state == active) {
2510 HFC_outb_nodebug(hc, R_FIFO,
2512 HFC_wait_nodebug(hc);
2513 HFC_outb_nodebug(hc,
2514 R_INC_RES_FIFO, V_RES_F);
2515 HFC_wait_nodebug(hc);
2518 schedule_event(dch, FLG_PHCHANGE);
2519 if (debug & DEBUG_HFCMULTI_STATE)
2521 "%s: S/T newstate %x port %d\n",
2522 __func__, dch->state,
2525 r_irq_statech >>= 1;
2528 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2529 plxsd_checksync(hc, 0);
2533 fifo_irq(struct hfc_multi *hc, int block)
2536 struct dchannel *dch;
2537 struct bchannel *bch;
2538 u_char r_irq_fifo_bl;
2540 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2543 ch = (block << 2) + (j >> 1);
2544 dch = hc->chan[ch].dch;
2545 bch = hc->chan[ch].bch;
2546 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2550 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2551 test_bit(FLG_ACTIVE, &dch->Flags)) {
2552 hfcmulti_tx(hc, ch);
2554 HFC_outb_nodebug(hc, R_FIFO, 0);
2555 HFC_wait_nodebug(hc);
2557 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2558 test_bit(FLG_ACTIVE, &bch->Flags)) {
2559 hfcmulti_tx(hc, ch);
2561 HFC_outb_nodebug(hc, R_FIFO, 0);
2562 HFC_wait_nodebug(hc);
2565 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2566 test_bit(FLG_ACTIVE, &dch->Flags)) {
2567 hfcmulti_rx(hc, ch);
2569 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2570 test_bit(FLG_ACTIVE, &bch->Flags)) {
2571 hfcmulti_rx(hc, ch);
2581 hfcmulti_interrupt(int intno, void *dev_id)
2583 #ifdef IRQCOUNT_DEBUG
2584 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2585 iq5 = 0, iq6 = 0, iqcnt = 0;
2587 struct hfc_multi *hc = dev_id;
2588 struct dchannel *dch;
2589 u_char r_irq_statech, status, r_irq_misc, r_irq_oview;
2591 void __iomem *plx_acc;
2593 u_char e1_syncsta, temp;
2597 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2601 spin_lock(&hc->lock);
2605 printk(KERN_ERR "irq for card %d during irq from "
2606 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2607 irqsem = hc->id + 1;
2610 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2611 spin_lock_irqsave(&plx_lock, flags);
2612 plx_acc = hc->plx_membase + PLX_INTCSR;
2613 wval = readw(plx_acc);
2614 spin_unlock_irqrestore(&plx_lock, flags);
2615 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2619 status = HFC_inb_nodebug(hc, R_STATUS);
2620 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2621 #ifdef IRQCOUNT_DEBUG
2624 if (status & V_DTMF_STA)
2626 if (status & V_LOST_STA)
2628 if (status & V_EXT_IRQSTA)
2630 if (status & V_MISC_IRQSTA)
2632 if (status & V_FR_IRQSTA)
2634 if (iqcnt++ > 5000) {
2635 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2636 iq1, iq2, iq3, iq4, iq5, iq6);
2641 if (!r_irq_statech &&
2642 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2643 V_MISC_IRQSTA | V_FR_IRQSTA))) {
2644 /* irq is not for us */
2648 if (r_irq_statech) {
2650 ph_state_irq(hc, r_irq_statech);
2652 if (status & V_EXT_IRQSTA)
2653 ; /* external IRQ */
2654 if (status & V_LOST_STA) {
2656 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2658 if (status & V_MISC_IRQSTA) {
2660 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2661 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2662 if (r_irq_misc & V_STA_IRQ) {
2663 if (hc->type == 1) {
2665 dch = hc->chan[hc->dslot].dch;
2666 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2667 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2668 && hc->e1_getclock) {
2669 if (e1_syncsta & V_FR_SYNC_E1)
2670 hc->syncronized = 1;
2672 hc->syncronized = 0;
2674 /* undocumented: status changes during read */
2675 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2676 while (dch->state != (temp =
2677 HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2678 if (debug & DEBUG_HFCMULTI_STATE)
2679 printk(KERN_DEBUG "%s: reread "
2680 "STATE because %d!=%d\n",
2683 dch->state = temp; /* repeat */
2685 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2687 schedule_event(dch, FLG_PHCHANGE);
2688 if (debug & DEBUG_HFCMULTI_STATE)
2690 "%s: E1 (id=%d) newstate %x\n",
2691 __func__, hc->id, dch->state);
2692 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2693 plxsd_checksync(hc, 0);
2696 if (r_irq_misc & V_TI_IRQ) {
2698 mISDN_clock_update(hc->iclock, poll, NULL);
2699 handle_timer_irq(hc);
2702 if (r_irq_misc & V_DTMF_IRQ) {
2705 if (r_irq_misc & V_IRQ_PROC) {
2706 static int irq_proc_cnt;
2707 if (!irq_proc_cnt++)
2708 printk(KERN_WARNING "%s: got V_IRQ_PROC -"
2709 " this should not happen\n", __func__);
2713 if (status & V_FR_IRQSTA) {
2715 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2716 for (i = 0; i < 8; i++) {
2717 if (r_irq_oview & (1 << i))
2725 spin_unlock(&hc->lock);
2732 spin_unlock(&hc->lock);
2738 * timer callback for D-chan busy resolution. Currently no function
2742 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2748 * activate/deactivate hardware for selected channels and mode
2750 * configure B-channel with the given protocol
2751 * ch eqals to the HFC-channel (0-31)
2752 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2753 * for S/T, 1-31 for E1)
2754 * the hdlc interrupts will be set/unset
2757 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2758 int bank_tx, int slot_rx, int bank_rx)
2760 int flow_tx = 0, flow_rx = 0, routing = 0;
2761 int oslot_tx, oslot_rx;
2764 if (ch < 0 || ch > 31)
2766 oslot_tx = hc->chan[ch].slot_tx;
2767 oslot_rx = hc->chan[ch].slot_rx;
2768 conf = hc->chan[ch].conf;
2770 if (debug & DEBUG_HFCMULTI_MODE)
2772 "%s: card %d channel %d protocol %x slot old=%d new=%d "
2773 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2774 __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2775 bank_tx, oslot_rx, slot_rx, bank_rx);
2777 if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2778 /* remove from slot */
2779 if (debug & DEBUG_HFCMULTI_MODE)
2780 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2781 __func__, oslot_tx);
2782 if (hc->slot_owner[oslot_tx<<1] == ch) {
2783 HFC_outb(hc, R_SLOT, oslot_tx << 1);
2784 HFC_outb(hc, A_SL_CFG, 0);
2785 HFC_outb(hc, A_CONF, 0);
2786 hc->slot_owner[oslot_tx<<1] = -1;
2788 if (debug & DEBUG_HFCMULTI_MODE)
2790 "%s: we are not owner of this tx slot "
2791 "anymore, channel %d is.\n",
2792 __func__, hc->slot_owner[oslot_tx<<1]);
2796 if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2797 /* remove from slot */
2798 if (debug & DEBUG_HFCMULTI_MODE)
2800 "%s: remove from slot %d (RX)\n",
2801 __func__, oslot_rx);
2802 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2803 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2804 HFC_outb(hc, A_SL_CFG, 0);
2805 hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2807 if (debug & DEBUG_HFCMULTI_MODE)
2809 "%s: we are not owner of this rx slot "
2810 "anymore, channel %d is.\n",
2812 hc->slot_owner[(oslot_rx << 1) | 1]);
2817 flow_tx = 0x80; /* FIFO->ST */
2818 /* disable pcm slot */
2819 hc->chan[ch].slot_tx = -1;
2820 hc->chan[ch].bank_tx = 0;
2823 if (hc->chan[ch].txpending)
2824 flow_tx = 0x80; /* FIFO->ST */
2826 flow_tx = 0xc0; /* PCM->ST */
2828 routing = bank_tx ? 0xc0 : 0x80;
2829 if (conf >= 0 || bank_tx > 1)
2830 routing = 0x40; /* loop */
2831 if (debug & DEBUG_HFCMULTI_MODE)
2832 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2833 " %d flow %02x routing %02x conf %d (TX)\n",
2834 __func__, ch, slot_tx, bank_tx,
2835 flow_tx, routing, conf);
2836 HFC_outb(hc, R_SLOT, slot_tx << 1);
2837 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
2838 HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL));
2839 hc->slot_owner[slot_tx << 1] = ch;
2840 hc->chan[ch].slot_tx = slot_tx;
2841 hc->chan[ch].bank_tx = bank_tx;
2844 /* disable pcm slot */
2845 flow_rx = 0x80; /* ST->FIFO */
2846 hc->chan[ch].slot_rx = -1;
2847 hc->chan[ch].bank_rx = 0;
2850 if (hc->chan[ch].txpending)
2851 flow_rx = 0x80; /* ST->FIFO */
2853 flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2855 routing = bank_rx?0x80:0xc0; /* reversed */
2856 if (conf >= 0 || bank_rx > 1)
2857 routing = 0x40; /* loop */
2858 if (debug & DEBUG_HFCMULTI_MODE)
2859 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2860 " %d flow %02x routing %02x conf %d (RX)\n",
2861 __func__, ch, slot_rx, bank_rx,
2862 flow_rx, routing, conf);
2863 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR);
2864 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing);
2865 hc->slot_owner[(slot_rx<<1)|1] = ch;
2866 hc->chan[ch].slot_rx = slot_rx;
2867 hc->chan[ch].bank_rx = bank_rx;
2872 /* disable TX fifo */
2873 HFC_outb(hc, R_FIFO, ch << 1);
2875 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2876 HFC_outb(hc, A_SUBCH_CFG, 0);
2877 HFC_outb(hc, A_IRQ_MSK, 0);
2878 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2880 /* disable RX fifo */
2881 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2883 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2884 HFC_outb(hc, A_SUBCH_CFG, 0);
2885 HFC_outb(hc, A_IRQ_MSK, 0);
2886 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2888 if (hc->chan[ch].bch && hc->type != 1) {
2889 hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2890 ((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN;
2891 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2892 /* undocumented: delay after R_ST_SEL */
2894 HFC_outb(hc, A_ST_CTRL0,
2895 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2897 if (hc->chan[ch].bch) {
2898 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2899 test_and_clear_bit(FLG_TRANSPARENT,
2900 &hc->chan[ch].bch->Flags);
2903 case (ISDN_P_B_RAW): /* B-channel */
2905 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2906 (hc->chan[ch].slot_rx < 0) &&
2907 (hc->chan[ch].slot_tx < 0)) {
2910 "Setting B-channel %d to echo cancelable "
2911 "state on PCM slot %d\n", ch,
2912 ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
2914 "Enabling pass through for channel\n");
2915 vpm_out(hc, ch, ((ch / 4) * 8) +
2916 ((ch % 4) * 4) + 1, 0x01);
2919 HFC_outb(hc, R_FIFO, (ch << 1));
2921 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2922 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2923 ((ch % 4) * 4) + 1) << 1);
2924 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
2927 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2929 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2930 HFC_outb(hc, A_SUBCH_CFG, 0);
2931 HFC_outb(hc, A_IRQ_MSK, 0);
2932 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2934 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2935 ((ch % 4) * 4) + 1) << 1) | 1);
2936 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
2940 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2942 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2943 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2944 ((ch % 4) * 4)) << 1) | 1);
2945 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
2948 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
2950 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2951 HFC_outb(hc, A_SUBCH_CFG, 0);
2952 HFC_outb(hc, A_IRQ_MSK, 0);
2953 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2956 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2957 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2958 ((ch % 4) * 4)) << 1);
2959 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
2961 /* enable TX fifo */
2962 HFC_outb(hc, R_FIFO, ch << 1);
2964 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
2965 V_HDLC_TRP | V_IFF);
2966 HFC_outb(hc, A_SUBCH_CFG, 0);
2967 HFC_outb(hc, A_IRQ_MSK, 0);
2968 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2971 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2972 /* enable RX fifo */
2973 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2975 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP);
2976 HFC_outb(hc, A_SUBCH_CFG, 0);
2977 HFC_outb(hc, A_IRQ_MSK, 0);
2978 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2981 if (hc->type != 1) {
2982 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
2983 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
2984 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2985 /* undocumented: delay after R_ST_SEL */
2987 HFC_outb(hc, A_ST_CTRL0,
2988 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2990 if (hc->chan[ch].bch)
2991 test_and_set_bit(FLG_TRANSPARENT,
2992 &hc->chan[ch].bch->Flags);
2994 case (ISDN_P_B_HDLC): /* B-channel */
2995 case (ISDN_P_TE_S0): /* D-channel */
2996 case (ISDN_P_NT_S0):
2997 case (ISDN_P_TE_E1):
2998 case (ISDN_P_NT_E1):
2999 /* enable TX fifo */
3000 HFC_outb(hc, R_FIFO, ch<<1);
3002 if (hc->type == 1 || hc->chan[ch].bch) {
3003 /* E1 or B-channel */
3004 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3005 HFC_outb(hc, A_SUBCH_CFG, 0);
3007 /* D-Channel without HDLC fill flags */
3008 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3009 HFC_outb(hc, A_SUBCH_CFG, 2);
3011 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3012 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3014 /* enable RX fifo */
3015 HFC_outb(hc, R_FIFO, (ch<<1)|1);
3017 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3018 if (hc->type == 1 || hc->chan[ch].bch)
3019 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3021 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3022 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3023 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3025 if (hc->chan[ch].bch) {
3026 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3027 if (hc->type != 1) {
3028 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3029 ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
3030 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3031 /* undocumented: delay after R_ST_SEL */
3033 HFC_outb(hc, A_ST_CTRL0,
3034 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3039 printk(KERN_DEBUG "%s: protocol not known %x\n",
3040 __func__, protocol);
3041 hc->chan[ch].protocol = ISDN_P_NONE;
3042 return -ENOPROTOOPT;
3044 hc->chan[ch].protocol = protocol;
3050 * connect/disconnect PCM
3054 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3055 int slot_rx, int bank_rx)
3057 if (slot_rx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3059 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3064 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3069 * set/disable conference
3073 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3075 if (num >= 0 && num <= 7)
3076 hc->chan[ch].conf = num;
3078 hc->chan[ch].conf = -1;
3079 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3080 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3081 hc->chan[ch].bank_rx);
3086 * set/disable sample loop
3089 /* NOTE: this function is experimental and therefore disabled */
3092 * Layer 1 callback function
3095 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3097 struct hfc_multi *hc = dch->hw;
3105 /* start activation */
3106 spin_lock_irqsave(&hc->lock, flags);
3107 if (hc->type == 1) {
3108 if (debug & DEBUG_HFCMULTI_MSG)
3110 "%s: HW_RESET_REQ no BRI\n",
3113 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3114 /* undocumented: delay after R_ST_SEL */
3116 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3117 udelay(6); /* wait at least 5,21us */
3118 HFC_outb(hc, A_ST_WR_STATE, 3);
3119 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3));
3122 spin_unlock_irqrestore(&hc->lock, flags);
3123 l1_event(dch->l1, HW_POWERUP_IND);
3126 /* start deactivation */
3127 spin_lock_irqsave(&hc->lock, flags);
3128 if (hc->type == 1) {
3129 if (debug & DEBUG_HFCMULTI_MSG)
3131 "%s: HW_DEACT_REQ no BRI\n",
3134 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3135 /* undocumented: delay after R_ST_SEL */
3137 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2);
3139 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3141 ~(1 << hc->chan[dch->slot].port);
3142 plxsd_checksync(hc, 0);
3145 skb_queue_purge(&dch->squeue);
3147 dev_kfree_skb(dch->tx_skb);
3152 dev_kfree_skb(dch->rx_skb);
3155 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3156 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3157 del_timer(&dch->timer);
3158 spin_unlock_irqrestore(&hc->lock, flags);
3160 case HW_POWERUP_REQ:
3161 spin_lock_irqsave(&hc->lock, flags);
3162 if (hc->type == 1) {
3163 if (debug & DEBUG_HFCMULTI_MSG)
3165 "%s: HW_POWERUP_REQ no BRI\n",
3168 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3169 /* undocumented: delay after R_ST_SEL */
3171 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3172 udelay(6); /* wait at least 5,21us */
3173 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3175 spin_unlock_irqrestore(&hc->lock, flags);
3177 case PH_ACTIVATE_IND:
3178 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3179 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3182 case PH_DEACTIVATE_IND:
3183 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3184 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3188 if (dch->debug & DEBUG_HW)
3189 printk(KERN_DEBUG "%s: unknown command %x\n",
3197 * Layer2 -> Layer 1 Transfer
3201 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3203 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
3204 struct dchannel *dch = container_of(dev, struct dchannel, dev);
3205 struct hfc_multi *hc = dch->hw;
3206 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3215 spin_lock_irqsave(&hc->lock, flags);
3216 ret = dchannel_senddata(dch, skb);
3217 if (ret > 0) { /* direct TX */
3218 id = hh->id; /* skb can be freed */
3219 hfcmulti_tx(hc, dch->slot);
3222 HFC_outb(hc, R_FIFO, 0);
3224 spin_unlock_irqrestore(&hc->lock, flags);
3225 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3227 spin_unlock_irqrestore(&hc->lock, flags);
3229 case PH_ACTIVATE_REQ:
3230 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3231 spin_lock_irqsave(&hc->lock, flags);
3233 if (debug & DEBUG_HFCMULTI_MSG)
3235 "%s: PH_ACTIVATE port %d (0..%d)\n",
3236 __func__, hc->chan[dch->slot].port,
3238 /* start activation */
3239 if (hc->type == 1) {
3240 ph_state_change(dch);
3241 if (debug & DEBUG_HFCMULTI_STATE)
3243 "%s: E1 report state %x \n",
3244 __func__, dch->state);
3246 HFC_outb(hc, R_ST_SEL,
3247 hc->chan[dch->slot].port);
3248 /* undocumented: delay after R_ST_SEL */
3250 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3252 udelay(6); /* wait at least 5,21us */
3253 HFC_outb(hc, A_ST_WR_STATE, 1);
3254 HFC_outb(hc, A_ST_WR_STATE, 1 |
3255 (V_ST_ACT*3)); /* activate */
3258 spin_unlock_irqrestore(&hc->lock, flags);
3260 ret = l1_event(dch->l1, hh->prim);
3262 case PH_DEACTIVATE_REQ:
3263 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3264 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3265 spin_lock_irqsave(&hc->lock, flags);
3266 if (debug & DEBUG_HFCMULTI_MSG)
3268 "%s: PH_DEACTIVATE port %d (0..%d)\n",
3269 __func__, hc->chan[dch->slot].port,
3271 /* start deactivation */
3272 if (hc->type == 1) {
3273 if (debug & DEBUG_HFCMULTI_MSG)
3275 "%s: PH_DEACTIVATE no BRI\n",
3278 HFC_outb(hc, R_ST_SEL,
3279 hc->chan[dch->slot].port);
3280 /* undocumented: delay after R_ST_SEL */
3282 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3286 skb_queue_purge(&dch->squeue);
3288 dev_kfree_skb(dch->tx_skb);
3293 dev_kfree_skb(dch->rx_skb);
3296 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3297 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3298 del_timer(&dch->timer);
3300 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3301 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3304 spin_unlock_irqrestore(&hc->lock, flags);
3306 ret = l1_event(dch->l1, hh->prim);
3315 deactivate_bchannel(struct bchannel *bch)
3317 struct hfc_multi *hc = bch->hw;
3320 spin_lock_irqsave(&hc->lock, flags);
3321 if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
3322 dev_kfree_skb(bch->next_skb);
3323 bch->next_skb = NULL;
3326 dev_kfree_skb(bch->tx_skb);
3331 dev_kfree_skb(bch->rx_skb);
3334 hc->chan[bch->slot].coeff_count = 0;
3335 test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
3336 test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
3337 hc->chan[bch->slot].rx_off = 0;
3338 hc->chan[bch->slot].conf = -1;
3339 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3340 spin_unlock_irqrestore(&hc->lock, flags);
3344 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3346 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3347 struct hfc_multi *hc = bch->hw;
3349 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3357 spin_lock_irqsave(&hc->lock, flags);
3358 ret = bchannel_senddata(bch, skb);
3359 if (ret > 0) { /* direct TX */
3360 id = hh->id; /* skb can be freed */
3361 hfcmulti_tx(hc, bch->slot);
3364 HFC_outb_nodebug(hc, R_FIFO, 0);
3365 HFC_wait_nodebug(hc);
3366 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3367 spin_unlock_irqrestore(&hc->lock, flags);
3368 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3370 spin_unlock_irqrestore(&hc->lock, flags);
3372 spin_unlock_irqrestore(&hc->lock, flags);
3374 case PH_ACTIVATE_REQ:
3375 if (debug & DEBUG_HFCMULTI_MSG)
3376 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3377 __func__, bch->slot);
3378 spin_lock_irqsave(&hc->lock, flags);
3379 /* activate B-channel if not already activated */
3380 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3381 hc->chan[bch->slot].txpending = 0;
3382 ret = mode_hfcmulti(hc, bch->slot,
3384 hc->chan[bch->slot].slot_tx,
3385 hc->chan[bch->slot].bank_tx,
3386 hc->chan[bch->slot].slot_rx,
3387 hc->chan[bch->slot].bank_rx);
3389 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3390 && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3393 if (debug & DEBUG_HFCMULTI_DTMF)
3395 "%s: start dtmf decoder\n",
3397 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3403 spin_unlock_irqrestore(&hc->lock, flags);
3405 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3408 case PH_CONTROL_REQ:
3409 spin_lock_irqsave(&hc->lock, flags);
3411 case HFC_SPL_LOOP_ON: /* set sample loop */
3412 if (debug & DEBUG_HFCMULTI_MSG)
3414 "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3415 __func__, skb->len);
3418 case HFC_SPL_LOOP_OFF: /* set silence */
3419 if (debug & DEBUG_HFCMULTI_MSG)
3420 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3426 "%s: unknown PH_CONTROL_REQ info %x\n",
3430 spin_unlock_irqrestore(&hc->lock, flags);
3432 case PH_DEACTIVATE_REQ:
3433 deactivate_bchannel(bch); /* locked there */
3434 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3445 * bchannel control function
3448 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3451 struct dsp_features *features =
3452 (struct dsp_features *)(*((u_long *)&cq->p1));
3453 struct hfc_multi *hc = bch->hw;
3461 case MISDN_CTRL_GETOP:
3462 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
3463 | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY;
3465 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3466 hc->chan[bch->slot].rx_off = !!cq->p1;
3467 if (!hc->chan[bch->slot].rx_off) {
3468 /* reset fifo on rx on */
3469 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3470 HFC_wait_nodebug(hc);
3471 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3472 HFC_wait_nodebug(hc);
3474 if (debug & DEBUG_HFCMULTI_MSG)
3475 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3476 __func__, bch->nr, hc->chan[bch->slot].rx_off);
3478 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
3479 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
3480 if (debug & DEBUG_HFCMULTI_MSG)
3481 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
3482 "off=%d)\n", __func__, bch->nr, !!cq->p1);
3484 case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3485 if (debug & DEBUG_HFCMULTI_MSG)
3486 printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3488 /* create confirm */
3489 features->hfc_id = hc->id;
3490 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3491 features->hfc_dtmf = 1;
3492 features->hfc_loops = 0;
3493 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3494 features->hfc_echocanhw = 1;
3496 features->pcm_id = hc->pcm;
3497 features->pcm_slots = hc->slots;
3498 features->pcm_banks = 2;
3501 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3502 slot_tx = cq->p1 & 0xff;
3503 bank_tx = cq->p1 >> 8;
3504 slot_rx = cq->p2 & 0xff;
3505 bank_rx = cq->p2 >> 8;
3506 if (debug & DEBUG_HFCMULTI_MSG)
3508 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3509 "slot %d bank %d (RX)\n",
3510 __func__, slot_tx, bank_tx,
3512 if (slot_tx < hc->slots && bank_tx <= 2 &&
3513 slot_rx < hc->slots && bank_rx <= 2)
3514 hfcmulti_pcm(hc, bch->slot,
3515 slot_tx, bank_tx, slot_rx, bank_rx);
3518 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3519 "slot %d bank %d (RX) out of range\n",
3520 __func__, slot_tx, bank_tx,
3525 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3526 if (debug & DEBUG_HFCMULTI_MSG)
3527 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3529 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3531 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3532 num = cq->p1 & 0xff;
3533 if (debug & DEBUG_HFCMULTI_MSG)
3534 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3537 hfcmulti_conf(hc, bch->slot, num);
3540 "%s: HW_CONF_JOIN conf %d out of range\n",
3545 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3546 if (debug & DEBUG_HFCMULTI_MSG)
3547 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3548 hfcmulti_conf(hc, bch->slot, -1);
3550 case MISDN_CTRL_HFC_ECHOCAN_ON:
3551 if (debug & DEBUG_HFCMULTI_MSG)
3552 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3553 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3554 vpm_echocan_on(hc, bch->slot, cq->p1);
3559 case MISDN_CTRL_HFC_ECHOCAN_OFF:
3560 if (debug & DEBUG_HFCMULTI_MSG)
3561 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3563 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3564 vpm_echocan_off(hc, bch->slot);
3569 printk(KERN_WARNING "%s: unknown Op %x\n",
3578 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3580 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3581 struct hfc_multi *hc = bch->hw;
3585 if (bch->debug & DEBUG_HW)
3586 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3587 __func__, cmd, arg);
3590 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3591 if (test_bit(FLG_ACTIVE, &bch->Flags))
3592 deactivate_bchannel(bch); /* locked there */
3593 ch->protocol = ISDN_P_NONE;
3595 module_put(THIS_MODULE);
3598 case CONTROL_CHANNEL:
3599 spin_lock_irqsave(&hc->lock, flags);
3600 err = channel_bctrl(bch, arg);
3601 spin_unlock_irqrestore(&hc->lock, flags);
3604 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3611 * handle D-channel events
3613 * handle state change event
3616 ph_state_change(struct dchannel *dch)
3618 struct hfc_multi *hc = dch->hw;
3622 printk(KERN_WARNING "%s: ERROR given dch is NULL\n",
3628 if (hc->type == 1) {
3629 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3630 if (debug & DEBUG_HFCMULTI_STATE)
3632 "%s: E1 TE (id=%d) newstate %x\n",
3633 __func__, hc->id, dch->state);
3635 if (debug & DEBUG_HFCMULTI_STATE)
3637 "%s: E1 NT (id=%d) newstate %x\n",
3638 __func__, hc->id, dch->state);
3640 switch (dch->state) {
3642 if (hc->e1_state != 1) {
3643 for (i = 1; i <= 31; i++) {
3644 /* reset fifos on e1 activation */
3645 HFC_outb_nodebug(hc, R_FIFO, (i << 1) | 1);
3646 HFC_wait_nodebug(hc);
3647 HFC_outb_nodebug(hc,
3648 R_INC_RES_FIFO, V_RES_F);
3649 HFC_wait_nodebug(hc);
3652 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3653 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3654 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3658 if (hc->e1_state != 1)
3660 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3661 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3662 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3664 hc->e1_state = dch->state;
3666 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3667 if (debug & DEBUG_HFCMULTI_STATE)
3669 "%s: S/T TE newstate %x\n",
3670 __func__, dch->state);
3671 switch (dch->state) {
3673 l1_event(dch->l1, HW_RESET_IND);
3676 l1_event(dch->l1, HW_DEACT_IND);
3680 l1_event(dch->l1, ANYSIGNAL);
3683 l1_event(dch->l1, INFO2);
3686 l1_event(dch->l1, INFO4_P8);
3690 if (debug & DEBUG_HFCMULTI_STATE)
3691 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3692 __func__, dch->state);
3693 switch (dch->state) {
3695 if (hc->chan[ch].nt_timer == 0) {
3696 hc->chan[ch].nt_timer = -1;
3697 HFC_outb(hc, R_ST_SEL,
3699 /* undocumented: delay after R_ST_SEL */
3701 HFC_outb(hc, A_ST_WR_STATE, 4 |
3702 V_ST_LD_STA); /* G4 */
3703 udelay(6); /* wait at least 5,21us */
3704 HFC_outb(hc, A_ST_WR_STATE, 4);
3707 /* one extra count for the next event */
3708 hc->chan[ch].nt_timer =
3709 nt_t1_count[poll_timer] + 1;
3710 HFC_outb(hc, R_ST_SEL,
3712 /* undocumented: delay after R_ST_SEL */
3714 /* allow G2 -> G3 transition */
3715 HFC_outb(hc, A_ST_WR_STATE, 2 |
3720 hc->chan[ch].nt_timer = -1;
3721 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3722 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3723 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3726 hc->chan[ch].nt_timer = -1;
3729 hc->chan[ch].nt_timer = -1;
3730 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3731 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3732 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3740 * called for card mode init message
3744 hfcmulti_initmode(struct dchannel *dch)
3746 struct hfc_multi *hc = dch->hw;
3747 u_char a_st_wr_state, r_e1_wr_sta;
3750 if (debug & DEBUG_HFCMULTI_INIT)
3751 printk(KERN_DEBUG "%s: entered\n", __func__);
3753 if (hc->type == 1) {
3754 hc->chan[hc->dslot].slot_tx = -1;
3755 hc->chan[hc->dslot].slot_rx = -1;
3756 hc->chan[hc->dslot].conf = -1;
3758 mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3760 dch->timer.function = (void *) hfcmulti_dbusy_timer;
3761 dch->timer.data = (long) dch;
3762 init_timer(&dch->timer);
3764 for (i = 1; i <= 31; i++) {
3767 hc->chan[i].slot_tx = -1;
3768 hc->chan[i].slot_rx = -1;
3769 hc->chan[i].conf = -1;
3770 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3773 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3774 HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3775 HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3777 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3778 HFC_outb(hc, R_RX0, 0);
3779 hc->hw.r_tx0 = 0 | V_OUT_EN;
3781 HFC_outb(hc, R_RX0, 1);
3782 hc->hw.r_tx0 = 1 | V_OUT_EN;
3784 hc->hw.r_tx1 = V_ATX | V_NTRI;
3785 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3786 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3787 HFC_outb(hc, R_TX_FR0, 0x00);
3788 HFC_outb(hc, R_TX_FR1, 0xf8);
3790 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3791 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3793 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3795 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3796 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3798 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3799 if (debug & DEBUG_HFCMULTI_INIT)
3800 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3802 r_e1_wr_sta = 0; /* G0 */
3803 hc->e1_getclock = 0;
3805 if (debug & DEBUG_HFCMULTI_INIT)
3806 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3808 r_e1_wr_sta = 0; /* F0 */
3809 hc->e1_getclock = 1;
3811 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3812 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3814 HFC_outb(hc, R_SYNC_OUT, 0);
3815 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3816 hc->e1_getclock = 1;
3817 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3818 hc->e1_getclock = 0;
3819 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3820 /* SLAVE (clock master) */
3821 if (debug & DEBUG_HFCMULTI_INIT)
3823 "%s: E1 port is clock master "
3824 "(clock from PCM)\n", __func__);
3825 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3827 if (hc->e1_getclock) {
3828 /* MASTER (clock slave) */
3829 if (debug & DEBUG_HFCMULTI_INIT)
3831 "%s: E1 port is clock slave "
3832 "(clock to PCM)\n", __func__);
3833 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3835 /* MASTER (clock master) */
3836 if (debug & DEBUG_HFCMULTI_INIT)
3837 printk(KERN_DEBUG "%s: E1 port is "
3839 "(clock from QUARTZ)\n",
3841 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3842 V_PCM_SYNC | V_JATT_OFF);
3843 HFC_outb(hc, R_SYNC_OUT, 0);
3846 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3847 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3848 HFC_outb(hc, R_PWM0, 0x50);
3849 HFC_outb(hc, R_PWM1, 0xff);
3850 /* state machine setup */
3851 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3852 udelay(6); /* wait at least 5,21us */
3853 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3854 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3855 hc->syncronized = 0;
3856 plxsd_checksync(hc, 0);
3860 hc->chan[i].slot_tx = -1;
3861 hc->chan[i].slot_rx = -1;
3862 hc->chan[i].conf = -1;
3863 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3864 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3865 dch->timer.data = (long) dch;
3866 init_timer(&dch->timer);
3867 hc->chan[i - 2].slot_tx = -1;
3868 hc->chan[i - 2].slot_rx = -1;
3869 hc->chan[i - 2].conf = -1;
3870 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3871 hc->chan[i - 1].slot_tx = -1;
3872 hc->chan[i - 1].slot_rx = -1;
3873 hc->chan[i - 1].conf = -1;
3874 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3876 pt = hc->chan[i].port;
3877 /* select interface */
3878 HFC_outb(hc, R_ST_SEL, pt);
3879 /* undocumented: delay after R_ST_SEL */
3881 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3882 if (debug & DEBUG_HFCMULTI_INIT)
3884 "%s: ST port %d is NT-mode\n",
3887 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3888 a_st_wr_state = 1; /* G1 */
3889 hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3891 if (debug & DEBUG_HFCMULTI_INIT)
3893 "%s: ST port %d is TE-mode\n",
3896 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3897 a_st_wr_state = 2; /* F2 */
3898 hc->hw.a_st_ctrl0[pt] = 0;
3900 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3901 hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3903 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
3904 /* disable E-channel */
3905 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3906 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3907 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
3909 HFC_outb(hc, A_ST_CTRL1, 0);
3910 /* enable B-channel receive */
3911 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN);
3912 /* state machine setup */
3913 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
3914 udelay(6); /* wait at least 5,21us */
3915 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
3916 hc->hw.r_sci_msk |= 1 << pt;
3917 /* state machine interrupts */
3918 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
3919 /* unset sync on port */
3920 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3922 ~(1 << hc->chan[dch->slot].port);
3923 plxsd_checksync(hc, 0);
3926 if (debug & DEBUG_HFCMULTI_INIT)
3927 printk("%s: done\n", __func__);
3932 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
3933 struct channel_req *rq)
3938 if (debug & DEBUG_HW_OPEN)
3939 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
3940 dch->dev.id, __builtin_return_address(0));
3941 if (rq->protocol == ISDN_P_NONE)
3943 if ((dch->dev.D.protocol != ISDN_P_NONE) &&
3944 (dch->dev.D.protocol != rq->protocol)) {
3945 if (debug & DEBUG_HFCMULTI_MODE)
3946 printk(KERN_WARNING "%s: change protocol %x to %x\n",
3947 __func__, dch->dev.D.protocol, rq->protocol);
3949 if ((dch->dev.D.protocol == ISDN_P_TE_S0)
3950 && (rq->protocol != ISDN_P_TE_S0))
3951 l1_event(dch->l1, CLOSE_CHANNEL);
3952 if (dch->dev.D.protocol != rq->protocol) {
3953 if (rq->protocol == ISDN_P_TE_S0) {
3954 err = create_l1(dch, hfcm_l1callback);
3958 dch->dev.D.protocol = rq->protocol;
3959 spin_lock_irqsave(&hc->lock, flags);
3960 hfcmulti_initmode(dch);
3961 spin_unlock_irqrestore(&hc->lock, flags);
3964 if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) ||
3965 ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) ||
3966 ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) ||
3967 ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) {
3968 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
3969 0, NULL, GFP_KERNEL);
3971 rq->ch = &dch->dev.D;
3972 if (!try_module_get(THIS_MODULE))
3973 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3978 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
3979 struct channel_req *rq)
3981 struct bchannel *bch;
3984 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
3986 if (rq->protocol == ISDN_P_NONE)
3989 ch = rq->adr.channel;
3991 ch = (rq->adr.channel - 1) + (dch->slot - 2);
3992 bch = hc->chan[ch].bch;
3994 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
3998 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
3999 return -EBUSY; /* b-channel can be only open once */
4000 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
4001 bch->ch.protocol = rq->protocol;
4002 hc->chan[ch].rx_off = 0;
4004 if (!try_module_get(THIS_MODULE))
4005 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4010 * device control function
4013 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4018 case MISDN_CTRL_GETOP:
4022 printk(KERN_WARNING "%s: unknown Op %x\n",
4031 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4033 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
4034 struct dchannel *dch = container_of(dev, struct dchannel, dev);
4035 struct hfc_multi *hc = dch->hw;
4036 struct channel_req *rq;
4040 if (dch->debug & DEBUG_HW)
4041 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4042 __func__, cmd, arg);
4046 switch (rq->protocol) {
4049 if (hc->type == 1) {
4053 err = open_dchannel(hc, dch, rq); /* locked there */
4057 if (hc->type != 1) {
4061 err = open_dchannel(hc, dch, rq); /* locked there */
4064 spin_lock_irqsave(&hc->lock, flags);
4065 err = open_bchannel(hc, dch, rq);
4066 spin_unlock_irqrestore(&hc->lock, flags);
4070 if (debug & DEBUG_HW_OPEN)
4071 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4072 __func__, dch->dev.id,
4073 __builtin_return_address(0));
4074 module_put(THIS_MODULE);
4076 case CONTROL_CHANNEL:
4077 spin_lock_irqsave(&hc->lock, flags);
4078 err = channel_dctrl(dch, arg);
4079 spin_unlock_irqrestore(&hc->lock, flags);
4082 if (dch->debug & DEBUG_HW)
4083 printk(KERN_DEBUG "%s: unknown command %x\n",
4091 clockctl(void *priv, int enable)
4093 struct hfc_multi *hc = priv;
4095 hc->iclock_on = enable;
4100 * initialize the card
4104 * start timer irq, wait some time and check if we have interrupts.
4105 * if not, reset chip and try again.
4108 init_card(struct hfc_multi *hc)
4112 void __iomem *plx_acc;
4115 if (debug & DEBUG_HFCMULTI_INIT)
4116 printk(KERN_DEBUG "%s: entered\n", __func__);
4118 spin_lock_irqsave(&hc->lock, flags);
4119 /* set interrupts but leave global interrupt disabled */
4120 hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4122 spin_unlock_irqrestore(&hc->lock, flags);
4124 if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED,
4126 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4130 hc->irq = hc->pci_dev->irq;
4132 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4133 spin_lock_irqsave(&plx_lock, plx_flags);
4134 plx_acc = hc->plx_membase + PLX_INTCSR;
4135 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4136 plx_acc); /* enable PCI & LINT1 irq */
4137 spin_unlock_irqrestore(&plx_lock, plx_flags);
4140 if (debug & DEBUG_HFCMULTI_INIT)
4141 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4142 __func__, hc->irq, hc->irqcnt);
4143 err = init_chip(hc);
4147 * Finally enable IRQ output
4148 * this is only allowed, if an IRQ routine is allready
4149 * established for this HFC, so don't do that earlier
4151 spin_lock_irqsave(&hc->lock, flags);
4153 spin_unlock_irqrestore(&hc->lock, flags);
4154 /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4155 set_current_state(TASK_UNINTERRUPTIBLE);
4156 schedule_timeout((100*HZ)/1000); /* Timeout 100ms */
4157 /* turn IRQ off until chip is completely initialized */
4158 spin_lock_irqsave(&hc->lock, flags);
4160 spin_unlock_irqrestore(&hc->lock, flags);
4161 if (debug & DEBUG_HFCMULTI_INIT)
4162 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4163 __func__, hc->irq, hc->irqcnt);
4165 if (debug & DEBUG_HFCMULTI_INIT)
4166 printk(KERN_DEBUG "%s: done\n", __func__);
4170 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4171 printk(KERN_INFO "ignoring missing interrupts\n");
4175 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4181 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4182 spin_lock_irqsave(&plx_lock, plx_flags);
4183 plx_acc = hc->plx_membase + PLX_INTCSR;
4184 writew(0x00, plx_acc); /*disable IRQs*/
4185 spin_unlock_irqrestore(&plx_lock, plx_flags);
4188 if (debug & DEBUG_HFCMULTI_INIT)
4189 printk(KERN_WARNING "%s: free irq %d\n", __func__, hc->irq);
4191 free_irq(hc->irq, hc);
4195 if (debug & DEBUG_HFCMULTI_INIT)
4196 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4201 * find pci device and set it up
4205 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4206 const struct pci_device_id *ent)
4208 struct hm_map *m = (struct hm_map *)ent->driver_data;
4211 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4212 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4216 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4218 if (ent->device == 0xB410) {
4219 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4220 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4221 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4225 if (hc->pci_dev->irq <= 0) {
4226 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4229 if (pci_enable_device(hc->pci_dev)) {
4230 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4234 hc->ledstate = 0xAFFEAFFE;
4235 hc->opticalsupport = m->opticalsupport;
4237 /* set memory access methods */
4238 if (m->io_mode) /* use mode from card config */
4239 hc->io_mode = m->io_mode;
4240 switch (hc->io_mode) {
4241 case HFC_IO_MODE_PLXSD:
4242 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4243 hc->slots = 128; /* required */
4245 case HFC_IO_MODE_PCIMEM:
4246 hc->HFC_outb = HFC_outb_pcimem;
4247 hc->HFC_inb = HFC_inb_pcimem;
4248 hc->HFC_inw = HFC_inw_pcimem;
4249 hc->HFC_wait = HFC_wait_pcimem;
4250 hc->read_fifo = read_fifo_pcimem;
4251 hc->write_fifo = write_fifo_pcimem;
4253 case HFC_IO_MODE_REGIO:
4254 hc->HFC_outb = HFC_outb_regio;
4255 hc->HFC_inb = HFC_inb_regio;
4256 hc->HFC_inw = HFC_inw_regio;
4257 hc->HFC_wait = HFC_wait_regio;
4258 hc->read_fifo = read_fifo_regio;
4259 hc->write_fifo = write_fifo_regio;
4262 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4263 pci_disable_device(hc->pci_dev);
4266 hc->HFC_outb_nodebug = hc->HFC_outb;
4267 hc->HFC_inb_nodebug = hc->HFC_inb;
4268 hc->HFC_inw_nodebug = hc->HFC_inw;
4269 hc->HFC_wait_nodebug = hc->HFC_wait;
4270 #ifdef HFC_REGISTER_DEBUG
4271 hc->HFC_outb = HFC_outb_debug;
4272 hc->HFC_inb = HFC_inb_debug;
4273 hc->HFC_inw = HFC_inw_debug;
4274 hc->HFC_wait = HFC_wait_debug;
4277 hc->pci_membase = NULL;
4278 hc->plx_membase = NULL;
4280 switch (hc->io_mode) {
4281 case HFC_IO_MODE_PLXSD:
4282 hc->plx_origmembase = hc->pci_dev->resource[0].start;
4283 /* MEMBASE 1 is PLX PCI Bridge */
4285 if (!hc->plx_origmembase) {
4287 "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4288 pci_disable_device(hc->pci_dev);
4292 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4293 if (!hc->plx_membase) {
4295 "HFC-multi: failed to remap plx address space. "
4296 "(internal error)\n");
4297 pci_disable_device(hc->pci_dev);
4301 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4302 (u_long)hc->plx_membase, hc->plx_origmembase);
4304 hc->pci_origmembase = hc->pci_dev->resource[2].start;
4305 /* MEMBASE 1 is PLX PCI Bridge */
4306 if (!hc->pci_origmembase) {
4308 "HFC-multi: No IO-Memory for PCI card found\n");
4309 pci_disable_device(hc->pci_dev);
4313 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4314 if (!hc->pci_membase) {
4315 printk(KERN_WARNING "HFC-multi: failed to remap io "
4316 "address space. (internal error)\n");
4317 pci_disable_device(hc->pci_dev);
4322 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4324 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4325 hc->pci_dev->irq, HZ, hc->leds);
4326 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4328 case HFC_IO_MODE_PCIMEM:
4329 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4330 if (!hc->pci_origmembase) {
4332 "HFC-multi: No IO-Memory for PCI card found\n");
4333 pci_disable_device(hc->pci_dev);
4337 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4338 if (!hc->pci_membase) {
4340 "HFC-multi: failed to remap io address space. "
4341 "(internal error)\n");
4342 pci_disable_device(hc->pci_dev);
4345 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d "
4346 "HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4347 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4348 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4350 case HFC_IO_MODE_REGIO:
4351 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4352 if (!hc->pci_iobase) {
4354 "HFC-multi: No IO for PCI card found\n");
4355 pci_disable_device(hc->pci_dev);
4359 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4360 printk(KERN_WARNING "HFC-multi: failed to request "
4361 "address space at 0x%08lx (internal error)\n",
4363 pci_disable_device(hc->pci_dev);
4368 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4369 m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4370 hc->pci_dev->irq, HZ, hc->leds);
4371 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4374 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4375 pci_disable_device(hc->pci_dev);
4379 pci_set_drvdata(hc->pci_dev, hc);
4381 /* At this point the needed PCI config is done */
4382 /* fifos are still not enabled */
4392 release_port(struct hfc_multi *hc, struct dchannel *dch)
4396 struct bchannel *pb;
4399 pt = hc->chan[ci].port;
4401 if (debug & DEBUG_HFCMULTI_INIT)
4402 printk(KERN_DEBUG "%s: entered for port %d\n",
4405 if (pt >= hc->ports) {
4406 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4411 if (debug & DEBUG_HFCMULTI_INIT)
4412 printk(KERN_DEBUG "%s: releasing port=%d\n",
4415 if (dch->dev.D.protocol == ISDN_P_TE_S0)
4416 l1_event(dch->l1, CLOSE_CHANNEL);
4418 hc->chan[ci].dch = NULL;
4420 if (hc->created[pt]) {
4421 hc->created[pt] = 0;
4422 mISDN_unregister_device(&dch->dev);
4425 spin_lock_irqsave(&hc->lock, flags);
4427 if (dch->timer.function) {
4428 del_timer(&dch->timer);
4429 dch->timer.function = NULL;
4432 if (hc->type == 1) { /* E1 */
4434 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4435 hc->syncronized = 0;
4436 plxsd_checksync(hc, 1);
4439 for (i = 0; i <= 31; i++) {
4440 if (hc->chan[i].bch) {
4441 if (debug & DEBUG_HFCMULTI_INIT)
4443 "%s: free port %d channel %d\n",
4444 __func__, hc->chan[i].port+1, i);
4445 pb = hc->chan[i].bch;
4446 hc->chan[i].bch = NULL;
4447 spin_unlock_irqrestore(&hc->lock, flags);
4448 mISDN_freebchannel(pb);
4450 kfree(hc->chan[i].coeff);
4451 spin_lock_irqsave(&hc->lock, flags);
4456 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4458 ~(1 << hc->chan[ci].port);
4459 plxsd_checksync(hc, 1);
4462 if (hc->chan[ci - 2].bch) {
4463 if (debug & DEBUG_HFCMULTI_INIT)
4465 "%s: free port %d channel %d\n",
4466 __func__, hc->chan[ci - 2].port+1,
4468 pb = hc->chan[ci - 2].bch;
4469 hc->chan[ci - 2].bch = NULL;
4470 spin_unlock_irqrestore(&hc->lock, flags);
4471 mISDN_freebchannel(pb);
4473 kfree(hc->chan[ci - 2].coeff);
4474 spin_lock_irqsave(&hc->lock, flags);
4476 if (hc->chan[ci - 1].bch) {
4477 if (debug & DEBUG_HFCMULTI_INIT)
4479 "%s: free port %d channel %d\n",
4480 __func__, hc->chan[ci - 1].port+1,
4482 pb = hc->chan[ci - 1].bch;
4483 hc->chan[ci - 1].bch = NULL;
4484 spin_unlock_irqrestore(&hc->lock, flags);
4485 mISDN_freebchannel(pb);
4487 kfree(hc->chan[ci - 1].coeff);
4488 spin_lock_irqsave(&hc->lock, flags);
4492 spin_unlock_irqrestore(&hc->lock, flags);
4494 if (debug & DEBUG_HFCMULTI_INIT)
4495 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4496 mISDN_freedchannel(dch);
4499 if (debug & DEBUG_HFCMULTI_INIT)
4500 printk(KERN_DEBUG "%s: done!\n", __func__);
4504 release_card(struct hfc_multi *hc)
4509 if (debug & DEBUG_HFCMULTI_INIT)
4510 printk(KERN_WARNING "%s: release card (%d) entered\n",
4513 /* unregister clock source */
4515 mISDN_unregister_clock(hc->iclock);
4518 spin_lock_irqsave(&hc->lock, flags);
4520 spin_unlock_irqrestore(&hc->lock, flags);
4527 /* disable D-channels & B-channels */
4528 if (debug & DEBUG_HFCMULTI_INIT)
4529 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4531 for (ch = 0; ch <= 31; ch++) {
4532 if (hc->chan[ch].dch)
4533 release_port(hc, hc->chan[ch].dch);
4536 /* release hardware & irq */
4538 if (debug & DEBUG_HFCMULTI_INIT)
4539 printk(KERN_WARNING "%s: free irq %d\n",
4541 free_irq(hc->irq, hc);
4545 release_io_hfcmulti(hc);
4547 if (debug & DEBUG_HFCMULTI_INIT)
4548 printk(KERN_WARNING "%s: remove instance from list\n",
4550 list_del(&hc->list);
4552 if (debug & DEBUG_HFCMULTI_INIT)
4553 printk(KERN_WARNING "%s: delete instance\n", __func__);
4554 if (hc == syncmaster)
4557 if (debug & DEBUG_HFCMULTI_INIT)
4558 printk(KERN_WARNING "%s: card successfully removed\n",
4563 init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4565 struct dchannel *dch;
4566 struct bchannel *bch;
4568 char name[MISDN_MAX_IDLEN];
4570 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4574 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4576 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4577 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4578 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4579 dch->dev.D.send = handle_dmsg;
4580 dch->dev.D.ctrl = hfcm_dctrl;
4581 dch->dev.nrbchan = (hc->dslot)?30:31;
4582 dch->slot = hc->dslot;
4583 hc->chan[hc->dslot].dch = dch;
4584 hc->chan[hc->dslot].port = 0;
4585 hc->chan[hc->dslot].nt_timer = -1;
4586 for (ch = 1; ch <= 31; ch++) {
4587 if (ch == hc->dslot) /* skip dchannel */
4589 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4591 printk(KERN_ERR "%s: no memory for bchannel\n",
4596 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4597 if (!hc->chan[ch].coeff) {
4598 printk(KERN_ERR "%s: no memory for coeffs\n",
4606 mISDN_initbchannel(bch, MAX_DATA_MEM);
4608 bch->ch.send = handle_bmsg;
4609 bch->ch.ctrl = hfcm_bctrl;
4611 list_add(&bch->ch.list, &dch->dev.bchannels);
4612 hc->chan[ch].bch = bch;
4613 hc->chan[ch].port = 0;
4614 set_channelmap(bch->nr, dch->dev.channelmap);
4616 /* set optical line type */
4617 if (port[Port_cnt] & 0x001) {
4618 if (!m->opticalsupport) {
4620 "This board has no optical "
4623 if (debug & DEBUG_HFCMULTI_INIT)
4625 "%s: PORT set optical "
4626 "interfacs: card(%d) "
4630 test_and_set_bit(HFC_CFG_OPTICAL,
4631 &hc->chan[hc->dslot].cfg);
4634 /* set LOS report */
4635 if (port[Port_cnt] & 0x004) {
4636 if (debug & DEBUG_HFCMULTI_INIT)
4637 printk(KERN_DEBUG "%s: PORT set "
4638 "LOS report: card(%d) port(%d)\n",
4639 __func__, HFC_cnt + 1, 1);
4640 test_and_set_bit(HFC_CFG_REPORT_LOS,
4641 &hc->chan[hc->dslot].cfg);
4643 /* set AIS report */
4644 if (port[Port_cnt] & 0x008) {
4645 if (debug & DEBUG_HFCMULTI_INIT)
4646 printk(KERN_DEBUG "%s: PORT set "
4647 "AIS report: card(%d) port(%d)\n",
4648 __func__, HFC_cnt + 1, 1);
4649 test_and_set_bit(HFC_CFG_REPORT_AIS,
4650 &hc->chan[hc->dslot].cfg);
4652 /* set SLIP report */
4653 if (port[Port_cnt] & 0x010) {
4654 if (debug & DEBUG_HFCMULTI_INIT)
4656 "%s: PORT set SLIP report: "
4657 "card(%d) port(%d)\n",
4658 __func__, HFC_cnt + 1, 1);
4659 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4660 &hc->chan[hc->dslot].cfg);
4662 /* set RDI report */
4663 if (port[Port_cnt] & 0x020) {
4664 if (debug & DEBUG_HFCMULTI_INIT)
4666 "%s: PORT set RDI report: "
4667 "card(%d) port(%d)\n",
4668 __func__, HFC_cnt + 1, 1);
4669 test_and_set_bit(HFC_CFG_REPORT_RDI,
4670 &hc->chan[hc->dslot].cfg);
4672 /* set CRC-4 Mode */
4673 if (!(port[Port_cnt] & 0x100)) {
4674 if (debug & DEBUG_HFCMULTI_INIT)
4675 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4676 " card(%d) port(%d)\n",
4677 __func__, HFC_cnt + 1, 1);
4678 test_and_set_bit(HFC_CFG_CRC4,
4679 &hc->chan[hc->dslot].cfg);
4681 if (debug & DEBUG_HFCMULTI_INIT)
4682 printk(KERN_DEBUG "%s: PORT turn off CRC4"
4683 " report: card(%d) port(%d)\n",
4684 __func__, HFC_cnt + 1, 1);
4686 /* set forced clock */
4687 if (port[Port_cnt] & 0x0200) {
4688 if (debug & DEBUG_HFCMULTI_INIT)
4689 printk(KERN_DEBUG "%s: PORT force getting clock from "
4690 "E1: card(%d) port(%d)\n",
4691 __func__, HFC_cnt + 1, 1);
4692 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4694 if (port[Port_cnt] & 0x0400) {
4695 if (debug & DEBUG_HFCMULTI_INIT)
4696 printk(KERN_DEBUG "%s: PORT force putting clock to "
4697 "E1: card(%d) port(%d)\n",
4698 __func__, HFC_cnt + 1, 1);
4699 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4702 if (port[Port_cnt] & 0x0800) {
4703 if (debug & DEBUG_HFCMULTI_INIT)
4704 printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4705 "E1: card(%d) port(%d)\n",
4706 __func__, HFC_cnt + 1, 1);
4707 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4709 /* set elastic jitter buffer */
4710 if (port[Port_cnt] & 0x3000) {
4711 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4712 if (debug & DEBUG_HFCMULTI_INIT)
4714 "%s: PORT set elastic "
4715 "buffer to %d: card(%d) port(%d)\n",
4716 __func__, hc->chan[hc->dslot].jitter,
4719 hc->chan[hc->dslot].jitter = 2; /* default */
4720 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4721 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4727 release_port(hc, dch);
4732 init_multi_port(struct hfc_multi *hc, int pt)
4734 struct dchannel *dch;
4735 struct bchannel *bch;
4737 char name[MISDN_MAX_IDLEN];
4739 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4743 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4745 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4746 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4747 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4748 dch->dev.D.send = handle_dmsg;
4749 dch->dev.D.ctrl = hfcm_dctrl;
4750 dch->dev.nrbchan = 2;
4753 hc->chan[i + 2].dch = dch;
4754 hc->chan[i + 2].port = pt;
4755 hc->chan[i + 2].nt_timer = -1;
4756 for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4757 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4759 printk(KERN_ERR "%s: no memory for bchannel\n",
4764 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4765 if (!hc->chan[i + ch].coeff) {
4766 printk(KERN_ERR "%s: no memory for coeffs\n",
4774 mISDN_initbchannel(bch, MAX_DATA_MEM);
4776 bch->ch.send = handle_bmsg;
4777 bch->ch.ctrl = hfcm_bctrl;
4778 bch->ch.nr = ch + 1;
4779 list_add(&bch->ch.list, &dch->dev.bchannels);
4780 hc->chan[i + ch].bch = bch;
4781 hc->chan[i + ch].port = pt;
4782 set_channelmap(bch->nr, dch->dev.channelmap);
4784 /* set master clock */
4785 if (port[Port_cnt] & 0x001) {
4786 if (debug & DEBUG_HFCMULTI_INIT)
4788 "%s: PROTOCOL set master clock: "
4789 "card(%d) port(%d)\n",
4790 __func__, HFC_cnt + 1, pt + 1);
4791 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4792 printk(KERN_ERR "Error: Master clock "
4793 "for port(%d) of card(%d) is only"
4794 " possible with TE-mode\n",
4795 pt + 1, HFC_cnt + 1);
4799 if (hc->masterclk >= 0) {
4800 printk(KERN_ERR "Error: Master clock "
4801 "for port(%d) of card(%d) already "
4802 "defined for port(%d)\n",
4803 pt + 1, HFC_cnt + 1, hc->masterclk+1);
4809 /* set transmitter line to non capacitive */
4810 if (port[Port_cnt] & 0x002) {
4811 if (debug & DEBUG_HFCMULTI_INIT)
4813 "%s: PROTOCOL set non capacitive "
4814 "transmitter: card(%d) port(%d)\n",
4815 __func__, HFC_cnt + 1, pt + 1);
4816 test_and_set_bit(HFC_CFG_NONCAP_TX,
4817 &hc->chan[i + 2].cfg);
4819 /* disable E-channel */
4820 if (port[Port_cnt] & 0x004) {
4821 if (debug & DEBUG_HFCMULTI_INIT)
4823 "%s: PROTOCOL disable E-channel: "
4824 "card(%d) port(%d)\n",
4825 __func__, HFC_cnt + 1, pt + 1);
4826 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4827 &hc->chan[i + 2].cfg);
4829 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4830 hc->type, HFC_cnt + 1, pt + 1);
4831 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4834 hc->created[pt] = 1;
4837 release_port(hc, dch);
4842 hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
4844 struct hm_map *m = (struct hm_map *)ent->driver_data;
4847 struct hfc_multi *hc;
4849 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4852 if (HFC_cnt >= MAX_CARDS) {
4853 printk(KERN_ERR "too many cards (max=%d).\n",
4857 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4858 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4859 "type[%d] %d was supplied as module parameter\n",
4860 m->vendor_name, m->card_name, m->type, HFC_cnt,
4861 type[HFC_cnt] & 0xff);
4862 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4863 "first, to see cards and their types.");
4866 if (debug & DEBUG_HFCMULTI_INIT)
4867 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4868 __func__, m->vendor_name, m->card_name, m->type,
4871 /* allocate card+fifo structure */
4872 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4874 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4877 spin_lock_init(&hc->lock);
4880 hc->ports = m->ports;
4882 hc->pcm = pcm[HFC_cnt];
4883 hc->io_mode = iomode[HFC_cnt];
4884 if (dslot[HFC_cnt] < 0 && hc->type == 1) {
4886 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
4888 } if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32 && hc->type == 1) {
4889 hc->dslot = dslot[HFC_cnt];
4890 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
4891 "time slot %d\n", dslot[HFC_cnt]);
4895 /* set chip specific features */
4897 if (type[HFC_cnt] & 0x100) {
4898 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
4899 hc->silence = 0xff; /* ulaw silence */
4901 hc->silence = 0x2a; /* alaw silence */
4902 if ((poll >> 1) > sizeof(hc->silence_data)) {
4903 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
4907 for (i = 0; i < (poll >> 1); i++)
4908 hc->silence_data[i] = hc->silence;
4910 if (!(type[HFC_cnt] & 0x200))
4911 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
4913 if (type[HFC_cnt] & 0x800)
4914 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4915 if (type[HFC_cnt] & 0x1000) {
4916 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4917 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4919 if (type[HFC_cnt] & 0x4000)
4920 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
4921 if (type[HFC_cnt] & 0x8000)
4922 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
4924 if (type[HFC_cnt] & 0x10000)
4926 if (type[HFC_cnt] & 0x20000)
4928 if (type[HFC_cnt] & 0x80000) {
4929 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
4931 hc->wdbyte = V_GPIO_OUT2;
4932 printk(KERN_NOTICE "Watchdog enabled\n");
4935 /* setup pci, hc->slots may change due to PLXSD */
4936 ret_err = setup_pci(hc, pdev, ent);
4938 if (hc == syncmaster)
4944 /* crate channels */
4945 for (pt = 0; pt < hc->ports; pt++) {
4946 if (Port_cnt >= MAX_PORTS) {
4947 printk(KERN_ERR "too many ports (max=%d).\n",
4953 ret_err = init_e1_port(hc, m);
4955 ret_err = init_multi_port(hc, pt);
4956 if (debug & DEBUG_HFCMULTI_INIT)
4958 "%s: Registering D-channel, card(%d) port(%d)"
4960 __func__, HFC_cnt + 1, pt, ret_err);
4963 while (pt) { /* release already registered ports */
4965 release_port(hc, hc->chan[(pt << 2) + 2].dch);
4973 switch (m->dip_type) {
4976 * Get DIP setting for beroNet 1S/2S/4S cards
4977 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
4978 * GPI 19/23 (R_GPI_IN2))
4980 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
4981 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
4982 (~HFC_inb(hc, R_GPI_IN2) & 0x08);
4984 /* Port mode (TE/NT) jumpers */
4985 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf);
4987 if (test_bit(HFC_CHIP_B410P, &hc->chip))
4990 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
4991 m->vendor_name, m->card_name, dips, pmj);
4995 * Get DIP Setting for beroNet 8S0+ cards
4996 * Enable PCI auxbridge function
4998 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
4999 /* prepare access to auxport */
5000 outw(0x4000, hc->pci_iobase + 4);
5002 * some dummy reads are required to
5003 * read valid DIP switch data
5005 dips = inb(hc->pci_iobase);
5006 dips = inb(hc->pci_iobase);
5007 dips = inb(hc->pci_iobase);
5008 dips = ~inb(hc->pci_iobase) & 0x3F;
5009 outw(0x0, hc->pci_iobase + 4);
5010 /* disable PCI auxbridge function */
5011 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5012 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5013 m->vendor_name, m->card_name, dips);
5017 * get DIP Setting for beroNet E1 cards
5018 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5020 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4;
5021 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5022 m->vendor_name, m->card_name, dips);
5027 spin_lock_irqsave(&HFClock, flags);
5028 list_add_tail(&hc->list, &HFClist);
5029 spin_unlock_irqrestore(&HFClock, flags);
5031 /* use as clock source */
5032 if (clock == HFC_cnt + 1)
5033 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5035 /* initialize hardware */
5036 ret_err = init_card(hc);
5038 printk(KERN_ERR "init card returns %d\n", ret_err);
5043 /* start IRQ and return */
5044 spin_lock_irqsave(&hc->lock, flags);
5046 spin_unlock_irqrestore(&hc->lock, flags);
5050 release_io_hfcmulti(hc);
5051 if (hc == syncmaster)
5057 static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5059 struct hfc_multi *card = pci_get_drvdata(pdev);
5063 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5064 "device:%x subvendor:%x subdevice:%x\n",
5065 pdev->vendor, pdev->device,
5066 pdev->subsystem_vendor, pdev->subsystem_device);
5069 spin_lock_irqsave(&HFClock, flags);
5071 spin_unlock_irqrestore(&HFClock, flags);
5074 printk(KERN_WARNING "%s: drvdata allready removed\n",
5079 #define VENDOR_CCD "Cologne Chip AG"
5080 #define VENDOR_BN "beroNet GmbH"
5081 #define VENDOR_DIG "Digium Inc."
5082 #define VENDOR_JH "Junghanns.NET GmbH"
5083 #define VENDOR_PRIM "PrimuX"
5085 static const struct hm_map hfcm_map[] = {
5086 /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0},
5087 /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0},
5088 /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0},
5089 /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0},
5090 /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0},
5091 /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0},
5092 /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0},
5093 /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0},
5094 /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO},
5095 /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0},
5096 /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0},
5097 /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0},
5099 /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0},
5100 /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5102 /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0},
5103 /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0},
5105 /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0},
5106 /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5107 /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5109 /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0},
5110 /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0},
5111 /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5112 /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5114 /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0},
5115 /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0},
5116 /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0},
5118 /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5120 /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5122 /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0},
5123 /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0},
5124 /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0},
5128 #define H(x) ((unsigned long)&hfcm_map[x])
5129 static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5131 /* Cards with HFC-4S Chip */
5132 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5133 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5134 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5135 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5136 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5137 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5138 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5139 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5140 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5141 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5142 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5143 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5144 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5145 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5146 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5147 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5148 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5149 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5150 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5151 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5152 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5153 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5154 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5155 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5156 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5157 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5158 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5159 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5161 /* Cards with HFC-8S Chip */
5162 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5163 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5164 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5165 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5166 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5167 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5168 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5169 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5170 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5171 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */
5172 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5173 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */
5174 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5175 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5176 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5177 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5180 /* Cards with HFC-E1 Chip */
5181 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5182 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5183 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5184 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5185 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5186 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5187 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5188 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5190 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5191 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5192 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5193 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5194 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5195 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5197 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5198 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5199 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5200 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5201 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID,
5203 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID,
5205 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID,
5211 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5214 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5216 struct hm_map *m = (struct hm_map *)ent->driver_data;
5219 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5220 ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5221 ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5222 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5224 "Unknown HFC multiport controller (vendor:%x device:%x "
5225 "subvendor:%x subdevice:%x)\n", ent->vendor, ent->device,
5226 ent->subvendor, ent->subdevice);
5228 "Please contact the driver maintainer for support.\n");
5231 ret = hfcmulti_init(pdev, ent);
5235 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5239 static struct pci_driver hfcmultipci_driver = {
5240 .name = "hfc_multi",
5241 .probe = hfcmulti_probe,
5242 .remove = __devexit_p(hfc_remove_pci),
5243 .id_table = hfmultipci_ids,
5247 HFCmulti_cleanup(void)
5249 struct hfc_multi *card, *next;
5251 /* get rid of all devices of this driver */
5252 list_for_each_entry_safe(card, next, &HFClist, list)
5254 pci_unregister_driver(&hfcmultipci_driver);
5262 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5265 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5268 spin_lock_init(&HFClock);
5269 spin_lock_init(&plx_lock);
5271 if (debug & DEBUG_HFCMULTI_INIT)
5272 printk(KERN_DEBUG "%s: init entered\n", __func__);
5299 "%s: Wrong poll value (%d).\n", __func__, poll);
5308 err = pci_register_driver(&hfcmultipci_driver);
5310 printk(KERN_ERR "error registering pci driver: %x\n", err);
5317 module_init(HFCmulti_init);
5318 module_exit(HFCmulti_cleanup);