2 * Copyright (C) 2006-2008 PA Semi, Inc
4 * Hardware register layout and descriptor formats for the on-board
5 * DMA engine on PA Semi PWRficient. Used by ethernet, function and security
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #ifndef ASM_PASEMI_DMA_H
23 #define ASM_PASEMI_DMA_H
25 /* status register layout in IOB region, at 0xfb800000 */
26 struct pasdma_status {
27 u64 rx_sta[64]; /* RX channel status */
28 u64 tx_sta[20]; /* TX channel status */
32 /* All these registers live in the PCI configuration space for the DMA PCI
33 * device. Use the normal PCI config access functions for them.
36 PAS_DMA_CAP_TXCH = 0x44, /* Transmit Channel Info */
37 PAS_DMA_CAP_RXCH = 0x48, /* Transmit Channel Info */
38 PAS_DMA_CAP_IFI = 0x4c, /* Interface Info */
39 PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
40 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
41 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
42 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
43 PAS_DMA_COM_CFG = 0x114, /* Common config reg */
44 PAS_DMA_TXF_SFLG0 = 0x140, /* Set flags */
45 PAS_DMA_TXF_SFLG1 = 0x144, /* Set flags */
46 PAS_DMA_TXF_CFLG0 = 0x148, /* Set flags */
47 PAS_DMA_TXF_CFLG1 = 0x14c, /* Set flags */
51 #define PAS_DMA_CAP_TXCH_TCHN_M 0x00ff0000 /* # of TX channels */
52 #define PAS_DMA_CAP_TXCH_TCHN_S 16
54 #define PAS_DMA_CAP_RXCH_RCHN_M 0x00ff0000 /* # of RX channels */
55 #define PAS_DMA_CAP_RXCH_RCHN_S 16
57 #define PAS_DMA_CAP_IFI_IOFF_M 0xff000000 /* Cfg reg for intf pointers */
58 #define PAS_DMA_CAP_IFI_IOFF_S 24
59 #define PAS_DMA_CAP_IFI_NIN_M 0x00ff0000 /* # of interfaces */
60 #define PAS_DMA_CAP_IFI_NIN_S 16
62 #define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */
63 #define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */
64 #define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */
65 #define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */
68 /* Per-interface and per-channel registers */
69 #define _PAS_DMA_RXINT_STRIDE 0x20
70 #define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
71 #define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001
72 #define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002
73 #define PAS_DMA_RXINT_RCMDSTA_MBT 0x00000008
74 #define PAS_DMA_RXINT_RCMDSTA_MDR 0x00000010
75 #define PAS_DMA_RXINT_RCMDSTA_MOO 0x00000020
76 #define PAS_DMA_RXINT_RCMDSTA_MBP 0x00000040
77 #define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800
78 #define PAS_DMA_RXINT_RCMDSTA_DR 0x00001000
79 #define PAS_DMA_RXINT_RCMDSTA_OO 0x00002000
80 #define PAS_DMA_RXINT_RCMDSTA_BP 0x00004000
81 #define PAS_DMA_RXINT_RCMDSTA_TB 0x00008000
82 #define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000
83 #define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000
84 #define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17
85 #define PAS_DMA_RXINT_CFG(i) (0x204+(i)*_PAS_DMA_RXINT_STRIDE)
86 #define PAS_DMA_RXINT_CFG_RBP 0x80000000
87 #define PAS_DMA_RXINT_CFG_ITRR 0x40000000
88 #define PAS_DMA_RXINT_CFG_DHL_M 0x07000000
89 #define PAS_DMA_RXINT_CFG_DHL_S 24
90 #define PAS_DMA_RXINT_CFG_DHL(x) (((x) << PAS_DMA_RXINT_CFG_DHL_S) & \
91 PAS_DMA_RXINT_CFG_DHL_M)
92 #define PAS_DMA_RXINT_CFG_ITR 0x00400000
93 #define PAS_DMA_RXINT_CFG_LW 0x00200000
94 #define PAS_DMA_RXINT_CFG_L2 0x00100000
95 #define PAS_DMA_RXINT_CFG_HEN 0x00080000
96 #define PAS_DMA_RXINT_CFG_WIF 0x00000002
97 #define PAS_DMA_RXINT_CFG_WIL 0x00000001
99 #define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
100 #define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff
101 #define PAS_DMA_RXINT_INCR_INCR_S 0
102 #define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff)
103 #define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
104 #define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f)
105 #define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
106 #define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff)
107 #define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */
108 #define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */
109 #define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
110 PAS_DMA_RXINT_BASEU_SIZ_M)
113 #define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */
114 #define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */
115 #define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */
116 #define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */
117 #define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */
118 #define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */
119 #define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */
120 #define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */
121 #define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
122 #define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */
123 #define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */
124 #define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */
125 #define PAS_DMA_TXCHAN_TCMDSTA_SZ 0x00000800
126 #define PAS_DMA_TXCHAN_TCMDSTA_DB 0x00000400
127 #define PAS_DMA_TXCHAN_TCMDSTA_DE 0x00000200
128 #define PAS_DMA_TXCHAN_TCMDSTA_DA 0x00000100
129 #define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
130 #define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
131 #define PAS_DMA_TXCHAN_CFG_TY_COPY 0x00000001 /* Type = copy only */
132 #define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = function */
133 #define PAS_DMA_TXCHAN_CFG_TY_XOR 0x00000003 /* Type = xor only */
134 #define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
135 #define PAS_DMA_TXCHAN_CFG_TATTR_S 2
136 #define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
137 PAS_DMA_TXCHAN_CFG_TATTR_M)
138 #define PAS_DMA_TXCHAN_CFG_LPDQ 0x00000800
139 #define PAS_DMA_TXCHAN_CFG_LPSQ 0x00000400
140 #define PAS_DMA_TXCHAN_CFG_WT_M 0x000003c0
141 #define PAS_DMA_TXCHAN_CFG_WT_S 6
142 #define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
143 PAS_DMA_TXCHAN_CFG_WT_M)
144 #define PAS_DMA_TXCHAN_CFG_TRD 0x00010000 /* translate data */
145 #define PAS_DMA_TXCHAN_CFG_TRR 0x00008000 /* translate rings */
146 #define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */
147 #define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */
148 #define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */
149 #define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
150 #define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
151 #define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0
152 #define PAS_DMA_TXCHAN_BASEL_BRBL_S 0
153 #define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
154 PAS_DMA_TXCHAN_BASEL_BRBL_M)
155 #define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
156 #define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff
157 #define PAS_DMA_TXCHAN_BASEU_BRBH_S 0
158 #define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
159 PAS_DMA_TXCHAN_BASEU_BRBH_M)
160 /* # of cache lines worth of buffer ring */
161 #define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000
162 #define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
163 #define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
164 PAS_DMA_TXCHAN_BASEU_SIZ_M)
166 #define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */
167 #define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */
168 #define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */
169 #define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */
170 #define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */
171 #define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */
172 #define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */
173 #define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
174 #define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */
175 #define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */
176 #define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */
177 #define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000
178 #define PAS_DMA_RXCHAN_CCMDSTA_OD 0x00002000
179 #define PAS_DMA_RXCHAN_CCMDSTA_FD 0x00001000
180 #define PAS_DMA_RXCHAN_CCMDSTA_DT 0x00000800
181 #define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
182 #define PAS_DMA_RXCHAN_CFG_CTR 0x00000400
183 #define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380
184 #define PAS_DMA_RXCHAN_CFG_HBU_S 7
185 #define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
186 PAS_DMA_RXCHAN_CFG_HBU_M)
187 #define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
188 #define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
189 #define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0
190 #define PAS_DMA_RXCHAN_BASEL_BRBL_S 0
191 #define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
192 PAS_DMA_RXCHAN_BASEL_BRBL_M)
193 #define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
194 #define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff
195 #define PAS_DMA_RXCHAN_BASEU_BRBH_S 0
196 #define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
197 PAS_DMA_RXCHAN_BASEU_BRBH_M)
198 /* # of cache lines worth of buffer ring */
199 #define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000
200 #define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
201 #define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
202 PAS_DMA_RXCHAN_BASEU_SIZ_M)
204 #define PAS_STATUS_PCNT_M 0x000000000000ffffull
205 #define PAS_STATUS_PCNT_S 0
206 #define PAS_STATUS_DCNT_M 0x00000000ffff0000ull
207 #define PAS_STATUS_DCNT_S 16
208 #define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull
209 #define PAS_STATUS_BPCNT_S 32
210 #define PAS_STATUS_CAUSE_M 0xf000000000000000ull
211 #define PAS_STATUS_TIMER 0x1000000000000000ull
212 #define PAS_STATUS_ERROR 0x2000000000000000ull
213 #define PAS_STATUS_SOFT 0x4000000000000000ull
214 #define PAS_STATUS_INT 0x8000000000000000ull
216 #define PAS_IOB_COM_PKTHDRCNT 0x120
217 #define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M 0x0fff0000
218 #define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S 16
219 #define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M 0x00000fff
220 #define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S 0
222 #define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4)
223 #define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff
224 #define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0
225 #define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
226 PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
227 #define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4)
228 #define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff
229 #define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0
230 #define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
231 PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
232 #define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4)
233 #define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
234 #define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff
235 #define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0
236 #define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
237 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
238 #define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4)
239 #define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
240 #define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff
241 #define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0
242 #define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
243 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
244 #define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4)
245 #define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000
246 #define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16
247 #define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
248 PAS_IOB_DMA_RXCH_RESET_PCNT_M)
249 #define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020
250 #define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010
251 #define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008
252 #define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004
253 #define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002
254 #define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001
255 #define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4)
256 #define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000
257 #define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16
258 #define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
259 PAS_IOB_DMA_TXCH_RESET_PCNT_M)
260 #define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020
261 #define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010
262 #define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008
263 #define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004
264 #define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002
265 #define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001
267 #define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700
268 #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff
269 #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0
270 #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
271 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
273 /* Transmit descriptor fields */
274 #define XCT_MACTX_T 0x8000000000000000ull
275 #define XCT_MACTX_ST 0x4000000000000000ull
276 #define XCT_MACTX_NORES 0x0000000000000000ull
277 #define XCT_MACTX_8BRES 0x1000000000000000ull
278 #define XCT_MACTX_24BRES 0x2000000000000000ull
279 #define XCT_MACTX_40BRES 0x3000000000000000ull
280 #define XCT_MACTX_I 0x0800000000000000ull
281 #define XCT_MACTX_O 0x0400000000000000ull
282 #define XCT_MACTX_E 0x0200000000000000ull
283 #define XCT_MACTX_VLAN_M 0x0180000000000000ull
284 #define XCT_MACTX_VLAN_NOP 0x0000000000000000ull
285 #define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull
286 #define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull
287 #define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull
288 #define XCT_MACTX_CRC_M 0x0060000000000000ull
289 #define XCT_MACTX_CRC_NOP 0x0000000000000000ull
290 #define XCT_MACTX_CRC_INSERT 0x0020000000000000ull
291 #define XCT_MACTX_CRC_PAD 0x0040000000000000ull
292 #define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull
293 #define XCT_MACTX_SS 0x0010000000000000ull
294 #define XCT_MACTX_LLEN_M 0x00007fff00000000ull
295 #define XCT_MACTX_LLEN_S 32ull
296 #define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \
298 #define XCT_MACTX_IPH_M 0x00000000f8000000ull
299 #define XCT_MACTX_IPH_S 27ull
300 #define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \
302 #define XCT_MACTX_IPO_M 0x0000000007c00000ull
303 #define XCT_MACTX_IPO_S 22ull
304 #define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \
306 #define XCT_MACTX_CSUM_M 0x0000000000000060ull
307 #define XCT_MACTX_CSUM_NOP 0x0000000000000000ull
308 #define XCT_MACTX_CSUM_TCP 0x0000000000000040ull
309 #define XCT_MACTX_CSUM_UDP 0x0000000000000060ull
310 #define XCT_MACTX_V6 0x0000000000000010ull
311 #define XCT_MACTX_C 0x0000000000000004ull
312 #define XCT_MACTX_AL2 0x0000000000000002ull
314 /* Receive descriptor fields */
315 #define XCT_MACRX_T 0x8000000000000000ull
316 #define XCT_MACRX_ST 0x4000000000000000ull
317 #define XCT_MACRX_RR_M 0x3000000000000000ull
318 #define XCT_MACRX_RR_NORES 0x0000000000000000ull
319 #define XCT_MACRX_RR_8BRES 0x1000000000000000ull
320 #define XCT_MACRX_O 0x0400000000000000ull
321 #define XCT_MACRX_E 0x0200000000000000ull
322 #define XCT_MACRX_FF 0x0100000000000000ull
323 #define XCT_MACRX_PF 0x0080000000000000ull
324 #define XCT_MACRX_OB 0x0040000000000000ull
325 #define XCT_MACRX_OD 0x0020000000000000ull
326 #define XCT_MACRX_FS 0x0010000000000000ull
327 #define XCT_MACRX_NB_M 0x000fc00000000000ull
328 #define XCT_MACRX_NB_S 46ULL
329 #define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \
331 #define XCT_MACRX_LLEN_M 0x00003fff00000000ull
332 #define XCT_MACRX_LLEN_S 32ULL
333 #define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \
335 #define XCT_MACRX_CRC 0x0000000080000000ull
336 #define XCT_MACRX_LEN_M 0x0000000060000000ull
337 #define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull
338 #define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull
339 #define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull
340 #define XCT_MACRX_CAST_M 0x0000000018000000ull
341 #define XCT_MACRX_CAST_UNI 0x0000000000000000ull
342 #define XCT_MACRX_CAST_MULTI 0x0000000008000000ull
343 #define XCT_MACRX_CAST_BROAD 0x0000000010000000ull
344 #define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull
345 #define XCT_MACRX_VLC_M 0x0000000006000000ull
346 #define XCT_MACRX_FM 0x0000000001000000ull
347 #define XCT_MACRX_HTY_M 0x0000000000c00000ull
348 #define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull
349 #define XCT_MACRX_HTY_IPV6 0x0000000000400000ull
350 #define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull
351 #define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull
352 #define XCT_MACRX_IPP_M 0x00000000003f0000ull
353 #define XCT_MACRX_IPP_S 16
354 #define XCT_MACRX_CSUM_M 0x000000000000ffffull
355 #define XCT_MACRX_CSUM_S 0
357 #define XCT_PTR_T 0x8000000000000000ull
358 #define XCT_PTR_LEN_M 0x7ffff00000000000ull
359 #define XCT_PTR_LEN_S 44
360 #define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \
362 #define XCT_PTR_ADDR_M 0x00000fffffffffffull
363 #define XCT_PTR_ADDR_S 0
364 #define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \
367 /* Receive interface 8byte result fields */
368 #define XCT_RXRES_8B_L4O_M 0xff00000000000000ull
369 #define XCT_RXRES_8B_L4O_S 56
370 #define XCT_RXRES_8B_RULE_M 0x00ffff0000000000ull
371 #define XCT_RXRES_8B_RULE_S 40
372 #define XCT_RXRES_8B_EVAL_M 0x000000ffff000000ull
373 #define XCT_RXRES_8B_EVAL_S 24
374 #define XCT_RXRES_8B_HTYPE_M 0x0000000000f00000ull
375 #define XCT_RXRES_8B_HASH_M 0x00000000000fffffull
376 #define XCT_RXRES_8B_HASH_S 0
378 /* Receive interface buffer fields */
379 #define XCT_RXB_LEN_M 0x0ffff00000000000ull
380 #define XCT_RXB_LEN_S 44
381 #define XCT_RXB_LEN(x) ((((long)(x)) << XCT_RXB_LEN_S) & \
383 #define XCT_RXB_ADDR_M 0x00000fffffffffffull
384 #define XCT_RXB_ADDR_S 0
385 #define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_RXB_ADDR_S) & \
388 /* Copy descriptor fields */
389 #define XCT_COPY_T 0x8000000000000000ull
390 #define XCT_COPY_ST 0x4000000000000000ull
391 #define XCT_COPY_RR_M 0x3000000000000000ull
392 #define XCT_COPY_RR_NORES 0x0000000000000000ull
393 #define XCT_COPY_RR_8BRES 0x1000000000000000ull
394 #define XCT_COPY_RR_24BRES 0x2000000000000000ull
395 #define XCT_COPY_RR_40BRES 0x3000000000000000ull
396 #define XCT_COPY_I 0x0800000000000000ull
397 #define XCT_COPY_O 0x0400000000000000ull
398 #define XCT_COPY_E 0x0200000000000000ull
399 #define XCT_COPY_STY_ZERO 0x01c0000000000000ull
400 #define XCT_COPY_DTY_PREF 0x0038000000000000ull
401 #define XCT_COPY_LLEN_M 0x0007ffff00000000ull
402 #define XCT_COPY_LLEN_S 32
403 #define XCT_COPY_LLEN(x) ((((long)(x)) << XCT_COPY_LLEN_S) & \
405 #define XCT_COPY_SE 0x0000000000000001ull
407 /* Function descriptor fields */
408 #define XCT_FUN_T 0x8000000000000000ull
409 #define XCT_FUN_ST 0x4000000000000000ull
410 #define XCT_FUN_RR_M 0x3000000000000000ull
411 #define XCT_FUN_RR_NORES 0x0000000000000000ull
412 #define XCT_FUN_RR_8BRES 0x1000000000000000ull
413 #define XCT_FUN_RR_24BRES 0x2000000000000000ull
414 #define XCT_FUN_RR_40BRES 0x3000000000000000ull
415 #define XCT_FUN_I 0x0800000000000000ull
416 #define XCT_FUN_O 0x0400000000000000ull
417 #define XCT_FUN_E 0x0200000000000000ull
418 #define XCT_FUN_FUN_M 0x01c0000000000000ull
419 #define XCT_FUN_FUN_S 54
420 #define XCT_FUN_FUN(x) ((((long)(x)) << XCT_FUN_FUN_S) & XCT_FUN_FUN_M)
421 #define XCT_FUN_CRM_M 0x0038000000000000ull
422 #define XCT_FUN_CRM_NOP 0x0000000000000000ull
423 #define XCT_FUN_CRM_SIG 0x0008000000000000ull
424 #define XCT_FUN_LLEN_M 0x0007ffff00000000ull
425 #define XCT_FUN_LLEN_S 32
426 #define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & XCT_FUN_LLEN_M)
427 #define XCT_FUN_SHL_M 0x00000000f8000000ull
428 #define XCT_FUN_SHL_S 27
429 #define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & XCT_FUN_SHL_M)
430 #define XCT_FUN_CHL_M 0x0000000007c00000ull
431 #define XCT_FUN_HSZ_M 0x00000000003c0000ull
432 #define XCT_FUN_ALG_M 0x0000000000038000ull
433 #define XCT_FUN_HP 0x0000000000004000ull
434 #define XCT_FUN_BCM_M 0x0000000000003800ull
435 #define XCT_FUN_BCP_M 0x0000000000000600ull
436 #define XCT_FUN_SIG_M 0x00000000000001f0ull
437 #define XCT_FUN_SIG_TCP4 0x0000000000000140ull
438 #define XCT_FUN_SIG_TCP6 0x0000000000000150ull
439 #define XCT_FUN_SIG_UDP4 0x0000000000000160ull
440 #define XCT_FUN_SIG_UDP6 0x0000000000000170ull
441 #define XCT_FUN_A 0x0000000000000008ull
442 #define XCT_FUN_C 0x0000000000000004ull
443 #define XCT_FUN_AL2 0x0000000000000002ull
444 #define XCT_FUN_SE 0x0000000000000001ull
446 /* Function descriptor 8byte result fields */
447 #define XCT_FUNRES_8B_CS_M 0x0000ffff00000000ull
448 #define XCT_FUNRES_8B_CS_S 32
449 #define XCT_FUNRES_8B_CRC_M 0x00000000ffffffffull
450 #define XCT_FUNRES_8B_CRC_S 0
452 /* Control descriptor fields */
453 #define CTRL_CMD_T 0x8000000000000000ull
454 #define CTRL_CMD_META_EVT 0x2000000000000000ull
455 #define CTRL_CMD_O 0x0400000000000000ull
456 #define CTRL_CMD_ETYPE_M 0x0038000000000000ull
457 #define CTRL_CMD_ETYPE_EXT 0x0000000000000000ull
458 #define CTRL_CMD_ETYPE_WSET 0x0020000000000000ull
459 #define CTRL_CMD_ETYPE_WCLR 0x0028000000000000ull
460 #define CTRL_CMD_ETYPE_SET 0x0030000000000000ull
461 #define CTRL_CMD_ETYPE_CLR 0x0038000000000000ull
462 #define CTRL_CMD_REG_M 0x000000000000007full
463 #define CTRL_CMD_REG_S 0
464 #define CTRL_CMD_REG(x) ((((long)(x)) << CTRL_CMD_REG_S) & \
469 /* Prototypes for the shared DMA functions in the platform code. */
471 /* DMA TX Channel type. Right now only limitations used are event types 0/1,
472 * for event-triggered DMA transactions.
475 enum pasemi_dmachan_type {
476 RXCHAN = 0, /* Any RX chan */
477 TXCHAN = 1, /* Any TX chan */
478 TXCHAN_EVT0 = 0x1001, /* TX chan in event class 0 (chan 0-9) */
479 TXCHAN_EVT1 = 0x2001, /* TX chan in event class 1 (chan 10-19) */
482 struct pasemi_dmachan {
483 int chno; /* Channel number */
484 enum pasemi_dmachan_type chan_type; /* TX / RX */
485 u64 *status; /* Ptr to cacheable status */
486 int irq; /* IRQ used by channel */
487 unsigned int ring_size; /* size of allocated ring */
488 dma_addr_t ring_dma; /* DMA address for ring */
489 u64 *ring_virt; /* Virt address for ring */
490 void *priv; /* Ptr to start of client struct */
493 /* Read/write the different registers in the I/O Bridge, Ethernet
496 extern unsigned int pasemi_read_iob_reg(unsigned int reg);
497 extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val);
499 extern unsigned int pasemi_read_mac_reg(int intf, unsigned int reg);
500 extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val);
502 extern unsigned int pasemi_read_dma_reg(unsigned int reg);
503 extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val);
505 /* Channel management routines */
507 extern void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type,
508 int total_size, int offset);
509 extern void pasemi_dma_free_chan(struct pasemi_dmachan *chan);
511 extern void pasemi_dma_start_chan(const struct pasemi_dmachan *chan,
513 extern int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan);
515 /* Common routines to allocate rings and buffers */
517 extern int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size);
518 extern void pasemi_dma_free_ring(struct pasemi_dmachan *chan);
520 extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
522 extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
525 /* Routines to allocate flags (events) for channel syncronization */
526 extern int pasemi_dma_alloc_flag(void);
527 extern void pasemi_dma_free_flag(int flag);
528 extern void pasemi_dma_set_flag(int flag);
529 extern void pasemi_dma_clear_flag(int flag);
531 /* Routines to allocate function engines */
532 extern int pasemi_dma_alloc_fun(void);
533 extern void pasemi_dma_free_fun(int fun);
535 /* Initialize the library, must be called before any other functions */
536 extern int pasemi_dma_init(void);
538 #endif /* ASM_PASEMI_DMA_H */
projects / linux-2.6 / blob