git.oblomov.eu Git - linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43
  44 #include <asm/system.h>
  45 #include <asm/io.h>
  46 #include <asm/byteorder.h>
  47 #include <asm/uaccess.h>
  48
  49 #ifdef CONFIG_SPARC64
  50 #include <asm/idprom.h>
  51 #include <asm/oplib.h>
  52 #include <asm/pbm.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #define TG3_TSO_SUPPORT 1
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define PFX DRV_MODULE_NAME     ": "
  67 #define DRV_MODULE_VERSION      "3.75"
  68 #define DRV_MODULE_RELDATE      "March 23, 2007"
  69
  70 #define TG3_DEF_MAC_MODE        0
  71 #define TG3_DEF_RX_MODE         0
  72 #define TG3_DEF_TX_MODE         0
  73 #define TG3_DEF_MSG_ENABLE        \
  74         (NETIF_MSG_DRV          | \
  75          NETIF_MSG_PROBE        | \
  76          NETIF_MSG_LINK         | \
  77          NETIF_MSG_TIMER        | \
  78          NETIF_MSG_IFDOWN       | \
  79          NETIF_MSG_IFUP         | \
  80          NETIF_MSG_RX_ERR       | \
  81          NETIF_MSG_TX_ERR)
  82
  83 /* length of time before we decide the hardware is borked,
  84  * and dev->tx_timeout() should be called to fix the problem
  85  */
  86 #define TG3_TX_TIMEOUT                  (5 * HZ)
  87
  88 /* hardware minimum and maximum for a single frame's data payload */
  89 #define TG3_MIN_MTU                     60
  90 #define TG3_MAX_MTU(tp) \
  91         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  92
  93 /* These numbers seem to be hard coded in the NIC firmware somehow.
  94  * You can't change the ring sizes, but you can change where you place
  95  * them in the NIC onboard memory.
  96  */
  97 #define TG3_RX_RING_SIZE                512
  98 #define TG3_DEF_RX_RING_PENDING         200
  99 #define TG3_RX_JUMBO_RING_SIZE          256
 100 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 101
 102 /* Do not place this n-ring entries value into the tp struct itself,
 103  * we really want to expose these constants to GCC so that modulo et
 104  * al.  operations are done with shifts and masks instead of with
 105  * hw multiply/modulo instructions.  Another solution would be to
 106  * replace things like '% foo' with '& (foo - 1)'.
 107  */
 108 #define TG3_RX_RCB_RING_SIZE(tp)        \
 109         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 110
 111 #define TG3_TX_RING_SIZE                512
 112 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 113
 114 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 115                                  TG3_RX_RING_SIZE)
 116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_JUMBO_RING_SIZE)
 118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 119                                    TG3_RX_RCB_RING_SIZE(tp))
 120 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 121                                  TG3_TX_RING_SIZE)
 122 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 123
 124 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 125 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 126
 127 /* minimum number of free TX descriptors required to wake up TX process */
 128 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 129
 130 /* number of ETHTOOL_GSTATS u64's */
 131 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 132
 133 #define TG3_NUM_TEST            6
 134
 135 static char version[] __devinitdata =
 136         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 137
 138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_MODULE_VERSION);
 142
 143 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 144 module_param(tg3_debug, int, 0);
 145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 146
 147 static struct pci_device_id tg3_pci_tbl[] = {
 148         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 208         {}
 209 };
 210
 211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 212
 213 static const struct {
 214         const char string[ETH_GSTRING_LEN];
 215 } ethtool_stats_keys[TG3_NUM_STATS] = {
 216         { "rx_octets" },
 217         { "rx_fragments" },
 218         { "rx_ucast_packets" },
 219         { "rx_mcast_packets" },
 220         { "rx_bcast_packets" },
 221         { "rx_fcs_errors" },
 222         { "rx_align_errors" },
 223         { "rx_xon_pause_rcvd" },
 224         { "rx_xoff_pause_rcvd" },
 225         { "rx_mac_ctrl_rcvd" },
 226         { "rx_xoff_entered" },
 227         { "rx_frame_too_long_errors" },
 228         { "rx_jabbers" },
 229         { "rx_undersize_packets" },
 230         { "rx_in_length_errors" },
 231         { "rx_out_length_errors" },
 232         { "rx_64_or_less_octet_packets" },
 233         { "rx_65_to_127_octet_packets" },
 234         { "rx_128_to_255_octet_packets" },
 235         { "rx_256_to_511_octet_packets" },
 236         { "rx_512_to_1023_octet_packets" },
 237         { "rx_1024_to_1522_octet_packets" },
 238         { "rx_1523_to_2047_octet_packets" },
 239         { "rx_2048_to_4095_octet_packets" },
 240         { "rx_4096_to_8191_octet_packets" },
 241         { "rx_8192_to_9022_octet_packets" },
 242
 243         { "tx_octets" },
 244         { "tx_collisions" },
 245
 246         { "tx_xon_sent" },
 247         { "tx_xoff_sent" },
 248         { "tx_flow_control" },
 249         { "tx_mac_errors" },
 250         { "tx_single_collisions" },
 251         { "tx_mult_collisions" },
 252         { "tx_deferred" },
 253         { "tx_excessive_collisions" },
 254         { "tx_late_collisions" },
 255         { "tx_collide_2times" },
 256         { "tx_collide_3times" },
 257         { "tx_collide_4times" },
 258         { "tx_collide_5times" },
 259         { "tx_collide_6times" },
 260         { "tx_collide_7times" },
 261         { "tx_collide_8times" },
 262         { "tx_collide_9times" },
 263         { "tx_collide_10times" },
 264         { "tx_collide_11times" },
 265         { "tx_collide_12times" },
 266         { "tx_collide_13times" },
 267         { "tx_collide_14times" },
 268         { "tx_collide_15times" },
 269         { "tx_ucast_packets" },
 270         { "tx_mcast_packets" },
 271         { "tx_bcast_packets" },
 272         { "tx_carrier_sense_errors" },
 273         { "tx_discards" },
 274         { "tx_errors" },
 275
 276         { "dma_writeq_full" },
 277         { "dma_write_prioq_full" },
 278         { "rxbds_empty" },
 279         { "rx_discards" },
 280         { "rx_errors" },
 281         { "rx_threshold_hit" },
 282
 283         { "dma_readq_full" },
 284         { "dma_read_prioq_full" },
 285         { "tx_comp_queue_full" },
 286
 287         { "ring_set_send_prod_index" },
 288         { "ring_status_update" },
 289         { "nic_irqs" },
 290         { "nic_avoided_irqs" },
 291         { "nic_tx_threshold_hit" }
 292 };
 293
 294 static const struct {
 295         const char string[ETH_GSTRING_LEN];
 296 } ethtool_test_keys[TG3_NUM_TEST] = {
 297         { "nvram test     (online) " },
 298         { "link test      (online) " },
 299         { "register test  (offline)" },
 300         { "memory test    (offline)" },
 301         { "loopback test  (offline)" },
 302         { "interrupt test (offline)" },
 303 };
 304
 305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 306 {
 307         writel(val, tp->regs + off);
 308 }
 309
 310 static u32 tg3_read32(struct tg3 *tp, u32 off)
 311 {
 312         return (readl(tp->regs + off));
 313 }
 314
 315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 316 {
 317         unsigned long flags;
 318
 319         spin_lock_irqsave(&tp->indirect_lock, flags);
 320         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 321         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 322         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 323 }
 324
 325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 326 {
 327         writel(val, tp->regs + off);
 328         readl(tp->regs + off);
 329 }
 330
 331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 332 {
 333         unsigned long flags;
 334         u32 val;
 335
 336         spin_lock_irqsave(&tp->indirect_lock, flags);
 337         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 338         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 339         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 340         return val;
 341 }
 342
 343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 344 {
 345         unsigned long flags;
 346
 347         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 348                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 349                                        TG3_64BIT_REG_LOW, val);
 350                 return;
 351         }
 352         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 353                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 354                                        TG3_64BIT_REG_LOW, val);
 355                 return;
 356         }
 357
 358         spin_lock_irqsave(&tp->indirect_lock, flags);
 359         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 360         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 361         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 362
 363         /* In indirect mode when disabling interrupts, we also need
 364          * to clear the interrupt bit in the GRC local ctrl register.
 365          */
 366         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 367             (val == 0x1)) {
 368                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 369                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 370         }
 371 }
 372
 373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 374 {
 375         unsigned long flags;
 376         u32 val;
 377
 378         spin_lock_irqsave(&tp->indirect_lock, flags);
 379         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 380         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 381         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 382         return val;
 383 }
 384
 385 /* usec_wait specifies the wait time in usec when writing to certain registers
 386  * where it is unsafe to read back the register without some delay.
 387  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 388  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 389  */
 390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 391 {
 392         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 393             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 394                 /* Non-posted methods */
 395                 tp->write32(tp, off, val);
 396         else {
 397                 /* Posted method */
 398                 tg3_write32(tp, off, val);
 399                 if (usec_wait)
 400                         udelay(usec_wait);
 401                 tp->read32(tp, off);
 402         }
 403         /* Wait again after the read for the posted method to guarantee that
 404          * the wait time is met.
 405          */
 406         if (usec_wait)
 407                 udelay(usec_wait);
 408 }
 409
 410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 411 {
 412         tp->write32_mbox(tp, off, val);
 413         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 414             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 415                 tp->read32_mbox(tp, off);
 416 }
 417
 418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 419 {
 420         void __iomem *mbox = tp->regs + off;
 421         writel(val, mbox);
 422         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 423                 writel(val, mbox);
 424         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 425                 readl(mbox);
 426 }
 427
 428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 429 {
 430         return (readl(tp->regs + off + GRCMBOX_BASE));
 431 }
 432
 433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 434 {
 435         writel(val, tp->regs + off + GRCMBOX_BASE);
 436 }
 437
 438 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 439 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 440 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 441 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 442 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 443
 444 #define tw32(reg,val)           tp->write32(tp, reg, val)
 445 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 447 #define tr32(reg)               tp->read32(tp, reg)
 448
 449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 450 {
 451         unsigned long flags;
 452
 453         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 454             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 455                 return;
 456
 457         spin_lock_irqsave(&tp->indirect_lock, flags);
 458         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 459                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 460                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 461
 462                 /* Always leave this as zero. */
 463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 464         } else {
 465                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 466                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 467
 468                 /* Always leave this as zero. */
 469                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 470         }
 471         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 472 }
 473
 474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 475 {
 476         unsigned long flags;
 477
 478         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 479             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 480                 *val = 0;
 481                 return;
 482         }
 483
 484         spin_lock_irqsave(&tp->indirect_lock, flags);
 485         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 486                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 487                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 488
 489                 /* Always leave this as zero. */
 490                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 491         } else {
 492                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 493                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 494
 495                 /* Always leave this as zero. */
 496                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 497         }
 498         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 499 }
 500
 501 static void tg3_disable_ints(struct tg3 *tp)
 502 {
 503         tw32(TG3PCI_MISC_HOST_CTRL,
 504              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 505         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 506 }
 507
 508 static inline void tg3_cond_int(struct tg3 *tp)
 509 {
 510         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 511             (tp->hw_status->status & SD_STATUS_UPDATED))
 512                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 513         else
 514                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 515                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 516 }
 517
 518 static void tg3_enable_ints(struct tg3 *tp)
 519 {
 520         tp->irq_sync = 0;
 521         wmb();
 522
 523         tw32(TG3PCI_MISC_HOST_CTRL,
 524              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 525         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 526                        (tp->last_tag << 24));
 527         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 528                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 529                                (tp->last_tag << 24));
 530         tg3_cond_int(tp);
 531 }
 532
 533 static inline unsigned int tg3_has_work(struct tg3 *tp)
 534 {
 535         struct tg3_hw_status *sblk = tp->hw_status;
 536         unsigned int work_exists = 0;
 537
 538         /* check for phy events */
 539         if (!(tp->tg3_flags &
 540               (TG3_FLAG_USE_LINKCHG_REG |
 541                TG3_FLAG_POLL_SERDES))) {
 542                 if (sblk->status & SD_STATUS_LINK_CHG)
 543                         work_exists = 1;
 544         }
 545         /* check for RX/TX work to do */
 546         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 547             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 548                 work_exists = 1;
 549
 550         return work_exists;
 551 }
 552
 553 /* tg3_restart_ints
 554  *  similar to tg3_enable_ints, but it accurately determines whether there
 555  *  is new work pending and can return without flushing the PIO write
 556  *  which reenables interrupts
 557  */
 558 static void tg3_restart_ints(struct tg3 *tp)
 559 {
 560         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 561                      tp->last_tag << 24);
 562         mmiowb();
 563
 564         /* When doing tagged status, this work check is unnecessary.
 565          * The last_tag we write above tells the chip which piece of
 566          * work we've completed.
 567          */
 568         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 569             tg3_has_work(tp))
 570                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 571                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 572 }
 573
 574 static inline void tg3_netif_stop(struct tg3 *tp)
 575 {
 576         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 577         netif_poll_disable(tp->dev);
 578         netif_tx_disable(tp->dev);
 579 }
 580
 581 static inline void tg3_netif_start(struct tg3 *tp)
 582 {
 583         netif_wake_queue(tp->dev);
 584         /* NOTE: unconditional netif_wake_queue is only appropriate
 585          * so long as all callers are assured to have free tx slots
 586          * (such as after tg3_init_hw)
 587          */
 588         netif_poll_enable(tp->dev);
 589         tp->hw_status->status |= SD_STATUS_UPDATED;
 590         tg3_enable_ints(tp);
 591 }
 592
 593 static void tg3_switch_clocks(struct tg3 *tp)
 594 {
 595         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 596         u32 orig_clock_ctrl;
 597
 598         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 599                 return;
 600
 601         orig_clock_ctrl = clock_ctrl;
 602         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 603                        CLOCK_CTRL_CLKRUN_OENABLE |
 604                        0x1f);
 605         tp->pci_clock_ctrl = clock_ctrl;
 606
 607         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 608                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 609                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 610                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 611                 }
 612         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 613                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 614                             clock_ctrl |
 615                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 616                             40);
 617                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 618                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 619                             40);
 620         }
 621         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 622 }
 623
 624 #define PHY_BUSY_LOOPS  5000
 625
 626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 627 {
 628         u32 frame_val;
 629         unsigned int loops;
 630         int ret;
 631
 632         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 633                 tw32_f(MAC_MI_MODE,
 634                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 635                 udelay(80);
 636         }
 637
 638         *val = 0x0;
 639
 640         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 641                       MI_COM_PHY_ADDR_MASK);
 642         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 643                       MI_COM_REG_ADDR_MASK);
 644         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 645
 646         tw32_f(MAC_MI_COM, frame_val);
 647
 648         loops = PHY_BUSY_LOOPS;
 649         while (loops != 0) {
 650                 udelay(10);
 651                 frame_val = tr32(MAC_MI_COM);
 652
 653                 if ((frame_val & MI_COM_BUSY) == 0) {
 654                         udelay(5);
 655                         frame_val = tr32(MAC_MI_COM);
 656                         break;
 657                 }
 658                 loops -= 1;
 659         }
 660
 661         ret = -EBUSY;
 662         if (loops != 0) {
 663                 *val = frame_val & MI_COM_DATA_MASK;
 664                 ret = 0;
 665         }
 666
 667         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 668                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 669                 udelay(80);
 670         }
 671
 672         return ret;
 673 }
 674
 675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 676 {
 677         u32 frame_val;
 678         unsigned int loops;
 679         int ret;
 680
 681         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 682             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 683                 return 0;
 684
 685         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 686                 tw32_f(MAC_MI_MODE,
 687                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 688                 udelay(80);
 689         }
 690
 691         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 692                       MI_COM_PHY_ADDR_MASK);
 693         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 694                       MI_COM_REG_ADDR_MASK);
 695         frame_val |= (val & MI_COM_DATA_MASK);
 696         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 697
 698         tw32_f(MAC_MI_COM, frame_val);
 699
 700         loops = PHY_BUSY_LOOPS;
 701         while (loops != 0) {
 702                 udelay(10);
 703                 frame_val = tr32(MAC_MI_COM);
 704                 if ((frame_val & MI_COM_BUSY) == 0) {
 705                         udelay(5);
 706                         frame_val = tr32(MAC_MI_COM);
 707                         break;
 708                 }
 709                 loops -= 1;
 710         }
 711
 712         ret = -EBUSY;
 713         if (loops != 0)
 714                 ret = 0;
 715
 716         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 717                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 718                 udelay(80);
 719         }
 720
 721         return ret;
 722 }
 723
 724 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 725 {
 726         u32 val;
 727
 728         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 729                 return;
 730
 731         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 732             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 733                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 734                              (val | (1 << 15) | (1 << 4)));
 735 }
 736
 737 static int tg3_bmcr_reset(struct tg3 *tp)
 738 {
 739         u32 phy_control;
 740         int limit, err;
 741
 742         /* OK, reset it, and poll the BMCR_RESET bit until it
 743          * clears or we time out.
 744          */
 745         phy_control = BMCR_RESET;
 746         err = tg3_writephy(tp, MII_BMCR, phy_control);
 747         if (err != 0)
 748                 return -EBUSY;
 749
 750         limit = 5000;
 751         while (limit--) {
 752                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 753                 if (err != 0)
 754                         return -EBUSY;
 755
 756                 if ((phy_control & BMCR_RESET) == 0) {
 757                         udelay(40);
 758                         break;
 759                 }
 760                 udelay(10);
 761         }
 762         if (limit <= 0)
 763                 return -EBUSY;
 764
 765         return 0;
 766 }
 767
 768 static int tg3_wait_macro_done(struct tg3 *tp)
 769 {
 770         int limit = 100;
 771
 772         while (limit--) {
 773                 u32 tmp32;
 774
 775                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 776                         if ((tmp32 & 0x1000) == 0)
 777                                 break;
 778                 }
 779         }
 780         if (limit <= 0)
 781                 return -EBUSY;
 782
 783         return 0;
 784 }
 785
 786 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 787 {
 788         static const u32 test_pat[4][6] = {
 789         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 790         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 791         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 792         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 793         };
 794         int chan;
 795
 796         for (chan = 0; chan < 4; chan++) {
 797                 int i;
 798
 799                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 800                              (chan * 0x2000) | 0x0200);
 801                 tg3_writephy(tp, 0x16, 0x0002);
 802
 803                 for (i = 0; i < 6; i++)
 804                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 805                                      test_pat[chan][i]);
 806
 807                 tg3_writephy(tp, 0x16, 0x0202);
 808                 if (tg3_wait_macro_done(tp)) {
 809                         *resetp = 1;
 810                         return -EBUSY;
 811                 }
 812
 813                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 814                              (chan * 0x2000) | 0x0200);
 815                 tg3_writephy(tp, 0x16, 0x0082);
 816                 if (tg3_wait_macro_done(tp)) {
 817                         *resetp = 1;
 818                         return -EBUSY;
 819                 }
 820
 821                 tg3_writephy(tp, 0x16, 0x0802);
 822                 if (tg3_wait_macro_done(tp)) {
 823                         *resetp = 1;
 824                         return -EBUSY;
 825                 }
 826
 827                 for (i = 0; i < 6; i += 2) {
 828                         u32 low, high;
 829
 830                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 831                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 832                             tg3_wait_macro_done(tp)) {
 833                                 *resetp = 1;
 834                                 return -EBUSY;
 835                         }
 836                         low &= 0x7fff;
 837                         high &= 0x000f;
 838                         if (low != test_pat[chan][i] ||
 839                             high != test_pat[chan][i+1]) {
 840                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 841                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 842                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 843
 844                                 return -EBUSY;
 845                         }
 846                 }
 847         }
 848
 849         return 0;
 850 }
 851
 852 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 853 {
 854         int chan;
 855
 856         for (chan = 0; chan < 4; chan++) {
 857                 int i;
 858
 859                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 860                              (chan * 0x2000) | 0x0200);
 861                 tg3_writephy(tp, 0x16, 0x0002);
 862                 for (i = 0; i < 6; i++)
 863                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 864                 tg3_writephy(tp, 0x16, 0x0202);
 865                 if (tg3_wait_macro_done(tp))
 866                         return -EBUSY;
 867         }
 868
 869         return 0;
 870 }
 871
 872 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 873 {
 874         u32 reg32, phy9_orig;
 875         int retries, do_phy_reset, err;
 876
 877         retries = 10;
 878         do_phy_reset = 1;
 879         do {
 880                 if (do_phy_reset) {
 881                         err = tg3_bmcr_reset(tp);
 882                         if (err)
 883                                 return err;
 884                         do_phy_reset = 0;
 885                 }
 886
 887                 /* Disable transmitter and interrupt.  */
 888                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 889                         continue;
 890
 891                 reg32 |= 0x3000;
 892                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 893
 894                 /* Set full-duplex, 1000 mbps.  */
 895                 tg3_writephy(tp, MII_BMCR,
 896                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 897
 898                 /* Set to master mode.  */
 899                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 900                         continue;
 901
 902                 tg3_writephy(tp, MII_TG3_CTRL,
 903                              (MII_TG3_CTRL_AS_MASTER |
 904                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 905
 906                 /* Enable SM_DSP_CLOCK and 6dB.  */
 907                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 908
 909                 /* Block the PHY control access.  */
 910                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 911                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 912
 913                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 914                 if (!err)
 915                         break;
 916         } while (--retries);
 917
 918         err = tg3_phy_reset_chanpat(tp);
 919         if (err)
 920                 return err;
 921
 922         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 923         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 924
 925         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 926         tg3_writephy(tp, 0x16, 0x0000);
 927
 928         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 929             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 930                 /* Set Extended packet length bit for jumbo frames */
 931                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 932         }
 933         else {
 934                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 935         }
 936
 937         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 938
 939         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 940                 reg32 &= ~0x3000;
 941                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 942         } else if (!err)
 943                 err = -EBUSY;
 944
 945         return err;
 946 }
 947
 948 static void tg3_link_report(struct tg3 *);
 949
 950 /* This will reset the tigon3 PHY if there is no valid
 951  * link unless the FORCE argument is non-zero.
 952  */
 953 static int tg3_phy_reset(struct tg3 *tp)
 954 {
 955         u32 phy_status;
 956         int err;
 957
 958         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 959                 u32 val;
 960
 961                 val = tr32(GRC_MISC_CFG);
 962                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
 963                 udelay(40);
 964         }
 965         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 966         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 967         if (err != 0)
 968                 return -EBUSY;
 969
 970         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 971                 netif_carrier_off(tp->dev);
 972                 tg3_link_report(tp);
 973         }
 974
 975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 978                 err = tg3_phy_reset_5703_4_5(tp);
 979                 if (err)
 980                         return err;
 981                 goto out;
 982         }
 983
 984         err = tg3_bmcr_reset(tp);
 985         if (err)
 986                 return err;
 987
 988 out:
 989         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 990                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 991                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 992                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 993                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 994                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 996         }
 997         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 998                 tg3_writephy(tp, 0x1c, 0x8d68);
 999                 tg3_writephy(tp, 0x1c, 0x8d68);
1000         }
1001         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010         }
1011         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1014                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016                         tg3_writephy(tp, MII_TG3_TEST1,
1017                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1018                 } else
1019                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1020                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021         }
1022         /* Set Extended packet length bit (bit 14) on all chips that */
1023         /* support jumbo frames */
1024         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025                 /* Cannot do read-modify-write on 5401 */
1026                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1027         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1028                 u32 phy_reg;
1029
1030                 /* Set bit 14 with read-modify-write to preserve other bits */
1031                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034         }
1035
1036         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037          * jumbo frames transmission.
1038          */
1039         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1040                 u32 phy_reg;
1041
1042                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045         }
1046
1047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048                 u32 phy_reg;
1049
1050                 /* adjust output voltage */
1051                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054                         u32 phy_reg2;
1055
1056                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058                         /* Enable auto-MDIX */
1059                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062                 }
1063         }
1064
1065         tg3_phy_set_wirespeed(tp);
1066         return 0;
1067 }
1068
1069 static void tg3_frob_aux_power(struct tg3 *tp)
1070 {
1071         struct tg3 *tp_peer = tp;
1072
1073         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1074                 return;
1075
1076         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078                 struct net_device *dev_peer;
1079
1080                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1081                 /* remove_one() may have been run on the peer. */
1082                 if (!dev_peer)
1083                         tp_peer = tp;
1084                 else
1085                         tp_peer = netdev_priv(dev_peer);
1086         }
1087
1088         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1089             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1092                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1094                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095                                     (GRC_LCLCTRL_GPIO_OE0 |
1096                                      GRC_LCLCTRL_GPIO_OE1 |
1097                                      GRC_LCLCTRL_GPIO_OE2 |
1098                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1099                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1100                                     100);
1101                 } else {
1102                         u32 no_gpio2;
1103                         u32 grc_local_ctrl = 0;
1104
1105                         if (tp_peer != tp &&
1106                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107                                 return;
1108
1109                         /* Workaround to prevent overdrawing Amps. */
1110                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111                             ASIC_REV_5714) {
1112                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1113                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114                                             grc_local_ctrl, 100);
1115                         }
1116
1117                         /* On 5753 and variants, GPIO2 cannot be used. */
1118                         no_gpio2 = tp->nic_sram_data_cfg &
1119                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
1121                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1122                                          GRC_LCLCTRL_GPIO_OE1 |
1123                                          GRC_LCLCTRL_GPIO_OE2 |
1124                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1125                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1126                         if (no_gpio2) {
1127                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1129                         }
1130                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131                                                     grc_local_ctrl, 100);
1132
1133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
1135                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136                                                     grc_local_ctrl, 100);
1137
1138                         if (!no_gpio2) {
1139                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1140                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141                                             grc_local_ctrl, 100);
1142                         }
1143                 }
1144         } else {
1145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147                         if (tp_peer != tp &&
1148                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149                                 return;
1150
1151                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152                                     (GRC_LCLCTRL_GPIO_OE1 |
1153                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1154
1155                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156                                     GRC_LCLCTRL_GPIO_OE1, 100);
1157
1158                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159                                     (GRC_LCLCTRL_GPIO_OE1 |
1160                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1161                 }
1162         }
1163 }
1164
1165 static int tg3_setup_phy(struct tg3 *, int);
1166
1167 #define RESET_KIND_SHUTDOWN     0
1168 #define RESET_KIND_INIT         1
1169 #define RESET_KIND_SUSPEND      2
1170
1171 static void tg3_write_sig_post_reset(struct tg3 *, int);
1172 static int tg3_halt_cpu(struct tg3 *, u32);
1173 static int tg3_nvram_lock(struct tg3 *);
1174 static void tg3_nvram_unlock(struct tg3 *);
1175
1176 static void tg3_power_down_phy(struct tg3 *tp)
1177 {
1178         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1179                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1180                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1181                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1182
1183                         sg_dig_ctrl |=
1184                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1185                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1186                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1187                 }
1188                 return;
1189         }
1190
1191         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1192                 u32 val;
1193
1194                 tg3_bmcr_reset(tp);
1195                 val = tr32(GRC_MISC_CFG);
1196                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1197                 udelay(40);
1198                 return;
1199         } else {
1200                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1201                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1202                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1203         }
1204
1205         /* The PHY should not be powered down on some chips because
1206          * of bugs.
1207          */
1208         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1209             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1210             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1211              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1212                 return;
1213         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1214 }
1215
1216 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1217 {
1218         u32 misc_host_ctrl;
1219         u16 power_control, power_caps;
1220         int pm = tp->pm_cap;
1221
1222         /* Make sure register accesses (indirect or otherwise)
1223          * will function correctly.
1224          */
1225         pci_write_config_dword(tp->pdev,
1226                                TG3PCI_MISC_HOST_CTRL,
1227                                tp->misc_host_ctrl);
1228
1229         pci_read_config_word(tp->pdev,
1230                              pm + PCI_PM_CTRL,
1231                              &power_control);
1232         power_control |= PCI_PM_CTRL_PME_STATUS;
1233         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1234         switch (state) {
1235         case PCI_D0:
1236                 power_control |= 0;
1237                 pci_write_config_word(tp->pdev,
1238                                       pm + PCI_PM_CTRL,
1239                                       power_control);
1240                 udelay(100);    /* Delay after power state change */
1241
1242                 /* Switch out of Vaux if it is a NIC */
1243                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1244                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1245
1246                 return 0;
1247
1248         case PCI_D1:
1249                 power_control |= 1;
1250                 break;
1251
1252         case PCI_D2:
1253                 power_control |= 2;
1254                 break;
1255
1256         case PCI_D3hot:
1257                 power_control |= 3;
1258                 break;
1259
1260         default:
1261                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1262                        "requested.\n",
1263                        tp->dev->name, state);
1264                 return -EINVAL;
1265         };
1266
1267         power_control |= PCI_PM_CTRL_PME_ENABLE;
1268
1269         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1270         tw32(TG3PCI_MISC_HOST_CTRL,
1271              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1272
1273         if (tp->link_config.phy_is_low_power == 0) {
1274                 tp->link_config.phy_is_low_power = 1;
1275                 tp->link_config.orig_speed = tp->link_config.speed;
1276                 tp->link_config.orig_duplex = tp->link_config.duplex;
1277                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1278         }
1279
1280         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1281                 tp->link_config.speed = SPEED_10;
1282                 tp->link_config.duplex = DUPLEX_HALF;
1283                 tp->link_config.autoneg = AUTONEG_ENABLE;
1284                 tg3_setup_phy(tp, 0);
1285         }
1286
1287         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1288                 u32 val;
1289
1290                 val = tr32(GRC_VCPU_EXT_CTRL);
1291                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1292         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1293                 int i;
1294                 u32 val;
1295
1296                 for (i = 0; i < 200; i++) {
1297                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1298                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1299                                 break;
1300                         msleep(1);
1301                 }
1302         }
1303         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1304                                              WOL_DRV_STATE_SHUTDOWN |
1305                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1306
1307         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1308
1309         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1310                 u32 mac_mode;
1311
1312                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1313                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1314                         udelay(40);
1315
1316                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1317                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1318                         else
1319                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1320
1321                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1322                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1323                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1324                 } else {
1325                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1326                 }
1327
1328                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1329                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1330
1331                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1332                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1333                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1334
1335                 tw32_f(MAC_MODE, mac_mode);
1336                 udelay(100);
1337
1338                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1339                 udelay(10);
1340         }
1341
1342         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1343             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1344              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1345                 u32 base_val;
1346
1347                 base_val = tp->pci_clock_ctrl;
1348                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1349                              CLOCK_CTRL_TXCLK_DISABLE);
1350
1351                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1352                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1353         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1354                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1355                 /* do nothing */
1356         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1357                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1358                 u32 newbits1, newbits2;
1359
1360                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1361                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1362                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1363                                     CLOCK_CTRL_TXCLK_DISABLE |
1364                                     CLOCK_CTRL_ALTCLK);
1365                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1366                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1367                         newbits1 = CLOCK_CTRL_625_CORE;
1368                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1369                 } else {
1370                         newbits1 = CLOCK_CTRL_ALTCLK;
1371                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1372                 }
1373
1374                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1375                             40);
1376
1377                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1378                             40);
1379
1380                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1381                         u32 newbits3;
1382
1383                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1384                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1385                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1386                                             CLOCK_CTRL_TXCLK_DISABLE |
1387                                             CLOCK_CTRL_44MHZ_CORE);
1388                         } else {
1389                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1390                         }
1391
1392                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1393                                     tp->pci_clock_ctrl | newbits3, 40);
1394                 }
1395         }
1396
1397         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1398             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1399                 tg3_power_down_phy(tp);
1400
1401         tg3_frob_aux_power(tp);
1402
1403         /* Workaround for unstable PLL clock */
1404         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1405             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1406                 u32 val = tr32(0x7d00);
1407
1408                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1409                 tw32(0x7d00, val);
1410                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1411                         int err;
1412
1413                         err = tg3_nvram_lock(tp);
1414                         tg3_halt_cpu(tp, RX_CPU_BASE);
1415                         if (!err)
1416                                 tg3_nvram_unlock(tp);
1417                 }
1418         }
1419
1420         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1421
1422         /* Finally, set the new power state. */
1423         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1424         udelay(100);    /* Delay after power state change */
1425
1426         return 0;
1427 }
1428
1429 static void tg3_link_report(struct tg3 *tp)
1430 {
1431         if (!netif_carrier_ok(tp->dev)) {
1432                 if (netif_msg_link(tp))
1433                         printk(KERN_INFO PFX "%s: Link is down.\n",
1434                                tp->dev->name);
1435         } else if (netif_msg_link(tp)) {
1436                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1437                        tp->dev->name,
1438                        (tp->link_config.active_speed == SPEED_1000 ?
1439                         1000 :
1440                         (tp->link_config.active_speed == SPEED_100 ?
1441                          100 : 10)),
1442                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1443                         "full" : "half"));
1444
1445                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1446                        "%s for RX.\n",
1447                        tp->dev->name,
1448                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1449                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1450         }
1451 }
1452
1453 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1454 {
1455         u32 new_tg3_flags = 0;
1456         u32 old_rx_mode = tp->rx_mode;
1457         u32 old_tx_mode = tp->tx_mode;
1458
1459         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1460
1461                 /* Convert 1000BaseX flow control bits to 1000BaseT
1462                  * bits before resolving flow control.
1463                  */
1464                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1465                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1466                                        ADVERTISE_PAUSE_ASYM);
1467                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1468
1469                         if (local_adv & ADVERTISE_1000XPAUSE)
1470                                 local_adv |= ADVERTISE_PAUSE_CAP;
1471                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1472                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1473                         if (remote_adv & LPA_1000XPAUSE)
1474                                 remote_adv |= LPA_PAUSE_CAP;
1475                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1476                                 remote_adv |= LPA_PAUSE_ASYM;
1477                 }
1478
1479                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1480                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1481                                 if (remote_adv & LPA_PAUSE_CAP)
1482                                         new_tg3_flags |=
1483                                                 (TG3_FLAG_RX_PAUSE |
1484                                                 TG3_FLAG_TX_PAUSE);
1485                                 else if (remote_adv & LPA_PAUSE_ASYM)
1486                                         new_tg3_flags |=
1487                                                 (TG3_FLAG_RX_PAUSE);
1488                         } else {
1489                                 if (remote_adv & LPA_PAUSE_CAP)
1490                                         new_tg3_flags |=
1491                                                 (TG3_FLAG_RX_PAUSE |
1492                                                 TG3_FLAG_TX_PAUSE);
1493                         }
1494                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1495                         if ((remote_adv & LPA_PAUSE_CAP) &&
1496                         (remote_adv & LPA_PAUSE_ASYM))
1497                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1498                 }
1499
1500                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1501                 tp->tg3_flags |= new_tg3_flags;
1502         } else {
1503                 new_tg3_flags = tp->tg3_flags;
1504         }
1505
1506         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1507                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1508         else
1509                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1510
1511         if (old_rx_mode != tp->rx_mode) {
1512                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1513         }
1514
1515         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1516                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1517         else
1518                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1519
1520         if (old_tx_mode != tp->tx_mode) {
1521                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1522         }
1523 }
1524
1525 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1526 {
1527         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1528         case MII_TG3_AUX_STAT_10HALF:
1529                 *speed = SPEED_10;
1530                 *duplex = DUPLEX_HALF;
1531                 break;
1532
1533         case MII_TG3_AUX_STAT_10FULL:
1534                 *speed = SPEED_10;
1535                 *duplex = DUPLEX_FULL;
1536                 break;
1537
1538         case MII_TG3_AUX_STAT_100HALF:
1539                 *speed = SPEED_100;
1540                 *duplex = DUPLEX_HALF;
1541                 break;
1542
1543         case MII_TG3_AUX_STAT_100FULL:
1544                 *speed = SPEED_100;
1545                 *duplex = DUPLEX_FULL;
1546                 break;
1547
1548         case MII_TG3_AUX_STAT_1000HALF:
1549                 *speed = SPEED_1000;
1550                 *duplex = DUPLEX_HALF;
1551                 break;
1552
1553         case MII_TG3_AUX_STAT_1000FULL:
1554                 *speed = SPEED_1000;
1555                 *duplex = DUPLEX_FULL;
1556                 break;
1557
1558         default:
1559                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1560                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1561                                  SPEED_10;
1562                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1563                                   DUPLEX_HALF;
1564                         break;
1565                 }
1566                 *speed = SPEED_INVALID;
1567                 *duplex = DUPLEX_INVALID;
1568                 break;
1569         };
1570 }
1571
1572 static void tg3_phy_copper_begin(struct tg3 *tp)
1573 {
1574         u32 new_adv;
1575         int i;
1576
1577         if (tp->link_config.phy_is_low_power) {
1578                 /* Entering low power mode.  Disable gigabit and
1579                  * 100baseT advertisements.
1580                  */
1581                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1582
1583                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1584                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1585                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1586                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1587
1588                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1589         } else if (tp->link_config.speed == SPEED_INVALID) {
1590                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1591                         tp->link_config.advertising &=
1592                                 ~(ADVERTISED_1000baseT_Half |
1593                                   ADVERTISED_1000baseT_Full);
1594
1595                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1596                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1597                         new_adv |= ADVERTISE_10HALF;
1598                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1599                         new_adv |= ADVERTISE_10FULL;
1600                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1601                         new_adv |= ADVERTISE_100HALF;
1602                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1603                         new_adv |= ADVERTISE_100FULL;
1604                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1605
1606                 if (tp->link_config.advertising &
1607                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1608                         new_adv = 0;
1609                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1610                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1611                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1612                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1613                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1614                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1615                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1616                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1617                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1618                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1619                 } else {
1620                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1621                 }
1622         } else {
1623                 /* Asking for a specific link mode. */
1624                 if (tp->link_config.speed == SPEED_1000) {
1625                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1626                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1627
1628                         if (tp->link_config.duplex == DUPLEX_FULL)
1629                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1630                         else
1631                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1632                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1633                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1634                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1635                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1636                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1637                 } else {
1638                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1639
1640                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1641                         if (tp->link_config.speed == SPEED_100) {
1642                                 if (tp->link_config.duplex == DUPLEX_FULL)
1643                                         new_adv |= ADVERTISE_100FULL;
1644                                 else
1645                                         new_adv |= ADVERTISE_100HALF;
1646                         } else {
1647                                 if (tp->link_config.duplex == DUPLEX_FULL)
1648                                         new_adv |= ADVERTISE_10FULL;
1649                                 else
1650                                         new_adv |= ADVERTISE_10HALF;
1651                         }
1652                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1653                 }
1654         }
1655
1656         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1657             tp->link_config.speed != SPEED_INVALID) {
1658                 u32 bmcr, orig_bmcr;
1659
1660                 tp->link_config.active_speed = tp->link_config.speed;
1661                 tp->link_config.active_duplex = tp->link_config.duplex;
1662
1663                 bmcr = 0;
1664                 switch (tp->link_config.speed) {
1665                 default:
1666                 case SPEED_10:
1667                         break;
1668
1669                 case SPEED_100:
1670                         bmcr |= BMCR_SPEED100;
1671                         break;
1672
1673                 case SPEED_1000:
1674                         bmcr |= TG3_BMCR_SPEED1000;
1675                         break;
1676                 };
1677
1678                 if (tp->link_config.duplex == DUPLEX_FULL)
1679                         bmcr |= BMCR_FULLDPLX;
1680
1681                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1682                     (bmcr != orig_bmcr)) {
1683                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1684                         for (i = 0; i < 1500; i++) {
1685                                 u32 tmp;
1686
1687                                 udelay(10);
1688                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1689                                     tg3_readphy(tp, MII_BMSR, &tmp))
1690                                         continue;
1691                                 if (!(tmp & BMSR_LSTATUS)) {
1692                                         udelay(40);
1693                                         break;
1694                                 }
1695                         }
1696                         tg3_writephy(tp, MII_BMCR, bmcr);
1697                         udelay(40);
1698                 }
1699         } else {
1700                 tg3_writephy(tp, MII_BMCR,
1701                              BMCR_ANENABLE | BMCR_ANRESTART);
1702         }
1703 }
1704
1705 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1706 {
1707         int err;
1708
1709         /* Turn off tap power management. */
1710         /* Set Extended packet length bit */
1711         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1712
1713         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1714         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1715
1716         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1717         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1718
1719         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1720         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1721
1722         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1723         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1724
1725         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1726         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1727
1728         udelay(40);
1729
1730         return err;
1731 }
1732
1733 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1734 {
1735         u32 adv_reg, all_mask = 0;
1736
1737         if (mask & ADVERTISED_10baseT_Half)
1738                 all_mask |= ADVERTISE_10HALF;
1739         if (mask & ADVERTISED_10baseT_Full)
1740                 all_mask |= ADVERTISE_10FULL;
1741         if (mask & ADVERTISED_100baseT_Half)
1742                 all_mask |= ADVERTISE_100HALF;
1743         if (mask & ADVERTISED_100baseT_Full)
1744                 all_mask |= ADVERTISE_100FULL;
1745
1746         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1747                 return 0;
1748
1749         if ((adv_reg & all_mask) != all_mask)
1750                 return 0;
1751         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1752                 u32 tg3_ctrl;
1753
1754                 all_mask = 0;
1755                 if (mask & ADVERTISED_1000baseT_Half)
1756                         all_mask |= ADVERTISE_1000HALF;
1757                 if (mask & ADVERTISED_1000baseT_Full)
1758                         all_mask |= ADVERTISE_1000FULL;
1759
1760                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1761                         return 0;
1762
1763                 if ((tg3_ctrl & all_mask) != all_mask)
1764                         return 0;
1765         }
1766         return 1;
1767 }
1768
1769 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1770 {
1771         int current_link_up;
1772         u32 bmsr, dummy;
1773         u16 current_speed;
1774         u8 current_duplex;
1775         int i, err;
1776
1777         tw32(MAC_EVENT, 0);
1778
1779         tw32_f(MAC_STATUS,
1780              (MAC_STATUS_SYNC_CHANGED |
1781               MAC_STATUS_CFG_CHANGED |
1782               MAC_STATUS_MI_COMPLETION |
1783               MAC_STATUS_LNKSTATE_CHANGED));
1784         udelay(40);
1785
1786         tp->mi_mode = MAC_MI_MODE_BASE;
1787         tw32_f(MAC_MI_MODE, tp->mi_mode);
1788         udelay(80);
1789
1790         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1791
1792         /* Some third-party PHYs need to be reset on link going
1793          * down.
1794          */
1795         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1796              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1797              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1798             netif_carrier_ok(tp->dev)) {
1799                 tg3_readphy(tp, MII_BMSR, &bmsr);
1800                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1801                     !(bmsr & BMSR_LSTATUS))
1802                         force_reset = 1;
1803         }
1804         if (force_reset)
1805                 tg3_phy_reset(tp);
1806
1807         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1808                 tg3_readphy(tp, MII_BMSR, &bmsr);
1809                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1810                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1811                         bmsr = 0;
1812
1813                 if (!(bmsr & BMSR_LSTATUS)) {
1814                         err = tg3_init_5401phy_dsp(tp);
1815                         if (err)
1816                                 return err;
1817
1818                         tg3_readphy(tp, MII_BMSR, &bmsr);
1819                         for (i = 0; i < 1000; i++) {
1820                                 udelay(10);
1821                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1822                                     (bmsr & BMSR_LSTATUS)) {
1823                                         udelay(40);
1824                                         break;
1825                                 }
1826                         }
1827
1828                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1829                             !(bmsr & BMSR_LSTATUS) &&
1830                             tp->link_config.active_speed == SPEED_1000) {
1831                                 err = tg3_phy_reset(tp);
1832                                 if (!err)
1833                                         err = tg3_init_5401phy_dsp(tp);
1834                                 if (err)
1835                                         return err;
1836                         }
1837                 }
1838         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1839                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1840                 /* 5701 {A0,B0} CRC bug workaround */
1841                 tg3_writephy(tp, 0x15, 0x0a75);
1842                 tg3_writephy(tp, 0x1c, 0x8c68);
1843                 tg3_writephy(tp, 0x1c, 0x8d68);
1844                 tg3_writephy(tp, 0x1c, 0x8c68);
1845         }
1846
1847         /* Clear pending interrupts... */
1848         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1849         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1850
1851         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1852                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1853         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1854                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1855
1856         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1857             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1858                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1859                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1860                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1861                 else
1862                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1863         }
1864
1865         current_link_up = 0;
1866         current_speed = SPEED_INVALID;
1867         current_duplex = DUPLEX_INVALID;
1868
1869         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1870                 u32 val;
1871
1872                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1873                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1874                 if (!(val & (1 << 10))) {
1875                         val |= (1 << 10);
1876                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1877                         goto relink;
1878                 }
1879         }
1880
1881         bmsr = 0;
1882         for (i = 0; i < 100; i++) {
1883                 tg3_readphy(tp, MII_BMSR, &bmsr);
1884                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1885                     (bmsr & BMSR_LSTATUS))
1886                         break;
1887                 udelay(40);
1888         }
1889
1890         if (bmsr & BMSR_LSTATUS) {
1891                 u32 aux_stat, bmcr;
1892
1893                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1894                 for (i = 0; i < 2000; i++) {
1895                         udelay(10);
1896                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1897                             aux_stat)
1898                                 break;
1899                 }
1900
1901                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1902                                              &current_speed,
1903                                              &current_duplex);
1904
1905                 bmcr = 0;
1906                 for (i = 0; i < 200; i++) {
1907                         tg3_readphy(tp, MII_BMCR, &bmcr);
1908                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1909                                 continue;
1910                         if (bmcr && bmcr != 0x7fff)
1911                                 break;
1912                         udelay(10);
1913                 }
1914
1915                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1916                         if (bmcr & BMCR_ANENABLE) {
1917                                 current_link_up = 1;
1918
1919                                 /* Force autoneg restart if we are exiting
1920                                  * low power mode.
1921                                  */
1922                                 if (!tg3_copper_is_advertising_all(tp,
1923                                                 tp->link_config.advertising))
1924                                         current_link_up = 0;
1925                         } else {
1926                                 current_link_up = 0;
1927                         }
1928                 } else {
1929                         if (!(bmcr & BMCR_ANENABLE) &&
1930                             tp->link_config.speed == current_speed &&
1931                             tp->link_config.duplex == current_duplex) {
1932                                 current_link_up = 1;
1933                         } else {
1934                                 current_link_up = 0;
1935                         }
1936                 }
1937
1938                 tp->link_config.active_speed = current_speed;
1939                 tp->link_config.active_duplex = current_duplex;
1940         }
1941
1942         if (current_link_up == 1 &&
1943             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1944             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1945                 u32 local_adv, remote_adv;
1946
1947                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1948                         local_adv = 0;
1949                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1950
1951                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1952                         remote_adv = 0;
1953
1954                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1955
1956                 /* If we are not advertising full pause capability,
1957                  * something is wrong.  Bring the link down and reconfigure.
1958                  */
1959                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1960                         current_link_up = 0;
1961                 } else {
1962                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1963                 }
1964         }
1965 relink:
1966         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1967                 u32 tmp;
1968
1969                 tg3_phy_copper_begin(tp);
1970
1971                 tg3_readphy(tp, MII_BMSR, &tmp);
1972                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1973                     (tmp & BMSR_LSTATUS))
1974                         current_link_up = 1;
1975         }
1976
1977         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1978         if (current_link_up == 1) {
1979                 if (tp->link_config.active_speed == SPEED_100 ||
1980                     tp->link_config.active_speed == SPEED_10)
1981                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1982                 else
1983                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1984         } else
1985                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1986
1987         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1988         if (tp->link_config.active_duplex == DUPLEX_HALF)
1989                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1990
1991         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1993                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1994                     (current_link_up == 1 &&
1995                      tp->link_config.active_speed == SPEED_10))
1996                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1997         } else {
1998                 if (current_link_up == 1)
1999                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2000         }
2001
2002         /* ??? Without this setting Netgear GA302T PHY does not
2003          * ??? send/receive packets...
2004          */
2005         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2006             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2007                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2008                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2009                 udelay(80);
2010         }
2011
2012         tw32_f(MAC_MODE, tp->mac_mode);
2013         udelay(40);
2014
2015         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2016                 /* Polled via timer. */
2017                 tw32_f(MAC_EVENT, 0);
2018         } else {
2019                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2020         }
2021         udelay(40);
2022
2023         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2024             current_link_up == 1 &&
2025             tp->link_config.active_speed == SPEED_1000 &&
2026             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2027              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2028                 udelay(120);
2029                 tw32_f(MAC_STATUS,
2030                      (MAC_STATUS_SYNC_CHANGED |
2031                       MAC_STATUS_CFG_CHANGED));
2032                 udelay(40);
2033                 tg3_write_mem(tp,
2034                               NIC_SRAM_FIRMWARE_MBOX,
2035                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2036         }
2037
2038         if (current_link_up != netif_carrier_ok(tp->dev)) {
2039                 if (current_link_up)
2040                         netif_carrier_on(tp->dev);
2041                 else
2042                         netif_carrier_off(tp->dev);
2043                 tg3_link_report(tp);
2044         }
2045
2046         return 0;
2047 }
2048
2049 struct tg3_fiber_aneginfo {
2050         int state;
2051 #define ANEG_STATE_UNKNOWN              0
2052 #define ANEG_STATE_AN_ENABLE            1
2053 #define ANEG_STATE_RESTART_INIT         2
2054 #define ANEG_STATE_RESTART              3
2055 #define ANEG_STATE_DISABLE_LINK_OK      4
2056 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2057 #define ANEG_STATE_ABILITY_DETECT       6
2058 #define ANEG_STATE_ACK_DETECT_INIT      7
2059 #define ANEG_STATE_ACK_DETECT           8
2060 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2061 #define ANEG_STATE_COMPLETE_ACK         10
2062 #define ANEG_STATE_IDLE_DETECT_INIT     11
2063 #define ANEG_STATE_IDLE_DETECT          12
2064 #define ANEG_STATE_LINK_OK              13
2065 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2066 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2067
2068         u32 flags;
2069 #define MR_AN_ENABLE            0x00000001
2070 #define MR_RESTART_AN           0x00000002
2071 #define MR_AN_COMPLETE          0x00000004
2072 #define MR_PAGE_RX              0x00000008
2073 #define MR_NP_LOADED            0x00000010
2074 #define MR_TOGGLE_TX            0x00000020
2075 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2076 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2077 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2078 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2079 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2080 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2081 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2082 #define MR_TOGGLE_RX            0x00002000
2083 #define MR_NP_RX                0x00004000
2084
2085 #define MR_LINK_OK              0x80000000
2086
2087         unsigned long link_time, cur_time;
2088
2089         u32 ability_match_cfg;
2090         int ability_match_count;
2091
2092         char ability_match, idle_match, ack_match;
2093
2094         u32 txconfig, rxconfig;
2095 #define ANEG_CFG_NP             0x00000080
2096 #define ANEG_CFG_ACK            0x00000040
2097 #define ANEG_CFG_RF2            0x00000020
2098 #define ANEG_CFG_RF1            0x00000010
2099 #define ANEG_CFG_PS2            0x00000001
2100 #define ANEG_CFG_PS1            0x00008000
2101 #define ANEG_CFG_HD             0x00004000
2102 #define ANEG_CFG_FD             0x00002000
2103 #define ANEG_CFG_INVAL          0x00001f06
2104
2105 };
2106 #define ANEG_OK         0
2107 #define ANEG_DONE       1
2108 #define ANEG_TIMER_ENAB 2
2109 #define ANEG_FAILED     -1
2110
2111 #define ANEG_STATE_SETTLE_TIME  10000
2112
2113 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2114                                    struct tg3_fiber_aneginfo *ap)
2115 {
2116         unsigned long delta;
2117         u32 rx_cfg_reg;
2118         int ret;
2119
2120         if (ap->state == ANEG_STATE_UNKNOWN) {
2121                 ap->rxconfig = 0;
2122                 ap->link_time = 0;
2123                 ap->cur_time = 0;
2124                 ap->ability_match_cfg = 0;
2125                 ap->ability_match_count = 0;
2126                 ap->ability_match = 0;
2127                 ap->idle_match = 0;
2128                 ap->ack_match = 0;
2129         }
2130         ap->cur_time++;
2131
2132         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2133                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2134
2135                 if (rx_cfg_reg != ap->ability_match_cfg) {
2136                         ap->ability_match_cfg = rx_cfg_reg;
2137                         ap->ability_match = 0;
2138                         ap->ability_match_count = 0;
2139                 } else {
2140                         if (++ap->ability_match_count > 1) {
2141                                 ap->ability_match = 1;
2142                                 ap->ability_match_cfg = rx_cfg_reg;
2143                         }
2144                 }
2145                 if (rx_cfg_reg & ANEG_CFG_ACK)
2146                         ap->ack_match = 1;
2147                 else
2148                         ap->ack_match = 0;
2149
2150                 ap->idle_match = 0;
2151         } else {
2152                 ap->idle_match = 1;
2153                 ap->ability_match_cfg = 0;
2154                 ap->ability_match_count = 0;
2155                 ap->ability_match = 0;
2156                 ap->ack_match = 0;
2157
2158                 rx_cfg_reg = 0;
2159         }
2160
2161         ap->rxconfig = rx_cfg_reg;
2162         ret = ANEG_OK;
2163
2164         switch(ap->state) {
2165         case ANEG_STATE_UNKNOWN:
2166                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2167                         ap->state = ANEG_STATE_AN_ENABLE;
2168
2169                 /* fallthru */
2170         case ANEG_STATE_AN_ENABLE:
2171                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2172                 if (ap->flags & MR_AN_ENABLE) {
2173                         ap->link_time = 0;
2174                         ap->cur_time = 0;
2175                         ap->ability_match_cfg = 0;
2176                         ap->ability_match_count = 0;
2177                         ap->ability_match = 0;
2178                         ap->idle_match = 0;
2179                         ap->ack_match = 0;
2180
2181                         ap->state = ANEG_STATE_RESTART_INIT;
2182                 } else {
2183                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2184                 }
2185                 break;
2186
2187         case ANEG_STATE_RESTART_INIT:
2188                 ap->link_time = ap->cur_time;
2189                 ap->flags &= ~(MR_NP_LOADED);
2190                 ap->txconfig = 0;
2191                 tw32(MAC_TX_AUTO_NEG, 0);
2192                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2193                 tw32_f(MAC_MODE, tp->mac_mode);
2194                 udelay(40);
2195
2196                 ret = ANEG_TIMER_ENAB;
2197                 ap->state = ANEG_STATE_RESTART;
2198
2199                 /* fallthru */
2200         case ANEG_STATE_RESTART:
2201                 delta = ap->cur_time - ap->link_time;
2202                 if (delta > ANEG_STATE_SETTLE_TIME) {
2203                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2204                 } else {
2205                         ret = ANEG_TIMER_ENAB;
2206                 }
2207                 break;
2208
2209         case ANEG_STATE_DISABLE_LINK_OK:
2210                 ret = ANEG_DONE;
2211                 break;
2212
2213         case ANEG_STATE_ABILITY_DETECT_INIT:
2214                 ap->flags &= ~(MR_TOGGLE_TX);
2215                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2216                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2217                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2218                 tw32_f(MAC_MODE, tp->mac_mode);
2219                 udelay(40);
2220
2221                 ap->state = ANEG_STATE_ABILITY_DETECT;
2222                 break;
2223
2224         case ANEG_STATE_ABILITY_DETECT:
2225                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2226                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2227                 }
2228                 break;
2229
2230         case ANEG_STATE_ACK_DETECT_INIT:
2231                 ap->txconfig |= ANEG_CFG_ACK;
2232                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2233                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2234                 tw32_f(MAC_MODE, tp->mac_mode);
2235                 udelay(40);
2236
2237                 ap->state = ANEG_STATE_ACK_DETECT;
2238
2239                 /* fallthru */
2240         case ANEG_STATE_ACK_DETECT:
2241                 if (ap->ack_match != 0) {
2242                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2243                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2244                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2245                         } else {
2246                                 ap->state = ANEG_STATE_AN_ENABLE;
2247                         }
2248                 } else if (ap->ability_match != 0 &&
2249                            ap->rxconfig == 0) {
2250                         ap->state = ANEG_STATE_AN_ENABLE;
2251                 }
2252                 break;
2253
2254         case ANEG_STATE_COMPLETE_ACK_INIT:
2255                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2256                         ret = ANEG_FAILED;
2257                         break;
2258                 }
2259                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2260                                MR_LP_ADV_HALF_DUPLEX |
2261                                MR_LP_ADV_SYM_PAUSE |
2262                                MR_LP_ADV_ASYM_PAUSE |
2263                                MR_LP_ADV_REMOTE_FAULT1 |
2264                                MR_LP_ADV_REMOTE_FAULT2 |
2265                                MR_LP_ADV_NEXT_PAGE |
2266                                MR_TOGGLE_RX |
2267                                MR_NP_RX);
2268                 if (ap->rxconfig & ANEG_CFG_FD)
2269                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2270                 if (ap->rxconfig & ANEG_CFG_HD)
2271                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2272                 if (ap->rxconfig & ANEG_CFG_PS1)
2273                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2274                 if (ap->rxconfig & ANEG_CFG_PS2)
2275                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2276                 if (ap->rxconfig & ANEG_CFG_RF1)
2277                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2278                 if (ap->rxconfig & ANEG_CFG_RF2)
2279                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2280                 if (ap->rxconfig & ANEG_CFG_NP)
2281                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2282
2283                 ap->link_time = ap->cur_time;
2284
2285                 ap->flags ^= (MR_TOGGLE_TX);
2286                 if (ap->rxconfig & 0x0008)
2287                         ap->flags |= MR_TOGGLE_RX;
2288                 if (ap->rxconfig & ANEG_CFG_NP)
2289                         ap->flags |= MR_NP_RX;
2290                 ap->flags |= MR_PAGE_RX;
2291
2292                 ap->state = ANEG_STATE_COMPLETE_ACK;
2293                 ret = ANEG_TIMER_ENAB;
2294                 break;
2295
2296         case ANEG_STATE_COMPLETE_ACK:
2297                 if (ap->ability_match != 0 &&
2298                     ap->rxconfig == 0) {
2299                         ap->state = ANEG_STATE_AN_ENABLE;
2300                         break;
2301                 }
2302                 delta = ap->cur_time - ap->link_time;
2303                 if (delta > ANEG_STATE_SETTLE_TIME) {
2304                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2305                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2306                         } else {
2307                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2308                                     !(ap->flags & MR_NP_RX)) {
2309                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2310                                 } else {
2311                                         ret = ANEG_FAILED;
2312                                 }
2313                         }
2314                 }
2315                 break;
2316
2317         case ANEG_STATE_IDLE_DETECT_INIT:
2318                 ap->link_time = ap->cur_time;
2319                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2320                 tw32_f(MAC_MODE, tp->mac_mode);
2321                 udelay(40);
2322
2323                 ap->state = ANEG_STATE_IDLE_DETECT;
2324                 ret = ANEG_TIMER_ENAB;
2325                 break;
2326
2327         case ANEG_STATE_IDLE_DETECT:
2328                 if (ap->ability_match != 0 &&
2329                     ap->rxconfig == 0) {
2330                         ap->state = ANEG_STATE_AN_ENABLE;
2331                         break;
2332                 }
2333                 delta = ap->cur_time - ap->link_time;
2334                 if (delta > ANEG_STATE_SETTLE_TIME) {
2335                         /* XXX another gem from the Broadcom driver :( */
2336                         ap->state = ANEG_STATE_LINK_OK;
2337                 }
2338                 break;
2339
2340         case ANEG_STATE_LINK_OK:
2341                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2342                 ret = ANEG_DONE;
2343                 break;
2344
2345         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2346                 /* ??? unimplemented */
2347                 break;
2348
2349         case ANEG_STATE_NEXT_PAGE_WAIT:
2350                 /* ??? unimplemented */
2351                 break;
2352
2353         default:
2354                 ret = ANEG_FAILED;
2355                 break;
2356         };
2357
2358         return ret;
2359 }
2360
2361 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2362 {
2363         int res = 0;
2364         struct tg3_fiber_aneginfo aninfo;
2365         int status = ANEG_FAILED;
2366         unsigned int tick;
2367         u32 tmp;
2368
2369         tw32_f(MAC_TX_AUTO_NEG, 0);
2370
2371         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2372         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2373         udelay(40);
2374
2375         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2376         udelay(40);
2377
2378         memset(&aninfo, 0, sizeof(aninfo));
2379         aninfo.flags |= MR_AN_ENABLE;
2380         aninfo.state = ANEG_STATE_UNKNOWN;
2381         aninfo.cur_time = 0;
2382         tick = 0;
2383         while (++tick < 195000) {
2384                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2385                 if (status == ANEG_DONE || status == ANEG_FAILED)
2386                         break;
2387
2388                 udelay(1);
2389         }
2390
2391         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2392         tw32_f(MAC_MODE, tp->mac_mode);
2393         udelay(40);
2394
2395         *flags = aninfo.flags;
2396
2397         if (status == ANEG_DONE &&
2398             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2399                              MR_LP_ADV_FULL_DUPLEX)))
2400                 res = 1;
2401
2402         return res;
2403 }
2404
2405 static void tg3_init_bcm8002(struct tg3 *tp)
2406 {
2407         u32 mac_status = tr32(MAC_STATUS);
2408         int i;
2409
2410         /* Reset when initting first time or we have a link. */
2411         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2412             !(mac_status & MAC_STATUS_PCS_SYNCED))
2413                 return;
2414
2415         /* Set PLL lock range. */
2416         tg3_writephy(tp, 0x16, 0x8007);
2417
2418         /* SW reset */
2419         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2420
2421         /* Wait for reset to complete. */
2422         /* XXX schedule_timeout() ... */
2423         for (i = 0; i < 500; i++)
2424                 udelay(10);
2425
2426         /* Config mode; select PMA/Ch 1 regs. */
2427         tg3_writephy(tp, 0x10, 0x8411);
2428
2429         /* Enable auto-lock and comdet, select txclk for tx. */
2430         tg3_writephy(tp, 0x11, 0x0a10);
2431
2432         tg3_writephy(tp, 0x18, 0x00a0);
2433         tg3_writephy(tp, 0x16, 0x41ff);
2434
2435         /* Assert and deassert POR. */
2436         tg3_writephy(tp, 0x13, 0x0400);
2437         udelay(40);
2438         tg3_writephy(tp, 0x13, 0x0000);
2439
2440         tg3_writephy(tp, 0x11, 0x0a50);
2441         udelay(40);
2442         tg3_writephy(tp, 0x11, 0x0a10);
2443
2444         /* Wait for signal to stabilize */
2445         /* XXX schedule_timeout() ... */
2446         for (i = 0; i < 15000; i++)
2447                 udelay(10);
2448
2449         /* Deselect the channel register so we can read the PHYID
2450          * later.
2451          */
2452         tg3_writephy(tp, 0x10, 0x8011);
2453 }
2454
2455 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2456 {
2457         u32 sg_dig_ctrl, sg_dig_status;
2458         u32 serdes_cfg, expected_sg_dig_ctrl;
2459         int workaround, port_a;
2460         int current_link_up;
2461
2462         serdes_cfg = 0;
2463         expected_sg_dig_ctrl = 0;
2464         workaround = 0;
2465         port_a = 1;
2466         current_link_up = 0;
2467
2468         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2469             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2470                 workaround = 1;
2471                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2472                         port_a = 0;
2473
2474                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2475                 /* preserve bits 20-23 for voltage regulator */
2476                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2477         }
2478
2479         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2480
2481         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2482                 if (sg_dig_ctrl & (1 << 31)) {
2483                         if (workaround) {
2484                                 u32 val = serdes_cfg;
2485
2486                                 if (port_a)
2487                                         val |= 0xc010000;
2488                                 else
2489                                         val |= 0x4010000;
2490                                 tw32_f(MAC_SERDES_CFG, val);
2491                         }
2492                         tw32_f(SG_DIG_CTRL, 0x01388400);
2493                 }
2494                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2495                         tg3_setup_flow_control(tp, 0, 0);
2496                         current_link_up = 1;
2497                 }
2498                 goto out;
2499         }
2500
2501         /* Want auto-negotiation.  */
2502         expected_sg_dig_ctrl = 0x81388400;
2503
2504         /* Pause capability */
2505         expected_sg_dig_ctrl |= (1 << 11);
2506
2507         /* Asymettric pause */
2508         expected_sg_dig_ctrl |= (1 << 12);
2509
2510         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2511                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2512                     tp->serdes_counter &&
2513                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2514                                     MAC_STATUS_RCVD_CFG)) ==
2515                      MAC_STATUS_PCS_SYNCED)) {
2516                         tp->serdes_counter--;
2517                         current_link_up = 1;
2518                         goto out;
2519                 }
2520 restart_autoneg:
2521                 if (workaround)
2522                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2523                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2524                 udelay(5);
2525                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2526
2527                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2528                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2529         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2530                                  MAC_STATUS_SIGNAL_DET)) {
2531                 sg_dig_status = tr32(SG_DIG_STATUS);
2532                 mac_status = tr32(MAC_STATUS);
2533
2534                 if ((sg_dig_status & (1 << 1)) &&
2535                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2536                         u32 local_adv, remote_adv;
2537
2538                         local_adv = ADVERTISE_PAUSE_CAP;
2539                         remote_adv = 0;
2540                         if (sg_dig_status & (1 << 19))
2541                                 remote_adv |= LPA_PAUSE_CAP;
2542                         if (sg_dig_status & (1 << 20))
2543                                 remote_adv |= LPA_PAUSE_ASYM;
2544
2545                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2546                         current_link_up = 1;
2547                         tp->serdes_counter = 0;
2548                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2549                 } else if (!(sg_dig_status & (1 << 1))) {
2550                         if (tp->serdes_counter)
2551                                 tp->serdes_counter--;
2552                         else {
2553                                 if (workaround) {
2554                                         u32 val = serdes_cfg;
2555
2556                                         if (port_a)
2557                                                 val |= 0xc010000;
2558                                         else
2559                                                 val |= 0x4010000;
2560
2561                                         tw32_f(MAC_SERDES_CFG, val);
2562                                 }
2563
2564                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2565                                 udelay(40);
2566
2567                                 /* Link parallel detection - link is up */
2568                                 /* only if we have PCS_SYNC and not */
2569                                 /* receiving config code words */
2570                                 mac_status = tr32(MAC_STATUS);
2571                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2572                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2573                                         tg3_setup_flow_control(tp, 0, 0);
2574                                         current_link_up = 1;
2575                                         tp->tg3_flags2 |=
2576                                                 TG3_FLG2_PARALLEL_DETECT;
2577                                         tp->serdes_counter =
2578                                                 SERDES_PARALLEL_DET_TIMEOUT;
2579                                 } else
2580                                         goto restart_autoneg;
2581                         }
2582                 }
2583         } else {
2584                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2585                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2586         }
2587
2588 out:
2589         return current_link_up;
2590 }
2591
2592 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2593 {
2594         int current_link_up = 0;
2595
2596         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2597                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2598                 goto out;
2599         }
2600
2601         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2602                 u32 flags;
2603                 int i;
2604
2605                 if (fiber_autoneg(tp, &flags)) {
2606                         u32 local_adv, remote_adv;
2607
2608                         local_adv = ADVERTISE_PAUSE_CAP;
2609                         remote_adv = 0;
2610                         if (flags & MR_LP_ADV_SYM_PAUSE)
2611                                 remote_adv |= LPA_PAUSE_CAP;
2612                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2613                                 remote_adv |= LPA_PAUSE_ASYM;
2614
2615                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2616
2617                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2618                         current_link_up = 1;
2619                 }
2620                 for (i = 0; i < 30; i++) {
2621                         udelay(20);
2622                         tw32_f(MAC_STATUS,
2623                                (MAC_STATUS_SYNC_CHANGED |
2624                                 MAC_STATUS_CFG_CHANGED));
2625                         udelay(40);
2626                         if ((tr32(MAC_STATUS) &
2627                              (MAC_STATUS_SYNC_CHANGED |
2628                               MAC_STATUS_CFG_CHANGED)) == 0)
2629                                 break;
2630                 }
2631
2632                 mac_status = tr32(MAC_STATUS);
2633                 if (current_link_up == 0 &&
2634                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2635                     !(mac_status & MAC_STATUS_RCVD_CFG))
2636                         current_link_up = 1;
2637         } else {
2638                 /* Forcing 1000FD link up. */
2639                 current_link_up = 1;
2640                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2641
2642                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2643                 udelay(40);
2644         }
2645
2646 out:
2647         return current_link_up;
2648 }
2649
2650 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2651 {
2652         u32 orig_pause_cfg;
2653         u16 orig_active_speed;
2654         u8 orig_active_duplex;
2655         u32 mac_status;
2656         int current_link_up;
2657         int i;
2658
2659         orig_pause_cfg =
2660                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2661                                   TG3_FLAG_TX_PAUSE));
2662         orig_active_speed = tp->link_config.active_speed;
2663         orig_active_duplex = tp->link_config.active_duplex;
2664
2665         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2666             netif_carrier_ok(tp->dev) &&
2667             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2668                 mac_status = tr32(MAC_STATUS);
2669                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2670                                MAC_STATUS_SIGNAL_DET |
2671                                MAC_STATUS_CFG_CHANGED |
2672                                MAC_STATUS_RCVD_CFG);
2673                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2674                                    MAC_STATUS_SIGNAL_DET)) {
2675                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2676                                             MAC_STATUS_CFG_CHANGED));
2677                         return 0;
2678                 }
2679         }
2680
2681         tw32_f(MAC_TX_AUTO_NEG, 0);
2682
2683         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2684         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2685         tw32_f(MAC_MODE, tp->mac_mode);
2686         udelay(40);
2687
2688         if (tp->phy_id == PHY_ID_BCM8002)
2689                 tg3_init_bcm8002(tp);
2690
2691         /* Enable link change event even when serdes polling.  */
2692         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2693         udelay(40);
2694
2695         current_link_up = 0;
2696         mac_status = tr32(MAC_STATUS);
2697
2698         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2699                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2700         else
2701                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2702
2703         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2704         tw32_f(MAC_MODE, tp->mac_mode);
2705         udelay(40);
2706
2707         tp->hw_status->status =
2708                 (SD_STATUS_UPDATED |
2709                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2710
2711         for (i = 0; i < 100; i++) {
2712                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2713                                     MAC_STATUS_CFG_CHANGED));
2714                 udelay(5);
2715                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2716                                          MAC_STATUS_CFG_CHANGED |
2717                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2718                         break;
2719         }
2720
2721         mac_status = tr32(MAC_STATUS);
2722         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2723                 current_link_up = 0;
2724                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2725                     tp->serdes_counter == 0) {
2726                         tw32_f(MAC_MODE, (tp->mac_mode |
2727                                           MAC_MODE_SEND_CONFIGS));
2728                         udelay(1);
2729                         tw32_f(MAC_MODE, tp->mac_mode);
2730                 }
2731         }
2732
2733         if (current_link_up == 1) {
2734                 tp->link_config.active_speed = SPEED_1000;
2735                 tp->link_config.active_duplex = DUPLEX_FULL;
2736                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2737                                     LED_CTRL_LNKLED_OVERRIDE |
2738                                     LED_CTRL_1000MBPS_ON));
2739         } else {
2740                 tp->link_config.active_speed = SPEED_INVALID;
2741                 tp->link_config.active_duplex = DUPLEX_INVALID;
2742                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2743                                     LED_CTRL_LNKLED_OVERRIDE |
2744                                     LED_CTRL_TRAFFIC_OVERRIDE));
2745         }
2746
2747         if (current_link_up != netif_carrier_ok(tp->dev)) {
2748                 if (current_link_up)
2749                         netif_carrier_on(tp->dev);
2750                 else
2751                         netif_carrier_off(tp->dev);
2752                 tg3_link_report(tp);
2753         } else {
2754                 u32 now_pause_cfg =
2755                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2756                                          TG3_FLAG_TX_PAUSE);
2757                 if (orig_pause_cfg != now_pause_cfg ||
2758                     orig_active_speed != tp->link_config.active_speed ||
2759                     orig_active_duplex != tp->link_config.active_duplex)
2760                         tg3_link_report(tp);
2761         }
2762
2763         return 0;
2764 }
2765
2766 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2767 {
2768         int current_link_up, err = 0;
2769         u32 bmsr, bmcr;
2770         u16 current_speed;
2771         u8 current_duplex;
2772
2773         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2774         tw32_f(MAC_MODE, tp->mac_mode);
2775         udelay(40);
2776
2777         tw32(MAC_EVENT, 0);
2778
2779         tw32_f(MAC_STATUS,
2780              (MAC_STATUS_SYNC_CHANGED |
2781               MAC_STATUS_CFG_CHANGED |
2782               MAC_STATUS_MI_COMPLETION |
2783               MAC_STATUS_LNKSTATE_CHANGED));
2784         udelay(40);
2785
2786         if (force_reset)
2787                 tg3_phy_reset(tp);
2788
2789         current_link_up = 0;
2790         current_speed = SPEED_INVALID;
2791         current_duplex = DUPLEX_INVALID;
2792
2793         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2794         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2795         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2796                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2797                         bmsr |= BMSR_LSTATUS;
2798                 else
2799                         bmsr &= ~BMSR_LSTATUS;
2800         }
2801
2802         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2803
2804         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2805             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2806                 /* do nothing, just check for link up at the end */
2807         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2808                 u32 adv, new_adv;
2809
2810                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2811                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2812                                   ADVERTISE_1000XPAUSE |
2813                                   ADVERTISE_1000XPSE_ASYM |
2814                                   ADVERTISE_SLCT);
2815
2816                 /* Always advertise symmetric PAUSE just like copper */
2817                 new_adv |= ADVERTISE_1000XPAUSE;
2818
2819                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2820                         new_adv |= ADVERTISE_1000XHALF;
2821                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2822                         new_adv |= ADVERTISE_1000XFULL;
2823
2824                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2825                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2826                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2827                         tg3_writephy(tp, MII_BMCR, bmcr);
2828
2829                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2830                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2831                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2832
2833                         return err;
2834                 }
2835         } else {
2836                 u32 new_bmcr;
2837
2838                 bmcr &= ~BMCR_SPEED1000;
2839                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2840
2841                 if (tp->link_config.duplex == DUPLEX_FULL)
2842                         new_bmcr |= BMCR_FULLDPLX;
2843
2844                 if (new_bmcr != bmcr) {
2845                         /* BMCR_SPEED1000 is a reserved bit that needs
2846                          * to be set on write.
2847                          */
2848                         new_bmcr |= BMCR_SPEED1000;
2849
2850                         /* Force a linkdown */
2851                         if (netif_carrier_ok(tp->dev)) {
2852                                 u32 adv;
2853
2854                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2855                                 adv &= ~(ADVERTISE_1000XFULL |
2856                                          ADVERTISE_1000XHALF |
2857                                          ADVERTISE_SLCT);
2858                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2859                                 tg3_writephy(tp, MII_BMCR, bmcr |
2860                                                            BMCR_ANRESTART |
2861                                                            BMCR_ANENABLE);
2862                                 udelay(10);
2863                                 netif_carrier_off(tp->dev);
2864                         }
2865                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2866                         bmcr = new_bmcr;
2867                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2868                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2869                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2870                             ASIC_REV_5714) {
2871                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2872                                         bmsr |= BMSR_LSTATUS;
2873                                 else
2874                                         bmsr &= ~BMSR_LSTATUS;
2875                         }
2876                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2877                 }
2878         }
2879
2880         if (bmsr & BMSR_LSTATUS) {
2881                 current_speed = SPEED_1000;
2882                 current_link_up = 1;
2883                 if (bmcr & BMCR_FULLDPLX)
2884                         current_duplex = DUPLEX_FULL;
2885                 else
2886                         current_duplex = DUPLEX_HALF;
2887
2888                 if (bmcr & BMCR_ANENABLE) {
2889                         u32 local_adv, remote_adv, common;
2890
2891                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2892                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2893                         common = local_adv & remote_adv;
2894                         if (common & (ADVERTISE_1000XHALF |
2895                                       ADVERTISE_1000XFULL)) {
2896                                 if (common & ADVERTISE_1000XFULL)
2897                                         current_duplex = DUPLEX_FULL;
2898                                 else
2899                                         current_duplex = DUPLEX_HALF;
2900
2901                                 tg3_setup_flow_control(tp, local_adv,
2902                                                        remote_adv);
2903                         }
2904                         else
2905                                 current_link_up = 0;
2906                 }
2907         }
2908
2909         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2910         if (tp->link_config.active_duplex == DUPLEX_HALF)
2911                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2912
2913         tw32_f(MAC_MODE, tp->mac_mode);
2914         udelay(40);
2915
2916         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2917
2918         tp->link_config.active_speed = current_speed;
2919         tp->link_config.active_duplex = current_duplex;
2920
2921         if (current_link_up != netif_carrier_ok(tp->dev)) {
2922                 if (current_link_up)
2923                         netif_carrier_on(tp->dev);
2924                 else {
2925                         netif_carrier_off(tp->dev);
2926                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2927                 }
2928                 tg3_link_report(tp);
2929         }
2930         return err;
2931 }
2932
2933 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2934 {
2935         if (tp->serdes_counter) {
2936                 /* Give autoneg time to complete. */
2937                 tp->serdes_counter--;
2938                 return;
2939         }
2940         if (!netif_carrier_ok(tp->dev) &&
2941             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2942                 u32 bmcr;
2943
2944                 tg3_readphy(tp, MII_BMCR, &bmcr);
2945                 if (bmcr & BMCR_ANENABLE) {
2946                         u32 phy1, phy2;
2947
2948                         /* Select shadow register 0x1f */
2949                         tg3_writephy(tp, 0x1c, 0x7c00);
2950                         tg3_readphy(tp, 0x1c, &phy1);
2951
2952                         /* Select expansion interrupt status register */
2953                         tg3_writephy(tp, 0x17, 0x0f01);
2954                         tg3_readphy(tp, 0x15, &phy2);
2955                         tg3_readphy(tp, 0x15, &phy2);
2956
2957                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2958                                 /* We have signal detect and not receiving
2959                                  * config code words, link is up by parallel
2960                                  * detection.
2961                                  */
2962
2963                                 bmcr &= ~BMCR_ANENABLE;
2964                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2965                                 tg3_writephy(tp, MII_BMCR, bmcr);
2966                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2967                         }
2968                 }
2969         }
2970         else if (netif_carrier_ok(tp->dev) &&
2971                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2972                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2973                 u32 phy2;
2974
2975                 /* Select expansion interrupt status register */
2976                 tg3_writephy(tp, 0x17, 0x0f01);
2977                 tg3_readphy(tp, 0x15, &phy2);
2978                 if (phy2 & 0x20) {
2979                         u32 bmcr;
2980
2981                         /* Config code words received, turn on autoneg. */
2982                         tg3_readphy(tp, MII_BMCR, &bmcr);
2983                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2984
2985                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2986
2987                 }
2988         }
2989 }
2990
2991 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2992 {
2993         int err;
2994
2995         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2996                 err = tg3_setup_fiber_phy(tp, force_reset);
2997         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2998                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2999         } else {
3000                 err = tg3_setup_copper_phy(tp, force_reset);
3001         }
3002
3003         if (tp->link_config.active_speed == SPEED_1000 &&
3004             tp->link_config.active_duplex == DUPLEX_HALF)
3005                 tw32(MAC_TX_LENGTHS,
3006                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3007                       (6 << TX_LENGTHS_IPG_SHIFT) |
3008                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3009         else
3010                 tw32(MAC_TX_LENGTHS,
3011                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3012                       (6 << TX_LENGTHS_IPG_SHIFT) |
3013                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3014
3015         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3016                 if (netif_carrier_ok(tp->dev)) {
3017                         tw32(HOSTCC_STAT_COAL_TICKS,
3018                              tp->coal.stats_block_coalesce_usecs);
3019                 } else {
3020                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3021                 }
3022         }
3023
3024         return err;
3025 }
3026
3027 /* This is called whenever we suspect that the system chipset is re-
3028  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3029  * is bogus tx completions. We try to recover by setting the
3030  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3031  * in the workqueue.
3032  */
3033 static void tg3_tx_recover(struct tg3 *tp)
3034 {
3035         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3036                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3037
3038         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3039                "mapped I/O cycles to the network device, attempting to "
3040                "recover. Please report the problem to the driver maintainer "
3041                "and include system chipset information.\n", tp->dev->name);
3042
3043         spin_lock(&tp->lock);
3044         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3045         spin_unlock(&tp->lock);
3046 }
3047
3048 static inline u32 tg3_tx_avail(struct tg3 *tp)
3049 {
3050         smp_mb();
3051         return (tp->tx_pending -
3052                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3053 }
3054
3055 /* Tigon3 never reports partial packet sends.  So we do not
3056  * need special logic to handle SKBs that have not had all
3057  * of their frags sent yet, like SunGEM does.
3058  */
3059 static void tg3_tx(struct tg3 *tp)
3060 {
3061         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3062         u32 sw_idx = tp->tx_cons;
3063
3064         while (sw_idx != hw_idx) {
3065                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3066                 struct sk_buff *skb = ri->skb;
3067                 int i, tx_bug = 0;
3068
3069                 if (unlikely(skb == NULL)) {
3070                         tg3_tx_recover(tp);
3071                         return;
3072                 }
3073
3074                 pci_unmap_single(tp->pdev,
3075                                  pci_unmap_addr(ri, mapping),
3076                                  skb_headlen(skb),
3077                                  PCI_DMA_TODEVICE);
3078
3079                 ri->skb = NULL;
3080
3081                 sw_idx = NEXT_TX(sw_idx);
3082
3083                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3084                         ri = &tp->tx_buffers[sw_idx];
3085                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3086                                 tx_bug = 1;
3087
3088                         pci_unmap_page(tp->pdev,
3089                                        pci_unmap_addr(ri, mapping),
3090                                        skb_shinfo(skb)->frags[i].size,
3091                                        PCI_DMA_TODEVICE);
3092
3093                         sw_idx = NEXT_TX(sw_idx);
3094                 }
3095
3096                 dev_kfree_skb(skb);
3097
3098                 if (unlikely(tx_bug)) {
3099                         tg3_tx_recover(tp);
3100                         return;
3101                 }
3102         }
3103
3104         tp->tx_cons = sw_idx;
3105
3106         /* Need to make the tx_cons update visible to tg3_start_xmit()
3107          * before checking for netif_queue_stopped().  Without the
3108          * memory barrier, there is a small possibility that tg3_start_xmit()
3109          * will miss it and cause the queue to be stopped forever.
3110          */
3111         smp_mb();
3112
3113         if (unlikely(netif_queue_stopped(tp->dev) &&
3114                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3115                 netif_tx_lock(tp->dev);
3116                 if (netif_queue_stopped(tp->dev) &&
3117                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3118                         netif_wake_queue(tp->dev);
3119                 netif_tx_unlock(tp->dev);
3120         }
3121 }
3122
3123 /* Returns size of skb allocated or < 0 on error.
3124  *
3125  * We only need to fill in the address because the other members
3126  * of the RX descriptor are invariant, see tg3_init_rings.
3127  *
3128  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3129  * posting buffers we only dirty the first cache line of the RX
3130  * descriptor (containing the address).  Whereas for the RX status
3131  * buffers the cpu only reads the last cacheline of the RX descriptor
3132  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3133  */
3134 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3135                             int src_idx, u32 dest_idx_unmasked)
3136 {
3137         struct tg3_rx_buffer_desc *desc;
3138         struct ring_info *map, *src_map;
3139         struct sk_buff *skb;
3140         dma_addr_t mapping;
3141         int skb_size, dest_idx;
3142
3143         src_map = NULL;
3144         switch (opaque_key) {
3145         case RXD_OPAQUE_RING_STD:
3146                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3147                 desc = &tp->rx_std[dest_idx];
3148                 map = &tp->rx_std_buffers[dest_idx];
3149                 if (src_idx >= 0)
3150                         src_map = &tp->rx_std_buffers[src_idx];
3151                 skb_size = tp->rx_pkt_buf_sz;
3152                 break;
3153
3154         case RXD_OPAQUE_RING_JUMBO:
3155                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3156                 desc = &tp->rx_jumbo[dest_idx];
3157                 map = &tp->rx_jumbo_buffers[dest_idx];
3158                 if (src_idx >= 0)
3159                         src_map = &tp->rx_jumbo_buffers[src_idx];
3160                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3161                 break;
3162
3163         default:
3164                 return -EINVAL;
3165         };
3166
3167         /* Do not overwrite any of the map or rp information
3168          * until we are sure we can commit to a new buffer.
3169          *
3170          * Callers depend upon this behavior and assume that
3171          * we leave everything unchanged if we fail.
3172          */
3173         skb = netdev_alloc_skb(tp->dev, skb_size);
3174         if (skb == NULL)
3175                 return -ENOMEM;
3176
3177         skb_reserve(skb, tp->rx_offset);
3178
3179         mapping = pci_map_single(tp->pdev, skb->data,
3180                                  skb_size - tp->rx_offset,
3181                                  PCI_DMA_FROMDEVICE);
3182
3183         map->skb = skb;
3184         pci_unmap_addr_set(map, mapping, mapping);
3185
3186         if (src_map != NULL)
3187                 src_map->skb = NULL;
3188
3189         desc->addr_hi = ((u64)mapping >> 32);
3190         desc->addr_lo = ((u64)mapping & 0xffffffff);
3191
3192         return skb_size;
3193 }
3194
3195 /* We only need to move over in the address because the other
3196  * members of the RX descriptor are invariant.  See notes above
3197  * tg3_alloc_rx_skb for full details.
3198  */
3199 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3200                            int src_idx, u32 dest_idx_unmasked)
3201 {
3202         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3203         struct ring_info *src_map, *dest_map;
3204         int dest_idx;
3205
3206         switch (opaque_key) {
3207         case RXD_OPAQUE_RING_STD:
3208                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3209                 dest_desc = &tp->rx_std[dest_idx];
3210                 dest_map = &tp->rx_std_buffers[dest_idx];
3211                 src_desc = &tp->rx_std[src_idx];
3212                 src_map = &tp->rx_std_buffers[src_idx];
3213                 break;
3214
3215         case RXD_OPAQUE_RING_JUMBO:
3216                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3217                 dest_desc = &tp->rx_jumbo[dest_idx];
3218                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3219                 src_desc = &tp->rx_jumbo[src_idx];
3220                 src_map = &tp->rx_jumbo_buffers[src_idx];
3221                 break;
3222
3223         default:
3224                 return;
3225         };
3226
3227         dest_map->skb = src_map->skb;
3228         pci_unmap_addr_set(dest_map, mapping,
3229                            pci_unmap_addr(src_map, mapping));
3230         dest_desc->addr_hi = src_desc->addr_hi;
3231         dest_desc->addr_lo = src_desc->addr_lo;
3232
3233         src_map->skb = NULL;
3234 }
3235
3236 #if TG3_VLAN_TAG_USED
3237 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3238 {
3239         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3240 }
3241 #endif
3242
3243 /* The RX ring scheme is composed of multiple rings which post fresh
3244  * buffers to the chip, and one special ring the chip uses to report
3245  * status back to the host.
3246  *
3247  * The special ring reports the status of received packets to the
3248  * host.  The chip does not write into the original descriptor the
3249  * RX buffer was obtained from.  The chip simply takes the original
3250  * descriptor as provided by the host, updates the status and length
3251  * field, then writes this into the next status ring entry.
3252  *
3253  * Each ring the host uses to post buffers to the chip is described
3254  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3255  * it is first placed into the on-chip ram.  When the packet's length
3256  * is known, it walks down the TG3_BDINFO entries to select the ring.
3257  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3258  * which is within the range of the new packet's length is chosen.
3259  *
3260  * The "separate ring for rx status" scheme may sound queer, but it makes
3261  * sense from a cache coherency perspective.  If only the host writes
3262  * to the buffer post rings, and only the chip writes to the rx status
3263  * rings, then cache lines never move beyond shared-modified state.
3264  * If both the host and chip were to write into the same ring, cache line
3265  * eviction could occur since both entities want it in an exclusive state.
3266  */
3267 static int tg3_rx(struct tg3 *tp, int budget)
3268 {
3269         u32 work_mask, rx_std_posted = 0;
3270         u32 sw_idx = tp->rx_rcb_ptr;
3271         u16 hw_idx;
3272         int received;
3273
3274         hw_idx = tp->hw_status->idx[0].rx_producer;
3275         /*
3276          * We need to order the read of hw_idx and the read of
3277          * the opaque cookie.
3278          */
3279         rmb();
3280         work_mask = 0;
3281         received = 0;
3282         while (sw_idx != hw_idx && budget > 0) {
3283                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3284                 unsigned int len;
3285                 struct sk_buff *skb;
3286                 dma_addr_t dma_addr;
3287                 u32 opaque_key, desc_idx, *post_ptr;
3288
3289                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3290                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3291                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3292                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3293                                                   mapping);
3294                         skb = tp->rx_std_buffers[desc_idx].skb;
3295                         post_ptr = &tp->rx_std_ptr;
3296                         rx_std_posted++;
3297                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3298                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3299                                                   mapping);
3300                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3301                         post_ptr = &tp->rx_jumbo_ptr;
3302                 }
3303                 else {
3304                         goto next_pkt_nopost;
3305                 }
3306
3307                 work_mask |= opaque_key;
3308
3309                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3310                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3311                 drop_it:
3312                         tg3_recycle_rx(tp, opaque_key,
3313                                        desc_idx, *post_ptr);
3314                 drop_it_no_recycle:
3315                         /* Other statistics kept track of by card. */
3316                         tp->net_stats.rx_dropped++;
3317                         goto next_pkt;
3318                 }
3319
3320                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3321
3322                 if (len > RX_COPY_THRESHOLD
3323                         && tp->rx_offset == 2
3324                         /* rx_offset != 2 iff this is a 5701 card running
3325                          * in PCI-X mode [see tg3_get_invariants()] */
3326                 ) {
3327                         int skb_size;
3328
3329                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3330                                                     desc_idx, *post_ptr);
3331                         if (skb_size < 0)
3332                                 goto drop_it;
3333
3334                         pci_unmap_single(tp->pdev, dma_addr,
3335                                          skb_size - tp->rx_offset,
3336                                          PCI_DMA_FROMDEVICE);
3337
3338                         skb_put(skb, len);
3339                 } else {
3340                         struct sk_buff *copy_skb;
3341
3342                         tg3_recycle_rx(tp, opaque_key,
3343                                        desc_idx, *post_ptr);
3344
3345                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3346                         if (copy_skb == NULL)
3347                                 goto drop_it_no_recycle;
3348
3349                         skb_reserve(copy_skb, 2);
3350                         skb_put(copy_skb, len);
3351                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3352                         memcpy(copy_skb->data, skb->data, len);
3353                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3354
3355                         /* We'll reuse the original ring buffer. */
3356                         skb = copy_skb;
3357                 }
3358
3359                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3360                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3361                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3362                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3363                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3364                 else
3365                         skb->ip_summed = CHECKSUM_NONE;
3366
3367                 skb->protocol = eth_type_trans(skb, tp->dev);
3368 #if TG3_VLAN_TAG_USED
3369                 if (tp->vlgrp != NULL &&
3370                     desc->type_flags & RXD_FLAG_VLAN) {
3371                         tg3_vlan_rx(tp, skb,
3372                                     desc->err_vlan & RXD_VLAN_MASK);
3373                 } else
3374 #endif
3375                         netif_receive_skb(skb);
3376
3377                 tp->dev->last_rx = jiffies;
3378                 received++;
3379                 budget--;
3380
3381 next_pkt:
3382                 (*post_ptr)++;
3383
3384                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3385                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3386
3387                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3388                                      TG3_64BIT_REG_LOW, idx);
3389                         work_mask &= ~RXD_OPAQUE_RING_STD;
3390                         rx_std_posted = 0;
3391                 }
3392 next_pkt_nopost:
3393                 sw_idx++;
3394                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3395
3396                 /* Refresh hw_idx to see if there is new work */
3397                 if (sw_idx == hw_idx) {
3398                         hw_idx = tp->hw_status->idx[0].rx_producer;
3399                         rmb();
3400                 }
3401         }
3402
3403         /* ACK the status ring. */
3404         tp->rx_rcb_ptr = sw_idx;
3405         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3406
3407         /* Refill RX ring(s). */
3408         if (work_mask & RXD_OPAQUE_RING_STD) {
3409                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3410                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3411                              sw_idx);
3412         }
3413         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3414                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3415                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3416                              sw_idx);
3417         }
3418         mmiowb();
3419
3420         return received;
3421 }
3422
3423 static int tg3_poll(struct net_device *netdev, int *budget)
3424 {
3425         struct tg3 *tp = netdev_priv(netdev);
3426         struct tg3_hw_status *sblk = tp->hw_status;
3427         int done;
3428
3429         /* handle link change and other phy events */
3430         if (!(tp->tg3_flags &
3431               (TG3_FLAG_USE_LINKCHG_REG |
3432                TG3_FLAG_POLL_SERDES))) {
3433                 if (sblk->status & SD_STATUS_LINK_CHG) {
3434                         sblk->status = SD_STATUS_UPDATED |
3435                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3436                         spin_lock(&tp->lock);
3437                         tg3_setup_phy(tp, 0);
3438                         spin_unlock(&tp->lock);
3439                 }
3440         }
3441
3442         /* run TX completion thread */
3443         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3444                 tg3_tx(tp);
3445                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3446                         netif_rx_complete(netdev);
3447                         schedule_work(&tp->reset_task);
3448                         return 0;
3449                 }
3450         }
3451
3452         /* run RX thread, within the bounds set by NAPI.
3453          * All RX "locking" is done by ensuring outside
3454          * code synchronizes with dev->poll()
3455          */
3456         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3457                 int orig_budget = *budget;
3458                 int work_done;
3459
3460                 if (orig_budget > netdev->quota)
3461                         orig_budget = netdev->quota;
3462
3463                 work_done = tg3_rx(tp, orig_budget);
3464
3465                 *budget -= work_done;
3466                 netdev->quota -= work_done;
3467         }
3468
3469         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3470                 tp->last_tag = sblk->status_tag;
3471                 rmb();
3472         } else
3473                 sblk->status &= ~SD_STATUS_UPDATED;
3474
3475         /* if no more work, tell net stack and NIC we're done */
3476         done = !tg3_has_work(tp);
3477         if (done) {
3478                 netif_rx_complete(netdev);
3479                 tg3_restart_ints(tp);
3480         }
3481
3482         return (done ? 0 : 1);
3483 }
3484
3485 static void tg3_irq_quiesce(struct tg3 *tp)
3486 {
3487         BUG_ON(tp->irq_sync);
3488
3489         tp->irq_sync = 1;
3490         smp_mb();
3491
3492         synchronize_irq(tp->pdev->irq);
3493 }
3494
3495 static inline int tg3_irq_sync(struct tg3 *tp)
3496 {
3497         return tp->irq_sync;
3498 }
3499
3500 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3501  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3502  * with as well.  Most of the time, this is not necessary except when
3503  * shutting down the device.
3504  */
3505 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3506 {
3507         if (irq_sync)
3508                 tg3_irq_quiesce(tp);
3509         spin_lock_bh(&tp->lock);
3510 }
3511
3512 static inline void tg3_full_unlock(struct tg3 *tp)
3513 {
3514         spin_unlock_bh(&tp->lock);
3515 }
3516
3517 /* One-shot MSI handler - Chip automatically disables interrupt
3518  * after sending MSI so driver doesn't have to do it.
3519  */
3520 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3521 {
3522         struct net_device *dev = dev_id;
3523         struct tg3 *tp = netdev_priv(dev);
3524
3525         prefetch(tp->hw_status);
3526         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3527
3528         if (likely(!tg3_irq_sync(tp)))
3529                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3530
3531         return IRQ_HANDLED;
3532 }
3533
3534 /* MSI ISR - No need to check for interrupt sharing and no need to
3535  * flush status block and interrupt mailbox. PCI ordering rules
3536  * guarantee that MSI will arrive after the status block.
3537  */
3538 static irqreturn_t tg3_msi(int irq, void *dev_id)
3539 {
3540         struct net_device *dev = dev_id;
3541         struct tg3 *tp = netdev_priv(dev);
3542
3543         prefetch(tp->hw_status);
3544         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3545         /*
3546          * Writing any value to intr-mbox-0 clears PCI INTA# and
3547          * chip-internal interrupt pending events.
3548          * Writing non-zero to intr-mbox-0 additional tells the
3549          * NIC to stop sending us irqs, engaging "in-intr-handler"
3550          * event coalescing.
3551          */
3552         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3553         if (likely(!tg3_irq_sync(tp)))
3554                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3555
3556         return IRQ_RETVAL(1);
3557 }
3558
3559 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3560 {
3561         struct net_device *dev = dev_id;
3562         struct tg3 *tp = netdev_priv(dev);
3563         struct tg3_hw_status *sblk = tp->hw_status;
3564         unsigned int handled = 1;
3565
3566         /* In INTx mode, it is possible for the interrupt to arrive at
3567          * the CPU before the status block posted prior to the interrupt.
3568          * Reading the PCI State register will confirm whether the
3569          * interrupt is ours and will flush the status block.
3570          */
3571         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3572                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3573                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3574                         handled = 0;
3575                         goto out;
3576                 }
3577         }
3578
3579         /*
3580          * Writing any value to intr-mbox-0 clears PCI INTA# and
3581          * chip-internal interrupt pending events.
3582          * Writing non-zero to intr-mbox-0 additional tells the
3583          * NIC to stop sending us irqs, engaging "in-intr-handler"
3584          * event coalescing.
3585          */
3586         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3587         if (tg3_irq_sync(tp))
3588                 goto out;
3589         sblk->status &= ~SD_STATUS_UPDATED;
3590         if (likely(tg3_has_work(tp))) {
3591                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3592                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3593         } else {
3594                 /* No work, shared interrupt perhaps?  re-enable
3595                  * interrupts, and flush that PCI write
3596                  */
3597                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3598                                0x00000000);
3599         }
3600 out:
3601         return IRQ_RETVAL(handled);
3602 }
3603
3604 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3605 {
3606         struct net_device *dev = dev_id;
3607         struct tg3 *tp = netdev_priv(dev);
3608         struct tg3_hw_status *sblk = tp->hw_status;
3609         unsigned int handled = 1;
3610
3611         /* In INTx mode, it is possible for the interrupt to arrive at
3612          * the CPU before the status block posted prior to the interrupt.
3613          * Reading the PCI State register will confirm whether the
3614          * interrupt is ours and will flush the status block.
3615          */
3616         if (unlikely(sblk->status_tag == tp->last_tag)) {
3617                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3618                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3619                         handled = 0;
3620                         goto out;
3621                 }
3622         }
3623
3624         /*
3625          * writing any value to intr-mbox-0 clears PCI INTA# and
3626          * chip-internal interrupt pending events.
3627          * writing non-zero to intr-mbox-0 additional tells the
3628          * NIC to stop sending us irqs, engaging "in-intr-handler"
3629          * event coalescing.
3630          */
3631         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3632         if (tg3_irq_sync(tp))
3633                 goto out;
3634         if (netif_rx_schedule_prep(dev)) {
3635                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3636                 /* Update last_tag to mark that this status has been
3637                  * seen. Because interrupt may be shared, we may be
3638                  * racing with tg3_poll(), so only update last_tag
3639                  * if tg3_poll() is not scheduled.
3640                  */
3641                 tp->last_tag = sblk->status_tag;
3642                 __netif_rx_schedule(dev);
3643         }
3644 out:
3645         return IRQ_RETVAL(handled);
3646 }
3647
3648 /* ISR for interrupt test */
3649 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3650 {
3651         struct net_device *dev = dev_id;
3652         struct tg3 *tp = netdev_priv(dev);
3653         struct tg3_hw_status *sblk = tp->hw_status;
3654
3655         if ((sblk->status & SD_STATUS_UPDATED) ||
3656             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3657                 tg3_disable_ints(tp);
3658                 return IRQ_RETVAL(1);
3659         }
3660         return IRQ_RETVAL(0);
3661 }
3662
3663 static int tg3_init_hw(struct tg3 *, int);
3664 static int tg3_halt(struct tg3 *, int, int);
3665
3666 /* Restart hardware after configuration changes, self-test, etc.
3667  * Invoked with tp->lock held.
3668  */
3669 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3670 {
3671         int err;
3672
3673         err = tg3_init_hw(tp, reset_phy);
3674         if (err) {
3675                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3676                        "aborting.\n", tp->dev->name);
3677                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3678                 tg3_full_unlock(tp);
3679                 del_timer_sync(&tp->timer);
3680                 tp->irq_sync = 0;
3681                 netif_poll_enable(tp->dev);
3682                 dev_close(tp->dev);
3683                 tg3_full_lock(tp, 0);
3684         }
3685         return err;
3686 }
3687
3688 #ifdef CONFIG_NET_POLL_CONTROLLER
3689 static void tg3_poll_controller(struct net_device *dev)
3690 {
3691         struct tg3 *tp = netdev_priv(dev);
3692
3693         tg3_interrupt(tp->pdev->irq, dev);
3694 }
3695 #endif
3696
3697 static void tg3_reset_task(struct work_struct *work)
3698 {
3699         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3700         unsigned int restart_timer;
3701
3702         tg3_full_lock(tp, 0);
3703         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3704
3705         if (!netif_running(tp->dev)) {
3706                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3707                 tg3_full_unlock(tp);
3708                 return;
3709         }
3710
3711         tg3_full_unlock(tp);
3712
3713         tg3_netif_stop(tp);
3714
3715         tg3_full_lock(tp, 1);
3716
3717         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3718         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3719
3720         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3721                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3722                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3723                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3724                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3725         }
3726
3727         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3728         if (tg3_init_hw(tp, 1))
3729                 goto out;
3730
3731         tg3_netif_start(tp);
3732
3733         if (restart_timer)
3734                 mod_timer(&tp->timer, jiffies + 1);
3735
3736 out:
3737         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3738
3739         tg3_full_unlock(tp);
3740 }
3741
3742 static void tg3_dump_short_state(struct tg3 *tp)
3743 {
3744         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3745                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3746         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3747                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3748 }
3749
3750 static void tg3_tx_timeout(struct net_device *dev)
3751 {
3752         struct tg3 *tp = netdev_priv(dev);
3753
3754         if (netif_msg_tx_err(tp)) {
3755                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3756                        dev->name);
3757                 tg3_dump_short_state(tp);
3758         }
3759
3760         schedule_work(&tp->reset_task);
3761 }
3762
3763 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3764 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3765 {
3766         u32 base = (u32) mapping & 0xffffffff;
3767
3768         return ((base > 0xffffdcc0) &&
3769                 (base + len + 8 < base));
3770 }
3771
3772 /* Test for DMA addresses > 40-bit */
3773 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3774                                           int len)
3775 {
3776 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3777         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3778                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3779         return 0;
3780 #else
3781         return 0;
3782 #endif
3783 }
3784
3785 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3786
3787 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3788 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3789                                        u32 last_plus_one, u32 *start,
3790                                        u32 base_flags, u32 mss)
3791 {
3792         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3793         dma_addr_t new_addr = 0;
3794         u32 entry = *start;
3795         int i, ret = 0;
3796
3797         if (!new_skb) {
3798                 ret = -1;
3799         } else {
3800                 /* New SKB is guaranteed to be linear. */
3801                 entry = *start;
3802                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3803                                           PCI_DMA_TODEVICE);
3804                 /* Make sure new skb does not cross any 4G boundaries.
3805                  * Drop the packet if it does.
3806                  */
3807                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3808                         ret = -1;
3809                         dev_kfree_skb(new_skb);
3810                         new_skb = NULL;
3811                 } else {
3812                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3813                                     base_flags, 1 | (mss << 1));
3814                         *start = NEXT_TX(entry);
3815                 }
3816         }
3817
3818         /* Now clean up the sw ring entries. */
3819         i = 0;
3820         while (entry != last_plus_one) {
3821                 int len;
3822
3823                 if (i == 0)
3824                         len = skb_headlen(skb);
3825                 else
3826                         len = skb_shinfo(skb)->frags[i-1].size;
3827                 pci_unmap_single(tp->pdev,
3828                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3829                                  len, PCI_DMA_TODEVICE);
3830                 if (i == 0) {
3831                         tp->tx_buffers[entry].skb = new_skb;
3832                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3833                 } else {
3834                         tp->tx_buffers[entry].skb = NULL;
3835                 }
3836                 entry = NEXT_TX(entry);
3837                 i++;
3838         }
3839
3840         dev_kfree_skb(skb);
3841
3842         return ret;
3843 }
3844
3845 static void tg3_set_txd(struct tg3 *tp, int entry,
3846                         dma_addr_t mapping, int len, u32 flags,
3847                         u32 mss_and_is_end)
3848 {
3849         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3850         int is_end = (mss_and_is_end & 0x1);
3851         u32 mss = (mss_and_is_end >> 1);
3852         u32 vlan_tag = 0;
3853
3854         if (is_end)
3855                 flags |= TXD_FLAG_END;
3856         if (flags & TXD_FLAG_VLAN) {
3857                 vlan_tag = flags >> 16;
3858                 flags &= 0xffff;
3859         }
3860         vlan_tag |= (mss << TXD_MSS_SHIFT);
3861
3862         txd->addr_hi = ((u64) mapping >> 32);
3863         txd->addr_lo = ((u64) mapping & 0xffffffff);
3864         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3865         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3866 }
3867
3868 /* hard_start_xmit for devices that don't have any bugs and
3869  * support TG3_FLG2_HW_TSO_2 only.
3870  */
3871 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3872 {
3873         struct tg3 *tp = netdev_priv(dev);
3874         dma_addr_t mapping;
3875         u32 len, entry, base_flags, mss;
3876
3877         len = skb_headlen(skb);
3878
3879         /* We are running in BH disabled context with netif_tx_lock
3880          * and TX reclaim runs via tp->poll inside of a software
3881          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3882          * no IRQ context deadlocks to worry about either.  Rejoice!
3883          */
3884         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3885                 if (!netif_queue_stopped(dev)) {
3886                         netif_stop_queue(dev);
3887
3888                         /* This is a hard error, log it. */
3889                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3890                                "queue awake!\n", dev->name);
3891                 }
3892                 return NETDEV_TX_BUSY;
3893         }
3894
3895         entry = tp->tx_prod;
3896         base_flags = 0;
3897         mss = 0;
3898         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3899             (mss = skb_shinfo(skb)->gso_size) != 0) {
3900                 int tcp_opt_len, ip_tcp_len;
3901
3902                 if (skb_header_cloned(skb) &&
3903                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3904                         dev_kfree_skb(skb);
3905                         goto out_unlock;
3906                 }
3907
3908                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3909                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3910                 else {
3911                         tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3912                         ip_tcp_len = (skb->nh.iph->ihl * 4) +
3913                                      sizeof(struct tcphdr);
3914
3915                         skb->nh.iph->check = 0;
3916                         skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3917                                                      tcp_opt_len);
3918                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3919                 }
3920
3921                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3922                                TXD_FLAG_CPU_POST_DMA);
3923
3924                 skb->h.th->check = 0;
3925
3926         }
3927         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3928                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3929 #if TG3_VLAN_TAG_USED
3930         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3931                 base_flags |= (TXD_FLAG_VLAN |
3932                                (vlan_tx_tag_get(skb) << 16));
3933 #endif
3934
3935         /* Queue skb data, a.k.a. the main skb fragment. */
3936         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3937
3938         tp->tx_buffers[entry].skb = skb;
3939         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3940
3941         tg3_set_txd(tp, entry, mapping, len, base_flags,
3942                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3943
3944         entry = NEXT_TX(entry);
3945
3946         /* Now loop through additional data fragments, and queue them. */
3947         if (skb_shinfo(skb)->nr_frags > 0) {
3948                 unsigned int i, last;
3949
3950                 last = skb_shinfo(skb)->nr_frags - 1;
3951                 for (i = 0; i <= last; i++) {
3952                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3953
3954                         len = frag->size;
3955                         mapping = pci_map_page(tp->pdev,
3956                                                frag->page,
3957                                                frag->page_offset,
3958                                                len, PCI_DMA_TODEVICE);
3959
3960                         tp->tx_buffers[entry].skb = NULL;
3961                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3962
3963                         tg3_set_txd(tp, entry, mapping, len,
3964                                     base_flags, (i == last) | (mss << 1));
3965
3966                         entry = NEXT_TX(entry);
3967                 }
3968         }
3969
3970         /* Packets are ready, update Tx producer idx local and on card. */
3971         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3972
3973         tp->tx_prod = entry;
3974         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3975                 netif_stop_queue(dev);
3976                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3977                         netif_wake_queue(tp->dev);
3978         }
3979
3980 out_unlock:
3981         mmiowb();
3982
3983         dev->trans_start = jiffies;
3984
3985         return NETDEV_TX_OK;
3986 }
3987
3988 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3989
3990 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3991  * TSO header is greater than 80 bytes.
3992  */
3993 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3994 {
3995         struct sk_buff *segs, *nskb;
3996
3997         /* Estimate the number of fragments in the worst case */
3998         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3999                 netif_stop_queue(tp->dev);
4000                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4001                         return NETDEV_TX_BUSY;
4002
4003                 netif_wake_queue(tp->dev);
4004         }
4005
4006         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4007         if (unlikely(IS_ERR(segs)))
4008                 goto tg3_tso_bug_end;
4009
4010         do {
4011                 nskb = segs;
4012                 segs = segs->next;
4013                 nskb->next = NULL;
4014                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4015         } while (segs);
4016
4017 tg3_tso_bug_end:
4018         dev_kfree_skb(skb);
4019
4020         return NETDEV_TX_OK;
4021 }
4022
4023 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4024  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4025  */
4026 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4027 {
4028         struct tg3 *tp = netdev_priv(dev);
4029         dma_addr_t mapping;
4030         u32 len, entry, base_flags, mss;
4031         int would_hit_hwbug;
4032
4033         len = skb_headlen(skb);
4034
4035         /* We are running in BH disabled context with netif_tx_lock
4036          * and TX reclaim runs via tp->poll inside of a software
4037          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4038          * no IRQ context deadlocks to worry about either.  Rejoice!
4039          */
4040         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4041                 if (!netif_queue_stopped(dev)) {
4042                         netif_stop_queue(dev);
4043
4044                         /* This is a hard error, log it. */
4045                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4046                                "queue awake!\n", dev->name);
4047                 }
4048                 return NETDEV_TX_BUSY;
4049         }
4050
4051         entry = tp->tx_prod;
4052         base_flags = 0;
4053         if (skb->ip_summed == CHECKSUM_PARTIAL)
4054                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4055         mss = 0;
4056         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4057             (mss = skb_shinfo(skb)->gso_size) != 0) {
4058                 int tcp_opt_len, ip_tcp_len, hdr_len;
4059
4060                 if (skb_header_cloned(skb) &&
4061                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4062                         dev_kfree_skb(skb);
4063                         goto out_unlock;
4064                 }
4065
4066                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4067                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4068
4069                 hdr_len = ip_tcp_len + tcp_opt_len;
4070                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4071                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4072                         return (tg3_tso_bug(tp, skb));
4073
4074                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4075                                TXD_FLAG_CPU_POST_DMA);
4076
4077                 skb->nh.iph->check = 0;
4078                 skb->nh.iph->tot_len = htons(mss + hdr_len);
4079                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4080                         skb->h.th->check = 0;
4081                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4082                 }
4083                 else {
4084                         skb->h.th->check =
4085                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4086                                                    skb->nh.iph->daddr,
4087                                                    0, IPPROTO_TCP, 0);
4088                 }
4089
4090                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4091                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4092                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4093                                 int tsflags;
4094
4095                                 tsflags = ((skb->nh.iph->ihl - 5) +
4096                                            (tcp_opt_len >> 2));
4097                                 mss |= (tsflags << 11);
4098                         }
4099                 } else {
4100                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4101                                 int tsflags;
4102
4103                                 tsflags = ((skb->nh.iph->ihl - 5) +
4104                                            (tcp_opt_len >> 2));
4105                                 base_flags |= tsflags << 12;
4106                         }
4107                 }
4108         }
4109 #if TG3_VLAN_TAG_USED
4110         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4111                 base_flags |= (TXD_FLAG_VLAN |
4112                                (vlan_tx_tag_get(skb) << 16));
4113 #endif
4114
4115         /* Queue skb data, a.k.a. the main skb fragment. */
4116         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4117
4118         tp->tx_buffers[entry].skb = skb;
4119         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4120
4121         would_hit_hwbug = 0;
4122
4123         if (tg3_4g_overflow_test(mapping, len))
4124                 would_hit_hwbug = 1;
4125
4126         tg3_set_txd(tp, entry, mapping, len, base_flags,
4127                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4128
4129         entry = NEXT_TX(entry);
4130
4131         /* Now loop through additional data fragments, and queue them. */
4132         if (skb_shinfo(skb)->nr_frags > 0) {
4133                 unsigned int i, last;
4134
4135                 last = skb_shinfo(skb)->nr_frags - 1;
4136                 for (i = 0; i <= last; i++) {
4137                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4138
4139                         len = frag->size;
4140                         mapping = pci_map_page(tp->pdev,
4141                                                frag->page,
4142                                                frag->page_offset,
4143                                                len, PCI_DMA_TODEVICE);
4144
4145                         tp->tx_buffers[entry].skb = NULL;
4146                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4147
4148                         if (tg3_4g_overflow_test(mapping, len))
4149                                 would_hit_hwbug = 1;
4150
4151                         if (tg3_40bit_overflow_test(tp, mapping, len))
4152                                 would_hit_hwbug = 1;
4153
4154                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4155                                 tg3_set_txd(tp, entry, mapping, len,
4156                                             base_flags, (i == last)|(mss << 1));
4157                         else
4158                                 tg3_set_txd(tp, entry, mapping, len,
4159                                             base_flags, (i == last));
4160
4161                         entry = NEXT_TX(entry);
4162                 }
4163         }
4164
4165         if (would_hit_hwbug) {
4166                 u32 last_plus_one = entry;
4167                 u32 start;
4168
4169                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4170                 start &= (TG3_TX_RING_SIZE - 1);
4171
4172                 /* If the workaround fails due to memory/mapping
4173                  * failure, silently drop this packet.
4174                  */
4175                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4176                                                 &start, base_flags, mss))
4177                         goto out_unlock;
4178
4179                 entry = start;
4180         }
4181
4182         /* Packets are ready, update Tx producer idx local and on card. */
4183         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4184
4185         tp->tx_prod = entry;
4186         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4187                 netif_stop_queue(dev);
4188                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4189                         netif_wake_queue(tp->dev);
4190         }
4191
4192 out_unlock:
4193         mmiowb();
4194
4195         dev->trans_start = jiffies;
4196
4197         return NETDEV_TX_OK;
4198 }
4199
4200 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4201                                int new_mtu)
4202 {
4203         dev->mtu = new_mtu;
4204
4205         if (new_mtu > ETH_DATA_LEN) {
4206                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4207                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4208                         ethtool_op_set_tso(dev, 0);
4209                 }
4210                 else
4211                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4212         } else {
4213                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4214                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4215                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4216         }
4217 }
4218
4219 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4220 {
4221         struct tg3 *tp = netdev_priv(dev);
4222         int err;
4223
4224         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4225                 return -EINVAL;
4226
4227         if (!netif_running(dev)) {
4228                 /* We'll just catch it later when the
4229                  * device is up'd.
4230                  */
4231                 tg3_set_mtu(dev, tp, new_mtu);
4232                 return 0;
4233         }
4234
4235         tg3_netif_stop(tp);
4236
4237         tg3_full_lock(tp, 1);
4238
4239         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4240
4241         tg3_set_mtu(dev, tp, new_mtu);
4242
4243         err = tg3_restart_hw(tp, 0);
4244
4245         if (!err)
4246                 tg3_netif_start(tp);
4247
4248         tg3_full_unlock(tp);
4249
4250         return err;
4251 }
4252
4253 /* Free up pending packets in all rx/tx rings.
4254  *
4255  * The chip has been shut down and the driver detached from
4256  * the networking, so no interrupts or new tx packets will
4257  * end up in the driver.  tp->{tx,}lock is not held and we are not
4258  * in an interrupt context and thus may sleep.
4259  */
4260 static void tg3_free_rings(struct tg3 *tp)
4261 {
4262         struct ring_info *rxp;
4263         int i;
4264
4265         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4266                 rxp = &tp->rx_std_buffers[i];
4267
4268                 if (rxp->skb == NULL)
4269                         continue;
4270                 pci_unmap_single(tp->pdev,
4271                                  pci_unmap_addr(rxp, mapping),
4272                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4273                                  PCI_DMA_FROMDEVICE);
4274                 dev_kfree_skb_any(rxp->skb);
4275                 rxp->skb = NULL;
4276         }
4277
4278         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4279                 rxp = &tp->rx_jumbo_buffers[i];
4280
4281                 if (rxp->skb == NULL)
4282                         continue;
4283                 pci_unmap_single(tp->pdev,
4284                                  pci_unmap_addr(rxp, mapping),
4285                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4286                                  PCI_DMA_FROMDEVICE);
4287                 dev_kfree_skb_any(rxp->skb);
4288                 rxp->skb = NULL;
4289         }
4290
4291         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4292                 struct tx_ring_info *txp;
4293                 struct sk_buff *skb;
4294                 int j;
4295
4296                 txp = &tp->tx_buffers[i];
4297                 skb = txp->skb;
4298
4299                 if (skb == NULL) {
4300                         i++;
4301                         continue;
4302                 }
4303
4304                 pci_unmap_single(tp->pdev,
4305                                  pci_unmap_addr(txp, mapping),
4306                                  skb_headlen(skb),
4307                                  PCI_DMA_TODEVICE);
4308                 txp->skb = NULL;
4309
4310                 i++;
4311
4312                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4313                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4314                         pci_unmap_page(tp->pdev,
4315                                        pci_unmap_addr(txp, mapping),
4316                                        skb_shinfo(skb)->frags[j].size,
4317                                        PCI_DMA_TODEVICE);
4318                         i++;
4319                 }
4320
4321                 dev_kfree_skb_any(skb);
4322         }
4323 }
4324
4325 /* Initialize tx/rx rings for packet processing.
4326  *
4327  * The chip has been shut down and the driver detached from
4328  * the networking, so no interrupts or new tx packets will
4329  * end up in the driver.  tp->{tx,}lock are held and thus
4330  * we may not sleep.
4331  */
4332 static int tg3_init_rings(struct tg3 *tp)
4333 {
4334         u32 i;
4335
4336         /* Free up all the SKBs. */
4337         tg3_free_rings(tp);
4338
4339         /* Zero out all descriptors. */
4340         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4341         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4342         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4343         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4344
4345         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4346         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4347             (tp->dev->mtu > ETH_DATA_LEN))
4348                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4349
4350         /* Initialize invariants of the rings, we only set this
4351          * stuff once.  This works because the card does not
4352          * write into the rx buffer posting rings.
4353          */
4354         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4355                 struct tg3_rx_buffer_desc *rxd;
4356
4357                 rxd = &tp->rx_std[i];
4358                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4359                         << RXD_LEN_SHIFT;
4360                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4361                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4362                                (i << RXD_OPAQUE_INDEX_SHIFT));
4363         }
4364
4365         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4366                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4367                         struct tg3_rx_buffer_desc *rxd;
4368
4369                         rxd = &tp->rx_jumbo[i];
4370                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4371                                 << RXD_LEN_SHIFT;
4372                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4373                                 RXD_FLAG_JUMBO;
4374                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4375                                (i << RXD_OPAQUE_INDEX_SHIFT));
4376                 }
4377         }
4378
4379         /* Now allocate fresh SKBs for each rx ring. */
4380         for (i = 0; i < tp->rx_pending; i++) {
4381                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4382                         printk(KERN_WARNING PFX
4383                                "%s: Using a smaller RX standard ring, "
4384                                "only %d out of %d buffers were allocated "
4385                                "successfully.\n",
4386                                tp->dev->name, i, tp->rx_pending);
4387                         if (i == 0)
4388                                 return -ENOMEM;
4389                         tp->rx_pending = i;
4390                         break;
4391                 }
4392         }
4393
4394         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4395                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4396                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4397                                              -1, i) < 0) {
4398                                 printk(KERN_WARNING PFX
4399                                        "%s: Using a smaller RX jumbo ring, "
4400                                        "only %d out of %d buffers were "
4401                                        "allocated successfully.\n",
4402                                        tp->dev->name, i, tp->rx_jumbo_pending);
4403                                 if (i == 0) {
4404                                         tg3_free_rings(tp);
4405                                         return -ENOMEM;
4406                                 }
4407                                 tp->rx_jumbo_pending = i;
4408                                 break;
4409                         }
4410                 }
4411         }
4412         return 0;
4413 }
4414
4415 /*
4416  * Must not be invoked with interrupt sources disabled and
4417  * the hardware shutdown down.
4418  */
4419 static void tg3_free_consistent(struct tg3 *tp)
4420 {
4421         kfree(tp->rx_std_buffers);
4422         tp->rx_std_buffers = NULL;
4423         if (tp->rx_std) {
4424                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4425                                     tp->rx_std, tp->rx_std_mapping);
4426                 tp->rx_std = NULL;
4427         }
4428         if (tp->rx_jumbo) {
4429                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4430                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4431                 tp->rx_jumbo = NULL;
4432         }
4433         if (tp->rx_rcb) {
4434                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4435                                     tp->rx_rcb, tp->rx_rcb_mapping);
4436                 tp->rx_rcb = NULL;
4437         }
4438         if (tp->tx_ring) {
4439                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4440                         tp->tx_ring, tp->tx_desc_mapping);
4441                 tp->tx_ring = NULL;
4442         }
4443         if (tp->hw_status) {
4444                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4445                                     tp->hw_status, tp->status_mapping);
4446                 tp->hw_status = NULL;
4447         }
4448         if (tp->hw_stats) {
4449                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4450                                     tp->hw_stats, tp->stats_mapping);
4451                 tp->hw_stats = NULL;
4452         }
4453 }
4454
4455 /*
4456  * Must not be invoked with interrupt sources disabled and
4457  * the hardware shutdown down.  Can sleep.
4458  */
4459 static int tg3_alloc_consistent(struct tg3 *tp)
4460 {
4461         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4462                                       (TG3_RX_RING_SIZE +
4463                                        TG3_RX_JUMBO_RING_SIZE)) +
4464                                      (sizeof(struct tx_ring_info) *
4465                                       TG3_TX_RING_SIZE),
4466                                      GFP_KERNEL);
4467         if (!tp->rx_std_buffers)
4468                 return -ENOMEM;
4469
4470         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4471         tp->tx_buffers = (struct tx_ring_info *)
4472                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4473
4474         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4475                                           &tp->rx_std_mapping);
4476         if (!tp->rx_std)
4477                 goto err_out;
4478
4479         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4480                                             &tp->rx_jumbo_mapping);
4481
4482         if (!tp->rx_jumbo)
4483                 goto err_out;
4484
4485         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4486                                           &tp->rx_rcb_mapping);
4487         if (!tp->rx_rcb)
4488                 goto err_out;
4489
4490         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4491                                            &tp->tx_desc_mapping);
4492         if (!tp->tx_ring)
4493                 goto err_out;
4494
4495         tp->hw_status = pci_alloc_consistent(tp->pdev,
4496                                              TG3_HW_STATUS_SIZE,
4497                                              &tp->status_mapping);
4498         if (!tp->hw_status)
4499                 goto err_out;
4500
4501         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4502                                             sizeof(struct tg3_hw_stats),
4503                                             &tp->stats_mapping);
4504         if (!tp->hw_stats)
4505                 goto err_out;
4506
4507         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4508         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4509
4510         return 0;
4511
4512 err_out:
4513         tg3_free_consistent(tp);
4514         return -ENOMEM;
4515 }
4516
4517 #define MAX_WAIT_CNT 1000
4518
4519 /* To stop a block, clear the enable bit and poll till it
4520  * clears.  tp->lock is held.
4521  */
4522 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4523 {
4524         unsigned int i;
4525         u32 val;
4526
4527         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4528                 switch (ofs) {
4529                 case RCVLSC_MODE:
4530                 case DMAC_MODE:
4531                 case MBFREE_MODE:
4532                 case BUFMGR_MODE:
4533                 case MEMARB_MODE:
4534                         /* We can't enable/disable these bits of the
4535                          * 5705/5750, just say success.
4536                          */
4537                         return 0;
4538
4539                 default:
4540                         break;
4541                 };
4542         }
4543
4544         val = tr32(ofs);
4545         val &= ~enable_bit;
4546         tw32_f(ofs, val);
4547
4548         for (i = 0; i < MAX_WAIT_CNT; i++) {
4549                 udelay(100);
4550                 val = tr32(ofs);
4551                 if ((val & enable_bit) == 0)
4552                         break;
4553         }
4554
4555         if (i == MAX_WAIT_CNT && !silent) {
4556                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4557                        "ofs=%lx enable_bit=%x\n",
4558                        ofs, enable_bit);
4559                 return -ENODEV;
4560         }
4561
4562         return 0;
4563 }
4564
4565 /* tp->lock is held. */
4566 static int tg3_abort_hw(struct tg3 *tp, int silent)
4567 {
4568         int i, err;
4569
4570         tg3_disable_ints(tp);
4571
4572         tp->rx_mode &= ~RX_MODE_ENABLE;
4573         tw32_f(MAC_RX_MODE, tp->rx_mode);
4574         udelay(10);
4575
4576         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4577         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4578         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4579         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4580         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4581         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4582
4583         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4584         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4585         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4586         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4587         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4588         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4589         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4590
4591         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4592         tw32_f(MAC_MODE, tp->mac_mode);
4593         udelay(40);
4594
4595         tp->tx_mode &= ~TX_MODE_ENABLE;
4596         tw32_f(MAC_TX_MODE, tp->tx_mode);
4597
4598         for (i = 0; i < MAX_WAIT_CNT; i++) {
4599                 udelay(100);
4600                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4601                         break;
4602         }
4603         if (i >= MAX_WAIT_CNT) {
4604                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4605                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4606                        tp->dev->name, tr32(MAC_TX_MODE));
4607                 err |= -ENODEV;
4608         }
4609
4610         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4611         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4612         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4613
4614         tw32(FTQ_RESET, 0xffffffff);
4615         tw32(FTQ_RESET, 0x00000000);
4616
4617         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4618         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4619
4620         if (tp->hw_status)
4621                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4622         if (tp->hw_stats)
4623                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4624
4625         return err;
4626 }
4627
4628 /* tp->lock is held. */
4629 static int tg3_nvram_lock(struct tg3 *tp)
4630 {
4631         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4632                 int i;
4633
4634                 if (tp->nvram_lock_cnt == 0) {
4635                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4636                         for (i = 0; i < 8000; i++) {
4637                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4638                                         break;
4639                                 udelay(20);
4640                         }
4641                         if (i == 8000) {
4642                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4643                                 return -ENODEV;
4644                         }
4645                 }
4646                 tp->nvram_lock_cnt++;
4647         }
4648         return 0;
4649 }
4650
4651 /* tp->lock is held. */
4652 static void tg3_nvram_unlock(struct tg3 *tp)
4653 {
4654         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4655                 if (tp->nvram_lock_cnt > 0)
4656                         tp->nvram_lock_cnt--;
4657                 if (tp->nvram_lock_cnt == 0)
4658                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4659         }
4660 }
4661
4662 /* tp->lock is held. */
4663 static void tg3_enable_nvram_access(struct tg3 *tp)
4664 {
4665         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4666             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4667                 u32 nvaccess = tr32(NVRAM_ACCESS);
4668
4669                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4670         }
4671 }
4672
4673 /* tp->lock is held. */
4674 static void tg3_disable_nvram_access(struct tg3 *tp)
4675 {
4676         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4677             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4678                 u32 nvaccess = tr32(NVRAM_ACCESS);
4679
4680                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4681         }
4682 }
4683
4684 /* tp->lock is held. */
4685 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4686 {
4687         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4688                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4689
4690         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4691                 switch (kind) {
4692                 case RESET_KIND_INIT:
4693                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4694                                       DRV_STATE_START);
4695                         break;
4696
4697                 case RESET_KIND_SHUTDOWN:
4698                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4699                                       DRV_STATE_UNLOAD);
4700                         break;
4701
4702                 case RESET_KIND_SUSPEND:
4703                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4704                                       DRV_STATE_SUSPEND);
4705                         break;
4706
4707                 default:
4708                         break;
4709                 };
4710         }
4711 }
4712
4713 /* tp->lock is held. */
4714 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4715 {
4716         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4717                 switch (kind) {
4718                 case RESET_KIND_INIT:
4719                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4720                                       DRV_STATE_START_DONE);
4721                         break;
4722
4723                 case RESET_KIND_SHUTDOWN:
4724                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4725                                       DRV_STATE_UNLOAD_DONE);
4726                         break;
4727
4728                 default:
4729                         break;
4730                 };
4731         }
4732 }
4733
4734 /* tp->lock is held. */
4735 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4736 {
4737         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4738                 switch (kind) {
4739                 case RESET_KIND_INIT:
4740                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4741                                       DRV_STATE_START);
4742                         break;
4743
4744                 case RESET_KIND_SHUTDOWN:
4745                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4746                                       DRV_STATE_UNLOAD);
4747                         break;
4748
4749                 case RESET_KIND_SUSPEND:
4750                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4751                                       DRV_STATE_SUSPEND);
4752                         break;
4753
4754                 default:
4755                         break;
4756                 };
4757         }
4758 }
4759
4760 static int tg3_poll_fw(struct tg3 *tp)
4761 {
4762         int i;
4763         u32 val;
4764
4765         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4766                 /* Wait up to 20ms for init done. */
4767                 for (i = 0; i < 200; i++) {
4768                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4769                                 return 0;
4770                         udelay(100);
4771                 }
4772                 return -ENODEV;
4773         }
4774
4775         /* Wait for firmware initialization to complete. */
4776         for (i = 0; i < 100000; i++) {
4777                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4778                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4779                         break;
4780                 udelay(10);
4781         }
4782
4783         /* Chip might not be fitted with firmware.  Some Sun onboard
4784          * parts are configured like that.  So don't signal the timeout
4785          * of the above loop as an error, but do report the lack of
4786          * running firmware once.
4787          */
4788         if (i >= 100000 &&
4789             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4790                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4791
4792                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4793                        tp->dev->name);
4794         }
4795
4796         return 0;
4797 }
4798
4799 static void tg3_stop_fw(struct tg3 *);
4800
4801 /* tp->lock is held. */
4802 static int tg3_chip_reset(struct tg3 *tp)
4803 {
4804         u32 val;
4805         void (*write_op)(struct tg3 *, u32, u32);
4806         int err;
4807
4808         tg3_nvram_lock(tp);
4809
4810         /* No matching tg3_nvram_unlock() after this because
4811          * chip reset below will undo the nvram lock.
4812          */
4813         tp->nvram_lock_cnt = 0;
4814
4815         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4816             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4817             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4818                 tw32(GRC_FASTBOOT_PC, 0);
4819
4820         /*
4821          * We must avoid the readl() that normally takes place.
4822          * It locks machines, causes machine checks, and other
4823          * fun things.  So, temporarily disable the 5701
4824          * hardware workaround, while we do the reset.
4825          */
4826         write_op = tp->write32;
4827         if (write_op == tg3_write_flush_reg32)
4828                 tp->write32 = tg3_write32;
4829
4830         /* Prevent the irq handler from reading or writing PCI registers
4831          * during chip reset when the memory enable bit in the PCI command
4832          * register may be cleared.  The chip does not generate interrupt
4833          * at this time, but the irq handler may still be called due to irq
4834          * sharing or irqpoll.
4835          */
4836         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4837         tp->hw_status->status = 0;
4838         tp->hw_status->status_tag = 0;
4839         tp->last_tag = 0;
4840         smp_mb();
4841         synchronize_irq(tp->pdev->irq);
4842
4843         /* do the reset */
4844         val = GRC_MISC_CFG_CORECLK_RESET;
4845
4846         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4847                 if (tr32(0x7e2c) == 0x60) {
4848                         tw32(0x7e2c, 0x20);
4849                 }
4850                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4851                         tw32(GRC_MISC_CFG, (1 << 29));
4852                         val |= (1 << 29);
4853                 }
4854         }
4855
4856         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4857                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4858                 tw32(GRC_VCPU_EXT_CTRL,
4859                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4860         }
4861
4862         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4863                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4864         tw32(GRC_MISC_CFG, val);
4865
4866         /* restore 5701 hardware bug workaround write method */
4867         tp->write32 = write_op;
4868
4869         /* Unfortunately, we have to delay before the PCI read back.
4870          * Some 575X chips even will not respond to a PCI cfg access
4871          * when the reset command is given to the chip.
4872          *
4873          * How do these hardware designers expect things to work
4874          * properly if the PCI write is posted for a long period
4875          * of time?  It is always necessary to have some method by
4876          * which a register read back can occur to push the write
4877          * out which does the reset.
4878          *
4879          * For most tg3 variants the trick below was working.
4880          * Ho hum...
4881          */
4882         udelay(120);
4883
4884         /* Flush PCI posted writes.  The normal MMIO registers
4885          * are inaccessible at this time so this is the only
4886          * way to make this reliably (actually, this is no longer
4887          * the case, see above).  I tried to use indirect
4888          * register read/write but this upset some 5701 variants.
4889          */
4890         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4891
4892         udelay(120);
4893
4894         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4895                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4896                         int i;
4897                         u32 cfg_val;
4898
4899                         /* Wait for link training to complete.  */
4900                         for (i = 0; i < 5000; i++)
4901                                 udelay(100);
4902
4903                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4904                         pci_write_config_dword(tp->pdev, 0xc4,
4905                                                cfg_val | (1 << 15));
4906                 }
4907                 /* Set PCIE max payload size and clear error status.  */
4908                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4909         }
4910
4911         /* Re-enable indirect register accesses. */
4912         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4913                                tp->misc_host_ctrl);
4914
4915         /* Set MAX PCI retry to zero. */
4916         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4917         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4918             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4919                 val |= PCISTATE_RETRY_SAME_DMA;
4920         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4921
4922         pci_restore_state(tp->pdev);
4923
4924         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4925
4926         /* Make sure PCI-X relaxed ordering bit is clear. */
4927         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4928         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4929         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4930
4931         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4932                 u32 val;
4933
4934                 /* Chip reset on 5780 will reset MSI enable bit,
4935                  * so need to restore it.
4936                  */
4937                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4938                         u16 ctrl;
4939
4940                         pci_read_config_word(tp->pdev,
4941                                              tp->msi_cap + PCI_MSI_FLAGS,
4942                                              &ctrl);
4943                         pci_write_config_word(tp->pdev,
4944                                               tp->msi_cap + PCI_MSI_FLAGS,
4945                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4946                         val = tr32(MSGINT_MODE);
4947                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4948                 }
4949
4950                 val = tr32(MEMARB_MODE);
4951                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4952
4953         } else
4954                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4955
4956         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4957                 tg3_stop_fw(tp);
4958                 tw32(0x5000, 0x400);
4959         }
4960
4961         tw32(GRC_MODE, tp->grc_mode);
4962
4963         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4964                 u32 val = tr32(0xc4);
4965
4966                 tw32(0xc4, val | (1 << 15));
4967         }
4968
4969         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4970             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4971                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4972                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4973                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4974                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4975         }
4976
4977         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4978                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4979                 tw32_f(MAC_MODE, tp->mac_mode);
4980         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4981                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4982                 tw32_f(MAC_MODE, tp->mac_mode);
4983         } else
4984                 tw32_f(MAC_MODE, 0);
4985         udelay(40);
4986
4987         err = tg3_poll_fw(tp);
4988         if (err)
4989                 return err;
4990
4991         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4992             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4993                 u32 val = tr32(0x7c00);
4994
4995                 tw32(0x7c00, val | (1 << 25));
4996         }
4997
4998         /* Reprobe ASF enable state.  */
4999         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5000         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5001         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5002         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5003                 u32 nic_cfg;
5004
5005                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5006                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5007                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5008                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5009                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5010                 }
5011         }
5012
5013         return 0;
5014 }
5015
5016 /* tp->lock is held. */
5017 static void tg3_stop_fw(struct tg3 *tp)
5018 {
5019         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5020                 u32 val;
5021                 int i;
5022
5023                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5024                 val = tr32(GRC_RX_CPU_EVENT);
5025                 val |= (1 << 14);
5026                 tw32(GRC_RX_CPU_EVENT, val);
5027
5028                 /* Wait for RX cpu to ACK the event.  */
5029                 for (i = 0; i < 100; i++) {
5030                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5031                                 break;
5032                         udelay(1);
5033                 }
5034         }
5035 }
5036
5037 /* tp->lock is held. */
5038 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5039 {
5040         int err;
5041
5042         tg3_stop_fw(tp);
5043
5044         tg3_write_sig_pre_reset(tp, kind);
5045
5046         tg3_abort_hw(tp, silent);
5047         err = tg3_chip_reset(tp);
5048
5049         tg3_write_sig_legacy(tp, kind);
5050         tg3_write_sig_post_reset(tp, kind);
5051
5052         if (err)
5053                 return err;
5054
5055         return 0;
5056 }
5057
5058 #define TG3_FW_RELEASE_MAJOR    0x0
5059 #define TG3_FW_RELASE_MINOR     0x0
5060 #define TG3_FW_RELEASE_FIX      0x0
5061 #define TG3_FW_START_ADDR       0x08000000
5062 #define TG3_FW_TEXT_ADDR        0x08000000
5063 #define TG3_FW_TEXT_LEN         0x9c0
5064 #define TG3_FW_RODATA_ADDR      0x080009c0
5065 #define TG3_FW_RODATA_LEN       0x60
5066 #define TG3_FW_DATA_ADDR        0x08000a40
5067 #define TG3_FW_DATA_LEN         0x20
5068 #define TG3_FW_SBSS_ADDR        0x08000a60
5069 #define TG3_FW_SBSS_LEN         0xc
5070 #define TG3_FW_BSS_ADDR         0x08000a70
5071 #define TG3_FW_BSS_LEN          0x10
5072
5073 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5074         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5075         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5076         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5077         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5078         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5079         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5080         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5081         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5082         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5083         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5084         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5085         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5086         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5087         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5088         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5089         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5090         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5091         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5092         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5093         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5094         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5095         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5096         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5097         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5098         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5099         0, 0, 0, 0, 0, 0,
5100         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5101         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5102         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5103         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5104         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5105         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5106         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5107         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5108         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5109         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5110         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5111         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5112         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5113         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5114         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5115         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5116         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5117         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5118         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5119         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5120         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5121         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5122         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5123         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5124         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5125         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5126         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5127         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5128         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5129         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5130         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5131         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5132         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5133         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5134         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5135         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5136         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5137         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5138         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5139         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5140         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5141         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5142         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5143         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5144         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5145         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5146         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5147         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5148         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5149         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5150         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5151         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5152         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5153         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5154         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5155         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5156         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5157         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5158         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5159         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5160         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5161         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5162         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5163         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5164         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5165 };
5166
5167 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5168         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5169         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5170         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5171         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5172         0x00000000
5173 };
5174
5175 #if 0 /* All zeros, don't eat up space with it. */
5176 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5177         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5178         0x00000000, 0x00000000, 0x00000000, 0x00000000
5179 };
5180 #endif
5181
5182 #define RX_CPU_SCRATCH_BASE     0x30000
5183 #define RX_CPU_SCRATCH_SIZE     0x04000
5184 #define TX_CPU_SCRATCH_BASE     0x34000
5185 #define TX_CPU_SCRATCH_SIZE     0x04000
5186
5187 /* tp->lock is held. */
5188 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5189 {
5190         int i;
5191
5192         BUG_ON(offset == TX_CPU_BASE &&
5193             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5194
5195         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5196                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5197
5198                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5199                 return 0;
5200         }
5201         if (offset == RX_CPU_BASE) {
5202                 for (i = 0; i < 10000; i++) {
5203                         tw32(offset + CPU_STATE, 0xffffffff);
5204                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5205                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5206                                 break;
5207                 }
5208
5209                 tw32(offset + CPU_STATE, 0xffffffff);
5210                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5211                 udelay(10);
5212         } else {
5213                 for (i = 0; i < 10000; i++) {
5214                         tw32(offset + CPU_STATE, 0xffffffff);
5215                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5216                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5217                                 break;
5218                 }
5219         }
5220
5221         if (i >= 10000) {
5222                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5223                        "and %s CPU\n",
5224                        tp->dev->name,
5225                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5226                 return -ENODEV;
5227         }
5228
5229         /* Clear firmware's nvram arbitration. */
5230         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5231                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5232         return 0;
5233 }
5234
5235 struct fw_info {
5236         unsigned int text_base;
5237         unsigned int text_len;
5238         const u32 *text_data;
5239         unsigned int rodata_base;
5240         unsigned int rodata_len;
5241         const u32 *rodata_data;
5242         unsigned int data_base;
5243         unsigned int data_len;
5244         const u32 *data_data;
5245 };
5246
5247 /* tp->lock is held. */
5248 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5249                                  int cpu_scratch_size, struct fw_info *info)
5250 {
5251         int err, lock_err, i;
5252         void (*write_op)(struct tg3 *, u32, u32);
5253
5254         if (cpu_base == TX_CPU_BASE &&
5255             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5256                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5257                        "TX cpu firmware on %s which is 5705.\n",
5258                        tp->dev->name);
5259                 return -EINVAL;
5260         }
5261
5262         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5263                 write_op = tg3_write_mem;
5264         else
5265                 write_op = tg3_write_indirect_reg32;
5266
5267         /* It is possible that bootcode is still loading at this point.
5268          * Get the nvram lock first before halting the cpu.
5269          */
5270         lock_err = tg3_nvram_lock(tp);
5271         err = tg3_halt_cpu(tp, cpu_base);
5272         if (!lock_err)
5273                 tg3_nvram_unlock(tp);
5274         if (err)
5275                 goto out;
5276
5277         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5278                 write_op(tp, cpu_scratch_base + i, 0);
5279         tw32(cpu_base + CPU_STATE, 0xffffffff);
5280         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5281         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5282                 write_op(tp, (cpu_scratch_base +
5283                               (info->text_base & 0xffff) +
5284                               (i * sizeof(u32))),
5285                          (info->text_data ?
5286                           info->text_data[i] : 0));
5287         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5288                 write_op(tp, (cpu_scratch_base +
5289                               (info->rodata_base & 0xffff) +
5290                               (i * sizeof(u32))),
5291                          (info->rodata_data ?
5292                           info->rodata_data[i] : 0));
5293         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5294                 write_op(tp, (cpu_scratch_base +
5295                               (info->data_base & 0xffff) +
5296                               (i * sizeof(u32))),
5297                          (info->data_data ?
5298                           info->data_data[i] : 0));
5299
5300         err = 0;
5301
5302 out:
5303         return err;
5304 }
5305
5306 /* tp->lock is held. */
5307 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5308 {
5309         struct fw_info info;
5310         int err, i;
5311
5312         info.text_base = TG3_FW_TEXT_ADDR;
5313         info.text_len = TG3_FW_TEXT_LEN;
5314         info.text_data = &tg3FwText[0];
5315         info.rodata_base = TG3_FW_RODATA_ADDR;
5316         info.rodata_len = TG3_FW_RODATA_LEN;
5317         info.rodata_data = &tg3FwRodata[0];
5318         info.data_base = TG3_FW_DATA_ADDR;
5319         info.data_len = TG3_FW_DATA_LEN;
5320         info.data_data = NULL;
5321
5322         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5323                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5324                                     &info);
5325         if (err)
5326                 return err;
5327
5328         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5329                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5330                                     &info);
5331         if (err)
5332                 return err;
5333
5334         /* Now startup only the RX cpu. */
5335         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5336         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5337
5338         for (i = 0; i < 5; i++) {
5339                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5340                         break;
5341                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5342                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5343                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5344                 udelay(1000);
5345         }
5346         if (i >= 5) {
5347                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5348                        "to set RX CPU PC, is %08x should be %08x\n",
5349                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5350                        TG3_FW_TEXT_ADDR);
5351                 return -ENODEV;
5352         }
5353         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5354         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5355
5356         return 0;
5357 }
5358
5359
5360 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5361 #define TG3_TSO_FW_RELASE_MINOR         0x6
5362 #define TG3_TSO_FW_RELEASE_FIX          0x0
5363 #define TG3_TSO_FW_START_ADDR           0x08000000
5364 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5365 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5366 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5367 #define TG3_TSO_FW_RODATA_LEN           0x60
5368 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5369 #define TG3_TSO_FW_DATA_LEN             0x30
5370 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5371 #define TG3_TSO_FW_SBSS_LEN             0x2c
5372 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5373 #define TG3_TSO_FW_BSS_LEN              0x894
5374
5375 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5376         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5377         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5378         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5379         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5380         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5381         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5382         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5383         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5384         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5385         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5386         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5387         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5388         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5389         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5390         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5391         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5392         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5393         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5394         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5395         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5396         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5397         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5398         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5399         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5400         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5401         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5402         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5403         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5404         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5405         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5406         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5407         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5408         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5409         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5410         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5411         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5412         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5413         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5414         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5415         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5416         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5417         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5418         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5419         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5420         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5421         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5422         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5423         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5424         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5425         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5426         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5427         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5428         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5429         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5430         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5431         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5432         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5433         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5434         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5435         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5436         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5437         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5438         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5439         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5440         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5441         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5442         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5443         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5444         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5445         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5446         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5447         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5448         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5449         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5450         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5451         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5452         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5453         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5454         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5455         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5456         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5457         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5458         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5459         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5460         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5461         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5462         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5463         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5464         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5465         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5466         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5467         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5468         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5469         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5470         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5471         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5472         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5473         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5474         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5475         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5476         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5477         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5478         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5479         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5480         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5481         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5482         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5483         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5484         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5485         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5486         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5487         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5488         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5489         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5490         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5491         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5492         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5493         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5494         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5495         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5496         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5497         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5498         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5499         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5500         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5501         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5502         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5503         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5504         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5505         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5506         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5507         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5508         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5509         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5510         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5511         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5512         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5513         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5514         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5515         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5516         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5517         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5518         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5519         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5520         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5521         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5522         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5523         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5524         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5525         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5526         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5527         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5528         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5529         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5530         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5531         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5532         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5533         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5534         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5535         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5536         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5537         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5538         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5539         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5540         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5541         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5542         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5543         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5544         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5545         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5546         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5547         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5548         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5549         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5550         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5551         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5552         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5553         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5554         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5555         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5556         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5557         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5558         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5559         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5560         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5561         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5562         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5563         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5564         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5565         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5566         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5567         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5568         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5569         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5570         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5571         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5572         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5573         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5574         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5575         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5576         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5577         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5578         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5579         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5580         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5581         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5582         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5583         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5584         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5585         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5586         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5587         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5588         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5589         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5590         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5591         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5592         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5593         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5594         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5595         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5596         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5597         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5598         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5599         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5600         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5601         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5602         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5603         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5604         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5605         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5606         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5607         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5608         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5609         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5610         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5611         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5612         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5613         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5614         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5615         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5616         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5617         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5618         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5619         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5620         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5621         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5622         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5623         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5624         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5625         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5626         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5627         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5628         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5629         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5630         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5631         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5632         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5633         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5634         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5635         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5636         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5637         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5638         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5639         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5640         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5641         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5642         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5643         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5644         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5645         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5646         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5647         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5648         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5649         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5650         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5651         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5652         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5653         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5654         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5655         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5656         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5657         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5658         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5659         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5660 };
5661
5662 static const u32 tg3TsoFwRodata[] = {
5663         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5664         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5665         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5666         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5667         0x00000000,
5668 };
5669
5670 static const u32 tg3TsoFwData[] = {
5671         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5672         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5673         0x00000000,
5674 };
5675
5676 /* 5705 needs a special version of the TSO firmware.  */
5677 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5678 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5679 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5680 #define TG3_TSO5_FW_START_ADDR          0x00010000
5681 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5682 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5683 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5684 #define TG3_TSO5_FW_RODATA_LEN          0x50
5685 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5686 #define TG3_TSO5_FW_DATA_LEN            0x20
5687 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5688 #define TG3_TSO5_FW_SBSS_LEN            0x28
5689 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5690 #define TG3_TSO5_FW_BSS_LEN             0x88
5691
5692 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5693         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5694         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5695         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5696         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5697         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5698         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5699         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5700         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5701         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5702         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5703         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5704         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5705         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5706         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5707         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5708         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5709         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5710         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5711         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5712         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5713         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5714         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5715         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5716         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5717         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5718         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5719         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5720         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5721         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5722         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5723         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5724         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5725         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5726         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5727         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5728         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5729         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5730         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5731         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5732         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5733         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5734         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5735         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5736         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5737         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5738         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5739         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5740         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5741         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5742         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5743         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5744         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5745         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5746         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5747         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5748         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5749         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5750         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5751         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5752         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5753         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5754         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5755         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5756         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5757         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5758         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5759         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5760         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5761         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5762         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5763         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5764         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5765         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5766         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5767         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5768         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5769         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5770         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5771         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5772         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5773         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5774         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5775         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5776         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5777         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5778         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5779         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5780         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5781         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5782         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5783         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5784         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5785         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5786         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5787         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5788         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5789         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5790         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5791         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5792         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5793         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5794         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5795         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5796         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5797         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5798         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5799         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5800         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5801         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5802         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5803         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5804         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5805         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5806         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5807         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5808         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5809         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5810         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5811         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5812         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5813         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5814         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5815         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5816         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5817         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5818         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5819         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5820         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5821         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5822         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5823         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5824         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5825         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5826         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5827         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5828         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5829         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5830         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5831         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5832         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5833         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5834         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5835         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5836         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5837         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5838         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5839         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5840         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5841         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5842         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5843         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5844         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5845         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5846         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5847         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5848         0x00000000, 0x00000000, 0x00000000,
5849 };
5850
5851 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5852         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5853         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5854         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5855         0x00000000, 0x00000000, 0x00000000,
5856 };
5857
5858 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5859         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5860         0x00000000, 0x00000000, 0x00000000,
5861 };
5862
5863 /* tp->lock is held. */
5864 static int tg3_load_tso_firmware(struct tg3 *tp)
5865 {
5866         struct fw_info info;
5867         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5868         int err, i;
5869
5870         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5871                 return 0;
5872
5873         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5874                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5875                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5876                 info.text_data = &tg3Tso5FwText[0];
5877                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5878                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5879                 info.rodata_data = &tg3Tso5FwRodata[0];
5880                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5881                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5882                 info.data_data = &tg3Tso5FwData[0];
5883                 cpu_base = RX_CPU_BASE;
5884                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5885                 cpu_scratch_size = (info.text_len +
5886                                     info.rodata_len +
5887                                     info.data_len +
5888                                     TG3_TSO5_FW_SBSS_LEN +
5889                                     TG3_TSO5_FW_BSS_LEN);
5890         } else {
5891                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5892                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5893                 info.text_data = &tg3TsoFwText[0];
5894                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5895                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5896                 info.rodata_data = &tg3TsoFwRodata[0];
5897                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5898                 info.data_len = TG3_TSO_FW_DATA_LEN;
5899                 info.data_data = &tg3TsoFwData[0];
5900                 cpu_base = TX_CPU_BASE;
5901                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5902                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5903         }
5904
5905         err = tg3_load_firmware_cpu(tp, cpu_base,
5906                                     cpu_scratch_base, cpu_scratch_size,
5907                                     &info);
5908         if (err)
5909                 return err;
5910
5911         /* Now startup the cpu. */
5912         tw32(cpu_base + CPU_STATE, 0xffffffff);
5913         tw32_f(cpu_base + CPU_PC,    info.text_base);
5914
5915         for (i = 0; i < 5; i++) {
5916                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5917                         break;
5918                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5919                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5920                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5921                 udelay(1000);
5922         }
5923         if (i >= 5) {
5924                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5925                        "to set CPU PC, is %08x should be %08x\n",
5926                        tp->dev->name, tr32(cpu_base + CPU_PC),
5927                        info.text_base);
5928                 return -ENODEV;
5929         }
5930         tw32(cpu_base + CPU_STATE, 0xffffffff);
5931         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5932         return 0;
5933 }
5934
5935
5936 /* tp->lock is held. */
5937 static void __tg3_set_mac_addr(struct tg3 *tp)
5938 {
5939         u32 addr_high, addr_low;
5940         int i;
5941
5942         addr_high = ((tp->dev->dev_addr[0] << 8) |
5943                      tp->dev->dev_addr[1]);
5944         addr_low = ((tp->dev->dev_addr[2] << 24) |
5945                     (tp->dev->dev_addr[3] << 16) |
5946                     (tp->dev->dev_addr[4] <<  8) |
5947                     (tp->dev->dev_addr[5] <<  0));
5948         for (i = 0; i < 4; i++) {
5949                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5950                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5951         }
5952
5953         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5954             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5955                 for (i = 0; i < 12; i++) {
5956                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5957                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5958                 }
5959         }
5960
5961         addr_high = (tp->dev->dev_addr[0] +
5962                      tp->dev->dev_addr[1] +
5963                      tp->dev->dev_addr[2] +
5964                      tp->dev->dev_addr[3] +
5965                      tp->dev->dev_addr[4] +
5966                      tp->dev->dev_addr[5]) &
5967                 TX_BACKOFF_SEED_MASK;
5968         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5969 }
5970
5971 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5972 {
5973         struct tg3 *tp = netdev_priv(dev);
5974         struct sockaddr *addr = p;
5975         int err = 0;
5976
5977         if (!is_valid_ether_addr(addr->sa_data))
5978                 return -EINVAL;
5979
5980         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5981
5982         if (!netif_running(dev))
5983                 return 0;
5984
5985         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5986                 /* Reset chip so that ASF can re-init any MAC addresses it
5987                  * needs.
5988                  */
5989                 tg3_netif_stop(tp);
5990                 tg3_full_lock(tp, 1);
5991
5992                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5993                 err = tg3_restart_hw(tp, 0);
5994                 if (!err)
5995                         tg3_netif_start(tp);
5996                 tg3_full_unlock(tp);
5997         } else {
5998                 spin_lock_bh(&tp->lock);
5999                 __tg3_set_mac_addr(tp);
6000                 spin_unlock_bh(&tp->lock);
6001         }
6002
6003         return err;
6004 }
6005
6006 /* tp->lock is held. */
6007 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6008                            dma_addr_t mapping, u32 maxlen_flags,
6009                            u32 nic_addr)
6010 {
6011         tg3_write_mem(tp,
6012                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6013                       ((u64) mapping >> 32));
6014         tg3_write_mem(tp,
6015                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6016                       ((u64) mapping & 0xffffffff));
6017         tg3_write_mem(tp,
6018                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6019                        maxlen_flags);
6020
6021         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6022                 tg3_write_mem(tp,
6023                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6024                               nic_addr);
6025 }
6026
6027 static void __tg3_set_rx_mode(struct net_device *);
6028 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6029 {
6030         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6031         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6032         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6033         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6034         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6035                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6036                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6037         }
6038         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6039         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6040         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6041                 u32 val = ec->stats_block_coalesce_usecs;
6042
6043                 if (!netif_carrier_ok(tp->dev))
6044                         val = 0;
6045
6046                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6047         }
6048 }
6049
6050 /* tp->lock is held. */
6051 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6052 {
6053         u32 val, rdmac_mode;
6054         int i, err, limit;
6055
6056         tg3_disable_ints(tp);
6057
6058         tg3_stop_fw(tp);
6059
6060         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6061
6062         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6063                 tg3_abort_hw(tp, 1);
6064         }
6065
6066         if (reset_phy)
6067                 tg3_phy_reset(tp);
6068
6069         err = tg3_chip_reset(tp);
6070         if (err)
6071                 return err;
6072
6073         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6074
6075         /* This works around an issue with Athlon chipsets on
6076          * B3 tigon3 silicon.  This bit has no effect on any
6077          * other revision.  But do not set this on PCI Express
6078          * chips.
6079          */
6080         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6081                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6082         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6083
6084         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6085             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6086                 val = tr32(TG3PCI_PCISTATE);
6087                 val |= PCISTATE_RETRY_SAME_DMA;
6088                 tw32(TG3PCI_PCISTATE, val);
6089         }
6090
6091         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6092                 /* Enable some hw fixes.  */
6093                 val = tr32(TG3PCI_MSI_DATA);
6094                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6095                 tw32(TG3PCI_MSI_DATA, val);
6096         }
6097
6098         /* Descriptor ring init may make accesses to the
6099          * NIC SRAM area to setup the TX descriptors, so we
6100          * can only do this after the hardware has been
6101          * successfully reset.
6102          */
6103         err = tg3_init_rings(tp);
6104         if (err)
6105                 return err;
6106
6107         /* This value is determined during the probe time DMA
6108          * engine test, tg3_test_dma.
6109          */
6110         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6111
6112         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6113                           GRC_MODE_4X_NIC_SEND_RINGS |
6114                           GRC_MODE_NO_TX_PHDR_CSUM |
6115                           GRC_MODE_NO_RX_PHDR_CSUM);
6116         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6117
6118         /* Pseudo-header checksum is done by hardware logic and not
6119          * the offload processers, so make the chip do the pseudo-
6120          * header checksums on receive.  For transmit it is more
6121          * convenient to do the pseudo-header checksum in software
6122          * as Linux does that on transmit for us in all cases.
6123          */
6124         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6125
6126         tw32(GRC_MODE,
6127              tp->grc_mode |
6128              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6129
6130         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6131         val = tr32(GRC_MISC_CFG);
6132         val &= ~0xff;
6133         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6134         tw32(GRC_MISC_CFG, val);
6135
6136         /* Initialize MBUF/DESC pool. */
6137         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6138                 /* Do nothing.  */
6139         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6140                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6141                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6142                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6143                 else
6144                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6145                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6146                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6147         }
6148         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6149                 int fw_len;
6150
6151                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6152                           TG3_TSO5_FW_RODATA_LEN +
6153                           TG3_TSO5_FW_DATA_LEN +
6154                           TG3_TSO5_FW_SBSS_LEN +
6155                           TG3_TSO5_FW_BSS_LEN);
6156                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6157                 tw32(BUFMGR_MB_POOL_ADDR,
6158                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6159                 tw32(BUFMGR_MB_POOL_SIZE,
6160                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6161         }
6162
6163         if (tp->dev->mtu <= ETH_DATA_LEN) {
6164                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6165                      tp->bufmgr_config.mbuf_read_dma_low_water);
6166                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6167                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6168                 tw32(BUFMGR_MB_HIGH_WATER,
6169                      tp->bufmgr_config.mbuf_high_water);
6170         } else {
6171                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6172                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6173                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6174                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6175                 tw32(BUFMGR_MB_HIGH_WATER,
6176                      tp->bufmgr_config.mbuf_high_water_jumbo);
6177         }
6178         tw32(BUFMGR_DMA_LOW_WATER,
6179              tp->bufmgr_config.dma_low_water);
6180         tw32(BUFMGR_DMA_HIGH_WATER,
6181              tp->bufmgr_config.dma_high_water);
6182
6183         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6184         for (i = 0; i < 2000; i++) {
6185                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6186                         break;
6187                 udelay(10);
6188         }
6189         if (i >= 2000) {
6190                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6191                        tp->dev->name);
6192                 return -ENODEV;
6193         }
6194
6195         /* Setup replenish threshold. */
6196         val = tp->rx_pending / 8;
6197         if (val == 0)
6198                 val = 1;
6199         else if (val > tp->rx_std_max_post)
6200                 val = tp->rx_std_max_post;
6201         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6202                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6203                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6204
6205                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6206                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6207         }
6208
6209         tw32(RCVBDI_STD_THRESH, val);
6210
6211         /* Initialize TG3_BDINFO's at:
6212          *  RCVDBDI_STD_BD:     standard eth size rx ring
6213          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6214          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6215          *
6216          * like so:
6217          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6218          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6219          *                              ring attribute flags
6220          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6221          *
6222          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6223          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6224          *
6225          * The size of each ring is fixed in the firmware, but the location is
6226          * configurable.
6227          */
6228         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6229              ((u64) tp->rx_std_mapping >> 32));
6230         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6231              ((u64) tp->rx_std_mapping & 0xffffffff));
6232         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6233              NIC_SRAM_RX_BUFFER_DESC);
6234
6235         /* Don't even try to program the JUMBO/MINI buffer descriptor
6236          * configs on 5705.
6237          */
6238         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6239                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6240                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6241         } else {
6242                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6243                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6244
6245                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6246                      BDINFO_FLAGS_DISABLED);
6247
6248                 /* Setup replenish threshold. */
6249                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6250
6251                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6252                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6253                              ((u64) tp->rx_jumbo_mapping >> 32));
6254                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6255                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6256                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6257                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6258                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6259                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6260                 } else {
6261                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6262                              BDINFO_FLAGS_DISABLED);
6263                 }
6264
6265         }
6266
6267         /* There is only one send ring on 5705/5750, no need to explicitly
6268          * disable the others.
6269          */
6270         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6271                 /* Clear out send RCB ring in SRAM. */
6272                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6273                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6274                                       BDINFO_FLAGS_DISABLED);
6275         }
6276
6277         tp->tx_prod = 0;
6278         tp->tx_cons = 0;
6279         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6280         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6281
6282         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6283                        tp->tx_desc_mapping,
6284                        (TG3_TX_RING_SIZE <<
6285                         BDINFO_FLAGS_MAXLEN_SHIFT),
6286                        NIC_SRAM_TX_BUFFER_DESC);
6287
6288         /* There is only one receive return ring on 5705/5750, no need
6289          * to explicitly disable the others.
6290          */
6291         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6292                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6293                      i += TG3_BDINFO_SIZE) {
6294                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6295                                       BDINFO_FLAGS_DISABLED);
6296                 }
6297         }
6298
6299         tp->rx_rcb_ptr = 0;
6300         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6301
6302         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6303                        tp->rx_rcb_mapping,
6304                        (TG3_RX_RCB_RING_SIZE(tp) <<
6305                         BDINFO_FLAGS_MAXLEN_SHIFT),
6306                        0);
6307
6308         tp->rx_std_ptr = tp->rx_pending;
6309         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6310                      tp->rx_std_ptr);
6311
6312         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6313                                                 tp->rx_jumbo_pending : 0;
6314         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6315                      tp->rx_jumbo_ptr);
6316
6317         /* Initialize MAC address and backoff seed. */
6318         __tg3_set_mac_addr(tp);
6319
6320         /* MTU + ethernet header + FCS + optional VLAN tag */
6321         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6322
6323         /* The slot time is changed by tg3_setup_phy if we
6324          * run at gigabit with half duplex.
6325          */
6326         tw32(MAC_TX_LENGTHS,
6327              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6328              (6 << TX_LENGTHS_IPG_SHIFT) |
6329              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6330
6331         /* Receive rules. */
6332         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6333         tw32(RCVLPC_CONFIG, 0x0181);
6334
6335         /* Calculate RDMAC_MODE setting early, we need it to determine
6336          * the RCVLPC_STATE_ENABLE mask.
6337          */
6338         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6339                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6340                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6341                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6342                       RDMAC_MODE_LNGREAD_ENAB);
6343
6344         /* If statement applies to 5705 and 5750 PCI devices only */
6345         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6346              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6347             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6348                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6349                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6350                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6351                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6352                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6353                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6354                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6355                 }
6356         }
6357
6358         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6359                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6360
6361         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6362                 rdmac_mode |= (1 << 27);
6363
6364         /* Receive/send statistics. */
6365         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6366                 val = tr32(RCVLPC_STATS_ENABLE);
6367                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6368                 tw32(RCVLPC_STATS_ENABLE, val);
6369         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6370                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6371                 val = tr32(RCVLPC_STATS_ENABLE);
6372                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6373                 tw32(RCVLPC_STATS_ENABLE, val);
6374         } else {
6375                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6376         }
6377         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6378         tw32(SNDDATAI_STATSENAB, 0xffffff);
6379         tw32(SNDDATAI_STATSCTRL,
6380              (SNDDATAI_SCTRL_ENABLE |
6381               SNDDATAI_SCTRL_FASTUPD));
6382
6383         /* Setup host coalescing engine. */
6384         tw32(HOSTCC_MODE, 0);
6385         for (i = 0; i < 2000; i++) {
6386                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6387                         break;
6388                 udelay(10);
6389         }
6390
6391         __tg3_set_coalesce(tp, &tp->coal);
6392
6393         /* set status block DMA address */
6394         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6395              ((u64) tp->status_mapping >> 32));
6396         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6397              ((u64) tp->status_mapping & 0xffffffff));
6398
6399         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6400                 /* Status/statistics block address.  See tg3_timer,
6401                  * the tg3_periodic_fetch_stats call there, and
6402                  * tg3_get_stats to see how this works for 5705/5750 chips.
6403                  */
6404                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6405                      ((u64) tp->stats_mapping >> 32));
6406                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6407                      ((u64) tp->stats_mapping & 0xffffffff));
6408                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6409                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6410         }
6411
6412         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6413
6414         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6415         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6416         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6417                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6418
6419         /* Clear statistics/status block in chip, and status block in ram. */
6420         for (i = NIC_SRAM_STATS_BLK;
6421              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6422              i += sizeof(u32)) {
6423                 tg3_write_mem(tp, i, 0);
6424                 udelay(40);
6425         }
6426         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6427
6428         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6429                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6430                 /* reset to prevent losing 1st rx packet intermittently */
6431                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6432                 udelay(10);
6433         }
6434
6435         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6436                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6437         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6438         udelay(40);
6439
6440         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6441          * If TG3_FLG2_IS_NIC is zero, we should read the
6442          * register to preserve the GPIO settings for LOMs. The GPIOs,
6443          * whether used as inputs or outputs, are set by boot code after
6444          * reset.
6445          */
6446         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6447                 u32 gpio_mask;
6448
6449                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6450                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6451                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6452
6453                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6454                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6455                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6456
6457                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6458                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6459
6460                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6461
6462                 /* GPIO1 must be driven high for eeprom write protect */
6463                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6464                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6465                                                GRC_LCLCTRL_GPIO_OUTPUT1);
6466         }
6467         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6468         udelay(100);
6469
6470         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6471         tp->last_tag = 0;
6472
6473         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6474                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6475                 udelay(40);
6476         }
6477
6478         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6479                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6480                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6481                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6482                WDMAC_MODE_LNGREAD_ENAB);
6483
6484         /* If statement applies to 5705 and 5750 PCI devices only */
6485         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6486              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6487             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6488                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6489                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6490                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6491                         /* nothing */
6492                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6493                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6494                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6495                         val |= WDMAC_MODE_RX_ACCEL;
6496                 }
6497         }
6498
6499         /* Enable host coalescing bug fix */
6500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6501             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6502                 val |= (1 << 29);
6503
6504         tw32_f(WDMAC_MODE, val);
6505         udelay(40);
6506
6507         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6508                 val = tr32(TG3PCI_X_CAPS);
6509                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6510                         val &= ~PCIX_CAPS_BURST_MASK;
6511                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6512                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6513                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6514                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6515                 }
6516                 tw32(TG3PCI_X_CAPS, val);
6517         }
6518
6519         tw32_f(RDMAC_MODE, rdmac_mode);
6520         udelay(40);
6521
6522         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6523         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6524                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6525         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6526         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6527         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6528         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6529         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6530         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6531                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6532         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6533         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6534
6535         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6536                 err = tg3_load_5701_a0_firmware_fix(tp);
6537                 if (err)
6538                         return err;
6539         }
6540
6541         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6542                 err = tg3_load_tso_firmware(tp);
6543                 if (err)
6544                         return err;
6545         }
6546
6547         tp->tx_mode = TX_MODE_ENABLE;
6548         tw32_f(MAC_TX_MODE, tp->tx_mode);
6549         udelay(100);
6550
6551         tp->rx_mode = RX_MODE_ENABLE;
6552         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6553                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6554
6555         tw32_f(MAC_RX_MODE, tp->rx_mode);
6556         udelay(10);
6557
6558         if (tp->link_config.phy_is_low_power) {
6559                 tp->link_config.phy_is_low_power = 0;
6560                 tp->link_config.speed = tp->link_config.orig_speed;
6561                 tp->link_config.duplex = tp->link_config.orig_duplex;
6562                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6563         }
6564
6565         tp->mi_mode = MAC_MI_MODE_BASE;
6566         tw32_f(MAC_MI_MODE, tp->mi_mode);
6567         udelay(80);
6568
6569         tw32(MAC_LED_CTRL, tp->led_ctrl);
6570
6571         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6572         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6573                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6574                 udelay(10);
6575         }
6576         tw32_f(MAC_RX_MODE, tp->rx_mode);
6577         udelay(10);
6578
6579         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6580                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6581                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6582                         /* Set drive transmission level to 1.2V  */
6583                         /* only if the signal pre-emphasis bit is not set  */
6584                         val = tr32(MAC_SERDES_CFG);
6585                         val &= 0xfffff000;
6586                         val |= 0x880;
6587                         tw32(MAC_SERDES_CFG, val);
6588                 }
6589                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6590                         tw32(MAC_SERDES_CFG, 0x616000);
6591         }
6592
6593         /* Prevent chip from dropping frames when flow control
6594          * is enabled.
6595          */
6596         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6597
6598         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6599             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6600                 /* Use hardware link auto-negotiation */
6601                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6602         }
6603
6604         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6605             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6606                 u32 tmp;
6607
6608                 tmp = tr32(SERDES_RX_CTRL);
6609                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6610                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6611                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6612                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6613         }
6614
6615         err = tg3_setup_phy(tp, 0);
6616         if (err)
6617                 return err;
6618
6619         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6620             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6621                 u32 tmp;
6622
6623                 /* Clear CRC stats. */
6624                 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6625                         tg3_writephy(tp, MII_TG3_TEST1,
6626                                      tmp | MII_TG3_TEST1_CRC_EN);
6627                         tg3_readphy(tp, 0x14, &tmp);
6628                 }
6629         }
6630
6631         __tg3_set_rx_mode(tp->dev);
6632
6633         /* Initialize receive rules. */
6634         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6635         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6636         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6637         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6638
6639         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6640             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6641                 limit = 8;
6642         else
6643                 limit = 16;
6644         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6645                 limit -= 4;
6646         switch (limit) {
6647         case 16:
6648                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6649         case 15:
6650                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6651         case 14:
6652                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6653         case 13:
6654                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6655         case 12:
6656                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6657         case 11:
6658                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6659         case 10:
6660                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6661         case 9:
6662                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6663         case 8:
6664                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6665         case 7:
6666                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6667         case 6:
6668                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6669         case 5:
6670                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6671         case 4:
6672                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6673         case 3:
6674                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6675         case 2:
6676         case 1:
6677
6678         default:
6679                 break;
6680         };
6681
6682         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6683
6684         return 0;
6685 }
6686
6687 /* Called at device open time to get the chip ready for
6688  * packet processing.  Invoked with tp->lock held.
6689  */
6690 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6691 {
6692         int err;
6693
6694         /* Force the chip into D0. */
6695         err = tg3_set_power_state(tp, PCI_D0);
6696         if (err)
6697                 goto out;
6698
6699         tg3_switch_clocks(tp);
6700
6701         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6702
6703         err = tg3_reset_hw(tp, reset_phy);
6704
6705 out:
6706         return err;
6707 }
6708
6709 #define TG3_STAT_ADD32(PSTAT, REG) \
6710 do {    u32 __val = tr32(REG); \
6711         (PSTAT)->low += __val; \
6712         if ((PSTAT)->low < __val) \
6713                 (PSTAT)->high += 1; \
6714 } while (0)
6715
6716 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6717 {
6718         struct tg3_hw_stats *sp = tp->hw_stats;
6719
6720         if (!netif_carrier_ok(tp->dev))
6721                 return;
6722
6723         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6724         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6725         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6726         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6727         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6728         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6729         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6730         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6731         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6732         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6733         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6734         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6735         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6736
6737         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6738         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6739         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6740         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6741         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6742         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6743         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6744         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6745         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6746         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6747         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6748         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6749         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6750         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6751
6752         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6753         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6754         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6755 }
6756
6757 static void tg3_timer(unsigned long __opaque)
6758 {
6759         struct tg3 *tp = (struct tg3 *) __opaque;
6760
6761         if (tp->irq_sync)
6762                 goto restart_timer;
6763
6764         spin_lock(&tp->lock);
6765
6766         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6767                 /* All of this garbage is because when using non-tagged
6768                  * IRQ status the mailbox/status_block protocol the chip
6769                  * uses with the cpu is race prone.
6770                  */
6771                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6772                         tw32(GRC_LOCAL_CTRL,
6773                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6774                 } else {
6775                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6776                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6777                 }
6778
6779                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6780                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6781                         spin_unlock(&tp->lock);
6782                         schedule_work(&tp->reset_task);
6783                         return;
6784                 }
6785         }
6786
6787         /* This part only runs once per second. */
6788         if (!--tp->timer_counter) {
6789                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6790                         tg3_periodic_fetch_stats(tp);
6791
6792                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6793                         u32 mac_stat;
6794                         int phy_event;
6795
6796                         mac_stat = tr32(MAC_STATUS);
6797
6798                         phy_event = 0;
6799                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6800                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6801                                         phy_event = 1;
6802                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6803                                 phy_event = 1;
6804
6805                         if (phy_event)
6806                                 tg3_setup_phy(tp, 0);
6807                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6808                         u32 mac_stat = tr32(MAC_STATUS);
6809                         int need_setup = 0;
6810
6811                         if (netif_carrier_ok(tp->dev) &&
6812                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6813                                 need_setup = 1;
6814                         }
6815                         if (! netif_carrier_ok(tp->dev) &&
6816                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6817                                          MAC_STATUS_SIGNAL_DET))) {
6818                                 need_setup = 1;
6819                         }
6820                         if (need_setup) {
6821                                 if (!tp->serdes_counter) {
6822                                         tw32_f(MAC_MODE,
6823                                              (tp->mac_mode &
6824                                               ~MAC_MODE_PORT_MODE_MASK));
6825                                         udelay(40);
6826                                         tw32_f(MAC_MODE, tp->mac_mode);
6827                                         udelay(40);
6828                                 }
6829                                 tg3_setup_phy(tp, 0);
6830                         }
6831                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6832                         tg3_serdes_parallel_detect(tp);
6833
6834                 tp->timer_counter = tp->timer_multiplier;
6835         }
6836
6837         /* Heartbeat is only sent once every 2 seconds.
6838          *
6839          * The heartbeat is to tell the ASF firmware that the host
6840          * driver is still alive.  In the event that the OS crashes,
6841          * ASF needs to reset the hardware to free up the FIFO space
6842          * that may be filled with rx packets destined for the host.
6843          * If the FIFO is full, ASF will no longer function properly.
6844          *
6845          * Unintended resets have been reported on real time kernels
6846          * where the timer doesn't run on time.  Netpoll will also have
6847          * same problem.
6848          *
6849          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6850          * to check the ring condition when the heartbeat is expiring
6851          * before doing the reset.  This will prevent most unintended
6852          * resets.
6853          */
6854         if (!--tp->asf_counter) {
6855                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6856                         u32 val;
6857
6858                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6859                                       FWCMD_NICDRV_ALIVE3);
6860                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6861                         /* 5 seconds timeout */
6862                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6863                         val = tr32(GRC_RX_CPU_EVENT);
6864                         val |= (1 << 14);
6865                         tw32(GRC_RX_CPU_EVENT, val);
6866                 }
6867                 tp->asf_counter = tp->asf_multiplier;
6868         }
6869
6870         spin_unlock(&tp->lock);
6871
6872 restart_timer:
6873         tp->timer.expires = jiffies + tp->timer_offset;
6874         add_timer(&tp->timer);
6875 }
6876
6877 static int tg3_request_irq(struct tg3 *tp)
6878 {
6879         irq_handler_t fn;
6880         unsigned long flags;
6881         struct net_device *dev = tp->dev;
6882
6883         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6884                 fn = tg3_msi;
6885                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6886                         fn = tg3_msi_1shot;
6887                 flags = IRQF_SAMPLE_RANDOM;
6888         } else {
6889                 fn = tg3_interrupt;
6890                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6891                         fn = tg3_interrupt_tagged;
6892                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6893         }
6894         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6895 }
6896
6897 static int tg3_test_interrupt(struct tg3 *tp)
6898 {
6899         struct net_device *dev = tp->dev;
6900         int err, i, intr_ok = 0;
6901
6902         if (!netif_running(dev))
6903                 return -ENODEV;
6904
6905         tg3_disable_ints(tp);
6906
6907         free_irq(tp->pdev->irq, dev);
6908
6909         err = request_irq(tp->pdev->irq, tg3_test_isr,
6910                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6911         if (err)
6912                 return err;
6913
6914         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6915         tg3_enable_ints(tp);
6916
6917         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6918                HOSTCC_MODE_NOW);
6919
6920         for (i = 0; i < 5; i++) {
6921                 u32 int_mbox, misc_host_ctrl;
6922
6923                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6924                                         TG3_64BIT_REG_LOW);
6925                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6926
6927                 if ((int_mbox != 0) ||
6928                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6929                         intr_ok = 1;
6930                         break;
6931                 }
6932
6933                 msleep(10);
6934         }
6935
6936         tg3_disable_ints(tp);
6937
6938         free_irq(tp->pdev->irq, dev);
6939
6940         err = tg3_request_irq(tp);
6941
6942         if (err)
6943                 return err;
6944
6945         if (intr_ok)
6946                 return 0;
6947
6948         return -EIO;
6949 }
6950
6951 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6952  * successfully restored
6953  */
6954 static int tg3_test_msi(struct tg3 *tp)
6955 {
6956         struct net_device *dev = tp->dev;
6957         int err;
6958         u16 pci_cmd;
6959
6960         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6961                 return 0;
6962
6963         /* Turn off SERR reporting in case MSI terminates with Master
6964          * Abort.
6965          */
6966         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6967         pci_write_config_word(tp->pdev, PCI_COMMAND,
6968                               pci_cmd & ~PCI_COMMAND_SERR);
6969
6970         err = tg3_test_interrupt(tp);
6971
6972         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6973
6974         if (!err)
6975                 return 0;
6976
6977         /* other failures */
6978         if (err != -EIO)
6979                 return err;
6980
6981         /* MSI test failed, go back to INTx mode */
6982         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6983                "switching to INTx mode. Please report this failure to "
6984                "the PCI maintainer and include system chipset information.\n",
6985                        tp->dev->name);
6986
6987         free_irq(tp->pdev->irq, dev);
6988         pci_disable_msi(tp->pdev);
6989
6990         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6991
6992         err = tg3_request_irq(tp);
6993         if (err)
6994                 return err;
6995
6996         /* Need to reset the chip because the MSI cycle may have terminated
6997          * with Master Abort.
6998          */
6999         tg3_full_lock(tp, 1);
7000
7001         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7002         err = tg3_init_hw(tp, 1);
7003
7004         tg3_full_unlock(tp);
7005
7006         if (err)
7007                 free_irq(tp->pdev->irq, dev);
7008
7009         return err;
7010 }
7011
7012 static int tg3_open(struct net_device *dev)
7013 {
7014         struct tg3 *tp = netdev_priv(dev);
7015         int err;
7016
7017         netif_carrier_off(tp->dev);
7018
7019         tg3_full_lock(tp, 0);
7020
7021         err = tg3_set_power_state(tp, PCI_D0);
7022         if (err) {
7023                 tg3_full_unlock(tp);
7024                 return err;
7025         }
7026
7027         tg3_disable_ints(tp);
7028         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7029
7030         tg3_full_unlock(tp);
7031
7032         /* The placement of this call is tied
7033          * to the setup and use of Host TX descriptors.
7034          */
7035         err = tg3_alloc_consistent(tp);
7036         if (err)
7037                 return err;
7038
7039         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7040             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
7041             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7042             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7043               (tp->pdev_peer == tp->pdev))) {
7044                 /* All MSI supporting chips should support tagged
7045                  * status.  Assert that this is the case.
7046                  */
7047                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7048                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7049                                "Not using MSI.\n", tp->dev->name);
7050                 } else if (pci_enable_msi(tp->pdev) == 0) {
7051                         u32 msi_mode;
7052
7053                         msi_mode = tr32(MSGINT_MODE);
7054                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7055                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7056                 }
7057         }
7058         err = tg3_request_irq(tp);
7059
7060         if (err) {
7061                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7062                         pci_disable_msi(tp->pdev);
7063                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7064                 }
7065                 tg3_free_consistent(tp);
7066                 return err;
7067         }
7068
7069         tg3_full_lock(tp, 0);
7070
7071         err = tg3_init_hw(tp, 1);
7072         if (err) {
7073                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7074                 tg3_free_rings(tp);
7075         } else {
7076                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7077                         tp->timer_offset = HZ;
7078                 else
7079                         tp->timer_offset = HZ / 10;
7080
7081                 BUG_ON(tp->timer_offset > HZ);
7082                 tp->timer_counter = tp->timer_multiplier =
7083                         (HZ / tp->timer_offset);
7084                 tp->asf_counter = tp->asf_multiplier =
7085                         ((HZ / tp->timer_offset) * 2);
7086
7087                 init_timer(&tp->timer);
7088                 tp->timer.expires = jiffies + tp->timer_offset;
7089                 tp->timer.data = (unsigned long) tp;
7090                 tp->timer.function = tg3_timer;
7091         }
7092
7093         tg3_full_unlock(tp);
7094
7095         if (err) {
7096                 free_irq(tp->pdev->irq, dev);
7097                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7098                         pci_disable_msi(tp->pdev);
7099                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7100                 }
7101                 tg3_free_consistent(tp);
7102                 return err;
7103         }
7104
7105         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7106                 err = tg3_test_msi(tp);
7107
7108                 if (err) {
7109                         tg3_full_lock(tp, 0);
7110
7111                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7112                                 pci_disable_msi(tp->pdev);
7113                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7114                         }
7115                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7116                         tg3_free_rings(tp);
7117                         tg3_free_consistent(tp);
7118
7119                         tg3_full_unlock(tp);
7120
7121                         return err;
7122                 }
7123
7124                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7125                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7126                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7127
7128                                 tw32(PCIE_TRANSACTION_CFG,
7129                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7130                         }
7131                 }
7132         }
7133
7134         tg3_full_lock(tp, 0);
7135
7136         add_timer(&tp->timer);
7137         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7138         tg3_enable_ints(tp);
7139
7140         tg3_full_unlock(tp);
7141
7142         netif_start_queue(dev);
7143
7144         return 0;
7145 }
7146
7147 #if 0
7148 /*static*/ void tg3_dump_state(struct tg3 *tp)
7149 {
7150         u32 val32, val32_2, val32_3, val32_4, val32_5;
7151         u16 val16;
7152         int i;
7153
7154         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7155         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7156         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7157                val16, val32);
7158
7159         /* MAC block */
7160         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7161                tr32(MAC_MODE), tr32(MAC_STATUS));
7162         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7163                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7164         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7165                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7166         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7167                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7168
7169         /* Send data initiator control block */
7170         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7171                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7172         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7173                tr32(SNDDATAI_STATSCTRL));
7174
7175         /* Send data completion control block */
7176         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7177
7178         /* Send BD ring selector block */
7179         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7180                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7181
7182         /* Send BD initiator control block */
7183         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7184                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7185
7186         /* Send BD completion control block */
7187         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7188
7189         /* Receive list placement control block */
7190         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7191                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7192         printk("       RCVLPC_STATSCTRL[%08x]\n",
7193                tr32(RCVLPC_STATSCTRL));
7194
7195         /* Receive data and receive BD initiator control block */
7196         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7197                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7198
7199         /* Receive data completion control block */
7200         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7201                tr32(RCVDCC_MODE));
7202
7203         /* Receive BD initiator control block */
7204         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7205                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7206
7207         /* Receive BD completion control block */
7208         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7209                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7210
7211         /* Receive list selector control block */
7212         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7213                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7214
7215         /* Mbuf cluster free block */
7216         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7217                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7218
7219         /* Host coalescing control block */
7220         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7221                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7222         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7223                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7224                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7225         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7226                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7227                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7228         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7229                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7230         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7231                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7232
7233         /* Memory arbiter control block */
7234         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7235                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7236
7237         /* Buffer manager control block */
7238         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7239                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7240         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7241                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7242         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7243                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7244                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7245                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7246
7247         /* Read DMA control block */
7248         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7249                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7250
7251         /* Write DMA control block */
7252         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7253                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7254
7255         /* DMA completion block */
7256         printk("DEBUG: DMAC_MODE[%08x]\n",
7257                tr32(DMAC_MODE));
7258
7259         /* GRC block */
7260         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7261                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7262         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7263                tr32(GRC_LOCAL_CTRL));
7264
7265         /* TG3_BDINFOs */
7266         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7267                tr32(RCVDBDI_JUMBO_BD + 0x0),
7268                tr32(RCVDBDI_JUMBO_BD + 0x4),
7269                tr32(RCVDBDI_JUMBO_BD + 0x8),
7270                tr32(RCVDBDI_JUMBO_BD + 0xc));
7271         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7272                tr32(RCVDBDI_STD_BD + 0x0),
7273                tr32(RCVDBDI_STD_BD + 0x4),
7274                tr32(RCVDBDI_STD_BD + 0x8),
7275                tr32(RCVDBDI_STD_BD + 0xc));
7276         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7277                tr32(RCVDBDI_MINI_BD + 0x0),
7278                tr32(RCVDBDI_MINI_BD + 0x4),
7279                tr32(RCVDBDI_MINI_BD + 0x8),
7280                tr32(RCVDBDI_MINI_BD + 0xc));
7281
7282         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7283         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7284         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7285         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7286         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7287                val32, val32_2, val32_3, val32_4);
7288
7289         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7290         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7291         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7292         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7293         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7294                val32, val32_2, val32_3, val32_4);
7295
7296         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7297         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7298         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7299         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7300         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7301         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7302                val32, val32_2, val32_3, val32_4, val32_5);
7303
7304         /* SW status block */
7305         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7306                tp->hw_status->status,
7307                tp->hw_status->status_tag,
7308                tp->hw_status->rx_jumbo_consumer,
7309                tp->hw_status->rx_consumer,
7310                tp->hw_status->rx_mini_consumer,
7311                tp->hw_status->idx[0].rx_producer,
7312                tp->hw_status->idx[0].tx_consumer);
7313
7314         /* SW statistics block */
7315         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7316                ((u32 *)tp->hw_stats)[0],
7317                ((u32 *)tp->hw_stats)[1],
7318                ((u32 *)tp->hw_stats)[2],
7319                ((u32 *)tp->hw_stats)[3]);
7320
7321         /* Mailboxes */
7322         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7323                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7324                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7325                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7326                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7327
7328         /* NIC side send descriptors. */
7329         for (i = 0; i < 6; i++) {
7330                 unsigned long txd;
7331
7332                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7333                         + (i * sizeof(struct tg3_tx_buffer_desc));
7334                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7335                        i,
7336                        readl(txd + 0x0), readl(txd + 0x4),
7337                        readl(txd + 0x8), readl(txd + 0xc));
7338         }
7339
7340         /* NIC side RX descriptors. */
7341         for (i = 0; i < 6; i++) {
7342                 unsigned long rxd;
7343
7344                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7345                         + (i * sizeof(struct tg3_rx_buffer_desc));
7346                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7347                        i,
7348                        readl(rxd + 0x0), readl(rxd + 0x4),
7349                        readl(rxd + 0x8), readl(rxd + 0xc));
7350                 rxd += (4 * sizeof(u32));
7351                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7352                        i,
7353                        readl(rxd + 0x0), readl(rxd + 0x4),
7354                        readl(rxd + 0x8), readl(rxd + 0xc));
7355         }
7356
7357         for (i = 0; i < 6; i++) {
7358                 unsigned long rxd;
7359
7360                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7361                         + (i * sizeof(struct tg3_rx_buffer_desc));
7362                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7363                        i,
7364                        readl(rxd + 0x0), readl(rxd + 0x4),
7365                        readl(rxd + 0x8), readl(rxd + 0xc));
7366                 rxd += (4 * sizeof(u32));
7367                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7368                        i,
7369                        readl(rxd + 0x0), readl(rxd + 0x4),
7370                        readl(rxd + 0x8), readl(rxd + 0xc));
7371         }
7372 }
7373 #endif
7374
7375 static struct net_device_stats *tg3_get_stats(struct net_device *);
7376 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7377
7378 static int tg3_close(struct net_device *dev)
7379 {
7380         struct tg3 *tp = netdev_priv(dev);
7381
7382         /* Calling flush_scheduled_work() may deadlock because
7383          * linkwatch_event() may be on the workqueue and it will try to get
7384          * the rtnl_lock which we are holding.
7385          */
7386         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7387                 msleep(1);
7388
7389         netif_stop_queue(dev);
7390
7391         del_timer_sync(&tp->timer);
7392
7393         tg3_full_lock(tp, 1);
7394 #if 0
7395         tg3_dump_state(tp);
7396 #endif
7397
7398         tg3_disable_ints(tp);
7399
7400         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7401         tg3_free_rings(tp);
7402         tp->tg3_flags &=
7403                 ~(TG3_FLAG_INIT_COMPLETE |
7404                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7405
7406         tg3_full_unlock(tp);
7407
7408         free_irq(tp->pdev->irq, dev);
7409         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7410                 pci_disable_msi(tp->pdev);
7411                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7412         }
7413
7414         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7415                sizeof(tp->net_stats_prev));
7416         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7417                sizeof(tp->estats_prev));
7418
7419         tg3_free_consistent(tp);
7420
7421         tg3_set_power_state(tp, PCI_D3hot);
7422
7423         netif_carrier_off(tp->dev);
7424
7425         return 0;
7426 }
7427
7428 static inline unsigned long get_stat64(tg3_stat64_t *val)
7429 {
7430         unsigned long ret;
7431
7432 #if (BITS_PER_LONG == 32)
7433         ret = val->low;
7434 #else
7435         ret = ((u64)val->high << 32) | ((u64)val->low);
7436 #endif
7437         return ret;
7438 }
7439
7440 static unsigned long calc_crc_errors(struct tg3 *tp)
7441 {
7442         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7443
7444         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7445             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7446              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7447                 u32 val;
7448
7449                 spin_lock_bh(&tp->lock);
7450                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7451                         tg3_writephy(tp, MII_TG3_TEST1,
7452                                      val | MII_TG3_TEST1_CRC_EN);
7453                         tg3_readphy(tp, 0x14, &val);
7454                 } else
7455                         val = 0;
7456                 spin_unlock_bh(&tp->lock);
7457
7458                 tp->phy_crc_errors += val;
7459
7460                 return tp->phy_crc_errors;
7461         }
7462
7463         return get_stat64(&hw_stats->rx_fcs_errors);
7464 }
7465
7466 #define ESTAT_ADD(member) \
7467         estats->member =        old_estats->member + \
7468                                 get_stat64(&hw_stats->member)
7469
7470 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7471 {
7472         struct tg3_ethtool_stats *estats = &tp->estats;
7473         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7474         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7475
7476         if (!hw_stats)
7477                 return old_estats;
7478
7479         ESTAT_ADD(rx_octets);
7480         ESTAT_ADD(rx_fragments);
7481         ESTAT_ADD(rx_ucast_packets);
7482         ESTAT_ADD(rx_mcast_packets);
7483         ESTAT_ADD(rx_bcast_packets);
7484         ESTAT_ADD(rx_fcs_errors);
7485         ESTAT_ADD(rx_align_errors);
7486         ESTAT_ADD(rx_xon_pause_rcvd);
7487         ESTAT_ADD(rx_xoff_pause_rcvd);
7488         ESTAT_ADD(rx_mac_ctrl_rcvd);
7489         ESTAT_ADD(rx_xoff_entered);
7490         ESTAT_ADD(rx_frame_too_long_errors);
7491         ESTAT_ADD(rx_jabbers);
7492         ESTAT_ADD(rx_undersize_packets);
7493         ESTAT_ADD(rx_in_length_errors);
7494         ESTAT_ADD(rx_out_length_errors);
7495         ESTAT_ADD(rx_64_or_less_octet_packets);
7496         ESTAT_ADD(rx_65_to_127_octet_packets);
7497         ESTAT_ADD(rx_128_to_255_octet_packets);
7498         ESTAT_ADD(rx_256_to_511_octet_packets);
7499         ESTAT_ADD(rx_512_to_1023_octet_packets);
7500         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7501         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7502         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7503         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7504         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7505
7506         ESTAT_ADD(tx_octets);
7507         ESTAT_ADD(tx_collisions);
7508         ESTAT_ADD(tx_xon_sent);
7509         ESTAT_ADD(tx_xoff_sent);
7510         ESTAT_ADD(tx_flow_control);
7511         ESTAT_ADD(tx_mac_errors);
7512         ESTAT_ADD(tx_single_collisions);
7513         ESTAT_ADD(tx_mult_collisions);
7514         ESTAT_ADD(tx_deferred);
7515         ESTAT_ADD(tx_excessive_collisions);
7516         ESTAT_ADD(tx_late_collisions);
7517         ESTAT_ADD(tx_collide_2times);
7518         ESTAT_ADD(tx_collide_3times);
7519         ESTAT_ADD(tx_collide_4times);
7520         ESTAT_ADD(tx_collide_5times);
7521         ESTAT_ADD(tx_collide_6times);
7522         ESTAT_ADD(tx_collide_7times);
7523         ESTAT_ADD(tx_collide_8times);
7524         ESTAT_ADD(tx_collide_9times);
7525         ESTAT_ADD(tx_collide_10times);
7526         ESTAT_ADD(tx_collide_11times);
7527         ESTAT_ADD(tx_collide_12times);
7528         ESTAT_ADD(tx_collide_13times);
7529         ESTAT_ADD(tx_collide_14times);
7530         ESTAT_ADD(tx_collide_15times);
7531         ESTAT_ADD(tx_ucast_packets);
7532         ESTAT_ADD(tx_mcast_packets);
7533         ESTAT_ADD(tx_bcast_packets);
7534         ESTAT_ADD(tx_carrier_sense_errors);
7535         ESTAT_ADD(tx_discards);
7536         ESTAT_ADD(tx_errors);
7537
7538         ESTAT_ADD(dma_writeq_full);
7539         ESTAT_ADD(dma_write_prioq_full);
7540         ESTAT_ADD(rxbds_empty);
7541         ESTAT_ADD(rx_discards);
7542         ESTAT_ADD(rx_errors);
7543         ESTAT_ADD(rx_threshold_hit);
7544
7545         ESTAT_ADD(dma_readq_full);
7546         ESTAT_ADD(dma_read_prioq_full);
7547         ESTAT_ADD(tx_comp_queue_full);
7548
7549         ESTAT_ADD(ring_set_send_prod_index);
7550         ESTAT_ADD(ring_status_update);
7551         ESTAT_ADD(nic_irqs);
7552         ESTAT_ADD(nic_avoided_irqs);
7553         ESTAT_ADD(nic_tx_threshold_hit);
7554
7555         return estats;
7556 }
7557
7558 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7559 {
7560         struct tg3 *tp = netdev_priv(dev);
7561         struct net_device_stats *stats = &tp->net_stats;
7562         struct net_device_stats *old_stats = &tp->net_stats_prev;
7563         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7564
7565         if (!hw_stats)
7566                 return old_stats;
7567
7568         stats->rx_packets = old_stats->rx_packets +
7569                 get_stat64(&hw_stats->rx_ucast_packets) +
7570                 get_stat64(&hw_stats->rx_mcast_packets) +
7571                 get_stat64(&hw_stats->rx_bcast_packets);
7572
7573         stats->tx_packets = old_stats->tx_packets +
7574                 get_stat64(&hw_stats->tx_ucast_packets) +
7575                 get_stat64(&hw_stats->tx_mcast_packets) +
7576                 get_stat64(&hw_stats->tx_bcast_packets);
7577
7578         stats->rx_bytes = old_stats->rx_bytes +
7579                 get_stat64(&hw_stats->rx_octets);
7580         stats->tx_bytes = old_stats->tx_bytes +
7581                 get_stat64(&hw_stats->tx_octets);
7582
7583         stats->rx_errors = old_stats->rx_errors +
7584                 get_stat64(&hw_stats->rx_errors);
7585         stats->tx_errors = old_stats->tx_errors +
7586                 get_stat64(&hw_stats->tx_errors) +
7587                 get_stat64(&hw_stats->tx_mac_errors) +
7588                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7589                 get_stat64(&hw_stats->tx_discards);
7590
7591         stats->multicast = old_stats->multicast +
7592                 get_stat64(&hw_stats->rx_mcast_packets);
7593         stats->collisions = old_stats->collisions +
7594                 get_stat64(&hw_stats->tx_collisions);
7595
7596         stats->rx_length_errors = old_stats->rx_length_errors +
7597                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7598                 get_stat64(&hw_stats->rx_undersize_packets);
7599
7600         stats->rx_over_errors = old_stats->rx_over_errors +
7601                 get_stat64(&hw_stats->rxbds_empty);
7602         stats->rx_frame_errors = old_stats->rx_frame_errors +
7603                 get_stat64(&hw_stats->rx_align_errors);
7604         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7605                 get_stat64(&hw_stats->tx_discards);
7606         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7607                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7608
7609         stats->rx_crc_errors = old_stats->rx_crc_errors +
7610                 calc_crc_errors(tp);
7611
7612         stats->rx_missed_errors = old_stats->rx_missed_errors +
7613                 get_stat64(&hw_stats->rx_discards);
7614
7615         return stats;
7616 }
7617
7618 static inline u32 calc_crc(unsigned char *buf, int len)
7619 {
7620         u32 reg;
7621         u32 tmp;
7622         int j, k;
7623
7624         reg = 0xffffffff;
7625
7626         for (j = 0; j < len; j++) {
7627                 reg ^= buf[j];
7628
7629                 for (k = 0; k < 8; k++) {
7630                         tmp = reg & 0x01;
7631
7632                         reg >>= 1;
7633
7634                         if (tmp) {
7635                                 reg ^= 0xedb88320;
7636                         }
7637                 }
7638         }
7639
7640         return ~reg;
7641 }
7642
7643 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7644 {
7645         /* accept or reject all multicast frames */
7646         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7647         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7648         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7649         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7650 }
7651
7652 static void __tg3_set_rx_mode(struct net_device *dev)
7653 {
7654         struct tg3 *tp = netdev_priv(dev);
7655         u32 rx_mode;
7656
7657         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7658                                   RX_MODE_KEEP_VLAN_TAG);
7659
7660         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7661          * flag clear.
7662          */
7663 #if TG3_VLAN_TAG_USED
7664         if (!tp->vlgrp &&
7665             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7666                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7667 #else
7668         /* By definition, VLAN is disabled always in this
7669          * case.
7670          */
7671         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7672                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7673 #endif
7674
7675         if (dev->flags & IFF_PROMISC) {
7676                 /* Promiscuous mode. */
7677                 rx_mode |= RX_MODE_PROMISC;
7678         } else if (dev->flags & IFF_ALLMULTI) {
7679                 /* Accept all multicast. */
7680                 tg3_set_multi (tp, 1);
7681         } else if (dev->mc_count < 1) {
7682                 /* Reject all multicast. */
7683                 tg3_set_multi (tp, 0);
7684         } else {
7685                 /* Accept one or more multicast(s). */
7686                 struct dev_mc_list *mclist;
7687                 unsigned int i;
7688                 u32 mc_filter[4] = { 0, };
7689                 u32 regidx;
7690                 u32 bit;
7691                 u32 crc;
7692
7693                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7694                      i++, mclist = mclist->next) {
7695
7696                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7697                         bit = ~crc & 0x7f;
7698                         regidx = (bit & 0x60) >> 5;
7699                         bit &= 0x1f;
7700                         mc_filter[regidx] |= (1 << bit);
7701                 }
7702
7703                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7704                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7705                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7706                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7707         }
7708
7709         if (rx_mode != tp->rx_mode) {
7710                 tp->rx_mode = rx_mode;
7711                 tw32_f(MAC_RX_MODE, rx_mode);
7712                 udelay(10);
7713         }
7714 }
7715
7716 static void tg3_set_rx_mode(struct net_device *dev)
7717 {
7718         struct tg3 *tp = netdev_priv(dev);
7719
7720         if (!netif_running(dev))
7721                 return;
7722
7723         tg3_full_lock(tp, 0);
7724         __tg3_set_rx_mode(dev);
7725         tg3_full_unlock(tp);
7726 }
7727
7728 #define TG3_REGDUMP_LEN         (32 * 1024)
7729
7730 static int tg3_get_regs_len(struct net_device *dev)
7731 {
7732         return TG3_REGDUMP_LEN;
7733 }
7734
7735 static void tg3_get_regs(struct net_device *dev,
7736                 struct ethtool_regs *regs, void *_p)
7737 {
7738         u32 *p = _p;
7739         struct tg3 *tp = netdev_priv(dev);
7740         u8 *orig_p = _p;
7741         int i;
7742
7743         regs->version = 0;
7744
7745         memset(p, 0, TG3_REGDUMP_LEN);
7746
7747         if (tp->link_config.phy_is_low_power)
7748                 return;
7749
7750         tg3_full_lock(tp, 0);
7751
7752 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7753 #define GET_REG32_LOOP(base,len)                \
7754 do {    p = (u32 *)(orig_p + (base));           \
7755         for (i = 0; i < len; i += 4)            \
7756                 __GET_REG32((base) + i);        \
7757 } while (0)
7758 #define GET_REG32_1(reg)                        \
7759 do {    p = (u32 *)(orig_p + (reg));            \
7760         __GET_REG32((reg));                     \
7761 } while (0)
7762
7763         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7764         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7765         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7766         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7767         GET_REG32_1(SNDDATAC_MODE);
7768         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7769         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7770         GET_REG32_1(SNDBDC_MODE);
7771         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7772         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7773         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7774         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7775         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7776         GET_REG32_1(RCVDCC_MODE);
7777         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7778         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7779         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7780         GET_REG32_1(MBFREE_MODE);
7781         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7782         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7783         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7784         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7785         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7786         GET_REG32_1(RX_CPU_MODE);
7787         GET_REG32_1(RX_CPU_STATE);
7788         GET_REG32_1(RX_CPU_PGMCTR);
7789         GET_REG32_1(RX_CPU_HWBKPT);
7790         GET_REG32_1(TX_CPU_MODE);
7791         GET_REG32_1(TX_CPU_STATE);
7792         GET_REG32_1(TX_CPU_PGMCTR);
7793         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7794         GET_REG32_LOOP(FTQ_RESET, 0x120);
7795         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7796         GET_REG32_1(DMAC_MODE);
7797         GET_REG32_LOOP(GRC_MODE, 0x4c);
7798         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7799                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7800
7801 #undef __GET_REG32
7802 #undef GET_REG32_LOOP
7803 #undef GET_REG32_1
7804
7805         tg3_full_unlock(tp);
7806 }
7807
7808 static int tg3_get_eeprom_len(struct net_device *dev)
7809 {
7810         struct tg3 *tp = netdev_priv(dev);
7811
7812         return tp->nvram_size;
7813 }
7814
7815 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7816 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7817
7818 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7819 {
7820         struct tg3 *tp = netdev_priv(dev);
7821         int ret;
7822         u8  *pd;
7823         u32 i, offset, len, val, b_offset, b_count;
7824
7825         if (tp->link_config.phy_is_low_power)
7826                 return -EAGAIN;
7827
7828         offset = eeprom->offset;
7829         len = eeprom->len;
7830         eeprom->len = 0;
7831
7832         eeprom->magic = TG3_EEPROM_MAGIC;
7833
7834         if (offset & 3) {
7835                 /* adjustments to start on required 4 byte boundary */
7836                 b_offset = offset & 3;
7837                 b_count = 4 - b_offset;
7838                 if (b_count > len) {
7839                         /* i.e. offset=1 len=2 */
7840                         b_count = len;
7841                 }
7842                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7843                 if (ret)
7844                         return ret;
7845                 val = cpu_to_le32(val);
7846                 memcpy(data, ((char*)&val) + b_offset, b_count);
7847                 len -= b_count;
7848                 offset += b_count;
7849                 eeprom->len += b_count;
7850         }
7851
7852         /* read bytes upto the last 4 byte boundary */
7853         pd = &data[eeprom->len];
7854         for (i = 0; i < (len - (len & 3)); i += 4) {
7855                 ret = tg3_nvram_read(tp, offset + i, &val);
7856                 if (ret) {
7857                         eeprom->len += i;
7858                         return ret;
7859                 }
7860                 val = cpu_to_le32(val);
7861                 memcpy(pd + i, &val, 4);
7862         }
7863         eeprom->len += i;
7864
7865         if (len & 3) {
7866                 /* read last bytes not ending on 4 byte boundary */
7867                 pd = &data[eeprom->len];
7868                 b_count = len & 3;
7869                 b_offset = offset + len - b_count;
7870                 ret = tg3_nvram_read(tp, b_offset, &val);
7871                 if (ret)
7872                         return ret;
7873                 val = cpu_to_le32(val);
7874                 memcpy(pd, ((char*)&val), b_count);
7875                 eeprom->len += b_count;
7876         }
7877         return 0;
7878 }
7879
7880 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7881
7882 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7883 {
7884         struct tg3 *tp = netdev_priv(dev);
7885         int ret;
7886         u32 offset, len, b_offset, odd_len, start, end;
7887         u8 *buf;
7888
7889         if (tp->link_config.phy_is_low_power)
7890                 return -EAGAIN;
7891
7892         if (eeprom->magic != TG3_EEPROM_MAGIC)
7893                 return -EINVAL;
7894
7895         offset = eeprom->offset;
7896         len = eeprom->len;
7897
7898         if ((b_offset = (offset & 3))) {
7899                 /* adjustments to start on required 4 byte boundary */
7900                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7901                 if (ret)
7902                         return ret;
7903                 start = cpu_to_le32(start);
7904                 len += b_offset;
7905                 offset &= ~3;
7906                 if (len < 4)
7907                         len = 4;
7908         }
7909
7910         odd_len = 0;
7911         if (len & 3) {
7912                 /* adjustments to end on required 4 byte boundary */
7913                 odd_len = 1;
7914                 len = (len + 3) & ~3;
7915                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7916                 if (ret)
7917                         return ret;
7918                 end = cpu_to_le32(end);
7919         }
7920
7921         buf = data;
7922         if (b_offset || odd_len) {
7923                 buf = kmalloc(len, GFP_KERNEL);
7924                 if (buf == 0)
7925                         return -ENOMEM;
7926                 if (b_offset)
7927                         memcpy(buf, &start, 4);
7928                 if (odd_len)
7929                         memcpy(buf+len-4, &end, 4);
7930                 memcpy(buf + b_offset, data, eeprom->len);
7931         }
7932
7933         ret = tg3_nvram_write_block(tp, offset, len, buf);
7934
7935         if (buf != data)
7936                 kfree(buf);
7937
7938         return ret;
7939 }
7940
7941 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7942 {
7943         struct tg3 *tp = netdev_priv(dev);
7944
7945         cmd->supported = (SUPPORTED_Autoneg);
7946
7947         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7948                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7949                                    SUPPORTED_1000baseT_Full);
7950
7951         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7952                 cmd->supported |= (SUPPORTED_100baseT_Half |
7953                                   SUPPORTED_100baseT_Full |
7954                                   SUPPORTED_10baseT_Half |
7955                                   SUPPORTED_10baseT_Full |
7956                                   SUPPORTED_MII);
7957                 cmd->port = PORT_TP;
7958         } else {
7959                 cmd->supported |= SUPPORTED_FIBRE;
7960                 cmd->port = PORT_FIBRE;
7961         }
7962
7963         cmd->advertising = tp->link_config.advertising;
7964         if (netif_running(dev)) {
7965                 cmd->speed = tp->link_config.active_speed;
7966                 cmd->duplex = tp->link_config.active_duplex;
7967         }
7968         cmd->phy_address = PHY_ADDR;
7969         cmd->transceiver = 0;
7970         cmd->autoneg = tp->link_config.autoneg;
7971         cmd->maxtxpkt = 0;
7972         cmd->maxrxpkt = 0;
7973         return 0;
7974 }
7975
7976 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7977 {
7978         struct tg3 *tp = netdev_priv(dev);
7979
7980         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7981                 /* These are the only valid advertisement bits allowed.  */
7982                 if (cmd->autoneg == AUTONEG_ENABLE &&
7983                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7984                                           ADVERTISED_1000baseT_Full |
7985                                           ADVERTISED_Autoneg |
7986                                           ADVERTISED_FIBRE)))
7987                         return -EINVAL;
7988                 /* Fiber can only do SPEED_1000.  */
7989                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7990                          (cmd->speed != SPEED_1000))
7991                         return -EINVAL;
7992         /* Copper cannot force SPEED_1000.  */
7993         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7994                    (cmd->speed == SPEED_1000))
7995                 return -EINVAL;
7996         else if ((cmd->speed == SPEED_1000) &&
7997                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7998                 return -EINVAL;
7999
8000         tg3_full_lock(tp, 0);
8001
8002         tp->link_config.autoneg = cmd->autoneg;
8003         if (cmd->autoneg == AUTONEG_ENABLE) {
8004                 tp->link_config.advertising = cmd->advertising;
8005                 tp->link_config.speed = SPEED_INVALID;
8006                 tp->link_config.duplex = DUPLEX_INVALID;
8007         } else {
8008                 tp->link_config.advertising = 0;
8009                 tp->link_config.speed = cmd->speed;
8010                 tp->link_config.duplex = cmd->duplex;
8011         }
8012
8013         tp->link_config.orig_speed = tp->link_config.speed;
8014         tp->link_config.orig_duplex = tp->link_config.duplex;
8015         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8016
8017         if (netif_running(dev))
8018                 tg3_setup_phy(tp, 1);
8019
8020         tg3_full_unlock(tp);
8021
8022         return 0;
8023 }
8024
8025 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8026 {
8027         struct tg3 *tp = netdev_priv(dev);
8028
8029         strcpy(info->driver, DRV_MODULE_NAME);
8030         strcpy(info->version, DRV_MODULE_VERSION);
8031         strcpy(info->fw_version, tp->fw_ver);
8032         strcpy(info->bus_info, pci_name(tp->pdev));
8033 }
8034
8035 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8036 {
8037         struct tg3 *tp = netdev_priv(dev);
8038
8039         wol->supported = WAKE_MAGIC;
8040         wol->wolopts = 0;
8041         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8042                 wol->wolopts = WAKE_MAGIC;
8043         memset(&wol->sopass, 0, sizeof(wol->sopass));
8044 }
8045
8046 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8047 {
8048         struct tg3 *tp = netdev_priv(dev);
8049
8050         if (wol->wolopts & ~WAKE_MAGIC)
8051                 return -EINVAL;
8052         if ((wol->wolopts & WAKE_MAGIC) &&
8053             tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
8054             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8055                 return -EINVAL;
8056
8057         spin_lock_bh(&tp->lock);
8058         if (wol->wolopts & WAKE_MAGIC)
8059                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8060         else
8061                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8062         spin_unlock_bh(&tp->lock);
8063
8064         return 0;
8065 }
8066
8067 static u32 tg3_get_msglevel(struct net_device *dev)
8068 {
8069         struct tg3 *tp = netdev_priv(dev);
8070         return tp->msg_enable;
8071 }
8072
8073 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8074 {
8075         struct tg3 *tp = netdev_priv(dev);
8076         tp->msg_enable = value;
8077 }
8078
8079 static int tg3_set_tso(struct net_device *dev, u32 value)
8080 {
8081         struct tg3 *tp = netdev_priv(dev);
8082
8083         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8084                 if (value)
8085                         return -EINVAL;
8086                 return 0;
8087         }
8088         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8089             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8090                 if (value)
8091                         dev->features |= NETIF_F_TSO6;
8092                 else
8093                         dev->features &= ~NETIF_F_TSO6;
8094         }
8095         return ethtool_op_set_tso(dev, value);
8096 }
8097
8098 static int tg3_nway_reset(struct net_device *dev)
8099 {
8100         struct tg3 *tp = netdev_priv(dev);
8101         u32 bmcr;
8102         int r;
8103
8104         if (!netif_running(dev))
8105                 return -EAGAIN;
8106
8107         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8108                 return -EINVAL;
8109
8110         spin_lock_bh(&tp->lock);
8111         r = -EINVAL;
8112         tg3_readphy(tp, MII_BMCR, &bmcr);
8113         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8114             ((bmcr & BMCR_ANENABLE) ||
8115              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8116                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8117                                            BMCR_ANENABLE);
8118                 r = 0;
8119         }
8120         spin_unlock_bh(&tp->lock);
8121
8122         return r;
8123 }
8124
8125 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8126 {
8127         struct tg3 *tp = netdev_priv(dev);
8128
8129         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8130         ering->rx_mini_max_pending = 0;
8131         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8132                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8133         else
8134                 ering->rx_jumbo_max_pending = 0;
8135
8136         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8137
8138         ering->rx_pending = tp->rx_pending;
8139         ering->rx_mini_pending = 0;
8140         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8141                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8142         else
8143                 ering->rx_jumbo_pending = 0;
8144
8145         ering->tx_pending = tp->tx_pending;
8146 }
8147
8148 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8149 {
8150         struct tg3 *tp = netdev_priv(dev);
8151         int irq_sync = 0, err = 0;
8152
8153         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8154             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8155             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8156             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8157             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8158              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8159                 return -EINVAL;
8160
8161         if (netif_running(dev)) {
8162                 tg3_netif_stop(tp);
8163                 irq_sync = 1;
8164         }
8165
8166         tg3_full_lock(tp, irq_sync);
8167
8168         tp->rx_pending = ering->rx_pending;
8169
8170         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8171             tp->rx_pending > 63)
8172                 tp->rx_pending = 63;
8173         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8174         tp->tx_pending = ering->tx_pending;
8175
8176         if (netif_running(dev)) {
8177                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8178                 err = tg3_restart_hw(tp, 1);
8179                 if (!err)
8180                         tg3_netif_start(tp);
8181         }
8182
8183         tg3_full_unlock(tp);
8184
8185         return err;
8186 }
8187
8188 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8189 {
8190         struct tg3 *tp = netdev_priv(dev);
8191
8192         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8193         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8194         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8195 }
8196
8197 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8198 {
8199         struct tg3 *tp = netdev_priv(dev);
8200         int irq_sync = 0, err = 0;
8201
8202         if (netif_running(dev)) {
8203                 tg3_netif_stop(tp);
8204                 irq_sync = 1;
8205         }
8206
8207         tg3_full_lock(tp, irq_sync);
8208
8209         if (epause->autoneg)
8210                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8211         else
8212                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8213         if (epause->rx_pause)
8214                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8215         else
8216                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8217         if (epause->tx_pause)
8218                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8219         else
8220                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8221
8222         if (netif_running(dev)) {
8223                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8224                 err = tg3_restart_hw(tp, 1);
8225                 if (!err)
8226                         tg3_netif_start(tp);
8227         }
8228
8229         tg3_full_unlock(tp);
8230
8231         return err;
8232 }
8233
8234 static u32 tg3_get_rx_csum(struct net_device *dev)
8235 {
8236         struct tg3 *tp = netdev_priv(dev);
8237         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8238 }
8239
8240 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8241 {
8242         struct tg3 *tp = netdev_priv(dev);
8243
8244         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8245                 if (data != 0)
8246                         return -EINVAL;
8247                 return 0;
8248         }
8249
8250         spin_lock_bh(&tp->lock);
8251         if (data)
8252                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8253         else
8254                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8255         spin_unlock_bh(&tp->lock);
8256
8257         return 0;
8258 }
8259
8260 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8261 {
8262         struct tg3 *tp = netdev_priv(dev);
8263
8264         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8265                 if (data != 0)
8266                         return -EINVAL;
8267                 return 0;
8268         }
8269
8270         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8271             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8272                 ethtool_op_set_tx_hw_csum(dev, data);
8273         else
8274                 ethtool_op_set_tx_csum(dev, data);
8275
8276         return 0;
8277 }
8278
8279 static int tg3_get_stats_count (struct net_device *dev)
8280 {
8281         return TG3_NUM_STATS;
8282 }
8283
8284 static int tg3_get_test_count (struct net_device *dev)
8285 {
8286         return TG3_NUM_TEST;
8287 }
8288
8289 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8290 {
8291         switch (stringset) {
8292         case ETH_SS_STATS:
8293                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8294                 break;
8295         case ETH_SS_TEST:
8296                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8297                 break;
8298         default:
8299                 WARN_ON(1);     /* we need a WARN() */
8300                 break;
8301         }
8302 }
8303
8304 static int tg3_phys_id(struct net_device *dev, u32 data)
8305 {
8306         struct tg3 *tp = netdev_priv(dev);
8307         int i;
8308
8309         if (!netif_running(tp->dev))
8310                 return -EAGAIN;
8311
8312         if (data == 0)
8313                 data = 2;
8314
8315         for (i = 0; i < (data * 2); i++) {
8316                 if ((i % 2) == 0)
8317                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8318                                            LED_CTRL_1000MBPS_ON |
8319                                            LED_CTRL_100MBPS_ON |
8320                                            LED_CTRL_10MBPS_ON |
8321                                            LED_CTRL_TRAFFIC_OVERRIDE |
8322                                            LED_CTRL_TRAFFIC_BLINK |
8323                                            LED_CTRL_TRAFFIC_LED);
8324
8325                 else
8326                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8327                                            LED_CTRL_TRAFFIC_OVERRIDE);
8328
8329                 if (msleep_interruptible(500))
8330                         break;
8331         }
8332         tw32(MAC_LED_CTRL, tp->led_ctrl);
8333         return 0;
8334 }
8335
8336 static void tg3_get_ethtool_stats (struct net_device *dev,
8337                                    struct ethtool_stats *estats, u64 *tmp_stats)
8338 {
8339         struct tg3 *tp = netdev_priv(dev);
8340         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8341 }
8342
8343 #define NVRAM_TEST_SIZE 0x100
8344 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8345 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8346 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8347
8348 static int tg3_test_nvram(struct tg3 *tp)
8349 {
8350         u32 *buf, csum, magic;
8351         int i, j, err = 0, size;
8352
8353         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8354                 return -EIO;
8355
8356         if (magic == TG3_EEPROM_MAGIC)
8357                 size = NVRAM_TEST_SIZE;
8358         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8359                 if ((magic & 0xe00000) == 0x200000)
8360                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8361                 else
8362                         return 0;
8363         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8364                 size = NVRAM_SELFBOOT_HW_SIZE;
8365         else
8366                 return -EIO;
8367
8368         buf = kmalloc(size, GFP_KERNEL);
8369         if (buf == NULL)
8370                 return -ENOMEM;
8371
8372         err = -EIO;
8373         for (i = 0, j = 0; i < size; i += 4, j++) {
8374                 u32 val;
8375
8376                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8377                         break;
8378                 buf[j] = cpu_to_le32(val);
8379         }
8380         if (i < size)
8381                 goto out;
8382
8383         /* Selfboot format */
8384         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8385             TG3_EEPROM_MAGIC_FW) {
8386                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8387
8388                 for (i = 0; i < size; i++)
8389                         csum8 += buf8[i];
8390
8391                 if (csum8 == 0) {
8392                         err = 0;
8393                         goto out;
8394                 }
8395
8396                 err = -EIO;
8397                 goto out;
8398         }
8399
8400         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8401             TG3_EEPROM_MAGIC_HW) {
8402                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8403                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8404                 u8 *buf8 = (u8 *) buf;
8405                 int j, k;
8406
8407                 /* Separate the parity bits and the data bytes.  */
8408                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8409                         if ((i == 0) || (i == 8)) {
8410                                 int l;
8411                                 u8 msk;
8412
8413                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8414                                         parity[k++] = buf8[i] & msk;
8415                                 i++;
8416                         }
8417                         else if (i == 16) {
8418                                 int l;
8419                                 u8 msk;
8420
8421                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8422                                         parity[k++] = buf8[i] & msk;
8423                                 i++;
8424
8425                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8426                                         parity[k++] = buf8[i] & msk;
8427                                 i++;
8428                         }
8429                         data[j++] = buf8[i];
8430                 }
8431
8432                 err = -EIO;
8433                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8434                         u8 hw8 = hweight8(data[i]);
8435
8436                         if ((hw8 & 0x1) && parity[i])
8437                                 goto out;
8438                         else if (!(hw8 & 0x1) && !parity[i])
8439                                 goto out;
8440                 }
8441                 err = 0;
8442                 goto out;
8443         }
8444
8445         /* Bootstrap checksum at offset 0x10 */
8446         csum = calc_crc((unsigned char *) buf, 0x10);
8447         if(csum != cpu_to_le32(buf[0x10/4]))
8448                 goto out;
8449
8450         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8451         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8452         if (csum != cpu_to_le32(buf[0xfc/4]))
8453                  goto out;
8454
8455         err = 0;
8456
8457 out:
8458         kfree(buf);
8459         return err;
8460 }
8461
8462 #define TG3_SERDES_TIMEOUT_SEC  2
8463 #define TG3_COPPER_TIMEOUT_SEC  6
8464
8465 static int tg3_test_link(struct tg3 *tp)
8466 {
8467         int i, max;
8468
8469         if (!netif_running(tp->dev))
8470                 return -ENODEV;
8471
8472         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8473                 max = TG3_SERDES_TIMEOUT_SEC;
8474         else
8475                 max = TG3_COPPER_TIMEOUT_SEC;
8476
8477         for (i = 0; i < max; i++) {
8478                 if (netif_carrier_ok(tp->dev))
8479                         return 0;
8480
8481                 if (msleep_interruptible(1000))
8482                         break;
8483         }
8484
8485         return -EIO;
8486 }
8487
8488 /* Only test the commonly used registers */
8489 static int tg3_test_registers(struct tg3 *tp)
8490 {
8491         int i, is_5705, is_5750;
8492         u32 offset, read_mask, write_mask, val, save_val, read_val;
8493         static struct {
8494                 u16 offset;
8495                 u16 flags;
8496 #define TG3_FL_5705     0x1
8497 #define TG3_FL_NOT_5705 0x2
8498 #define TG3_FL_NOT_5788 0x4
8499 #define TG3_FL_NOT_5750 0x8
8500                 u32 read_mask;
8501                 u32 write_mask;
8502         } reg_tbl[] = {
8503                 /* MAC Control Registers */
8504                 { MAC_MODE, TG3_FL_NOT_5705,
8505                         0x00000000, 0x00ef6f8c },
8506                 { MAC_MODE, TG3_FL_5705,
8507                         0x00000000, 0x01ef6b8c },
8508                 { MAC_STATUS, TG3_FL_NOT_5705,
8509                         0x03800107, 0x00000000 },
8510                 { MAC_STATUS, TG3_FL_5705,
8511                         0x03800100, 0x00000000 },
8512                 { MAC_ADDR_0_HIGH, 0x0000,
8513                         0x00000000, 0x0000ffff },
8514                 { MAC_ADDR_0_LOW, 0x0000,
8515                         0x00000000, 0xffffffff },
8516                 { MAC_RX_MTU_SIZE, 0x0000,
8517                         0x00000000, 0x0000ffff },
8518                 { MAC_TX_MODE, 0x0000,
8519                         0x00000000, 0x00000070 },
8520                 { MAC_TX_LENGTHS, 0x0000,
8521                         0x00000000, 0x00003fff },
8522                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8523                         0x00000000, 0x000007fc },
8524                 { MAC_RX_MODE, TG3_FL_5705,
8525                         0x00000000, 0x000007dc },
8526                 { MAC_HASH_REG_0, 0x0000,
8527                         0x00000000, 0xffffffff },
8528                 { MAC_HASH_REG_1, 0x0000,
8529                         0x00000000, 0xffffffff },
8530                 { MAC_HASH_REG_2, 0x0000,
8531                         0x00000000, 0xffffffff },
8532                 { MAC_HASH_REG_3, 0x0000,
8533                         0x00000000, 0xffffffff },
8534
8535                 /* Receive Data and Receive BD Initiator Control Registers. */
8536                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8537                         0x00000000, 0xffffffff },
8538                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8539                         0x00000000, 0xffffffff },
8540                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8541                         0x00000000, 0x00000003 },
8542                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8543                         0x00000000, 0xffffffff },
8544                 { RCVDBDI_STD_BD+0, 0x0000,
8545                         0x00000000, 0xffffffff },
8546                 { RCVDBDI_STD_BD+4, 0x0000,
8547                         0x00000000, 0xffffffff },
8548                 { RCVDBDI_STD_BD+8, 0x0000,
8549                         0x00000000, 0xffff0002 },
8550                 { RCVDBDI_STD_BD+0xc, 0x0000,
8551                         0x00000000, 0xffffffff },
8552
8553                 /* Receive BD Initiator Control Registers. */
8554                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8555                         0x00000000, 0xffffffff },
8556                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8557                         0x00000000, 0x000003ff },
8558                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8559                         0x00000000, 0xffffffff },
8560
8561                 /* Host Coalescing Control Registers. */
8562                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8563                         0x00000000, 0x00000004 },
8564                 { HOSTCC_MODE, TG3_FL_5705,
8565                         0x00000000, 0x000000f6 },
8566                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8567                         0x00000000, 0xffffffff },
8568                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8569                         0x00000000, 0x000003ff },
8570                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8571                         0x00000000, 0xffffffff },
8572                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8573                         0x00000000, 0x000003ff },
8574                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8575                         0x00000000, 0xffffffff },
8576                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8577                         0x00000000, 0x000000ff },
8578                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8579                         0x00000000, 0xffffffff },
8580                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8581                         0x00000000, 0x000000ff },
8582                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8583                         0x00000000, 0xffffffff },
8584                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8585                         0x00000000, 0xffffffff },
8586                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8587                         0x00000000, 0xffffffff },
8588                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8589                         0x00000000, 0x000000ff },
8590                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8591                         0x00000000, 0xffffffff },
8592                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8593                         0x00000000, 0x000000ff },
8594                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8595                         0x00000000, 0xffffffff },
8596                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8597                         0x00000000, 0xffffffff },
8598                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8599                         0x00000000, 0xffffffff },
8600                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8601                         0x00000000, 0xffffffff },
8602                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8603                         0x00000000, 0xffffffff },
8604                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8605                         0xffffffff, 0x00000000 },
8606                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8607                         0xffffffff, 0x00000000 },
8608
8609                 /* Buffer Manager Control Registers. */
8610                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8611                         0x00000000, 0x007fff80 },
8612                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8613                         0x00000000, 0x007fffff },
8614                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8615                         0x00000000, 0x0000003f },
8616                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8617                         0x00000000, 0x000001ff },
8618                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8619                         0x00000000, 0x000001ff },
8620                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8621                         0xffffffff, 0x00000000 },
8622                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8623                         0xffffffff, 0x00000000 },
8624
8625                 /* Mailbox Registers */
8626                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8627                         0x00000000, 0x000001ff },
8628                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8629                         0x00000000, 0x000001ff },
8630                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8631                         0x00000000, 0x000007ff },
8632                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8633                         0x00000000, 0x000001ff },
8634
8635                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8636         };
8637
8638         is_5705 = is_5750 = 0;
8639         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8640                 is_5705 = 1;
8641                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8642                         is_5750 = 1;
8643         }
8644
8645         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8646                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8647                         continue;
8648
8649                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8650                         continue;
8651
8652                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8653                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8654                         continue;
8655
8656                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8657                         continue;
8658
8659                 offset = (u32) reg_tbl[i].offset;
8660                 read_mask = reg_tbl[i].read_mask;
8661                 write_mask = reg_tbl[i].write_mask;
8662
8663                 /* Save the original register content */
8664                 save_val = tr32(offset);
8665
8666                 /* Determine the read-only value. */
8667                 read_val = save_val & read_mask;
8668
8669                 /* Write zero to the register, then make sure the read-only bits
8670                  * are not changed and the read/write bits are all zeros.
8671                  */
8672                 tw32(offset, 0);
8673
8674                 val = tr32(offset);
8675
8676                 /* Test the read-only and read/write bits. */
8677                 if (((val & read_mask) != read_val) || (val & write_mask))
8678                         goto out;
8679
8680                 /* Write ones to all the bits defined by RdMask and WrMask, then
8681                  * make sure the read-only bits are not changed and the
8682                  * read/write bits are all ones.
8683                  */
8684                 tw32(offset, read_mask | write_mask);
8685
8686                 val = tr32(offset);
8687
8688                 /* Test the read-only bits. */
8689                 if ((val & read_mask) != read_val)
8690                         goto out;
8691
8692                 /* Test the read/write bits. */
8693                 if ((val & write_mask) != write_mask)
8694                         goto out;
8695
8696                 tw32(offset, save_val);
8697         }
8698
8699         return 0;
8700
8701 out:
8702         if (netif_msg_hw(tp))
8703                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8704                        offset);
8705         tw32(offset, save_val);
8706         return -EIO;
8707 }
8708
8709 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8710 {
8711         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8712         int i;
8713         u32 j;
8714
8715         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8716                 for (j = 0; j < len; j += 4) {
8717                         u32 val;
8718
8719                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8720                         tg3_read_mem(tp, offset + j, &val);
8721                         if (val != test_pattern[i])
8722                                 return -EIO;
8723                 }
8724         }
8725         return 0;
8726 }
8727
8728 static int tg3_test_memory(struct tg3 *tp)
8729 {
8730         static struct mem_entry {
8731                 u32 offset;
8732                 u32 len;
8733         } mem_tbl_570x[] = {
8734                 { 0x00000000, 0x00b50},
8735                 { 0x00002000, 0x1c000},
8736                 { 0xffffffff, 0x00000}
8737         }, mem_tbl_5705[] = {
8738                 { 0x00000100, 0x0000c},
8739                 { 0x00000200, 0x00008},
8740                 { 0x00004000, 0x00800},
8741                 { 0x00006000, 0x01000},
8742                 { 0x00008000, 0x02000},
8743                 { 0x00010000, 0x0e000},
8744                 { 0xffffffff, 0x00000}
8745         }, mem_tbl_5755[] = {
8746                 { 0x00000200, 0x00008},
8747                 { 0x00004000, 0x00800},
8748                 { 0x00006000, 0x00800},
8749                 { 0x00008000, 0x02000},
8750                 { 0x00010000, 0x0c000},
8751                 { 0xffffffff, 0x00000}
8752         }, mem_tbl_5906[] = {
8753                 { 0x00000200, 0x00008},
8754                 { 0x00004000, 0x00400},
8755                 { 0x00006000, 0x00400},
8756                 { 0x00008000, 0x01000},
8757                 { 0x00010000, 0x01000},
8758                 { 0xffffffff, 0x00000}
8759         };
8760         struct mem_entry *mem_tbl;
8761         int err = 0;
8762         int i;
8763
8764         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8765                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8766                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8767                         mem_tbl = mem_tbl_5755;
8768                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8769                         mem_tbl = mem_tbl_5906;
8770                 else
8771                         mem_tbl = mem_tbl_5705;
8772         } else
8773                 mem_tbl = mem_tbl_570x;
8774
8775         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8776                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8777                     mem_tbl[i].len)) != 0)
8778                         break;
8779         }
8780
8781         return err;
8782 }
8783
8784 #define TG3_MAC_LOOPBACK        0
8785 #define TG3_PHY_LOOPBACK        1
8786
8787 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8788 {
8789         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8790         u32 desc_idx;
8791         struct sk_buff *skb, *rx_skb;
8792         u8 *tx_data;
8793         dma_addr_t map;
8794         int num_pkts, tx_len, rx_len, i, err;
8795         struct tg3_rx_buffer_desc *desc;
8796
8797         if (loopback_mode == TG3_MAC_LOOPBACK) {
8798                 /* HW errata - mac loopback fails in some cases on 5780.
8799                  * Normal traffic and PHY loopback are not affected by
8800                  * errata.
8801                  */
8802                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8803                         return 0;
8804
8805                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8806                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8807                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8808                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8809                 else
8810                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8811                 tw32(MAC_MODE, mac_mode);
8812         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8813                 u32 val;
8814
8815                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8816                         u32 phytest;
8817
8818                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8819                                 u32 phy;
8820
8821                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8822                                              phytest | MII_TG3_EPHY_SHADOW_EN);
8823                                 if (!tg3_readphy(tp, 0x1b, &phy))
8824                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
8825                                 if (!tg3_readphy(tp, 0x10, &phy))
8826                                         tg3_writephy(tp, 0x10, phy & ~0x4000);
8827                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8828                         }
8829                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8830                 } else
8831                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8832
8833                 tg3_writephy(tp, MII_BMCR, val);
8834                 udelay(40);
8835
8836                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8837                            MAC_MODE_LINK_POLARITY;
8838                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8839                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8840                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8841                 } else
8842                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8843
8844                 /* reset to prevent losing 1st rx packet intermittently */
8845                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8846                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8847                         udelay(10);
8848                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8849                 }
8850                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8851                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8852                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8853                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8854                 }
8855                 tw32(MAC_MODE, mac_mode);
8856         }
8857         else
8858                 return -EINVAL;
8859
8860         err = -EIO;
8861
8862         tx_len = 1514;
8863         skb = netdev_alloc_skb(tp->dev, tx_len);
8864         if (!skb)
8865                 return -ENOMEM;
8866
8867         tx_data = skb_put(skb, tx_len);
8868         memcpy(tx_data, tp->dev->dev_addr, 6);
8869         memset(tx_data + 6, 0x0, 8);
8870
8871         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8872
8873         for (i = 14; i < tx_len; i++)
8874                 tx_data[i] = (u8) (i & 0xff);
8875
8876         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8877
8878         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8879              HOSTCC_MODE_NOW);
8880
8881         udelay(10);
8882
8883         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8884
8885         num_pkts = 0;
8886
8887         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8888
8889         tp->tx_prod++;
8890         num_pkts++;
8891
8892         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8893                      tp->tx_prod);
8894         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8895
8896         udelay(10);
8897
8898         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
8899         for (i = 0; i < 25; i++) {
8900                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8901                        HOSTCC_MODE_NOW);
8902
8903                 udelay(10);
8904
8905                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8906                 rx_idx = tp->hw_status->idx[0].rx_producer;
8907                 if ((tx_idx == tp->tx_prod) &&
8908                     (rx_idx == (rx_start_idx + num_pkts)))
8909                         break;
8910         }
8911
8912         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8913         dev_kfree_skb(skb);
8914
8915         if (tx_idx != tp->tx_prod)
8916                 goto out;
8917
8918         if (rx_idx != rx_start_idx + num_pkts)
8919                 goto out;
8920
8921         desc = &tp->rx_rcb[rx_start_idx];
8922         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8923         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8924         if (opaque_key != RXD_OPAQUE_RING_STD)
8925                 goto out;
8926
8927         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8928             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8929                 goto out;
8930
8931         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8932         if (rx_len != tx_len)
8933                 goto out;
8934
8935         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8936
8937         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8938         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8939
8940         for (i = 14; i < tx_len; i++) {
8941                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8942                         goto out;
8943         }
8944         err = 0;
8945
8946         /* tg3_free_rings will unmap and free the rx_skb */
8947 out:
8948         return err;
8949 }
8950
8951 #define TG3_MAC_LOOPBACK_FAILED         1
8952 #define TG3_PHY_LOOPBACK_FAILED         2
8953 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8954                                          TG3_PHY_LOOPBACK_FAILED)
8955
8956 static int tg3_test_loopback(struct tg3 *tp)
8957 {
8958         int err = 0;
8959
8960         if (!netif_running(tp->dev))
8961                 return TG3_LOOPBACK_FAILED;
8962
8963         err = tg3_reset_hw(tp, 1);
8964         if (err)
8965                 return TG3_LOOPBACK_FAILED;
8966
8967         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8968                 err |= TG3_MAC_LOOPBACK_FAILED;
8969         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8970                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8971                         err |= TG3_PHY_LOOPBACK_FAILED;
8972         }
8973
8974         return err;
8975 }
8976
8977 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8978                           u64 *data)
8979 {
8980         struct tg3 *tp = netdev_priv(dev);
8981
8982         if (tp->link_config.phy_is_low_power)
8983                 tg3_set_power_state(tp, PCI_D0);
8984
8985         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8986
8987         if (tg3_test_nvram(tp) != 0) {
8988                 etest->flags |= ETH_TEST_FL_FAILED;
8989                 data[0] = 1;
8990         }
8991         if (tg3_test_link(tp) != 0) {
8992                 etest->flags |= ETH_TEST_FL_FAILED;
8993                 data[1] = 1;
8994         }
8995         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8996                 int err, irq_sync = 0;
8997
8998                 if (netif_running(dev)) {
8999                         tg3_netif_stop(tp);
9000                         irq_sync = 1;
9001                 }
9002
9003                 tg3_full_lock(tp, irq_sync);
9004
9005                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9006                 err = tg3_nvram_lock(tp);
9007                 tg3_halt_cpu(tp, RX_CPU_BASE);
9008                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9009                         tg3_halt_cpu(tp, TX_CPU_BASE);
9010                 if (!err)
9011                         tg3_nvram_unlock(tp);
9012
9013                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9014                         tg3_phy_reset(tp);
9015
9016                 if (tg3_test_registers(tp) != 0) {
9017                         etest->flags |= ETH_TEST_FL_FAILED;
9018                         data[2] = 1;
9019                 }
9020                 if (tg3_test_memory(tp) != 0) {
9021                         etest->flags |= ETH_TEST_FL_FAILED;
9022                         data[3] = 1;
9023                 }
9024                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9025                         etest->flags |= ETH_TEST_FL_FAILED;
9026
9027                 tg3_full_unlock(tp);
9028
9029                 if (tg3_test_interrupt(tp) != 0) {
9030                         etest->flags |= ETH_TEST_FL_FAILED;
9031                         data[5] = 1;
9032                 }
9033
9034                 tg3_full_lock(tp, 0);
9035
9036                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9037                 if (netif_running(dev)) {
9038                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9039                         if (!tg3_restart_hw(tp, 1))
9040                                 tg3_netif_start(tp);
9041                 }
9042
9043                 tg3_full_unlock(tp);
9044         }
9045         if (tp->link_config.phy_is_low_power)
9046                 tg3_set_power_state(tp, PCI_D3hot);
9047
9048 }
9049
9050 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9051 {
9052         struct mii_ioctl_data *data = if_mii(ifr);
9053         struct tg3 *tp = netdev_priv(dev);
9054         int err;
9055
9056         switch(cmd) {
9057         case SIOCGMIIPHY:
9058                 data->phy_id = PHY_ADDR;
9059
9060                 /* fallthru */
9061         case SIOCGMIIREG: {
9062                 u32 mii_regval;
9063
9064                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9065                         break;                  /* We have no PHY */
9066
9067                 if (tp->link_config.phy_is_low_power)
9068                         return -EAGAIN;
9069
9070                 spin_lock_bh(&tp->lock);
9071                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9072                 spin_unlock_bh(&tp->lock);
9073
9074                 data->val_out = mii_regval;
9075
9076                 return err;
9077         }
9078
9079         case SIOCSMIIREG:
9080                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9081                         break;                  /* We have no PHY */
9082
9083                 if (!capable(CAP_NET_ADMIN))
9084                         return -EPERM;
9085
9086                 if (tp->link_config.phy_is_low_power)
9087                         return -EAGAIN;
9088
9089                 spin_lock_bh(&tp->lock);
9090                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9091                 spin_unlock_bh(&tp->lock);
9092
9093                 return err;
9094
9095         default:
9096                 /* do nothing */
9097                 break;
9098         }
9099         return -EOPNOTSUPP;
9100 }
9101
9102 #if TG3_VLAN_TAG_USED
9103 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9104 {
9105         struct tg3 *tp = netdev_priv(dev);
9106
9107         if (netif_running(dev))
9108                 tg3_netif_stop(tp);
9109
9110         tg3_full_lock(tp, 0);
9111
9112         tp->vlgrp = grp;
9113
9114         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9115         __tg3_set_rx_mode(dev);
9116
9117         tg3_full_unlock(tp);
9118
9119         if (netif_running(dev))
9120                 tg3_netif_start(tp);
9121 }
9122
9123 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9124 {
9125         struct tg3 *tp = netdev_priv(dev);
9126
9127         if (netif_running(dev))
9128                 tg3_netif_stop(tp);
9129
9130         tg3_full_lock(tp, 0);
9131         vlan_group_set_device(tp->vlgrp, vid, NULL);
9132         tg3_full_unlock(tp);
9133
9134         if (netif_running(dev))
9135                 tg3_netif_start(tp);
9136 }
9137 #endif
9138
9139 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9140 {
9141         struct tg3 *tp = netdev_priv(dev);
9142
9143         memcpy(ec, &tp->coal, sizeof(*ec));
9144         return 0;
9145 }
9146
9147 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9148 {
9149         struct tg3 *tp = netdev_priv(dev);
9150         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9151         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9152
9153         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9154                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9155                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9156                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9157                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9158         }
9159
9160         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9161             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9162             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9163             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9164             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9165             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9166             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9167             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9168             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9169             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9170                 return -EINVAL;
9171
9172         /* No rx interrupts will be generated if both are zero */
9173         if ((ec->rx_coalesce_usecs == 0) &&
9174             (ec->rx_max_coalesced_frames == 0))
9175                 return -EINVAL;
9176
9177         /* No tx interrupts will be generated if both are zero */
9178         if ((ec->tx_coalesce_usecs == 0) &&
9179             (ec->tx_max_coalesced_frames == 0))
9180                 return -EINVAL;
9181
9182         /* Only copy relevant parameters, ignore all others. */
9183         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9184         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9185         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9186         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9187         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9188         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9189         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9190         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9191         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9192
9193         if (netif_running(dev)) {
9194                 tg3_full_lock(tp, 0);
9195                 __tg3_set_coalesce(tp, &tp->coal);
9196                 tg3_full_unlock(tp);
9197         }
9198         return 0;
9199 }
9200
9201 static const struct ethtool_ops tg3_ethtool_ops = {
9202         .get_settings           = tg3_get_settings,
9203         .set_settings           = tg3_set_settings,
9204         .get_drvinfo            = tg3_get_drvinfo,
9205         .get_regs_len           = tg3_get_regs_len,
9206         .get_regs               = tg3_get_regs,
9207         .get_wol                = tg3_get_wol,
9208         .set_wol                = tg3_set_wol,
9209         .get_msglevel           = tg3_get_msglevel,
9210         .set_msglevel           = tg3_set_msglevel,
9211         .nway_reset             = tg3_nway_reset,
9212         .get_link               = ethtool_op_get_link,
9213         .get_eeprom_len         = tg3_get_eeprom_len,
9214         .get_eeprom             = tg3_get_eeprom,
9215         .set_eeprom             = tg3_set_eeprom,
9216         .get_ringparam          = tg3_get_ringparam,
9217         .set_ringparam          = tg3_set_ringparam,
9218         .get_pauseparam         = tg3_get_pauseparam,
9219         .set_pauseparam         = tg3_set_pauseparam,
9220         .get_rx_csum            = tg3_get_rx_csum,
9221         .set_rx_csum            = tg3_set_rx_csum,
9222         .get_tx_csum            = ethtool_op_get_tx_csum,
9223         .set_tx_csum            = tg3_set_tx_csum,
9224         .get_sg                 = ethtool_op_get_sg,
9225         .set_sg                 = ethtool_op_set_sg,
9226         .get_tso                = ethtool_op_get_tso,
9227         .set_tso                = tg3_set_tso,
9228         .self_test_count        = tg3_get_test_count,
9229         .self_test              = tg3_self_test,
9230         .get_strings            = tg3_get_strings,
9231         .phys_id                = tg3_phys_id,
9232         .get_stats_count        = tg3_get_stats_count,
9233         .get_ethtool_stats      = tg3_get_ethtool_stats,
9234         .get_coalesce           = tg3_get_coalesce,
9235         .set_coalesce           = tg3_set_coalesce,
9236         .get_perm_addr          = ethtool_op_get_perm_addr,
9237 };
9238
9239 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9240 {
9241         u32 cursize, val, magic;
9242
9243         tp->nvram_size = EEPROM_CHIP_SIZE;
9244
9245         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9246                 return;
9247
9248         if ((magic != TG3_EEPROM_MAGIC) &&
9249             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9250             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9251                 return;
9252
9253         /*
9254          * Size the chip by reading offsets at increasing powers of two.
9255          * When we encounter our validation signature, we know the addressing
9256          * has wrapped around, and thus have our chip size.
9257          */
9258         cursize = 0x10;
9259
9260         while (cursize < tp->nvram_size) {
9261                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9262                         return;
9263
9264                 if (val == magic)
9265                         break;
9266
9267                 cursize <<= 1;
9268         }
9269
9270         tp->nvram_size = cursize;
9271 }
9272
9273 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9274 {
9275         u32 val;
9276
9277         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9278                 return;
9279
9280         /* Selfboot format */
9281         if (val != TG3_EEPROM_MAGIC) {
9282                 tg3_get_eeprom_size(tp);
9283                 return;
9284         }
9285
9286         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9287                 if (val != 0) {
9288                         tp->nvram_size = (val >> 16) * 1024;
9289                         return;
9290                 }
9291         }
9292         tp->nvram_size = 0x20000;
9293 }
9294
9295 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9296 {
9297         u32 nvcfg1;
9298
9299         nvcfg1 = tr32(NVRAM_CFG1);
9300         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9301                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9302         }
9303         else {
9304                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9305                 tw32(NVRAM_CFG1, nvcfg1);
9306         }
9307
9308         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9309             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9310                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9311                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9312                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9313                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9314                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9315                                 break;
9316                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9317                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9318                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9319                                 break;
9320                         case FLASH_VENDOR_ATMEL_EEPROM:
9321                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9322                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9323                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9324                                 break;
9325                         case FLASH_VENDOR_ST:
9326                                 tp->nvram_jedecnum = JEDEC_ST;
9327                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9328                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9329                                 break;
9330                         case FLASH_VENDOR_SAIFUN:
9331                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9332                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9333                                 break;
9334                         case FLASH_VENDOR_SST_SMALL:
9335                         case FLASH_VENDOR_SST_LARGE:
9336                                 tp->nvram_jedecnum = JEDEC_SST;
9337                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9338                                 break;
9339                 }
9340         }
9341         else {
9342                 tp->nvram_jedecnum = JEDEC_ATMEL;
9343                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9344                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9345         }
9346 }
9347
9348 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9349 {
9350         u32 nvcfg1;
9351
9352         nvcfg1 = tr32(NVRAM_CFG1);
9353
9354         /* NVRAM protection for TPM */
9355         if (nvcfg1 & (1 << 27))
9356                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9357
9358         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9359                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9360                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9361                         tp->nvram_jedecnum = JEDEC_ATMEL;
9362                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9363                         break;
9364                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9365                         tp->nvram_jedecnum = JEDEC_ATMEL;
9366                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9367                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9368                         break;
9369                 case FLASH_5752VENDOR_ST_M45PE10:
9370                 case FLASH_5752VENDOR_ST_M45PE20:
9371                 case FLASH_5752VENDOR_ST_M45PE40:
9372                         tp->nvram_jedecnum = JEDEC_ST;
9373                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9374                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9375                         break;
9376         }
9377
9378         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9379                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9380                         case FLASH_5752PAGE_SIZE_256:
9381                                 tp->nvram_pagesize = 256;
9382                                 break;
9383                         case FLASH_5752PAGE_SIZE_512:
9384                                 tp->nvram_pagesize = 512;
9385                                 break;
9386                         case FLASH_5752PAGE_SIZE_1K:
9387                                 tp->nvram_pagesize = 1024;
9388                                 break;
9389                         case FLASH_5752PAGE_SIZE_2K:
9390                                 tp->nvram_pagesize = 2048;
9391                                 break;
9392                         case FLASH_5752PAGE_SIZE_4K:
9393                                 tp->nvram_pagesize = 4096;
9394                                 break;
9395                         case FLASH_5752PAGE_SIZE_264:
9396                                 tp->nvram_pagesize = 264;
9397                                 break;
9398                 }
9399         }
9400         else {
9401                 /* For eeprom, set pagesize to maximum eeprom size */
9402                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9403
9404                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9405                 tw32(NVRAM_CFG1, nvcfg1);
9406         }
9407 }
9408
9409 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9410 {
9411         u32 nvcfg1;
9412
9413         nvcfg1 = tr32(NVRAM_CFG1);
9414
9415         /* NVRAM protection for TPM */
9416         if (nvcfg1 & (1 << 27))
9417                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9418
9419         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9420                 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9421                 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9422                         tp->nvram_jedecnum = JEDEC_ATMEL;
9423                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9424                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9425
9426                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9427                         tw32(NVRAM_CFG1, nvcfg1);
9428                         break;
9429                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9430                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9431                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9432                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9433                 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9434                         tp->nvram_jedecnum = JEDEC_ATMEL;
9435                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9436                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9437                         tp->nvram_pagesize = 264;
9438                         break;
9439                 case FLASH_5752VENDOR_ST_M45PE10:
9440                 case FLASH_5752VENDOR_ST_M45PE20:
9441                 case FLASH_5752VENDOR_ST_M45PE40:
9442                         tp->nvram_jedecnum = JEDEC_ST;
9443                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9444                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9445                         tp->nvram_pagesize = 256;
9446                         break;
9447         }
9448 }
9449
9450 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9451 {
9452         u32 nvcfg1;
9453
9454         nvcfg1 = tr32(NVRAM_CFG1);
9455
9456         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9457                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9458                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9459                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9460                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9461                         tp->nvram_jedecnum = JEDEC_ATMEL;
9462                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9463                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9464
9465                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9466                         tw32(NVRAM_CFG1, nvcfg1);
9467                         break;
9468                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9469                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9470                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9471                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9472                         tp->nvram_jedecnum = JEDEC_ATMEL;
9473                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9474                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9475                         tp->nvram_pagesize = 264;
9476                         break;
9477                 case FLASH_5752VENDOR_ST_M45PE10:
9478                 case FLASH_5752VENDOR_ST_M45PE20:
9479                 case FLASH_5752VENDOR_ST_M45PE40:
9480                         tp->nvram_jedecnum = JEDEC_ST;
9481                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9482                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9483                         tp->nvram_pagesize = 256;
9484                         break;
9485         }
9486 }
9487
9488 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9489 {
9490         tp->nvram_jedecnum = JEDEC_ATMEL;
9491         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9492         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9493 }
9494
9495 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9496 static void __devinit tg3_nvram_init(struct tg3 *tp)
9497 {
9498         tw32_f(GRC_EEPROM_ADDR,
9499              (EEPROM_ADDR_FSM_RESET |
9500               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9501                EEPROM_ADDR_CLKPERD_SHIFT)));
9502
9503         msleep(1);
9504
9505         /* Enable seeprom accesses. */
9506         tw32_f(GRC_LOCAL_CTRL,
9507              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9508         udelay(100);
9509
9510         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9511             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9512                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9513
9514                 if (tg3_nvram_lock(tp)) {
9515                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9516                                "tg3_nvram_init failed.\n", tp->dev->name);
9517                         return;
9518                 }
9519                 tg3_enable_nvram_access(tp);
9520
9521                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9522                         tg3_get_5752_nvram_info(tp);
9523                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9524                         tg3_get_5755_nvram_info(tp);
9525                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9526                         tg3_get_5787_nvram_info(tp);
9527                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9528                         tg3_get_5906_nvram_info(tp);
9529                 else
9530                         tg3_get_nvram_info(tp);
9531
9532                 tg3_get_nvram_size(tp);
9533
9534                 tg3_disable_nvram_access(tp);
9535                 tg3_nvram_unlock(tp);
9536
9537         } else {
9538                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9539
9540                 tg3_get_eeprom_size(tp);
9541         }
9542 }
9543
9544 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9545                                         u32 offset, u32 *val)
9546 {
9547         u32 tmp;
9548         int i;
9549
9550         if (offset > EEPROM_ADDR_ADDR_MASK ||
9551             (offset % 4) != 0)
9552                 return -EINVAL;
9553
9554         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9555                                         EEPROM_ADDR_DEVID_MASK |
9556                                         EEPROM_ADDR_READ);
9557         tw32(GRC_EEPROM_ADDR,
9558              tmp |
9559              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9560              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9561               EEPROM_ADDR_ADDR_MASK) |
9562              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9563
9564         for (i = 0; i < 1000; i++) {
9565                 tmp = tr32(GRC_EEPROM_ADDR);
9566
9567                 if (tmp & EEPROM_ADDR_COMPLETE)
9568                         break;
9569                 msleep(1);
9570         }
9571         if (!(tmp & EEPROM_ADDR_COMPLETE))
9572                 return -EBUSY;
9573
9574         *val = tr32(GRC_EEPROM_DATA);
9575         return 0;
9576 }
9577
9578 #define NVRAM_CMD_TIMEOUT 10000
9579
9580 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9581 {
9582         int i;
9583
9584         tw32(NVRAM_CMD, nvram_cmd);
9585         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9586                 udelay(10);
9587                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9588                         udelay(10);
9589                         break;
9590                 }
9591         }
9592         if (i == NVRAM_CMD_TIMEOUT) {
9593                 return -EBUSY;
9594         }
9595         return 0;
9596 }
9597
9598 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9599 {
9600         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9601             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9602             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9603             (tp->nvram_jedecnum == JEDEC_ATMEL))
9604
9605                 addr = ((addr / tp->nvram_pagesize) <<
9606                         ATMEL_AT45DB0X1B_PAGE_POS) +
9607                        (addr % tp->nvram_pagesize);
9608
9609         return addr;
9610 }
9611
9612 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9613 {
9614         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9615             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9616             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9617             (tp->nvram_jedecnum == JEDEC_ATMEL))
9618
9619                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9620                         tp->nvram_pagesize) +
9621                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9622
9623         return addr;
9624 }
9625
9626 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9627 {
9628         int ret;
9629
9630         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9631                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9632
9633         offset = tg3_nvram_phys_addr(tp, offset);
9634
9635         if (offset > NVRAM_ADDR_MSK)
9636                 return -EINVAL;
9637
9638         ret = tg3_nvram_lock(tp);
9639         if (ret)
9640                 return ret;
9641
9642         tg3_enable_nvram_access(tp);
9643
9644         tw32(NVRAM_ADDR, offset);
9645         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9646                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9647
9648         if (ret == 0)
9649                 *val = swab32(tr32(NVRAM_RDDATA));
9650
9651         tg3_disable_nvram_access(tp);
9652
9653         tg3_nvram_unlock(tp);
9654
9655         return ret;
9656 }
9657
9658 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9659 {
9660         int err;
9661         u32 tmp;
9662
9663         err = tg3_nvram_read(tp, offset, &tmp);
9664         *val = swab32(tmp);
9665         return err;
9666 }
9667
9668 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9669                                     u32 offset, u32 len, u8 *buf)
9670 {
9671         int i, j, rc = 0;
9672         u32 val;
9673
9674         for (i = 0; i < len; i += 4) {
9675                 u32 addr, data;
9676
9677                 addr = offset + i;
9678
9679                 memcpy(&data, buf + i, 4);
9680
9681                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9682
9683                 val = tr32(GRC_EEPROM_ADDR);
9684                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9685
9686                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9687                         EEPROM_ADDR_READ);
9688                 tw32(GRC_EEPROM_ADDR, val |
9689                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9690                         (addr & EEPROM_ADDR_ADDR_MASK) |
9691                         EEPROM_ADDR_START |
9692                         EEPROM_ADDR_WRITE);
9693
9694                 for (j = 0; j < 1000; j++) {
9695                         val = tr32(GRC_EEPROM_ADDR);
9696
9697                         if (val & EEPROM_ADDR_COMPLETE)
9698                                 break;
9699                         msleep(1);
9700                 }
9701                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9702                         rc = -EBUSY;
9703                         break;
9704                 }
9705         }
9706
9707         return rc;
9708 }
9709
9710 /* offset and length are dword aligned */
9711 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9712                 u8 *buf)
9713 {
9714         int ret = 0;
9715         u32 pagesize = tp->nvram_pagesize;
9716         u32 pagemask = pagesize - 1;
9717         u32 nvram_cmd;
9718         u8 *tmp;
9719
9720         tmp = kmalloc(pagesize, GFP_KERNEL);
9721         if (tmp == NULL)
9722                 return -ENOMEM;
9723
9724         while (len) {
9725                 int j;
9726                 u32 phy_addr, page_off, size;
9727
9728                 phy_addr = offset & ~pagemask;
9729
9730                 for (j = 0; j < pagesize; j += 4) {
9731                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9732                                                 (u32 *) (tmp + j))))
9733                                 break;
9734                 }
9735                 if (ret)
9736                         break;
9737
9738                 page_off = offset & pagemask;
9739                 size = pagesize;
9740                 if (len < size)
9741                         size = len;
9742
9743                 len -= size;
9744
9745                 memcpy(tmp + page_off, buf, size);
9746
9747                 offset = offset + (pagesize - page_off);
9748
9749                 tg3_enable_nvram_access(tp);
9750
9751                 /*
9752                  * Before we can erase the flash page, we need
9753                  * to issue a special "write enable" command.
9754                  */
9755                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9756
9757                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9758                         break;
9759
9760                 /* Erase the target page */
9761                 tw32(NVRAM_ADDR, phy_addr);
9762
9763                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9764                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9765
9766                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9767                         break;
9768
9769                 /* Issue another write enable to start the write. */
9770                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9771
9772                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9773                         break;
9774
9775                 for (j = 0; j < pagesize; j += 4) {
9776                         u32 data;
9777
9778                         data = *((u32 *) (tmp + j));
9779                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9780
9781                         tw32(NVRAM_ADDR, phy_addr + j);
9782
9783                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9784                                 NVRAM_CMD_WR;
9785
9786                         if (j == 0)
9787                                 nvram_cmd |= NVRAM_CMD_FIRST;
9788                         else if (j == (pagesize - 4))
9789                                 nvram_cmd |= NVRAM_CMD_LAST;
9790
9791                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9792                                 break;
9793                 }
9794                 if (ret)
9795                         break;
9796         }
9797
9798         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9799         tg3_nvram_exec_cmd(tp, nvram_cmd);
9800
9801         kfree(tmp);
9802
9803         return ret;
9804 }
9805
9806 /* offset and length are dword aligned */
9807 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9808                 u8 *buf)
9809 {
9810         int i, ret = 0;
9811
9812         for (i = 0; i < len; i += 4, offset += 4) {
9813                 u32 data, page_off, phy_addr, nvram_cmd;
9814
9815                 memcpy(&data, buf + i, 4);
9816                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9817
9818                 page_off = offset % tp->nvram_pagesize;
9819
9820                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9821
9822                 tw32(NVRAM_ADDR, phy_addr);
9823
9824                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9825
9826                 if ((page_off == 0) || (i == 0))
9827                         nvram_cmd |= NVRAM_CMD_FIRST;
9828                 if (page_off == (tp->nvram_pagesize - 4))
9829                         nvram_cmd |= NVRAM_CMD_LAST;
9830
9831                 if (i == (len - 4))
9832                         nvram_cmd |= NVRAM_CMD_LAST;
9833
9834                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9835                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9836                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9837                     (tp->nvram_jedecnum == JEDEC_ST) &&
9838                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9839
9840                         if ((ret = tg3_nvram_exec_cmd(tp,
9841                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9842                                 NVRAM_CMD_DONE)))
9843
9844                                 break;
9845                 }
9846                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9847                         /* We always do complete word writes to eeprom. */
9848                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9849                 }
9850
9851                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9852                         break;
9853         }
9854         return ret;
9855 }
9856
9857 /* offset and length are dword aligned */
9858 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9859 {
9860         int ret;
9861
9862         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9863                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9864                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9865                 udelay(40);
9866         }
9867
9868         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9869                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9870         }
9871         else {
9872                 u32 grc_mode;
9873
9874                 ret = tg3_nvram_lock(tp);
9875                 if (ret)
9876                         return ret;
9877
9878                 tg3_enable_nvram_access(tp);
9879                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9880                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9881                         tw32(NVRAM_WRITE1, 0x406);
9882
9883                 grc_mode = tr32(GRC_MODE);
9884                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9885
9886                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9887                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9888
9889                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9890                                 buf);
9891                 }
9892                 else {
9893                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9894                                 buf);
9895                 }
9896
9897                 grc_mode = tr32(GRC_MODE);
9898                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9899
9900                 tg3_disable_nvram_access(tp);
9901                 tg3_nvram_unlock(tp);
9902         }
9903
9904         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9905                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9906                 udelay(40);
9907         }
9908
9909         return ret;
9910 }
9911
9912 struct subsys_tbl_ent {
9913         u16 subsys_vendor, subsys_devid;
9914         u32 phy_id;
9915 };
9916
9917 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9918         /* Broadcom boards. */
9919         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9920         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9921         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9922         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9923         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9924         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9925         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9926         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9927         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9928         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9929         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9930
9931         /* 3com boards. */
9932         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9933         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9934         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9935         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9936         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9937
9938         /* DELL boards. */
9939         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9940         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9941         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9942         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9943
9944         /* Compaq boards. */
9945         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9946         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9947         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9948         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9949         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9950
9951         /* IBM boards. */
9952         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9953 };
9954
9955 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9956 {
9957         int i;
9958
9959         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9960                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9961                      tp->pdev->subsystem_vendor) &&
9962                     (subsys_id_to_phy_id[i].subsys_devid ==
9963                      tp->pdev->subsystem_device))
9964                         return &subsys_id_to_phy_id[i];
9965         }
9966         return NULL;
9967 }
9968
9969 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9970 {
9971         u32 val;
9972         u16 pmcsr;
9973
9974         /* On some early chips the SRAM cannot be accessed in D3hot state,
9975          * so need make sure we're in D0.
9976          */
9977         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9978         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9979         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9980         msleep(1);
9981
9982         /* Make sure register accesses (indirect or otherwise)
9983          * will function correctly.
9984          */
9985         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9986                                tp->misc_host_ctrl);
9987
9988         /* The memory arbiter has to be enabled in order for SRAM accesses
9989          * to succeed.  Normally on powerup the tg3 chip firmware will make
9990          * sure it is enabled, but other entities such as system netboot
9991          * code might disable it.
9992          */
9993         val = tr32(MEMARB_MODE);
9994         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9995
9996         tp->phy_id = PHY_ID_INVALID;
9997         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9998
9999         /* Assume an onboard device by default.  */
10000         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10001
10002         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10003                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10004                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10005                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10006                 }
10007                 return;
10008         }
10009
10010         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10011         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10012                 u32 nic_cfg, led_cfg;
10013                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10014                 int eeprom_phy_serdes = 0;
10015
10016                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10017                 tp->nic_sram_data_cfg = nic_cfg;
10018
10019                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10020                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10021                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10022                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10023                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10024                     (ver > 0) && (ver < 0x100))
10025                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10026
10027                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10028                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10029                         eeprom_phy_serdes = 1;
10030
10031                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10032                 if (nic_phy_id != 0) {
10033                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10034                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10035
10036                         eeprom_phy_id  = (id1 >> 16) << 10;
10037                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10038                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10039                 } else
10040                         eeprom_phy_id = 0;
10041
10042                 tp->phy_id = eeprom_phy_id;
10043                 if (eeprom_phy_serdes) {
10044                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10045                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10046                         else
10047                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10048                 }
10049
10050                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10051                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10052                                     SHASTA_EXT_LED_MODE_MASK);
10053                 else
10054                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10055
10056                 switch (led_cfg) {
10057                 default:
10058                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10059                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10060                         break;
10061
10062                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10063                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10064                         break;
10065
10066                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10067                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10068
10069                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10070                          * read on some older 5700/5701 bootcode.
10071                          */
10072                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10073                             ASIC_REV_5700 ||
10074                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10075                             ASIC_REV_5701)
10076                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10077
10078                         break;
10079
10080                 case SHASTA_EXT_LED_SHARED:
10081                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10082                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10083                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10084                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10085                                                  LED_CTRL_MODE_PHY_2);
10086                         break;
10087
10088                 case SHASTA_EXT_LED_MAC:
10089                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10090                         break;
10091
10092                 case SHASTA_EXT_LED_COMBO:
10093                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10094                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10095                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10096                                                  LED_CTRL_MODE_PHY_2);
10097                         break;
10098
10099                 };
10100
10101                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10102                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10103                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10104                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10105
10106                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10107                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10108                         if ((tp->pdev->subsystem_vendor ==
10109                              PCI_VENDOR_ID_ARIMA) &&
10110                             (tp->pdev->subsystem_device == 0x205a ||
10111                              tp->pdev->subsystem_device == 0x2063))
10112                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10113                 } else {
10114                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10115                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10116                 }
10117
10118                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10119                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10120                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10121                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10122                 }
10123                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10124                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10125
10126                 if (cfg2 & (1 << 17))
10127                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10128
10129                 /* serdes signal pre-emphasis in register 0x590 set by */
10130                 /* bootcode if bit 18 is set */
10131                 if (cfg2 & (1 << 18))
10132                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10133         }
10134 }
10135
10136 static int __devinit tg3_phy_probe(struct tg3 *tp)
10137 {
10138         u32 hw_phy_id_1, hw_phy_id_2;
10139         u32 hw_phy_id, hw_phy_id_masked;
10140         int err;
10141
10142         /* Reading the PHY ID register can conflict with ASF
10143          * firwmare access to the PHY hardware.
10144          */
10145         err = 0;
10146         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10147                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10148         } else {
10149                 /* Now read the physical PHY_ID from the chip and verify
10150                  * that it is sane.  If it doesn't look good, we fall back
10151                  * to either the hard-coded table based PHY_ID and failing
10152                  * that the value found in the eeprom area.
10153                  */
10154                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10155                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10156
10157                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10158                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10159                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10160
10161                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10162         }
10163
10164         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10165                 tp->phy_id = hw_phy_id;
10166                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10167                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10168                 else
10169                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10170         } else {
10171                 if (tp->phy_id != PHY_ID_INVALID) {
10172                         /* Do nothing, phy ID already set up in
10173                          * tg3_get_eeprom_hw_cfg().
10174                          */
10175                 } else {
10176                         struct subsys_tbl_ent *p;
10177
10178                         /* No eeprom signature?  Try the hardcoded
10179                          * subsys device table.
10180                          */
10181                         p = lookup_by_subsys(tp);
10182                         if (!p)
10183                                 return -ENODEV;
10184
10185                         tp->phy_id = p->phy_id;
10186                         if (!tp->phy_id ||
10187                             tp->phy_id == PHY_ID_BCM8002)
10188                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10189                 }
10190         }
10191
10192         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10193             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10194                 u32 bmsr, adv_reg, tg3_ctrl, mask;
10195
10196                 tg3_readphy(tp, MII_BMSR, &bmsr);
10197                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10198                     (bmsr & BMSR_LSTATUS))
10199                         goto skip_phy_reset;
10200
10201                 err = tg3_phy_reset(tp);
10202                 if (err)
10203                         return err;
10204
10205                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10206                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10207                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10208                 tg3_ctrl = 0;
10209                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10210                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10211                                     MII_TG3_CTRL_ADV_1000_FULL);
10212                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10213                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10214                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10215                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10216                 }
10217
10218                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10219                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10220                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10221                 if (!tg3_copper_is_advertising_all(tp, mask)) {
10222                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10223
10224                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10225                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10226
10227                         tg3_writephy(tp, MII_BMCR,
10228                                      BMCR_ANENABLE | BMCR_ANRESTART);
10229                 }
10230                 tg3_phy_set_wirespeed(tp);
10231
10232                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10233                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10234                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10235         }
10236
10237 skip_phy_reset:
10238         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10239                 err = tg3_init_5401phy_dsp(tp);
10240                 if (err)
10241                         return err;
10242         }
10243
10244         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10245                 err = tg3_init_5401phy_dsp(tp);
10246         }
10247
10248         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10249                 tp->link_config.advertising =
10250                         (ADVERTISED_1000baseT_Half |
10251                          ADVERTISED_1000baseT_Full |
10252                          ADVERTISED_Autoneg |
10253                          ADVERTISED_FIBRE);
10254         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10255                 tp->link_config.advertising &=
10256                         ~(ADVERTISED_1000baseT_Half |
10257                           ADVERTISED_1000baseT_Full);
10258
10259         return err;
10260 }
10261
10262 static void __devinit tg3_read_partno(struct tg3 *tp)
10263 {
10264         unsigned char vpd_data[256];
10265         unsigned int i;
10266         u32 magic;
10267
10268         if (tg3_nvram_read_swab(tp, 0x0, &magic))
10269                 goto out_not_found;
10270
10271         if (magic == TG3_EEPROM_MAGIC) {
10272                 for (i = 0; i < 256; i += 4) {
10273                         u32 tmp;
10274
10275                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10276                                 goto out_not_found;
10277
10278                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
10279                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
10280                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10281                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10282                 }
10283         } else {
10284                 int vpd_cap;
10285
10286                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10287                 for (i = 0; i < 256; i += 4) {
10288                         u32 tmp, j = 0;
10289                         u16 tmp16;
10290
10291                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10292                                               i);
10293                         while (j++ < 100) {
10294                                 pci_read_config_word(tp->pdev, vpd_cap +
10295                                                      PCI_VPD_ADDR, &tmp16);
10296                                 if (tmp16 & 0x8000)
10297                                         break;
10298                                 msleep(1);
10299                         }
10300                         if (!(tmp16 & 0x8000))
10301                                 goto out_not_found;
10302
10303                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10304                                               &tmp);
10305                         tmp = cpu_to_le32(tmp);
10306                         memcpy(&vpd_data[i], &tmp, 4);
10307                 }
10308         }
10309
10310         /* Now parse and find the part number. */
10311         for (i = 0; i < 254; ) {
10312                 unsigned char val = vpd_data[i];
10313                 unsigned int block_end;
10314
10315                 if (val == 0x82 || val == 0x91) {
10316                         i = (i + 3 +
10317                              (vpd_data[i + 1] +
10318                               (vpd_data[i + 2] << 8)));
10319                         continue;
10320                 }
10321
10322                 if (val != 0x90)
10323                         goto out_not_found;
10324
10325                 block_end = (i + 3 +
10326                              (vpd_data[i + 1] +
10327                               (vpd_data[i + 2] << 8)));
10328                 i += 3;
10329
10330                 if (block_end > 256)
10331                         goto out_not_found;
10332
10333                 while (i < (block_end - 2)) {
10334                         if (vpd_data[i + 0] == 'P' &&
10335                             vpd_data[i + 1] == 'N') {
10336                                 int partno_len = vpd_data[i + 2];
10337
10338                                 i += 3;
10339                                 if (partno_len > 24 || (partno_len + i) > 256)
10340                                         goto out_not_found;
10341
10342                                 memcpy(tp->board_part_number,
10343                                        &vpd_data[i], partno_len);
10344
10345                                 /* Success. */
10346                                 return;
10347                         }
10348                         i += 3 + vpd_data[i + 2];
10349                 }
10350
10351                 /* Part number not found. */
10352                 goto out_not_found;
10353         }
10354
10355 out_not_found:
10356         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10357                 strcpy(tp->board_part_number, "BCM95906");
10358         else
10359                 strcpy(tp->board_part_number, "none");
10360 }
10361
10362 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10363 {
10364         u32 val, offset, start;
10365
10366         if (tg3_nvram_read_swab(tp, 0, &val))
10367                 return;
10368
10369         if (val != TG3_EEPROM_MAGIC)
10370                 return;
10371
10372         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10373             tg3_nvram_read_swab(tp, 0x4, &start))
10374                 return;
10375
10376         offset = tg3_nvram_logical_addr(tp, offset);
10377         if (tg3_nvram_read_swab(tp, offset, &val))
10378                 return;
10379
10380         if ((val & 0xfc000000) == 0x0c000000) {
10381                 u32 ver_offset, addr;
10382                 int i;
10383
10384                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10385                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10386                         return;
10387
10388                 if (val != 0)
10389                         return;
10390
10391                 addr = offset + ver_offset - start;
10392                 for (i = 0; i < 16; i += 4) {
10393                         if (tg3_nvram_read(tp, addr + i, &val))
10394                                 return;
10395
10396                         val = cpu_to_le32(val);
10397                         memcpy(tp->fw_ver + i, &val, 4);
10398                 }
10399         }
10400 }
10401
10402 static int __devinit tg3_get_invariants(struct tg3 *tp)
10403 {
10404         static struct pci_device_id write_reorder_chipsets[] = {
10405                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10406                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10407                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10408                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10409                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10410                              PCI_DEVICE_ID_VIA_8385_0) },
10411                 { },
10412         };
10413         u32 misc_ctrl_reg;
10414         u32 cacheline_sz_reg;
10415         u32 pci_state_reg, grc_misc_cfg;
10416         u32 val;
10417         u16 pci_cmd;
10418         int err, pcie_cap;
10419
10420         /* Force memory write invalidate off.  If we leave it on,
10421          * then on 5700_BX chips we have to enable a workaround.
10422          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10423          * to match the cacheline size.  The Broadcom driver have this
10424          * workaround but turns MWI off all the times so never uses
10425          * it.  This seems to suggest that the workaround is insufficient.
10426          */
10427         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10428         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10429         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10430
10431         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10432          * has the register indirect write enable bit set before
10433          * we try to access any of the MMIO registers.  It is also
10434          * critical that the PCI-X hw workaround situation is decided
10435          * before that as well.
10436          */
10437         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10438                               &misc_ctrl_reg);
10439
10440         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10441                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10442
10443         /* Wrong chip ID in 5752 A0. This code can be removed later
10444          * as A0 is not in production.
10445          */
10446         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10447                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10448
10449         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10450          * we need to disable memory and use config. cycles
10451          * only to access all registers. The 5702/03 chips
10452          * can mistakenly decode the special cycles from the
10453          * ICH chipsets as memory write cycles, causing corruption
10454          * of register and memory space. Only certain ICH bridges
10455          * will drive special cycles with non-zero data during the
10456          * address phase which can fall within the 5703's address
10457          * range. This is not an ICH bug as the PCI spec allows
10458          * non-zero address during special cycles. However, only
10459          * these ICH bridges are known to drive non-zero addresses
10460          * during special cycles.
10461          *
10462          * Since special cycles do not cross PCI bridges, we only
10463          * enable this workaround if the 5703 is on the secondary
10464          * bus of these ICH bridges.
10465          */
10466         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10467             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10468                 static struct tg3_dev_id {
10469                         u32     vendor;
10470                         u32     device;
10471                         u32     rev;
10472                 } ich_chipsets[] = {
10473                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10474                           PCI_ANY_ID },
10475                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10476                           PCI_ANY_ID },
10477                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10478                           0xa },
10479                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10480                           PCI_ANY_ID },
10481                         { },
10482                 };
10483                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10484                 struct pci_dev *bridge = NULL;
10485
10486                 while (pci_id->vendor != 0) {
10487                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10488                                                 bridge);
10489                         if (!bridge) {
10490                                 pci_id++;
10491                                 continue;
10492                         }
10493                         if (pci_id->rev != PCI_ANY_ID) {
10494                                 u8 rev;
10495
10496                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10497                                                      &rev);
10498                                 if (rev > pci_id->rev)
10499                                         continue;
10500                         }
10501                         if (bridge->subordinate &&
10502                             (bridge->subordinate->number ==
10503                              tp->pdev->bus->number)) {
10504
10505                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10506                                 pci_dev_put(bridge);
10507                                 break;
10508                         }
10509                 }
10510         }
10511
10512         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10513          * DMA addresses > 40-bit. This bridge may have other additional
10514          * 57xx devices behind it in some 4-port NIC designs for example.
10515          * Any tg3 device found behind the bridge will also need the 40-bit
10516          * DMA workaround.
10517          */
10518         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10519             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10520                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10521                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10522                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10523         }
10524         else {
10525                 struct pci_dev *bridge = NULL;
10526
10527                 do {
10528                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10529                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10530                                                 bridge);
10531                         if (bridge && bridge->subordinate &&
10532                             (bridge->subordinate->number <=
10533                              tp->pdev->bus->number) &&
10534                             (bridge->subordinate->subordinate >=
10535                              tp->pdev->bus->number)) {
10536                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10537                                 pci_dev_put(bridge);
10538                                 break;
10539                         }
10540                 } while (bridge);
10541         }
10542
10543         /* Initialize misc host control in PCI block. */
10544         tp->misc_host_ctrl |= (misc_ctrl_reg &
10545                                MISC_HOST_CTRL_CHIPREV);
10546         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10547                                tp->misc_host_ctrl);
10548
10549         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10550                               &cacheline_sz_reg);
10551
10552         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10553         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10554         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10555         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10556
10557         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10558             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10559             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10560             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10561             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10562             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10563                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10564
10565         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10566             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10567                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10568
10569         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10570                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10571                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10572                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10573                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10574                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10575                 } else {
10576                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10577                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10578                                 ASIC_REV_5750 &&
10579                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10580                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10581                 }
10582         }
10583
10584         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10585             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10586             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10587             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10588             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10589             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10590                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10591
10592         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10593         if (pcie_cap != 0) {
10594                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10595                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10596                         u16 lnkctl;
10597
10598                         pci_read_config_word(tp->pdev,
10599                                              pcie_cap + PCI_EXP_LNKCTL,
10600                                              &lnkctl);
10601                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10602                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10603                 }
10604         }
10605
10606         /* If we have an AMD 762 or VIA K8T800 chipset, write
10607          * reordering to the mailbox registers done by the host
10608          * controller can cause major troubles.  We read back from
10609          * every mailbox register write to force the writes to be
10610          * posted to the chip in order.
10611          */
10612         if (pci_dev_present(write_reorder_chipsets) &&
10613             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10614                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10615
10616         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10617             tp->pci_lat_timer < 64) {
10618                 tp->pci_lat_timer = 64;
10619
10620                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10621                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10622                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10623                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10624
10625                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10626                                        cacheline_sz_reg);
10627         }
10628
10629         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10630                               &pci_state_reg);
10631
10632         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10633                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10634
10635                 /* If this is a 5700 BX chipset, and we are in PCI-X
10636                  * mode, enable register write workaround.
10637                  *
10638                  * The workaround is to use indirect register accesses
10639                  * for all chip writes not to mailbox registers.
10640                  */
10641                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10642                         u32 pm_reg;
10643                         u16 pci_cmd;
10644
10645                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10646
10647                         /* The chip can have it's power management PCI config
10648                          * space registers clobbered due to this bug.
10649                          * So explicitly force the chip into D0 here.
10650                          */
10651                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10652                                               &pm_reg);
10653                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10654                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10655                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10656                                                pm_reg);
10657
10658                         /* Also, force SERR#/PERR# in PCI command. */
10659                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10660                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10661                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10662                 }
10663         }
10664
10665         /* 5700 BX chips need to have their TX producer index mailboxes
10666          * written twice to workaround a bug.
10667          */
10668         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10669                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10670
10671         /* Back to back register writes can cause problems on this chip,
10672          * the workaround is to read back all reg writes except those to
10673          * mailbox regs.  See tg3_write_indirect_reg32().
10674          *
10675          * PCI Express 5750_A0 rev chips need this workaround too.
10676          */
10677         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10678             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10679              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10680                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10681
10682         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10683                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10684         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10685                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10686
10687         /* Chip-specific fixup from Broadcom driver */
10688         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10689             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10690                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10691                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10692         }
10693
10694         /* Default fast path register access methods */
10695         tp->read32 = tg3_read32;
10696         tp->write32 = tg3_write32;
10697         tp->read32_mbox = tg3_read32;
10698         tp->write32_mbox = tg3_write32;
10699         tp->write32_tx_mbox = tg3_write32;
10700         tp->write32_rx_mbox = tg3_write32;
10701
10702         /* Various workaround register access methods */
10703         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10704                 tp->write32 = tg3_write_indirect_reg32;
10705         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10706                 tp->write32 = tg3_write_flush_reg32;
10707
10708         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10709             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10710                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10711                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10712                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10713         }
10714
10715         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10716                 tp->read32 = tg3_read_indirect_reg32;
10717                 tp->write32 = tg3_write_indirect_reg32;
10718                 tp->read32_mbox = tg3_read_indirect_mbox;
10719                 tp->write32_mbox = tg3_write_indirect_mbox;
10720                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10721                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10722
10723                 iounmap(tp->regs);
10724                 tp->regs = NULL;
10725
10726                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10727                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10728                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10729         }
10730         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10731                 tp->read32_mbox = tg3_read32_mbox_5906;
10732                 tp->write32_mbox = tg3_write32_mbox_5906;
10733                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10734                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10735         }
10736
10737         if (tp->write32 == tg3_write_indirect_reg32 ||
10738             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10739              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10740               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10741                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10742
10743         /* Get eeprom hw config before calling tg3_set_power_state().
10744          * In particular, the TG3_FLG2_IS_NIC flag must be
10745          * determined before calling tg3_set_power_state() so that
10746          * we know whether or not to switch out of Vaux power.
10747          * When the flag is set, it means that GPIO1 is used for eeprom
10748          * write protect and also implies that it is a LOM where GPIOs
10749          * are not used to switch power.
10750          */
10751         tg3_get_eeprom_hw_cfg(tp);
10752
10753         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10754          * GPIO1 driven high will bring 5700's external PHY out of reset.
10755          * It is also used as eeprom write protect on LOMs.
10756          */
10757         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10758         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10759             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10760                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10761                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10762         /* Unused GPIO3 must be driven as output on 5752 because there
10763          * are no pull-up resistors on unused GPIO pins.
10764          */
10765         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10766                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10767
10768         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10769                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10770
10771         /* Force the chip into D0. */
10772         err = tg3_set_power_state(tp, PCI_D0);
10773         if (err) {
10774                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10775                        pci_name(tp->pdev));
10776                 return err;
10777         }
10778
10779         /* 5700 B0 chips do not support checksumming correctly due
10780          * to hardware bugs.
10781          */
10782         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10783                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10784
10785         /* Derive initial jumbo mode from MTU assigned in
10786          * ether_setup() via the alloc_etherdev() call
10787          */
10788         if (tp->dev->mtu > ETH_DATA_LEN &&
10789             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10790                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10791
10792         /* Determine WakeOnLan speed to use. */
10793         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10794             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10795             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10796             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10797                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10798         } else {
10799                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10800         }
10801
10802         /* A few boards don't want Ethernet@WireSpeed phy feature */
10803         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10804             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10805              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10806              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10807             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10808             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10809                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10810
10811         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10812             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10813                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10814         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10815                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10816
10817         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10818                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10819                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10820                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10821                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10822                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10823                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10824                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10825                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10826                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10827         }
10828
10829         tp->coalesce_mode = 0;
10830         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10831             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10832                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10833
10834         /* Initialize MAC MI mode, polling disabled. */
10835         tw32_f(MAC_MI_MODE, tp->mi_mode);
10836         udelay(80);
10837
10838         /* Initialize data/descriptor byte/word swapping. */
10839         val = tr32(GRC_MODE);
10840         val &= GRC_MODE_HOST_STACKUP;
10841         tw32(GRC_MODE, val | tp->grc_mode);
10842
10843         tg3_switch_clocks(tp);
10844
10845         /* Clear this out for sanity. */
10846         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10847
10848         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10849                               &pci_state_reg);
10850         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10851             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10852                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10853
10854                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10855                     chiprevid == CHIPREV_ID_5701_B0 ||
10856                     chiprevid == CHIPREV_ID_5701_B2 ||
10857                     chiprevid == CHIPREV_ID_5701_B5) {
10858                         void __iomem *sram_base;
10859
10860                         /* Write some dummy words into the SRAM status block
10861                          * area, see if it reads back correctly.  If the return
10862                          * value is bad, force enable the PCIX workaround.
10863                          */
10864                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10865
10866                         writel(0x00000000, sram_base);
10867                         writel(0x00000000, sram_base + 4);
10868                         writel(0xffffffff, sram_base + 4);
10869                         if (readl(sram_base) != 0x00000000)
10870                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10871                 }
10872         }
10873
10874         udelay(50);
10875         tg3_nvram_init(tp);
10876
10877         grc_misc_cfg = tr32(GRC_MISC_CFG);
10878         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10879
10880         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10881             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10882              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10883                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10884
10885         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10886             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10887                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10888         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10889                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10890                                       HOSTCC_MODE_CLRTICK_TXBD);
10891
10892                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10893                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10894                                        tp->misc_host_ctrl);
10895         }
10896
10897         /* these are limited to 10/100 only */
10898         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10899              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10900             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10901              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10902              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10903               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10904               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10905             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10906              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10907               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10908               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10909             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10910                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10911
10912         err = tg3_phy_probe(tp);
10913         if (err) {
10914                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10915                        pci_name(tp->pdev), err);
10916                 /* ... but do not return immediately ... */
10917         }
10918
10919         tg3_read_partno(tp);
10920         tg3_read_fw_ver(tp);
10921
10922         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10923                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10924         } else {
10925                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10926                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10927                 else
10928                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10929         }
10930
10931         /* 5700 {AX,BX} chips have a broken status block link
10932          * change bit implementation, so we must use the
10933          * status register in those cases.
10934          */
10935         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10936                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10937         else
10938                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10939
10940         /* The led_ctrl is set during tg3_phy_probe, here we might
10941          * have to force the link status polling mechanism based
10942          * upon subsystem IDs.
10943          */
10944         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10945             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10946                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10947                                   TG3_FLAG_USE_LINKCHG_REG);
10948         }
10949
10950         /* For all SERDES we poll the MAC status register. */
10951         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10952                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10953         else
10954                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10955
10956         /* All chips before 5787 can get confused if TX buffers
10957          * straddle the 4GB address boundary in some cases.
10958          */
10959         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10960             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10961             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10962                 tp->dev->hard_start_xmit = tg3_start_xmit;
10963         else
10964                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10965
10966         tp->rx_offset = 2;
10967         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10968             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10969                 tp->rx_offset = 0;
10970
10971         tp->rx_std_max_post = TG3_RX_RING_SIZE;
10972
10973         /* Increment the rx prod index on the rx std ring by at most
10974          * 8 for these chips to workaround hw errata.
10975          */
10976         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10978             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10979                 tp->rx_std_max_post = 8;
10980
10981         /* By default, disable wake-on-lan.  User can change this
10982          * using ETHTOOL_SWOL.
10983          */
10984         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10985
10986         return err;
10987 }
10988
10989 #ifdef CONFIG_SPARC64
10990 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10991 {
10992         struct net_device *dev = tp->dev;
10993         struct pci_dev *pdev = tp->pdev;
10994         struct pcidev_cookie *pcp = pdev->sysdata;
10995
10996         if (pcp != NULL) {
10997                 unsigned char *addr;
10998                 int len;
10999
11000                 addr = of_get_property(pcp->prom_node, "local-mac-address",
11001                                         &len);
11002                 if (addr && len == 6) {
11003                         memcpy(dev->dev_addr, addr, 6);
11004                         memcpy(dev->perm_addr, dev->dev_addr, 6);
11005                         return 0;
11006                 }
11007         }
11008         return -ENODEV;
11009 }
11010
11011 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11012 {
11013         struct net_device *dev = tp->dev;
11014
11015         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11016         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11017         return 0;
11018 }
11019 #endif
11020
11021 static int __devinit tg3_get_device_address(struct tg3 *tp)
11022 {
11023         struct net_device *dev = tp->dev;
11024         u32 hi, lo, mac_offset;
11025         int addr_ok = 0;
11026
11027 #ifdef CONFIG_SPARC64
11028         if (!tg3_get_macaddr_sparc(tp))
11029                 return 0;
11030 #endif
11031
11032         mac_offset = 0x7c;
11033         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11034             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11035                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11036                         mac_offset = 0xcc;
11037                 if (tg3_nvram_lock(tp))
11038                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11039                 else
11040                         tg3_nvram_unlock(tp);
11041         }
11042         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11043                 mac_offset = 0x10;
11044
11045         /* First try to get it from MAC address mailbox. */
11046         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11047         if ((hi >> 16) == 0x484b) {
11048                 dev->dev_addr[0] = (hi >>  8) & 0xff;
11049                 dev->dev_addr[1] = (hi >>  0) & 0xff;
11050
11051                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11052                 dev->dev_addr[2] = (lo >> 24) & 0xff;
11053                 dev->dev_addr[3] = (lo >> 16) & 0xff;
11054                 dev->dev_addr[4] = (lo >>  8) & 0xff;
11055                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11056
11057                 /* Some old bootcode may report a 0 MAC address in SRAM */
11058                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11059         }
11060         if (!addr_ok) {
11061                 /* Next, try NVRAM. */
11062                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11063                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11064                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11065                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
11066                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
11067                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
11068                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
11069                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
11070                 }
11071                 /* Finally just fetch it out of the MAC control regs. */
11072                 else {
11073                         hi = tr32(MAC_ADDR_0_HIGH);
11074                         lo = tr32(MAC_ADDR_0_LOW);
11075
11076                         dev->dev_addr[5] = lo & 0xff;
11077                         dev->dev_addr[4] = (lo >> 8) & 0xff;
11078                         dev->dev_addr[3] = (lo >> 16) & 0xff;
11079                         dev->dev_addr[2] = (lo >> 24) & 0xff;
11080                         dev->dev_addr[1] = hi & 0xff;
11081                         dev->dev_addr[0] = (hi >> 8) & 0xff;
11082                 }
11083         }
11084
11085         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11086 #ifdef CONFIG_SPARC64
11087                 if (!tg3_get_default_macaddr_sparc(tp))
11088                         return 0;
11089 #endif
11090                 return -EINVAL;
11091         }
11092         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11093         return 0;
11094 }
11095
11096 #define BOUNDARY_SINGLE_CACHELINE       1
11097 #define BOUNDARY_MULTI_CACHELINE        2
11098
11099 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11100 {
11101         int cacheline_size;
11102         u8 byte;
11103         int goal;
11104
11105         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11106         if (byte == 0)
11107                 cacheline_size = 1024;
11108         else
11109                 cacheline_size = (int) byte * 4;
11110
11111         /* On 5703 and later chips, the boundary bits have no
11112          * effect.
11113          */
11114         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11115             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11116             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11117                 goto out;
11118
11119 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11120         goal = BOUNDARY_MULTI_CACHELINE;
11121 #else
11122 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11123         goal = BOUNDARY_SINGLE_CACHELINE;
11124 #else
11125         goal = 0;
11126 #endif
11127 #endif
11128
11129         if (!goal)
11130                 goto out;
11131
11132         /* PCI controllers on most RISC systems tend to disconnect
11133          * when a device tries to burst across a cache-line boundary.
11134          * Therefore, letting tg3 do so just wastes PCI bandwidth.
11135          *
11136          * Unfortunately, for PCI-E there are only limited
11137          * write-side controls for this, and thus for reads
11138          * we will still get the disconnects.  We'll also waste
11139          * these PCI cycles for both read and write for chips
11140          * other than 5700 and 5701 which do not implement the
11141          * boundary bits.
11142          */
11143         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11144             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11145                 switch (cacheline_size) {
11146                 case 16:
11147                 case 32:
11148                 case 64:
11149                 case 128:
11150                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11151                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11152                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11153                         } else {
11154                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11155                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11156                         }
11157                         break;
11158
11159                 case 256:
11160                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11161                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11162                         break;
11163
11164                 default:
11165                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11166                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11167                         break;
11168                 };
11169         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11170                 switch (cacheline_size) {
11171                 case 16:
11172                 case 32:
11173                 case 64:
11174                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11175                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11176                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11177                                 break;
11178                         }
11179                         /* fallthrough */
11180                 case 128:
11181                 default:
11182                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11183                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11184                         break;
11185                 };
11186         } else {
11187                 switch (cacheline_size) {
11188                 case 16:
11189                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11190                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11191                                         DMA_RWCTRL_WRITE_BNDRY_16);
11192                                 break;
11193                         }
11194                         /* fallthrough */
11195                 case 32:
11196                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11197                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11198                                         DMA_RWCTRL_WRITE_BNDRY_32);
11199                                 break;
11200                         }
11201                         /* fallthrough */
11202                 case 64:
11203                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11204                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11205                                         DMA_RWCTRL_WRITE_BNDRY_64);
11206                                 break;
11207                         }
11208                         /* fallthrough */
11209                 case 128:
11210                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11211                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11212                                         DMA_RWCTRL_WRITE_BNDRY_128);
11213                                 break;
11214                         }
11215                         /* fallthrough */
11216                 case 256:
11217                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
11218                                 DMA_RWCTRL_WRITE_BNDRY_256);
11219                         break;
11220                 case 512:
11221                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
11222                                 DMA_RWCTRL_WRITE_BNDRY_512);
11223                         break;
11224                 case 1024:
11225                 default:
11226                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11227                                 DMA_RWCTRL_WRITE_BNDRY_1024);
11228                         break;
11229                 };
11230         }
11231
11232 out:
11233         return val;
11234 }
11235
11236 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11237 {
11238         struct tg3_internal_buffer_desc test_desc;
11239         u32 sram_dma_descs;
11240         int i, ret;
11241
11242         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11243
11244         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11245         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11246         tw32(RDMAC_STATUS, 0);
11247         tw32(WDMAC_STATUS, 0);
11248
11249         tw32(BUFMGR_MODE, 0);
11250         tw32(FTQ_RESET, 0);
11251
11252         test_desc.addr_hi = ((u64) buf_dma) >> 32;
11253         test_desc.addr_lo = buf_dma & 0xffffffff;
11254         test_desc.nic_mbuf = 0x00002100;
11255         test_desc.len = size;
11256
11257         /*
11258          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11259          * the *second* time the tg3 driver was getting loaded after an
11260          * initial scan.
11261          *
11262          * Broadcom tells me:
11263          *   ...the DMA engine is connected to the GRC block and a DMA
11264          *   reset may affect the GRC block in some unpredictable way...
11265          *   The behavior of resets to individual blocks has not been tested.
11266          *
11267          * Broadcom noted the GRC reset will also reset all sub-components.
11268          */
11269         if (to_device) {
11270                 test_desc.cqid_sqid = (13 << 8) | 2;
11271
11272                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11273                 udelay(40);
11274         } else {
11275                 test_desc.cqid_sqid = (16 << 8) | 7;
11276
11277                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11278                 udelay(40);
11279         }
11280         test_desc.flags = 0x00000005;
11281
11282         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11283                 u32 val;
11284
11285                 val = *(((u32 *)&test_desc) + i);
11286                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11287                                        sram_dma_descs + (i * sizeof(u32)));
11288                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11289         }
11290         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11291
11292         if (to_device) {
11293                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11294         } else {
11295                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11296         }
11297
11298         ret = -ENODEV;
11299         for (i = 0; i < 40; i++) {
11300                 u32 val;
11301
11302                 if (to_device)
11303                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11304                 else
11305                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11306                 if ((val & 0xffff) == sram_dma_descs) {
11307                         ret = 0;
11308                         break;
11309                 }
11310
11311                 udelay(100);
11312         }
11313
11314         return ret;
11315 }
11316
11317 #define TEST_BUFFER_SIZE        0x2000
11318
11319 static int __devinit tg3_test_dma(struct tg3 *tp)
11320 {
11321         dma_addr_t buf_dma;
11322         u32 *buf, saved_dma_rwctrl;
11323         int ret;
11324
11325         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11326         if (!buf) {
11327                 ret = -ENOMEM;
11328                 goto out_nofree;
11329         }
11330
11331         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11332                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11333
11334         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11335
11336         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11337                 /* DMA read watermark not used on PCIE */
11338                 tp->dma_rwctrl |= 0x00180000;
11339         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11340                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11341                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11342                         tp->dma_rwctrl |= 0x003f0000;
11343                 else
11344                         tp->dma_rwctrl |= 0x003f000f;
11345         } else {
11346                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11347                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11348                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11349                         u32 read_water = 0x7;
11350
11351                         /* If the 5704 is behind the EPB bridge, we can
11352                          * do the less restrictive ONE_DMA workaround for
11353                          * better performance.
11354                          */
11355                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11356                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11357                                 tp->dma_rwctrl |= 0x8000;
11358                         else if (ccval == 0x6 || ccval == 0x7)
11359                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11360
11361                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11362                                 read_water = 4;
11363                         /* Set bit 23 to enable PCIX hw bug fix */
11364                         tp->dma_rwctrl |=
11365                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11366                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11367                                 (1 << 23);
11368                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11369                         /* 5780 always in PCIX mode */
11370                         tp->dma_rwctrl |= 0x00144000;
11371                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11372                         /* 5714 always in PCIX mode */
11373                         tp->dma_rwctrl |= 0x00148000;
11374                 } else {
11375                         tp->dma_rwctrl |= 0x001b000f;
11376                 }
11377         }
11378
11379         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11380             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11381                 tp->dma_rwctrl &= 0xfffffff0;
11382
11383         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11384             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11385                 /* Remove this if it causes problems for some boards. */
11386                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11387
11388                 /* On 5700/5701 chips, we need to set this bit.
11389                  * Otherwise the chip will issue cacheline transactions
11390                  * to streamable DMA memory with not all the byte
11391                  * enables turned on.  This is an error on several
11392                  * RISC PCI controllers, in particular sparc64.
11393                  *
11394                  * On 5703/5704 chips, this bit has been reassigned
11395                  * a different meaning.  In particular, it is used
11396                  * on those chips to enable a PCI-X workaround.
11397                  */
11398                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11399         }
11400
11401         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11402
11403 #if 0
11404         /* Unneeded, already done by tg3_get_invariants.  */
11405         tg3_switch_clocks(tp);
11406 #endif
11407
11408         ret = 0;
11409         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11410             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11411                 goto out;
11412
11413         /* It is best to perform DMA test with maximum write burst size
11414          * to expose the 5700/5701 write DMA bug.
11415          */
11416         saved_dma_rwctrl = tp->dma_rwctrl;
11417         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11418         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11419
11420         while (1) {
11421                 u32 *p = buf, i;
11422
11423                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11424                         p[i] = i;
11425
11426                 /* Send the buffer to the chip. */
11427                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11428                 if (ret) {
11429                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11430                         break;
11431                 }
11432
11433 #if 0
11434                 /* validate data reached card RAM correctly. */
11435                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11436                         u32 val;
11437                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
11438                         if (le32_to_cpu(val) != p[i]) {
11439                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
11440                                 /* ret = -ENODEV here? */
11441                         }
11442                         p[i] = 0;
11443                 }
11444 #endif
11445                 /* Now read it back. */
11446                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11447                 if (ret) {
11448                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11449
11450                         break;
11451                 }
11452
11453                 /* Verify it. */
11454                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11455                         if (p[i] == i)
11456                                 continue;
11457
11458                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11459                             DMA_RWCTRL_WRITE_BNDRY_16) {
11460                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11461                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11462                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11463                                 break;
11464                         } else {
11465                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11466                                 ret = -ENODEV;
11467                                 goto out;
11468                         }
11469                 }
11470
11471                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11472                         /* Success. */
11473                         ret = 0;
11474                         break;
11475                 }
11476         }
11477         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11478             DMA_RWCTRL_WRITE_BNDRY_16) {
11479                 static struct pci_device_id dma_wait_state_chipsets[] = {
11480                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11481                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11482                         { },
11483                 };
11484
11485                 /* DMA test passed without adjusting DMA boundary,
11486                  * now look for chipsets that are known to expose the
11487                  * DMA bug without failing the test.
11488                  */
11489                 if (pci_dev_present(dma_wait_state_chipsets)) {
11490                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11491                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11492                 }
11493                 else
11494                         /* Safe to use the calculated DMA boundary. */
11495                         tp->dma_rwctrl = saved_dma_rwctrl;
11496
11497                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11498         }
11499
11500 out:
11501         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11502 out_nofree:
11503         return ret;
11504 }
11505
11506 static void __devinit tg3_init_link_config(struct tg3 *tp)
11507 {
11508         tp->link_config.advertising =
11509                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11510                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11511                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11512                  ADVERTISED_Autoneg | ADVERTISED_MII);
11513         tp->link_config.speed = SPEED_INVALID;
11514         tp->link_config.duplex = DUPLEX_INVALID;
11515         tp->link_config.autoneg = AUTONEG_ENABLE;
11516         tp->link_config.active_speed = SPEED_INVALID;
11517         tp->link_config.active_duplex = DUPLEX_INVALID;
11518         tp->link_config.phy_is_low_power = 0;
11519         tp->link_config.orig_speed = SPEED_INVALID;
11520         tp->link_config.orig_duplex = DUPLEX_INVALID;
11521         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11522 }
11523
11524 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11525 {
11526         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11527                 tp->bufmgr_config.mbuf_read_dma_low_water =
11528                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11529                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11530                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11531                 tp->bufmgr_config.mbuf_high_water =
11532                         DEFAULT_MB_HIGH_WATER_5705;
11533                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11534                         tp->bufmgr_config.mbuf_mac_rx_low_water =
11535                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
11536                         tp->bufmgr_config.mbuf_high_water =
11537                                 DEFAULT_MB_HIGH_WATER_5906;
11538                 }
11539
11540                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11541                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11542                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11543                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11544                 tp->bufmgr_config.mbuf_high_water_jumbo =
11545                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11546         } else {
11547                 tp->bufmgr_config.mbuf_read_dma_low_water =
11548                         DEFAULT_MB_RDMA_LOW_WATER;
11549                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11550                         DEFAULT_MB_MACRX_LOW_WATER;
11551                 tp->bufmgr_config.mbuf_high_water =
11552                         DEFAULT_MB_HIGH_WATER;
11553
11554                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11555                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11556                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11557                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11558                 tp->bufmgr_config.mbuf_high_water_jumbo =
11559                         DEFAULT_MB_HIGH_WATER_JUMBO;
11560         }
11561
11562         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11563         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11564 }
11565
11566 static char * __devinit tg3_phy_string(struct tg3 *tp)
11567 {
11568         switch (tp->phy_id & PHY_ID_MASK) {
11569         case PHY_ID_BCM5400:    return "5400";
11570         case PHY_ID_BCM5401:    return "5401";
11571         case PHY_ID_BCM5411:    return "5411";
11572         case PHY_ID_BCM5701:    return "5701";
11573         case PHY_ID_BCM5703:    return "5703";
11574         case PHY_ID_BCM5704:    return "5704";
11575         case PHY_ID_BCM5705:    return "5705";
11576         case PHY_ID_BCM5750:    return "5750";
11577         case PHY_ID_BCM5752:    return "5752";
11578         case PHY_ID_BCM5714:    return "5714";
11579         case PHY_ID_BCM5780:    return "5780";
11580         case PHY_ID_BCM5755:    return "5755";
11581         case PHY_ID_BCM5787:    return "5787";
11582         case PHY_ID_BCM5756:    return "5722/5756";
11583         case PHY_ID_BCM5906:    return "5906";
11584         case PHY_ID_BCM8002:    return "8002/serdes";
11585         case 0:                 return "serdes";
11586         default:                return "unknown";
11587         };
11588 }
11589
11590 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11591 {
11592         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11593                 strcpy(str, "PCI Express");
11594                 return str;
11595         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11596                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11597
11598                 strcpy(str, "PCIX:");
11599
11600                 if ((clock_ctrl == 7) ||
11601                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11602                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11603                         strcat(str, "133MHz");
11604                 else if (clock_ctrl == 0)
11605                         strcat(str, "33MHz");
11606                 else if (clock_ctrl == 2)
11607                         strcat(str, "50MHz");
11608                 else if (clock_ctrl == 4)
11609                         strcat(str, "66MHz");
11610                 else if (clock_ctrl == 6)
11611                         strcat(str, "100MHz");
11612         } else {
11613                 strcpy(str, "PCI:");
11614                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11615                         strcat(str, "66MHz");
11616                 else
11617                         strcat(str, "33MHz");
11618         }
11619         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11620                 strcat(str, ":32-bit");
11621         else
11622                 strcat(str, ":64-bit");
11623         return str;
11624 }
11625
11626 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11627 {
11628         struct pci_dev *peer;
11629         unsigned int func, devnr = tp->pdev->devfn & ~7;
11630
11631         for (func = 0; func < 8; func++) {
11632                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11633                 if (peer && peer != tp->pdev)
11634                         break;
11635                 pci_dev_put(peer);
11636         }
11637         /* 5704 can be configured in single-port mode, set peer to
11638          * tp->pdev in that case.
11639          */
11640         if (!peer) {
11641                 peer = tp->pdev;
11642                 return peer;
11643         }
11644
11645         /*
11646          * We don't need to keep the refcount elevated; there's no way
11647          * to remove one half of this device without removing the other
11648          */
11649         pci_dev_put(peer);
11650
11651         return peer;
11652 }
11653
11654 static void __devinit tg3_init_coal(struct tg3 *tp)
11655 {
11656         struct ethtool_coalesce *ec = &tp->coal;
11657
11658         memset(ec, 0, sizeof(*ec));
11659         ec->cmd = ETHTOOL_GCOALESCE;
11660         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11661         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11662         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11663         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11664         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11665         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11666         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11667         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11668         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11669
11670         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11671                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11672                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11673                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11674                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11675                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11676         }
11677
11678         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11679                 ec->rx_coalesce_usecs_irq = 0;
11680                 ec->tx_coalesce_usecs_irq = 0;
11681                 ec->stats_block_coalesce_usecs = 0;
11682         }
11683 }
11684
11685 static int __devinit tg3_init_one(struct pci_dev *pdev,
11686                                   const struct pci_device_id *ent)
11687 {
11688         static int tg3_version_printed = 0;
11689         unsigned long tg3reg_base, tg3reg_len;
11690         struct net_device *dev;
11691         struct tg3 *tp;
11692         int i, err, pm_cap;
11693         char str[40];
11694         u64 dma_mask, persist_dma_mask;
11695
11696         if (tg3_version_printed++ == 0)
11697                 printk(KERN_INFO "%s", version);
11698
11699         err = pci_enable_device(pdev);
11700         if (err) {
11701                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11702                        "aborting.\n");
11703                 return err;
11704         }
11705
11706         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11707                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11708                        "base address, aborting.\n");
11709                 err = -ENODEV;
11710                 goto err_out_disable_pdev;
11711         }
11712
11713         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11714         if (err) {
11715                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11716                        "aborting.\n");
11717                 goto err_out_disable_pdev;
11718         }
11719
11720         pci_set_master(pdev);
11721
11722         /* Find power-management capability. */
11723         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11724         if (pm_cap == 0) {
11725                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11726                        "aborting.\n");
11727                 err = -EIO;
11728                 goto err_out_free_res;
11729         }
11730
11731         tg3reg_base = pci_resource_start(pdev, 0);
11732         tg3reg_len = pci_resource_len(pdev, 0);
11733
11734         dev = alloc_etherdev(sizeof(*tp));
11735         if (!dev) {
11736                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11737                 err = -ENOMEM;
11738                 goto err_out_free_res;
11739         }
11740
11741         SET_MODULE_OWNER(dev);
11742         SET_NETDEV_DEV(dev, &pdev->dev);
11743
11744 #if TG3_VLAN_TAG_USED
11745         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11746         dev->vlan_rx_register = tg3_vlan_rx_register;
11747         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11748 #endif
11749
11750         tp = netdev_priv(dev);
11751         tp->pdev = pdev;
11752         tp->dev = dev;
11753         tp->pm_cap = pm_cap;
11754         tp->mac_mode = TG3_DEF_MAC_MODE;
11755         tp->rx_mode = TG3_DEF_RX_MODE;
11756         tp->tx_mode = TG3_DEF_TX_MODE;
11757         tp->mi_mode = MAC_MI_MODE_BASE;
11758         if (tg3_debug > 0)
11759                 tp->msg_enable = tg3_debug;
11760         else
11761                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11762
11763         /* The word/byte swap controls here control register access byte
11764          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11765          * setting below.
11766          */
11767         tp->misc_host_ctrl =
11768                 MISC_HOST_CTRL_MASK_PCI_INT |
11769                 MISC_HOST_CTRL_WORD_SWAP |
11770                 MISC_HOST_CTRL_INDIR_ACCESS |
11771                 MISC_HOST_CTRL_PCISTATE_RW;
11772
11773         /* The NONFRM (non-frame) byte/word swap controls take effect
11774          * on descriptor entries, anything which isn't packet data.
11775          *
11776          * The StrongARM chips on the board (one for tx, one for rx)
11777          * are running in big-endian mode.
11778          */
11779         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11780                         GRC_MODE_WSWAP_NONFRM_DATA);
11781 #ifdef __BIG_ENDIAN
11782         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11783 #endif
11784         spin_lock_init(&tp->lock);
11785         spin_lock_init(&tp->indirect_lock);
11786         INIT_WORK(&tp->reset_task, tg3_reset_task);
11787
11788         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11789         if (tp->regs == 0UL) {
11790                 printk(KERN_ERR PFX "Cannot map device registers, "
11791                        "aborting.\n");
11792                 err = -ENOMEM;
11793                 goto err_out_free_dev;
11794         }
11795
11796         tg3_init_link_config(tp);
11797
11798         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11799         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11800         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11801
11802         dev->open = tg3_open;
11803         dev->stop = tg3_close;
11804         dev->get_stats = tg3_get_stats;
11805         dev->set_multicast_list = tg3_set_rx_mode;
11806         dev->set_mac_address = tg3_set_mac_addr;
11807         dev->do_ioctl = tg3_ioctl;
11808         dev->tx_timeout = tg3_tx_timeout;
11809         dev->poll = tg3_poll;
11810         dev->ethtool_ops = &tg3_ethtool_ops;
11811         dev->weight = 64;
11812         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11813         dev->change_mtu = tg3_change_mtu;
11814         dev->irq = pdev->irq;
11815 #ifdef CONFIG_NET_POLL_CONTROLLER
11816         dev->poll_controller = tg3_poll_controller;
11817 #endif
11818
11819         err = tg3_get_invariants(tp);
11820         if (err) {
11821                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11822                        "aborting.\n");
11823                 goto err_out_iounmap;
11824         }
11825
11826         /* The EPB bridge inside 5714, 5715, and 5780 and any
11827          * device behind the EPB cannot support DMA addresses > 40-bit.
11828          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11829          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11830          * do DMA address check in tg3_start_xmit().
11831          */
11832         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11833                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11834         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11835                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11836 #ifdef CONFIG_HIGHMEM
11837                 dma_mask = DMA_64BIT_MASK;
11838 #endif
11839         } else
11840                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11841
11842         /* Configure DMA attributes. */
11843         if (dma_mask > DMA_32BIT_MASK) {
11844                 err = pci_set_dma_mask(pdev, dma_mask);
11845                 if (!err) {
11846                         dev->features |= NETIF_F_HIGHDMA;
11847                         err = pci_set_consistent_dma_mask(pdev,
11848                                                           persist_dma_mask);
11849                         if (err < 0) {
11850                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11851                                        "DMA for consistent allocations\n");
11852                                 goto err_out_iounmap;
11853                         }
11854                 }
11855         }
11856         if (err || dma_mask == DMA_32BIT_MASK) {
11857                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11858                 if (err) {
11859                         printk(KERN_ERR PFX "No usable DMA configuration, "
11860                                "aborting.\n");
11861                         goto err_out_iounmap;
11862                 }
11863         }
11864
11865         tg3_init_bufmgr_config(tp);
11866
11867         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11868                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11869         }
11870         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11871             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11872             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11873             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11874             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11875                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11876         } else {
11877                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11878         }
11879
11880         /* TSO is on by default on chips that support hardware TSO.
11881          * Firmware TSO on older chips gives lower performance, so it
11882          * is off by default, but can be enabled using ethtool.
11883          */
11884         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11885                 dev->features |= NETIF_F_TSO;
11886                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11887                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11888                         dev->features |= NETIF_F_TSO6;
11889         }
11890
11891
11892         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11893             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11894             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11895                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11896                 tp->rx_pending = 63;
11897         }
11898
11899         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11900             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11901                 tp->pdev_peer = tg3_find_peer(tp);
11902
11903         err = tg3_get_device_address(tp);
11904         if (err) {
11905                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11906                        "aborting.\n");
11907                 goto err_out_iounmap;
11908         }
11909
11910         /*
11911          * Reset chip in case UNDI or EFI driver did not shutdown
11912          * DMA self test will enable WDMAC and we'll see (spurious)
11913          * pending DMA on the PCI bus at that point.
11914          */
11915         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11916             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11917                 pci_save_state(tp->pdev);
11918                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11919                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11920         }
11921
11922         err = tg3_test_dma(tp);
11923         if (err) {
11924                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11925                 goto err_out_iounmap;
11926         }
11927
11928         /* Tigon3 can do ipv4 only... and some chips have buggy
11929          * checksumming.
11930          */
11931         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11932                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11933                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11934                         dev->features |= NETIF_F_HW_CSUM;
11935                 else
11936                         dev->features |= NETIF_F_IP_CSUM;
11937                 dev->features |= NETIF_F_SG;
11938                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11939         } else
11940                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11941
11942         /* flow control autonegotiation is default behavior */
11943         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11944
11945         tg3_init_coal(tp);
11946
11947         /* Now that we have fully setup the chip, save away a snapshot
11948          * of the PCI config space.  We need to restore this after
11949          * GRC_MISC_CFG core clock resets and some resume events.
11950          */
11951         pci_save_state(tp->pdev);
11952
11953         pci_set_drvdata(pdev, dev);
11954
11955         err = register_netdev(dev);
11956         if (err) {
11957                 printk(KERN_ERR PFX "Cannot register net device, "
11958                        "aborting.\n");
11959                 goto err_out_iounmap;
11960         }
11961
11962         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
11963                dev->name,
11964                tp->board_part_number,
11965                tp->pci_chip_rev_id,
11966                tg3_phy_string(tp),
11967                tg3_bus_string(tp, str),
11968                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11969                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11970                  "10/100/1000Base-T")));
11971
11972         for (i = 0; i < 6; i++)
11973                 printk("%2.2x%c", dev->dev_addr[i],
11974                        i == 5 ? '\n' : ':');
11975
11976         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11977                "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
11978                dev->name,
11979                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11980                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11981                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11982                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11983                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11984                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11985         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11986                dev->name, tp->dma_rwctrl,
11987                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11988                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11989
11990         return 0;
11991
11992 err_out_iounmap:
11993         if (tp->regs) {
11994                 iounmap(tp->regs);
11995                 tp->regs = NULL;
11996         }
11997
11998 err_out_free_dev:
11999         free_netdev(dev);
12000
12001 err_out_free_res:
12002         pci_release_regions(pdev);
12003
12004 err_out_disable_pdev:
12005         pci_disable_device(pdev);
12006         pci_set_drvdata(pdev, NULL);
12007         return err;
12008 }
12009
12010 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12011 {
12012         struct net_device *dev = pci_get_drvdata(pdev);
12013
12014         if (dev) {
12015                 struct tg3 *tp = netdev_priv(dev);
12016
12017                 flush_scheduled_work();
12018                 unregister_netdev(dev);
12019                 if (tp->regs) {
12020                         iounmap(tp->regs);
12021                         tp->regs = NULL;
12022                 }
12023                 free_netdev(dev);
12024                 pci_release_regions(pdev);
12025                 pci_disable_device(pdev);
12026                 pci_set_drvdata(pdev, NULL);
12027         }
12028 }
12029
12030 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12031 {
12032         struct net_device *dev = pci_get_drvdata(pdev);
12033         struct tg3 *tp = netdev_priv(dev);
12034         int err;
12035
12036         if (!netif_running(dev))
12037                 return 0;
12038
12039         flush_scheduled_work();
12040         tg3_netif_stop(tp);
12041
12042         del_timer_sync(&tp->timer);
12043
12044         tg3_full_lock(tp, 1);
12045         tg3_disable_ints(tp);
12046         tg3_full_unlock(tp);
12047
12048         netif_device_detach(dev);
12049
12050         tg3_full_lock(tp, 0);
12051         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12052         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12053         tg3_full_unlock(tp);
12054
12055         /* Save MSI address and data for resume.  */
12056         pci_save_state(pdev);
12057
12058         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12059         if (err) {
12060                 tg3_full_lock(tp, 0);
12061
12062                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12063                 if (tg3_restart_hw(tp, 1))
12064                         goto out;
12065
12066                 tp->timer.expires = jiffies + tp->timer_offset;
12067                 add_timer(&tp->timer);
12068
12069                 netif_device_attach(dev);
12070                 tg3_netif_start(tp);
12071
12072 out:
12073                 tg3_full_unlock(tp);
12074         }
12075
12076         return err;
12077 }
12078
12079 static int tg3_resume(struct pci_dev *pdev)
12080 {
12081         struct net_device *dev = pci_get_drvdata(pdev);
12082         struct tg3 *tp = netdev_priv(dev);
12083         int err;
12084
12085         if (!netif_running(dev))
12086                 return 0;
12087
12088         pci_restore_state(tp->pdev);
12089
12090         err = tg3_set_power_state(tp, PCI_D0);
12091         if (err)
12092                 return err;
12093
12094         netif_device_attach(dev);
12095
12096         tg3_full_lock(tp, 0);
12097
12098         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12099         err = tg3_restart_hw(tp, 1);
12100         if (err)
12101                 goto out;
12102
12103         tp->timer.expires = jiffies + tp->timer_offset;
12104         add_timer(&tp->timer);
12105
12106         tg3_netif_start(tp);
12107
12108 out:
12109         tg3_full_unlock(tp);
12110
12111         return err;
12112 }
12113
12114 static struct pci_driver tg3_driver = {
12115         .name           = DRV_MODULE_NAME,
12116         .id_table       = tg3_pci_tbl,
12117         .probe          = tg3_init_one,
12118         .remove         = __devexit_p(tg3_remove_one),
12119         .suspend        = tg3_suspend,
12120         .resume         = tg3_resume
12121 };
12122
12123 static int __init tg3_init(void)
12124 {
12125         return pci_register_driver(&tg3_driver);
12126 }
12127
12128 static void __exit tg3_cleanup(void)
12129 {
12130         pci_unregister_driver(&tg3_driver);
12131 }
12132
12133 module_init(tg3_init);
12134 module_exit(tg3_cleanup);