git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt61pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/eeprom_93cx6.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt61pci.h"
  39
  40 /*
  41  * Allow hardware encryption to be disabled.
  42  */
  43 static int modparam_nohwcrypt = 0;
  44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  46
  47 /*
  48  * Register access.
  49  * BBP and RF register require indirect register access,
  50  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  51  * These indirect registers work with busy bits,
  52  * and we will try maximal REGISTER_BUSY_COUNT times to access
  53  * the register while taking a REGISTER_BUSY_DELAY us delay
  54  * between each attampt. When the busy bit is still set at that time,
  55  * the access attempt is considered to have failed,
  56  * and we will print an error.
  57  */
  58 #define WAIT_FOR_BBP(__dev, __reg) \
  59         rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  60 #define WAIT_FOR_RF(__dev, __reg) \
  61         rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  62 #define WAIT_FOR_MCU(__dev, __reg) \
  63         rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  64                                H2M_MAILBOX_CSR_OWNER, (__reg))
  65
  66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  67                               const unsigned int word, const u8 value)
  68 {
  69         u32 reg;
  70
  71         mutex_lock(&rt2x00dev->csr_mutex);
  72
  73         /*
  74          * Wait until the BBP becomes available, afterwards we
  75          * can safely write the new data into the register.
  76          */
  77         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  78                 reg = 0;
  79                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  80                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  81                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  82                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  83
  84                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  85         }
  86
  87         mutex_unlock(&rt2x00dev->csr_mutex);
  88 }
  89
  90 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  91                              const unsigned int word, u8 *value)
  92 {
  93         u32 reg;
  94
  95         mutex_lock(&rt2x00dev->csr_mutex);
  96
  97         /*
  98          * Wait until the BBP becomes available, afterwards we
  99          * can safely write the read request into the register.
 100          * After the data has been written, we wait until hardware
 101          * returns the correct value, if at any time the register
 102          * doesn't become available in time, reg will be 0xffffffff
 103          * which means we return 0xff to the caller.
 104          */
 105         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 106                 reg = 0;
 107                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 108                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 109                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 110
 111                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 112
 113                 WAIT_FOR_BBP(rt2x00dev, &reg);
 114         }
 115
 116         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 117
 118         mutex_unlock(&rt2x00dev->csr_mutex);
 119 }
 120
 121 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 122                              const unsigned int word, const u32 value)
 123 {
 124         u32 reg;
 125
 126         if (!word)
 127                 return;
 128
 129         mutex_lock(&rt2x00dev->csr_mutex);
 130
 131         /*
 132          * Wait until the RF becomes available, afterwards we
 133          * can safely write the new data into the register.
 134          */
 135         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 136                 reg = 0;
 137                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 138                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 139                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 140                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 141
 142                 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 143                 rt2x00_rf_write(rt2x00dev, word, value);
 144         }
 145
 146         mutex_unlock(&rt2x00dev->csr_mutex);
 147 }
 148
 149 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 150                                 const u8 command, const u8 token,
 151                                 const u8 arg0, const u8 arg1)
 152 {
 153         u32 reg;
 154
 155         mutex_lock(&rt2x00dev->csr_mutex);
 156
 157         /*
 158          * Wait until the MCU becomes available, afterwards we
 159          * can safely write the new data into the register.
 160          */
 161         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 162                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 163                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 164                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 165                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 166                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 167
 168                 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 169                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 170                 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 171                 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 172         }
 173
 174         mutex_unlock(&rt2x00dev->csr_mutex);
 175
 176 }
 177
 178 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 179 {
 180         struct rt2x00_dev *rt2x00dev = eeprom->data;
 181         u32 reg;
 182
 183         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 184
 185         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 186         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 187         eeprom->reg_data_clock =
 188             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 189         eeprom->reg_chip_select =
 190             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 191 }
 192
 193 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 194 {
 195         struct rt2x00_dev *rt2x00dev = eeprom->data;
 196         u32 reg = 0;
 197
 198         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 199         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 200         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 201                            !!eeprom->reg_data_clock);
 202         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 203                            !!eeprom->reg_chip_select);
 204
 205         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 206 }
 207
 208 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 209 static const struct rt2x00debug rt61pci_rt2x00debug = {
 210         .owner  = THIS_MODULE,
 211         .csr    = {
 212                 .read           = rt2x00pci_register_read,
 213                 .write          = rt2x00pci_register_write,
 214                 .flags          = RT2X00DEBUGFS_OFFSET,
 215                 .word_base      = CSR_REG_BASE,
 216                 .word_size      = sizeof(u32),
 217                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 218         },
 219         .eeprom = {
 220                 .read           = rt2x00_eeprom_read,
 221                 .write          = rt2x00_eeprom_write,
 222                 .word_base      = EEPROM_BASE,
 223                 .word_size      = sizeof(u16),
 224                 .word_count     = EEPROM_SIZE / sizeof(u16),
 225         },
 226         .bbp    = {
 227                 .read           = rt61pci_bbp_read,
 228                 .write          = rt61pci_bbp_write,
 229                 .word_base      = BBP_BASE,
 230                 .word_size      = sizeof(u8),
 231                 .word_count     = BBP_SIZE / sizeof(u8),
 232         },
 233         .rf     = {
 234                 .read           = rt2x00_rf_read,
 235                 .write          = rt61pci_rf_write,
 236                 .word_base      = RF_BASE,
 237                 .word_size      = sizeof(u32),
 238                 .word_count     = RF_SIZE / sizeof(u32),
 239         },
 240 };
 241 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 242
 243 #ifdef CONFIG_RT2X00_LIB_RFKILL
 244 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 245 {
 246         u32 reg;
 247
 248         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 249         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 250 }
 251 #else
 252 #define rt61pci_rfkill_poll     NULL
 253 #endif /* CONFIG_RT2X00_LIB_RFKILL */
 254
 255 #ifdef CONFIG_RT2X00_LIB_LEDS
 256 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
 257                                    enum led_brightness brightness)
 258 {
 259         struct rt2x00_led *led =
 260             container_of(led_cdev, struct rt2x00_led, led_dev);
 261         unsigned int enabled = brightness != LED_OFF;
 262         unsigned int a_mode =
 263             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 264         unsigned int bg_mode =
 265             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 266
 267         if (led->type == LED_TYPE_RADIO) {
 268                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 269                                    MCU_LEDCS_RADIO_STATUS, enabled);
 270
 271                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 272                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 273                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 274         } else if (led->type == LED_TYPE_ASSOC) {
 275                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 276                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 277                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 278                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 279
 280                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 281                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 282                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 283         } else if (led->type == LED_TYPE_QUALITY) {
 284                 /*
 285                  * The brightness is divided into 6 levels (0 - 5),
 286                  * this means we need to convert the brightness
 287                  * argument into the matching level within that range.
 288                  */
 289                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 290                                     brightness / (LED_FULL / 6), 0);
 291         }
 292 }
 293
 294 static int rt61pci_blink_set(struct led_classdev *led_cdev,
 295                              unsigned long *delay_on,
 296                              unsigned long *delay_off)
 297 {
 298         struct rt2x00_led *led =
 299             container_of(led_cdev, struct rt2x00_led, led_dev);
 300         u32 reg;
 301
 302         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 303         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 304         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 305         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
 306
 307         return 0;
 308 }
 309
 310 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
 311                              struct rt2x00_led *led,
 312                              enum led_type type)
 313 {
 314         led->rt2x00dev = rt2x00dev;
 315         led->type = type;
 316         led->led_dev.brightness_set = rt61pci_brightness_set;
 317         led->led_dev.blink_set = rt61pci_blink_set;
 318         led->flags = LED_INITIALIZED;
 319 }
 320 #endif /* CONFIG_RT2X00_LIB_LEDS */
 321
 322 /*
 323  * Configuration handlers.
 324  */
 325 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 326                                      struct rt2x00lib_crypto *crypto,
 327                                      struct ieee80211_key_conf *key)
 328 {
 329         struct hw_key_entry key_entry;
 330         struct rt2x00_field32 field;
 331         u32 mask;
 332         u32 reg;
 333
 334         if (crypto->cmd == SET_KEY) {
 335                 /*
 336                  * rt2x00lib can't determine the correct free
 337                  * key_idx for shared keys. We have 1 register
 338                  * with key valid bits. The goal is simple, read
 339                  * the register, if that is full we have no slots
 340                  * left.
 341                  * Note that each BSS is allowed to have up to 4
 342                  * shared keys, so put a mask over the allowed
 343                  * entries.
 344                  */
 345                 mask = (0xf << crypto->bssidx);
 346
 347                 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 348                 reg &= mask;
 349
 350                 if (reg && reg == mask)
 351                         return -ENOSPC;
 352
 353                 key->hw_key_idx += reg ? ffz(reg) : 0;
 354
 355                 /*
 356                  * Upload key to hardware
 357                  */
 358                 memcpy(key_entry.key, crypto->key,
 359                        sizeof(key_entry.key));
 360                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 361                        sizeof(key_entry.tx_mic));
 362                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 363                        sizeof(key_entry.rx_mic));
 364
 365                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 366                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 367                                               &key_entry, sizeof(key_entry));
 368
 369                 /*
 370                  * The cipher types are stored over 2 registers.
 371                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 372                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 373                  * Using the correct defines correctly will cause overhead,
 374                  * so just calculate the correct offset.
 375                  */
 376                 if (key->hw_key_idx < 8) {
 377                         field.bit_offset = (3 * key->hw_key_idx);
 378                         field.bit_mask = 0x7 << field.bit_offset;
 379
 380                         rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
 381                         rt2x00_set_field32(&reg, field, crypto->cipher);
 382                         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
 383                 } else {
 384                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 385                         field.bit_mask = 0x7 << field.bit_offset;
 386
 387                         rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
 388                         rt2x00_set_field32(&reg, field, crypto->cipher);
 389                         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
 390                 }
 391
 392                 /*
 393                  * The driver does not support the IV/EIV generation
 394                  * in hardware. However it doesn't support the IV/EIV
 395                  * inside the ieee80211 frame either, but requires it
 396                  * to be provided seperately for the descriptor.
 397                  * rt2x00lib will cut the IV/EIV data out of all frames
 398                  * given to us by mac80211, but we must tell mac80211
 399                  * to generate the IV/EIV data.
 400                  */
 401                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 402         }
 403
 404         /*
 405          * SEC_CSR0 contains only single-bit fields to indicate
 406          * a particular key is valid. Because using the FIELD32()
 407          * defines directly will cause a lot of overhead we use
 408          * a calculation to determine the correct bit directly.
 409          */
 410         mask = 1 << key->hw_key_idx;
 411
 412         rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 413         if (crypto->cmd == SET_KEY)
 414                 reg |= mask;
 415         else if (crypto->cmd == DISABLE_KEY)
 416                 reg &= ~mask;
 417         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
 418
 419         return 0;
 420 }
 421
 422 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 423                                        struct rt2x00lib_crypto *crypto,
 424                                        struct ieee80211_key_conf *key)
 425 {
 426         struct hw_pairwise_ta_entry addr_entry;
 427         struct hw_key_entry key_entry;
 428         u32 mask;
 429         u32 reg;
 430
 431         if (crypto->cmd == SET_KEY) {
 432                 /*
 433                  * rt2x00lib can't determine the correct free
 434                  * key_idx for pairwise keys. We have 2 registers
 435                  * with key valid bits. The goal is simple, read
 436                  * the first register, if that is full move to
 437                  * the next register.
 438                  * When both registers are full, we drop the key,
 439                  * otherwise we use the first invalid entry.
 440                  */
 441                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 442                 if (reg && reg == ~0) {
 443                         key->hw_key_idx = 32;
 444                         rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 445                         if (reg && reg == ~0)
 446                                 return -ENOSPC;
 447                 }
 448
 449                 key->hw_key_idx += reg ? ffz(reg) : 0;
 450
 451                 /*
 452                  * Upload key to hardware
 453                  */
 454                 memcpy(key_entry.key, crypto->key,
 455                        sizeof(key_entry.key));
 456                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 457                        sizeof(key_entry.tx_mic));
 458                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 459                        sizeof(key_entry.rx_mic));
 460
 461                 memset(&addr_entry, 0, sizeof(addr_entry));
 462                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 463                 addr_entry.cipher = crypto->cipher;
 464
 465                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 466                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 467                                               &key_entry, sizeof(key_entry));
 468
 469                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 470                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 471                                               &addr_entry, sizeof(addr_entry));
 472
 473                 /*
 474                  * Enable pairwise lookup table for given BSS idx,
 475                  * without this received frames will not be decrypted
 476                  * by the hardware.
 477                  */
 478                 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
 479                 reg |= (1 << crypto->bssidx);
 480                 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
 481
 482                 /*
 483                  * The driver does not support the IV/EIV generation
 484                  * in hardware. However it doesn't support the IV/EIV
 485                  * inside the ieee80211 frame either, but requires it
 486                  * to be provided seperately for the descriptor.
 487                  * rt2x00lib will cut the IV/EIV data out of all frames
 488                  * given to us by mac80211, but we must tell mac80211
 489                  * to generate the IV/EIV data.
 490                  */
 491                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 492         }
 493
 494         /*
 495          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 496          * a particular key is valid. Because using the FIELD32()
 497          * defines directly will cause a lot of overhead we use
 498          * a calculation to determine the correct bit directly.
 499          */
 500         if (key->hw_key_idx < 32) {
 501                 mask = 1 << key->hw_key_idx;
 502
 503                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 504                 if (crypto->cmd == SET_KEY)
 505                         reg |= mask;
 506                 else if (crypto->cmd == DISABLE_KEY)
 507                         reg &= ~mask;
 508                 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
 509         } else {
 510                 mask = 1 << (key->hw_key_idx - 32);
 511
 512                 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 513                 if (crypto->cmd == SET_KEY)
 514                         reg |= mask;
 515                 else if (crypto->cmd == DISABLE_KEY)
 516                         reg &= ~mask;
 517                 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
 518         }
 519
 520         return 0;
 521 }
 522
 523 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 524                                   const unsigned int filter_flags)
 525 {
 526         u32 reg;
 527
 528         /*
 529          * Start configuration steps.
 530          * Note that the version error will always be dropped
 531          * and broadcast frames will always be accepted since
 532          * there is no filter for it at this time.
 533          */
 534         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 535         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 536                            !(filter_flags & FIF_FCSFAIL));
 537         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 538                            !(filter_flags & FIF_PLCPFAIL));
 539         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 540                            !(filter_flags & FIF_CONTROL));
 541         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 542                            !(filter_flags & FIF_PROMISC_IN_BSS));
 543         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 544                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 545                            !rt2x00dev->intf_ap_count);
 546         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 547         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 548                            !(filter_flags & FIF_ALLMULTI));
 549         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 550         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 551                            !(filter_flags & FIF_CONTROL));
 552         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 553 }
 554
 555 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 556                                 struct rt2x00_intf *intf,
 557                                 struct rt2x00intf_conf *conf,
 558                                 const unsigned int flags)
 559 {
 560         unsigned int beacon_base;
 561         u32 reg;
 562
 563         if (flags & CONFIG_UPDATE_TYPE) {
 564                 /*
 565                  * Clear current synchronisation setup.
 566                  * For the Beacon base registers we only need to clear
 567                  * the first byte since that byte contains the VALID and OWNER
 568                  * bits which (when set to 0) will invalidate the entire beacon.
 569                  */
 570                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 571                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 572
 573                 /*
 574                  * Enable synchronisation.
 575                  */
 576                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 577                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 578                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 579                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 580                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 581         }
 582
 583         if (flags & CONFIG_UPDATE_MAC) {
 584                 reg = le32_to_cpu(conf->mac[1]);
 585                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 586                 conf->mac[1] = cpu_to_le32(reg);
 587
 588                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 589                                               conf->mac, sizeof(conf->mac));
 590         }
 591
 592         if (flags & CONFIG_UPDATE_BSSID) {
 593                 reg = le32_to_cpu(conf->bssid[1]);
 594                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 595                 conf->bssid[1] = cpu_to_le32(reg);
 596
 597                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 598                                               conf->bssid, sizeof(conf->bssid));
 599         }
 600 }
 601
 602 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 603                                struct rt2x00lib_erp *erp)
 604 {
 605         u32 reg;
 606
 607         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 608         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 609         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 610
 611         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 612         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 613                            !!erp->short_preamble);
 614         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 615
 616         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
 617
 618         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 619         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 620         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 621
 622         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 623         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 624         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 625         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 626         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 627 }
 628
 629 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 630                                       struct antenna_setup *ant)
 631 {
 632         u8 r3;
 633         u8 r4;
 634         u8 r77;
 635
 636         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 637         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 638         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 639
 640         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 641                           rt2x00_rf(&rt2x00dev->chip, RF5325));
 642
 643         /*
 644          * Configure the RX antenna.
 645          */
 646         switch (ant->rx) {
 647         case ANTENNA_HW_DIVERSITY:
 648                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 649                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 650                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 651                 break;
 652         case ANTENNA_A:
 653                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 654                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 655                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 656                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 657                 else
 658                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 659                 break;
 660         case ANTENNA_B:
 661         default:
 662                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 663                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 664                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 665                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 666                 else
 667                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 668                 break;
 669         }
 670
 671         rt61pci_bbp_write(rt2x00dev, 77, r77);
 672         rt61pci_bbp_write(rt2x00dev, 3, r3);
 673         rt61pci_bbp_write(rt2x00dev, 4, r4);
 674 }
 675
 676 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 677                                       struct antenna_setup *ant)
 678 {
 679         u8 r3;
 680         u8 r4;
 681         u8 r77;
 682
 683         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 684         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 685         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 686
 687         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 688                           rt2x00_rf(&rt2x00dev->chip, RF2529));
 689         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 690                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 691
 692         /*
 693          * Configure the RX antenna.
 694          */
 695         switch (ant->rx) {
 696         case ANTENNA_HW_DIVERSITY:
 697                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 698                 break;
 699         case ANTENNA_A:
 700                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 701                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 702                 break;
 703         case ANTENNA_B:
 704         default:
 705                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 706                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 707                 break;
 708         }
 709
 710         rt61pci_bbp_write(rt2x00dev, 77, r77);
 711         rt61pci_bbp_write(rt2x00dev, 3, r3);
 712         rt61pci_bbp_write(rt2x00dev, 4, r4);
 713 }
 714
 715 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 716                                            const int p1, const int p2)
 717 {
 718         u32 reg;
 719
 720         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 721
 722         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 723         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 724
 725         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 726         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 727
 728         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 729 }
 730
 731 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 732                                         struct antenna_setup *ant)
 733 {
 734         u8 r3;
 735         u8 r4;
 736         u8 r77;
 737
 738         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 739         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 740         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 741
 742         /*
 743          * Configure the RX antenna.
 744          */
 745         switch (ant->rx) {
 746         case ANTENNA_A:
 747                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 748                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 749                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 750                 break;
 751         case ANTENNA_HW_DIVERSITY:
 752                 /*
 753                  * FIXME: Antenna selection for the rf 2529 is very confusing
 754                  * in the legacy driver. Just default to antenna B until the
 755                  * legacy code can be properly translated into rt2x00 code.
 756                  */
 757         case ANTENNA_B:
 758         default:
 759                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 760                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 761                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 762                 break;
 763         }
 764
 765         rt61pci_bbp_write(rt2x00dev, 77, r77);
 766         rt61pci_bbp_write(rt2x00dev, 3, r3);
 767         rt61pci_bbp_write(rt2x00dev, 4, r4);
 768 }
 769
 770 struct antenna_sel {
 771         u8 word;
 772         /*
 773          * value[0] -> non-LNA
 774          * value[1] -> LNA
 775          */
 776         u8 value[2];
 777 };
 778
 779 static const struct antenna_sel antenna_sel_a[] = {
 780         { 96,  { 0x58, 0x78 } },
 781         { 104, { 0x38, 0x48 } },
 782         { 75,  { 0xfe, 0x80 } },
 783         { 86,  { 0xfe, 0x80 } },
 784         { 88,  { 0xfe, 0x80 } },
 785         { 35,  { 0x60, 0x60 } },
 786         { 97,  { 0x58, 0x58 } },
 787         { 98,  { 0x58, 0x58 } },
 788 };
 789
 790 static const struct antenna_sel antenna_sel_bg[] = {
 791         { 96,  { 0x48, 0x68 } },
 792         { 104, { 0x2c, 0x3c } },
 793         { 75,  { 0xfe, 0x80 } },
 794         { 86,  { 0xfe, 0x80 } },
 795         { 88,  { 0xfe, 0x80 } },
 796         { 35,  { 0x50, 0x50 } },
 797         { 97,  { 0x48, 0x48 } },
 798         { 98,  { 0x48, 0x48 } },
 799 };
 800
 801 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
 802                                struct antenna_setup *ant)
 803 {
 804         const struct antenna_sel *sel;
 805         unsigned int lna;
 806         unsigned int i;
 807         u32 reg;
 808
 809         /*
 810          * We should never come here because rt2x00lib is supposed
 811          * to catch this and send us the correct antenna explicitely.
 812          */
 813         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 814                ant->tx == ANTENNA_SW_DIVERSITY);
 815
 816         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 817                 sel = antenna_sel_a;
 818                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 819         } else {
 820                 sel = antenna_sel_bg;
 821                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 822         }
 823
 824         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 825                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 826
 827         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 828
 829         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 830                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 831         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 832                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 833
 834         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 835
 836         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 837             rt2x00_rf(&rt2x00dev->chip, RF5325))
 838                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 839         else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
 840                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 841         else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
 842                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
 843                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 844                 else
 845                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 846         }
 847 }
 848
 849 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 850                                     struct rt2x00lib_conf *libconf)
 851 {
 852         u16 eeprom;
 853         short lna_gain = 0;
 854
 855         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
 856                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
 857                         lna_gain += 14;
 858
 859                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 860                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 861         } else {
 862                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 863                         lna_gain += 14;
 864
 865                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 866                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 867         }
 868
 869         rt2x00dev->lna_gain = lna_gain;
 870 }
 871
 872 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 873                                    struct rf_channel *rf, const int txpower)
 874 {
 875         u8 r3;
 876         u8 r94;
 877         u8 smart;
 878
 879         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 880         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 881
 882         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 883                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 884
 885         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 886         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 887         rt61pci_bbp_write(rt2x00dev, 3, r3);
 888
 889         r94 = 6;
 890         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 891                 r94 += txpower - MAX_TXPOWER;
 892         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 893                 r94 += txpower;
 894         rt61pci_bbp_write(rt2x00dev, 94, r94);
 895
 896         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 897         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 898         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 899         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 900
 901         udelay(200);
 902
 903         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 904         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 905         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 906         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 907
 908         udelay(200);
 909
 910         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 911         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 912         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 913         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 914
 915         msleep(1);
 916 }
 917
 918 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 919                                    const int txpower)
 920 {
 921         struct rf_channel rf;
 922
 923         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 924         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 925         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 926         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 927
 928         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 929 }
 930
 931 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 932                                     struct rt2x00lib_conf *libconf)
 933 {
 934         u32 reg;
 935
 936         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 937         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 938                            libconf->conf->long_frame_max_tx_count);
 939         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 940                            libconf->conf->short_frame_max_tx_count);
 941         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 942 }
 943
 944 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
 945                                     struct rt2x00lib_conf *libconf)
 946 {
 947         u32 reg;
 948
 949         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 950         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 951         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 952
 953         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 954         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 955         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 956
 957         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 958         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 959                            libconf->conf->beacon_int * 16);
 960         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 961 }
 962
 963 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
 964                                 struct rt2x00lib_conf *libconf)
 965 {
 966         enum dev_state state =
 967             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 968                 STATE_SLEEP : STATE_AWAKE;
 969         u32 reg;
 970
 971         if (state == STATE_SLEEP) {
 972                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
 973                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
 974                                    libconf->conf->beacon_int - 10);
 975                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
 976                                    libconf->conf->listen_interval - 1);
 977                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
 978
 979                 /* We must first disable autowake before it can be enabled */
 980                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 981                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 982
 983                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
 984                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 985
 986                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
 987                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
 988                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
 989
 990                 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
 991         } else {
 992                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
 993                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
 994                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
 995                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 996                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
 997                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 998
 999                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
1000                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
1001                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
1002
1003                 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1004         }
1005 }
1006
1007 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
1008                            struct rt2x00lib_conf *libconf,
1009                            const unsigned int flags)
1010 {
1011         /* Always recalculate LNA gain before changing configuration */
1012         rt61pci_config_lna_gain(rt2x00dev, libconf);
1013
1014         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1015                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
1016                                        libconf->conf->power_level);
1017         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
1018             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
1019                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1020         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1021                 rt61pci_config_retry_limit(rt2x00dev, libconf);
1022         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1023                 rt61pci_config_duration(rt2x00dev, libconf);
1024         if (flags & IEEE80211_CONF_CHANGE_PS)
1025                 rt61pci_config_ps(rt2x00dev, libconf);
1026 }
1027
1028 /*
1029  * Link tuning
1030  */
1031 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1032                                struct link_qual *qual)
1033 {
1034         u32 reg;
1035
1036         /*
1037          * Update FCS error count from register.
1038          */
1039         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1040         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1041
1042         /*
1043          * Update False CCA count from register.
1044          */
1045         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1046         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1047 }
1048
1049 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1050                                    struct link_qual *qual, u8 vgc_level)
1051 {
1052         if (qual->vgc_level != vgc_level) {
1053                 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1054                 qual->vgc_level = vgc_level;
1055                 qual->vgc_level_reg = vgc_level;
1056         }
1057 }
1058
1059 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1060                                 struct link_qual *qual)
1061 {
1062         rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1063 }
1064
1065 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1066                                struct link_qual *qual, const u32 count)
1067 {
1068         u8 up_bound;
1069         u8 low_bound;
1070
1071         /*
1072          * Determine r17 bounds.
1073          */
1074         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1075                 low_bound = 0x28;
1076                 up_bound = 0x48;
1077                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1078                         low_bound += 0x10;
1079                         up_bound += 0x10;
1080                 }
1081         } else {
1082                 low_bound = 0x20;
1083                 up_bound = 0x40;
1084                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1085                         low_bound += 0x10;
1086                         up_bound += 0x10;
1087                 }
1088         }
1089
1090         /*
1091          * If we are not associated, we should go straight to the
1092          * dynamic CCA tuning.
1093          */
1094         if (!rt2x00dev->intf_associated)
1095                 goto dynamic_cca_tune;
1096
1097         /*
1098          * Special big-R17 for very short distance
1099          */
1100         if (qual->rssi >= -35) {
1101                 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1102                 return;
1103         }
1104
1105         /*
1106          * Special big-R17 for short distance
1107          */
1108         if (qual->rssi >= -58) {
1109                 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1110                 return;
1111         }
1112
1113         /*
1114          * Special big-R17 for middle-short distance
1115          */
1116         if (qual->rssi >= -66) {
1117                 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1118                 return;
1119         }
1120
1121         /*
1122          * Special mid-R17 for middle distance
1123          */
1124         if (qual->rssi >= -74) {
1125                 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1126                 return;
1127         }
1128
1129         /*
1130          * Special case: Change up_bound based on the rssi.
1131          * Lower up_bound when rssi is weaker then -74 dBm.
1132          */
1133         up_bound -= 2 * (-74 - qual->rssi);
1134         if (low_bound > up_bound)
1135                 up_bound = low_bound;
1136
1137         if (qual->vgc_level > up_bound) {
1138                 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1139                 return;
1140         }
1141
1142 dynamic_cca_tune:
1143
1144         /*
1145          * r17 does not yet exceed upper limit, continue and base
1146          * the r17 tuning on the false CCA count.
1147          */
1148         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1149                 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1150         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1151                 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1152 }
1153
1154 /*
1155  * Firmware functions
1156  */
1157 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1158 {
1159         char *fw_name;
1160
1161         switch (rt2x00dev->chip.rt) {
1162         case RT2561:
1163                 fw_name = FIRMWARE_RT2561;
1164                 break;
1165         case RT2561s:
1166                 fw_name = FIRMWARE_RT2561s;
1167                 break;
1168         case RT2661:
1169                 fw_name = FIRMWARE_RT2661;
1170                 break;
1171         default:
1172                 fw_name = NULL;
1173                 break;
1174         }
1175
1176         return fw_name;
1177 }
1178
1179 static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
1180 {
1181         u16 crc;
1182
1183         /*
1184          * Use the crc itu-t algorithm.
1185          * The last 2 bytes in the firmware array are the crc checksum itself,
1186          * this means that we should never pass those 2 bytes to the crc
1187          * algorithm.
1188          */
1189         crc = crc_itu_t(0, data, len - 2);
1190         crc = crc_itu_t_byte(crc, 0);
1191         crc = crc_itu_t_byte(crc, 0);
1192
1193         return crc;
1194 }
1195
1196 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1197                                  const size_t len)
1198 {
1199         int i;
1200         u32 reg;
1201
1202         if (len != 8192) {
1203                 ERROR(rt2x00dev, "Invalid firmware file length (len=%zu)\n", len);
1204                 return -ENOENT;
1205         }
1206
1207         /*
1208          * Wait for stable hardware.
1209          */
1210         for (i = 0; i < 100; i++) {
1211                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1212                 if (reg)
1213                         break;
1214                 msleep(1);
1215         }
1216
1217         if (!reg) {
1218                 ERROR(rt2x00dev, "Unstable hardware.\n");
1219                 return -EBUSY;
1220         }
1221
1222         /*
1223          * Prepare MCU and mailbox for firmware loading.
1224          */
1225         reg = 0;
1226         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1227         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1228         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1229         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1230         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1231
1232         /*
1233          * Write firmware to device.
1234          */
1235         reg = 0;
1236         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1237         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1238         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1239
1240         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1241                                       data, len);
1242
1243         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1244         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1245
1246         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1247         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1248
1249         for (i = 0; i < 100; i++) {
1250                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1251                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1252                         break;
1253                 msleep(1);
1254         }
1255
1256         if (i == 100) {
1257                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1258                 return -EBUSY;
1259         }
1260
1261         /*
1262          * Hardware needs another millisecond before it is ready.
1263          */
1264         msleep(1);
1265
1266         /*
1267          * Reset MAC and BBP registers.
1268          */
1269         reg = 0;
1270         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1271         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1272         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1273
1274         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1275         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1276         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1277         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1278
1279         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1280         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1281         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1282
1283         return 0;
1284 }
1285
1286 /*
1287  * Initialization functions.
1288  */
1289 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1290 {
1291         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1292         u32 word;
1293
1294         if (entry->queue->qid == QID_RX) {
1295                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1296
1297                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1298         } else {
1299                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1300
1301                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1302                         rt2x00_get_field32(word, TXD_W0_VALID));
1303         }
1304 }
1305
1306 static void rt61pci_clear_entry(struct queue_entry *entry)
1307 {
1308         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1309         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1310         u32 word;
1311
1312         if (entry->queue->qid == QID_RX) {
1313                 rt2x00_desc_read(entry_priv->desc, 5, &word);
1314                 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1315                                    skbdesc->skb_dma);
1316                 rt2x00_desc_write(entry_priv->desc, 5, word);
1317
1318                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1319                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1320                 rt2x00_desc_write(entry_priv->desc, 0, word);
1321         } else {
1322                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1323                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1324                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1325                 rt2x00_desc_write(entry_priv->desc, 0, word);
1326         }
1327 }
1328
1329 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1330 {
1331         struct queue_entry_priv_pci *entry_priv;
1332         u32 reg;
1333
1334         /*
1335          * Initialize registers.
1336          */
1337         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1338         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1339                            rt2x00dev->tx[0].limit);
1340         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1341                            rt2x00dev->tx[1].limit);
1342         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1343                            rt2x00dev->tx[2].limit);
1344         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1345                            rt2x00dev->tx[3].limit);
1346         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1347
1348         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1349         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1350                            rt2x00dev->tx[0].desc_size / 4);
1351         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1352
1353         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1354         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1355         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1356                            entry_priv->desc_dma);
1357         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1358
1359         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1360         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1361         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1362                            entry_priv->desc_dma);
1363         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1364
1365         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1366         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1367         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1368                            entry_priv->desc_dma);
1369         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1370
1371         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1372         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1373         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1374                            entry_priv->desc_dma);
1375         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1376
1377         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1378         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1379         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1380                            rt2x00dev->rx->desc_size / 4);
1381         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1382         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1383
1384         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1385         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1386         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1387                            entry_priv->desc_dma);
1388         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1389
1390         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1391         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1392         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1393         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1394         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1395         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1396
1397         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1398         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1399         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1400         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1401         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1402         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1403
1404         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1405         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1406         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1407
1408         return 0;
1409 }
1410
1411 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1412 {
1413         u32 reg;
1414
1415         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1416         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1417         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1418         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1419         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1420
1421         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1422         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1423         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1424         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1425         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1426         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1427         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1428         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1429         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1430         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1431
1432         /*
1433          * CCK TXD BBP registers
1434          */
1435         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1436         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1437         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1438         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1439         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1440         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1441         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1442         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1443         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1444         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1445
1446         /*
1447          * OFDM TXD BBP registers
1448          */
1449         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1450         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1451         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1452         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1453         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1454         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1455         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1456         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1457
1458         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1459         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1460         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1461         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1462         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1463         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1464
1465         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1466         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1467         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1468         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1469         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1470         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1471
1472         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1473         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1474         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1475         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1476         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1477         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1478         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1479         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1480
1481         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1482
1483         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1484
1485         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1486         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1487         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1488
1489         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1490
1491         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1492                 return -EBUSY;
1493
1494         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1495
1496         /*
1497          * Invalidate all Shared Keys (SEC_CSR0),
1498          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1499          */
1500         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1501         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1502         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1503
1504         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1505         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1506         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1507         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1508
1509         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1510
1511         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1512
1513         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1514
1515         /*
1516          * Clear all beacons
1517          * For the Beacon base registers we only need to clear
1518          * the first byte since that byte contains the VALID and OWNER
1519          * bits which (when set to 0) will invalidate the entire beacon.
1520          */
1521         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1522         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1523         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1524         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1525
1526         /*
1527          * We must clear the error counters.
1528          * These registers are cleared on read,
1529          * so we may pass a useless variable to store the value.
1530          */
1531         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1532         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1533         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1534
1535         /*
1536          * Reset MAC and BBP registers.
1537          */
1538         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1539         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1540         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1541         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1542
1543         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1544         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1545         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1546         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1547
1548         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1549         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1550         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1551
1552         return 0;
1553 }
1554
1555 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1556 {
1557         unsigned int i;
1558         u8 value;
1559
1560         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1561                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1562                 if ((value != 0xff) && (value != 0x00))
1563                         return 0;
1564                 udelay(REGISTER_BUSY_DELAY);
1565         }
1566
1567         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1568         return -EACCES;
1569 }
1570
1571 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1572 {
1573         unsigned int i;
1574         u16 eeprom;
1575         u8 reg_id;
1576         u8 value;
1577
1578         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1579                 return -EACCES;
1580
1581         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1582         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1583         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1584         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1585         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1586         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1587         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1588         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1589         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1590         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1591         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1592         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1593         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1594         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1595         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1596         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1597         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1598         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1599         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1600         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1601         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1602         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1603         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1604         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1605
1606         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1607                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1608
1609                 if (eeprom != 0xffff && eeprom != 0x0000) {
1610                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1611                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1612                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1613                 }
1614         }
1615
1616         return 0;
1617 }
1618
1619 /*
1620  * Device state switch handlers.
1621  */
1622 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1623                               enum dev_state state)
1624 {
1625         u32 reg;
1626
1627         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1628         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1629                            (state == STATE_RADIO_RX_OFF) ||
1630                            (state == STATE_RADIO_RX_OFF_LINK));
1631         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1632 }
1633
1634 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1635                                enum dev_state state)
1636 {
1637         int mask = (state == STATE_RADIO_IRQ_OFF);
1638         u32 reg;
1639
1640         /*
1641          * When interrupts are being enabled, the interrupt registers
1642          * should clear the register to assure a clean state.
1643          */
1644         if (state == STATE_RADIO_IRQ_ON) {
1645                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1646                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1647
1648                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1649                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1650         }
1651
1652         /*
1653          * Only toggle the interrupts bits we are going to use.
1654          * Non-checked interrupt bits are disabled by default.
1655          */
1656         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1657         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1658         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1659         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1660         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1661         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1662
1663         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1664         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1665         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1666         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1667         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1668         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1669         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1670         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1671         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1672         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1673 }
1674
1675 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1676 {
1677         u32 reg;
1678
1679         /*
1680          * Initialize all registers.
1681          */
1682         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1683                      rt61pci_init_registers(rt2x00dev) ||
1684                      rt61pci_init_bbp(rt2x00dev)))
1685                 return -EIO;
1686
1687         /*
1688          * Enable RX.
1689          */
1690         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1691         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1692         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1693
1694         return 0;
1695 }
1696
1697 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1698 {
1699         /*
1700          * Disable power
1701          */
1702         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1703 }
1704
1705 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1706 {
1707         u32 reg;
1708         unsigned int i;
1709         char put_to_sleep;
1710
1711         put_to_sleep = (state != STATE_AWAKE);
1712
1713         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1714         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1715         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1716         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1717
1718         /*
1719          * Device is not guaranteed to be in the requested state yet.
1720          * We must wait until the register indicates that the
1721          * device has entered the correct state.
1722          */
1723         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1724                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1725                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1726                 if (state == !put_to_sleep)
1727                         return 0;
1728                 msleep(10);
1729         }
1730
1731         return -EBUSY;
1732 }
1733
1734 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1735                                     enum dev_state state)
1736 {
1737         int retval = 0;
1738
1739         switch (state) {
1740         case STATE_RADIO_ON:
1741                 retval = rt61pci_enable_radio(rt2x00dev);
1742                 break;
1743         case STATE_RADIO_OFF:
1744                 rt61pci_disable_radio(rt2x00dev);
1745                 break;
1746         case STATE_RADIO_RX_ON:
1747         case STATE_RADIO_RX_ON_LINK:
1748         case STATE_RADIO_RX_OFF:
1749         case STATE_RADIO_RX_OFF_LINK:
1750                 rt61pci_toggle_rx(rt2x00dev, state);
1751                 break;
1752         case STATE_RADIO_IRQ_ON:
1753         case STATE_RADIO_IRQ_OFF:
1754                 rt61pci_toggle_irq(rt2x00dev, state);
1755                 break;
1756         case STATE_DEEP_SLEEP:
1757         case STATE_SLEEP:
1758         case STATE_STANDBY:
1759         case STATE_AWAKE:
1760                 retval = rt61pci_set_state(rt2x00dev, state);
1761                 break;
1762         default:
1763                 retval = -ENOTSUPP;
1764                 break;
1765         }
1766
1767         if (unlikely(retval))
1768                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1769                       state, retval);
1770
1771         return retval;
1772 }
1773
1774 /*
1775  * TX descriptor initialization
1776  */
1777 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1778                                   struct sk_buff *skb,
1779                                   struct txentry_desc *txdesc)
1780 {
1781         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1782         __le32 *txd = skbdesc->desc;
1783         u32 word;
1784
1785         /*
1786          * Start writing the descriptor words.
1787          */
1788         rt2x00_desc_read(txd, 1, &word);
1789         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1790         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1791         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1792         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1793         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1794         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1795                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1796         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1797         rt2x00_desc_write(txd, 1, word);
1798
1799         rt2x00_desc_read(txd, 2, &word);
1800         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1801         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1802         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1803         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1804         rt2x00_desc_write(txd, 2, word);
1805
1806         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1807                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1808                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1809         }
1810
1811         rt2x00_desc_read(txd, 5, &word);
1812         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1813         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1814                            skbdesc->entry->entry_idx);
1815         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1816                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1817         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1818         rt2x00_desc_write(txd, 5, word);
1819
1820         rt2x00_desc_read(txd, 6, &word);
1821         rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1822                            skbdesc->skb_dma);
1823         rt2x00_desc_write(txd, 6, word);
1824
1825         if (skbdesc->desc_len > TXINFO_SIZE) {
1826                 rt2x00_desc_read(txd, 11, &word);
1827                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1828                 rt2x00_desc_write(txd, 11, word);
1829         }
1830
1831         rt2x00_desc_read(txd, 0, &word);
1832         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1833         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1834         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1835                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1836         rt2x00_set_field32(&word, TXD_W0_ACK,
1837                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1838         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1839                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1840         rt2x00_set_field32(&word, TXD_W0_OFDM,
1841                            (txdesc->rate_mode == RATE_MODE_OFDM));
1842         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1843         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1844                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1845         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1846                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1847         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1848                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1849         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1850         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1851         rt2x00_set_field32(&word, TXD_W0_BURST,
1852                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1853         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1854         rt2x00_desc_write(txd, 0, word);
1855 }
1856
1857 /*
1858  * TX data initialization
1859  */
1860 static void rt61pci_write_beacon(struct queue_entry *entry)
1861 {
1862         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1863         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1864         unsigned int beacon_base;
1865         u32 reg;
1866
1867         /*
1868          * Disable beaconing while we are reloading the beacon data,
1869          * otherwise we might be sending out invalid data.
1870          */
1871         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1872         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1873         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1874         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1875         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1876
1877         /*
1878          * Write entire beacon with descriptor to register.
1879          */
1880         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1881         rt2x00pci_register_multiwrite(rt2x00dev,
1882                                       beacon_base,
1883                                       skbdesc->desc, skbdesc->desc_len);
1884         rt2x00pci_register_multiwrite(rt2x00dev,
1885                                       beacon_base + skbdesc->desc_len,
1886                                       entry->skb->data, entry->skb->len);
1887
1888         /*
1889          * Clean up beacon skb.
1890          */
1891         dev_kfree_skb_any(entry->skb);
1892         entry->skb = NULL;
1893 }
1894
1895 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1896                                   const enum data_queue_qid queue)
1897 {
1898         u32 reg;
1899
1900         if (queue == QID_BEACON) {
1901                 /*
1902                  * For Wi-Fi faily generated beacons between participating
1903                  * stations. Set TBTT phase adaptive adjustment step to 8us.
1904                  */
1905                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1906
1907                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1908                 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1909                         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1910                         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1911                         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1912                         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1913                 }
1914                 return;
1915         }
1916
1917         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1918         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1919         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1920         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1921         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1922         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1923 }
1924
1925 static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1926                                   const enum data_queue_qid qid)
1927 {
1928         u32 reg;
1929
1930         if (qid == QID_BEACON) {
1931                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1932                 return;
1933         }
1934
1935         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1936         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE));
1937         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK));
1938         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI));
1939         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO));
1940         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1941 }
1942
1943 /*
1944  * RX control handlers
1945  */
1946 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1947 {
1948         u8 offset = rt2x00dev->lna_gain;
1949         u8 lna;
1950
1951         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1952         switch (lna) {
1953         case 3:
1954                 offset += 90;
1955                 break;
1956         case 2:
1957                 offset += 74;
1958                 break;
1959         case 1:
1960                 offset += 64;
1961                 break;
1962         default:
1963                 return 0;
1964         }
1965
1966         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1967                 if (lna == 3 || lna == 2)
1968                         offset += 10;
1969         }
1970
1971         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1972 }
1973
1974 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1975                                 struct rxdone_entry_desc *rxdesc)
1976 {
1977         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1978         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1979         u32 word0;
1980         u32 word1;
1981
1982         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1983         rt2x00_desc_read(entry_priv->desc, 1, &word1);
1984
1985         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1986                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1987
1988         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1989                 rxdesc->cipher =
1990                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1991                 rxdesc->cipher_status =
1992                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1993         }
1994
1995         if (rxdesc->cipher != CIPHER_NONE) {
1996                 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
1997                 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
1998                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1999
2000                 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
2001                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
2002
2003                 /*
2004                  * Hardware has stripped IV/EIV data from 802.11 frame during
2005                  * decryption. It has provided the data seperately but rt2x00lib
2006                  * should decide if it should be reinserted.
2007                  */
2008                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2009
2010                 /*
2011                  * FIXME: Legacy driver indicates that the frame does
2012                  * contain the Michael Mic. Unfortunately, in rt2x00
2013                  * the MIC seems to be missing completely...
2014                  */
2015                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2016
2017                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2018                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2019                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2020                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2021         }
2022
2023         /*
2024          * Obtain the status about this packet.
2025          * When frame was received with an OFDM bitrate,
2026          * the signal is the PLCP value. If it was received with
2027          * a CCK bitrate the signal is the rate in 100kbit/s.
2028          */
2029         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2030         rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2031         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2032
2033         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2034                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2035         else
2036                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2037         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2038                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2039 }
2040
2041 /*
2042  * Interrupt functions.
2043  */
2044 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2045 {
2046         struct data_queue *queue;
2047         struct queue_entry *entry;
2048         struct queue_entry *entry_done;
2049         struct queue_entry_priv_pci *entry_priv;
2050         struct txdone_entry_desc txdesc;
2051         u32 word;
2052         u32 reg;
2053         u32 old_reg;
2054         int type;
2055         int index;
2056
2057         /*
2058          * During each loop we will compare the freshly read
2059          * STA_CSR4 register value with the value read from
2060          * the previous loop. If the 2 values are equal then
2061          * we should stop processing because the chance it
2062          * quite big that the device has been unplugged and
2063          * we risk going into an endless loop.
2064          */
2065         old_reg = 0;
2066
2067         while (1) {
2068                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2069                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2070                         break;
2071
2072                 if (old_reg == reg)
2073                         break;
2074                 old_reg = reg;
2075
2076                 /*
2077                  * Skip this entry when it contains an invalid
2078                  * queue identication number.
2079                  */
2080                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2081                 queue = rt2x00queue_get_queue(rt2x00dev, type);
2082                 if (unlikely(!queue))
2083                         continue;
2084
2085                 /*
2086                  * Skip this entry when it contains an invalid
2087                  * index number.
2088                  */
2089                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2090                 if (unlikely(index >= queue->limit))
2091                         continue;
2092
2093                 entry = &queue->entries[index];
2094                 entry_priv = entry->priv_data;
2095                 rt2x00_desc_read(entry_priv->desc, 0, &word);
2096
2097                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2098                     !rt2x00_get_field32(word, TXD_W0_VALID))
2099                         return;
2100
2101                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2102                 while (entry != entry_done) {
2103                         /* Catch up.
2104                          * Just report any entries we missed as failed.
2105                          */
2106                         WARNING(rt2x00dev,
2107                                 "TX status report missed for entry %d\n",
2108                                 entry_done->entry_idx);
2109
2110                         txdesc.flags = 0;
2111                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2112                         txdesc.retry = 0;
2113
2114                         rt2x00lib_txdone(entry_done, &txdesc);
2115                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2116                 }
2117
2118                 /*
2119                  * Obtain the status about this packet.
2120                  */
2121                 txdesc.flags = 0;
2122                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2123                 case 0: /* Success, maybe with retry */
2124                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2125                         break;
2126                 case 6: /* Failure, excessive retries */
2127                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2128                         /* Don't break, this is a failed frame! */
2129                 default: /* Failure */
2130                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
2131                 }
2132                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2133
2134                 rt2x00lib_txdone(entry, &txdesc);
2135         }
2136 }
2137
2138 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2139 {
2140         struct rt2x00_dev *rt2x00dev = dev_instance;
2141         u32 reg_mcu;
2142         u32 reg;
2143
2144         /*
2145          * Get the interrupt sources & saved to local variable.
2146          * Write register value back to clear pending interrupts.
2147          */
2148         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2149         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2150
2151         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2152         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2153
2154         if (!reg && !reg_mcu)
2155                 return IRQ_NONE;
2156
2157         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2158                 return IRQ_HANDLED;
2159
2160         /*
2161          * Handle interrupts, walk through all bits
2162          * and run the tasks, the bits are checked in order of
2163          * priority.
2164          */
2165
2166         /*
2167          * 1 - Rx ring done interrupt.
2168          */
2169         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2170                 rt2x00pci_rxdone(rt2x00dev);
2171
2172         /*
2173          * 2 - Tx ring done interrupt.
2174          */
2175         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2176                 rt61pci_txdone(rt2x00dev);
2177
2178         /*
2179          * 3 - Handle MCU command done.
2180          */
2181         if (reg_mcu)
2182                 rt2x00pci_register_write(rt2x00dev,
2183                                          M2H_CMD_DONE_CSR, 0xffffffff);
2184
2185         return IRQ_HANDLED;
2186 }
2187
2188 /*
2189  * Device probe functions.
2190  */
2191 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2192 {
2193         struct eeprom_93cx6 eeprom;
2194         u32 reg;
2195         u16 word;
2196         u8 *mac;
2197         s8 value;
2198
2199         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2200
2201         eeprom.data = rt2x00dev;
2202         eeprom.register_read = rt61pci_eepromregister_read;
2203         eeprom.register_write = rt61pci_eepromregister_write;
2204         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2205             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2206         eeprom.reg_data_in = 0;
2207         eeprom.reg_data_out = 0;
2208         eeprom.reg_data_clock = 0;
2209         eeprom.reg_chip_select = 0;
2210
2211         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2212                                EEPROM_SIZE / sizeof(u16));
2213
2214         /*
2215          * Start validation of the data that has been read.
2216          */
2217         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2218         if (!is_valid_ether_addr(mac)) {
2219                 random_ether_addr(mac);
2220                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2221         }
2222
2223         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2224         if (word == 0xffff) {
2225                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2226                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2227                                    ANTENNA_B);
2228                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2229                                    ANTENNA_B);
2230                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2231                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2232                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2233                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2234                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2235                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2236         }
2237
2238         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2239         if (word == 0xffff) {
2240                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2241                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2242                 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2243                 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
2244                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2245                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2246                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2247                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2248                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2249         }
2250
2251         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2252         if (word == 0xffff) {
2253                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2254                                    LED_MODE_DEFAULT);
2255                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2256                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2257         }
2258
2259         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2260         if (word == 0xffff) {
2261                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2262                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2263                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2264                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2265         }
2266
2267         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2268         if (word == 0xffff) {
2269                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2270                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2271                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2272                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2273         } else {
2274                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2275                 if (value < -10 || value > 10)
2276                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2277                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2278                 if (value < -10 || value > 10)
2279                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2280                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2281         }
2282
2283         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2284         if (word == 0xffff) {
2285                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2286                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2287                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2288                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2289         } else {
2290                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2291                 if (value < -10 || value > 10)
2292                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2293                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2294                 if (value < -10 || value > 10)
2295                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2296                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2297         }
2298
2299         return 0;
2300 }
2301
2302 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2303 {
2304         u32 reg;
2305         u16 value;
2306         u16 eeprom;
2307         u16 device;
2308
2309         /*
2310          * Read EEPROM word for configuration.
2311          */
2312         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2313
2314         /*
2315          * Identify RF chipset.
2316          * To determine the RT chip we have to read the
2317          * PCI header of the device.
2318          */
2319         pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2320                              PCI_CONFIG_HEADER_DEVICE, &device);
2321         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2322         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2323         rt2x00_set_chip(rt2x00dev, device, value, reg);
2324
2325         if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2326             !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2327             !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2328             !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2329                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2330                 return -ENODEV;
2331         }
2332
2333         /*
2334          * Determine number of antenna's.
2335          */
2336         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2337                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2338
2339         /*
2340          * Identify default antenna configuration.
2341          */
2342         rt2x00dev->default_ant.tx =
2343             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2344         rt2x00dev->default_ant.rx =
2345             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2346
2347         /*
2348          * Read the Frame type.
2349          */
2350         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2351                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2352
2353         /*
2354          * Detect if this device has an hardware controlled radio.
2355          */
2356 #ifdef CONFIG_RT2X00_LIB_RFKILL
2357         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2358                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2359 #endif /* CONFIG_RT2X00_LIB_RFKILL */
2360
2361         /*
2362          * Read frequency offset and RF programming sequence.
2363          */
2364         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2365         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2366                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2367
2368         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2369
2370         /*
2371          * Read external LNA informations.
2372          */
2373         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2374
2375         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2376                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2377         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2378                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2379
2380         /*
2381          * When working with a RF2529 chip without double antenna
2382          * the antenna settings should be gathered from the NIC
2383          * eeprom word.
2384          */
2385         if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2386             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2387                 rt2x00dev->default_ant.rx =
2388                     ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2389                 rt2x00dev->default_ant.tx =
2390                     ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
2391
2392                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2393                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2394                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2395                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2396         }
2397
2398         /*
2399          * Store led settings, for correct led behaviour.
2400          * If the eeprom value is invalid,
2401          * switch to default led mode.
2402          */
2403 #ifdef CONFIG_RT2X00_LIB_LEDS
2404         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2405         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2406
2407         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2408         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2409         if (value == LED_MODE_SIGNAL_STRENGTH)
2410                 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2411                                  LED_TYPE_QUALITY);
2412
2413         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2414         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2415                            rt2x00_get_field16(eeprom,
2416                                               EEPROM_LED_POLARITY_GPIO_0));
2417         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2418                            rt2x00_get_field16(eeprom,
2419                                               EEPROM_LED_POLARITY_GPIO_1));
2420         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2421                            rt2x00_get_field16(eeprom,
2422                                               EEPROM_LED_POLARITY_GPIO_2));
2423         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2424                            rt2x00_get_field16(eeprom,
2425                                               EEPROM_LED_POLARITY_GPIO_3));
2426         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2427                            rt2x00_get_field16(eeprom,
2428                                               EEPROM_LED_POLARITY_GPIO_4));
2429         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2430                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2431         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2432                            rt2x00_get_field16(eeprom,
2433                                               EEPROM_LED_POLARITY_RDY_G));
2434         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2435                            rt2x00_get_field16(eeprom,
2436                                               EEPROM_LED_POLARITY_RDY_A));
2437 #endif /* CONFIG_RT2X00_LIB_LEDS */
2438
2439         return 0;
2440 }
2441
2442 /*
2443  * RF value list for RF5225 & RF5325
2444  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2445  */
2446 static const struct rf_channel rf_vals_noseq[] = {
2447         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2448         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2449         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2450         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2451         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2452         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2453         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2454         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2455         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2456         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2457         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2458         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2459         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2460         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2461
2462         /* 802.11 UNI / HyperLan 2 */
2463         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2464         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2465         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2466         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2467         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2468         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2469         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2470         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2471
2472         /* 802.11 HyperLan 2 */
2473         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2474         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2475         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2476         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2477         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2478         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2479         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2480         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2481         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2482         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2483
2484         /* 802.11 UNII */
2485         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2486         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2487         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2488         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2489         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2490         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2491
2492         /* MMAC(Japan)J52 ch 34,38,42,46 */
2493         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2494         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2495         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2496         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2497 };
2498
2499 /*
2500  * RF value list for RF5225 & RF5325
2501  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2502  */
2503 static const struct rf_channel rf_vals_seq[] = {
2504         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2505         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2506         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2507         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2508         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2509         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2510         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2511         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2512         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2513         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2514         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2515         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2516         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2517         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2518
2519         /* 802.11 UNI / HyperLan 2 */
2520         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2521         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2522         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2523         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2524         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2525         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2526         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2527         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2528
2529         /* 802.11 HyperLan 2 */
2530         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2531         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2532         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2533         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2534         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2535         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2536         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2537         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2538         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2539         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2540
2541         /* 802.11 UNII */
2542         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2543         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2544         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2545         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2546         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2547         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2548
2549         /* MMAC(Japan)J52 ch 34,38,42,46 */
2550         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2551         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2552         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2553         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2554 };
2555
2556 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2557 {
2558         struct hw_mode_spec *spec = &rt2x00dev->spec;
2559         struct channel_info *info;
2560         char *tx_power;
2561         unsigned int i;
2562
2563         /*
2564          * Initialize all hw fields.
2565          */
2566         rt2x00dev->hw->flags =
2567             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2568             IEEE80211_HW_SIGNAL_DBM |
2569             IEEE80211_HW_SUPPORTS_PS |
2570             IEEE80211_HW_PS_NULLFUNC_STACK;
2571         rt2x00dev->hw->extra_tx_headroom = 0;
2572
2573         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2574         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2575                                 rt2x00_eeprom_addr(rt2x00dev,
2576                                                    EEPROM_MAC_ADDR_0));
2577
2578         /*
2579          * Initialize hw_mode information.
2580          */
2581         spec->supported_bands = SUPPORT_BAND_2GHZ;
2582         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2583
2584         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2585                 spec->num_channels = 14;
2586                 spec->channels = rf_vals_noseq;
2587         } else {
2588                 spec->num_channels = 14;
2589                 spec->channels = rf_vals_seq;
2590         }
2591
2592         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2593             rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2594                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2595                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2596         }
2597
2598         /*
2599          * Create channel information array
2600          */
2601         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2602         if (!info)
2603                 return -ENOMEM;
2604
2605         spec->channels_info = info;
2606
2607         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2608         for (i = 0; i < 14; i++)
2609                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2610
2611         if (spec->num_channels > 14) {
2612                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2613                 for (i = 14; i < spec->num_channels; i++)
2614                         info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2615         }
2616
2617         return 0;
2618 }
2619
2620 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2621 {
2622         int retval;
2623
2624         /*
2625          * Allocate eeprom data.
2626          */
2627         retval = rt61pci_validate_eeprom(rt2x00dev);
2628         if (retval)
2629                 return retval;
2630
2631         retval = rt61pci_init_eeprom(rt2x00dev);
2632         if (retval)
2633                 return retval;
2634
2635         /*
2636          * Initialize hw specifications.
2637          */
2638         retval = rt61pci_probe_hw_mode(rt2x00dev);
2639         if (retval)
2640                 return retval;
2641
2642         /*
2643          * This device requires firmware and DMA mapped skbs.
2644          */
2645         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2646         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2647         if (!modparam_nohwcrypt)
2648                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2649
2650         /*
2651          * Set the rssi offset.
2652          */
2653         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2654
2655         return 0;
2656 }
2657
2658 /*
2659  * IEEE80211 stack callback functions.
2660  */
2661 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2662                            const struct ieee80211_tx_queue_params *params)
2663 {
2664         struct rt2x00_dev *rt2x00dev = hw->priv;
2665         struct data_queue *queue;
2666         struct rt2x00_field32 field;
2667         int retval;
2668         u32 reg;
2669         u32 offset;
2670
2671         /*
2672          * First pass the configuration through rt2x00lib, that will
2673          * update the queue settings and validate the input. After that
2674          * we are free to update the registers based on the value
2675          * in the queue parameter.
2676          */
2677         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2678         if (retval)
2679                 return retval;
2680
2681         /*
2682          * We only need to perform additional register initialization
2683          * for WMM queues/
2684          */
2685         if (queue_idx >= 4)
2686                 return 0;
2687
2688         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2689
2690         /* Update WMM TXOP register */
2691         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2692         field.bit_offset = (queue_idx & 1) * 16;
2693         field.bit_mask = 0xffff << field.bit_offset;
2694
2695         rt2x00pci_register_read(rt2x00dev, offset, &reg);
2696         rt2x00_set_field32(&reg, field, queue->txop);
2697         rt2x00pci_register_write(rt2x00dev, offset, reg);
2698
2699         /* Update WMM registers */
2700         field.bit_offset = queue_idx * 4;
2701         field.bit_mask = 0xf << field.bit_offset;
2702
2703         rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2704         rt2x00_set_field32(&reg, field, queue->aifs);
2705         rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2706
2707         rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2708         rt2x00_set_field32(&reg, field, queue->cw_min);
2709         rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2710
2711         rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2712         rt2x00_set_field32(&reg, field, queue->cw_max);
2713         rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2714
2715         return 0;
2716 }
2717
2718 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2719 {
2720         struct rt2x00_dev *rt2x00dev = hw->priv;
2721         u64 tsf;
2722         u32 reg;
2723
2724         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2725         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2726         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2727         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2728
2729         return tsf;
2730 }
2731
2732 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2733         .tx                     = rt2x00mac_tx,
2734         .start                  = rt2x00mac_start,
2735         .stop                   = rt2x00mac_stop,
2736         .add_interface          = rt2x00mac_add_interface,
2737         .remove_interface       = rt2x00mac_remove_interface,
2738         .config                 = rt2x00mac_config,
2739         .config_interface       = rt2x00mac_config_interface,
2740         .configure_filter       = rt2x00mac_configure_filter,
2741         .set_key                = rt2x00mac_set_key,
2742         .get_stats              = rt2x00mac_get_stats,
2743         .bss_info_changed       = rt2x00mac_bss_info_changed,
2744         .conf_tx                = rt61pci_conf_tx,
2745         .get_tx_stats           = rt2x00mac_get_tx_stats,
2746         .get_tsf                = rt61pci_get_tsf,
2747 };
2748
2749 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2750         .irq_handler            = rt61pci_interrupt,
2751         .probe_hw               = rt61pci_probe_hw,
2752         .get_firmware_name      = rt61pci_get_firmware_name,
2753         .get_firmware_crc       = rt61pci_get_firmware_crc,
2754         .load_firmware          = rt61pci_load_firmware,
2755         .initialize             = rt2x00pci_initialize,
2756         .uninitialize           = rt2x00pci_uninitialize,
2757         .get_entry_state        = rt61pci_get_entry_state,
2758         .clear_entry            = rt61pci_clear_entry,
2759         .set_device_state       = rt61pci_set_device_state,
2760         .rfkill_poll            = rt61pci_rfkill_poll,
2761         .link_stats             = rt61pci_link_stats,
2762         .reset_tuner            = rt61pci_reset_tuner,
2763         .link_tuner             = rt61pci_link_tuner,
2764         .write_tx_desc          = rt61pci_write_tx_desc,
2765         .write_tx_data          = rt2x00pci_write_tx_data,
2766         .write_beacon           = rt61pci_write_beacon,
2767         .kick_tx_queue          = rt61pci_kick_tx_queue,
2768         .kill_tx_queue          = rt61pci_kill_tx_queue,
2769         .fill_rxdone            = rt61pci_fill_rxdone,
2770         .config_shared_key      = rt61pci_config_shared_key,
2771         .config_pairwise_key    = rt61pci_config_pairwise_key,
2772         .config_filter          = rt61pci_config_filter,
2773         .config_intf            = rt61pci_config_intf,
2774         .config_erp             = rt61pci_config_erp,
2775         .config_ant             = rt61pci_config_ant,
2776         .config                 = rt61pci_config,
2777 };
2778
2779 static const struct data_queue_desc rt61pci_queue_rx = {
2780         .entry_num              = RX_ENTRIES,
2781         .data_size              = DATA_FRAME_SIZE,
2782         .desc_size              = RXD_DESC_SIZE,
2783         .priv_size              = sizeof(struct queue_entry_priv_pci),
2784 };
2785
2786 static const struct data_queue_desc rt61pci_queue_tx = {
2787         .entry_num              = TX_ENTRIES,
2788         .data_size              = DATA_FRAME_SIZE,
2789         .desc_size              = TXD_DESC_SIZE,
2790         .priv_size              = sizeof(struct queue_entry_priv_pci),
2791 };
2792
2793 static const struct data_queue_desc rt61pci_queue_bcn = {
2794         .entry_num              = 4 * BEACON_ENTRIES,
2795         .data_size              = 0, /* No DMA required for beacons */
2796         .desc_size              = TXINFO_SIZE,
2797         .priv_size              = sizeof(struct queue_entry_priv_pci),
2798 };
2799
2800 static const struct rt2x00_ops rt61pci_ops = {
2801         .name           = KBUILD_MODNAME,
2802         .max_sta_intf   = 1,
2803         .max_ap_intf    = 4,
2804         .eeprom_size    = EEPROM_SIZE,
2805         .rf_size        = RF_SIZE,
2806         .tx_queues      = NUM_TX_QUEUES,
2807         .rx             = &rt61pci_queue_rx,
2808         .tx             = &rt61pci_queue_tx,
2809         .bcn            = &rt61pci_queue_bcn,
2810         .lib            = &rt61pci_rt2x00_ops,
2811         .hw             = &rt61pci_mac80211_ops,
2812 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2813         .debugfs        = &rt61pci_rt2x00debug,
2814 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2815 };
2816
2817 /*
2818  * RT61pci module information.
2819  */
2820 static struct pci_device_id rt61pci_device_table[] = {
2821         /* RT2561s */
2822         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2823         /* RT2561 v2 */
2824         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2825         /* RT2661 */
2826         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2827         { 0, }
2828 };
2829
2830 MODULE_AUTHOR(DRV_PROJECT);
2831 MODULE_VERSION(DRV_VERSION);
2832 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2833 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2834                         "PCI & PCMCIA chipset based cards");
2835 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2836 MODULE_FIRMWARE(FIRMWARE_RT2561);
2837 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2838 MODULE_FIRMWARE(FIRMWARE_RT2661);
2839 MODULE_LICENSE("GPL");
2840
2841 static struct pci_driver rt61pci_driver = {
2842         .name           = KBUILD_MODNAME,
2843         .id_table       = rt61pci_device_table,
2844         .probe          = rt2x00pci_probe,
2845         .remove         = __devexit_p(rt2x00pci_remove),
2846         .suspend        = rt2x00pci_suspend,
2847         .resume         = rt2x00pci_resume,
2848 };
2849
2850 static int __init rt61pci_init(void)
2851 {
2852         return pci_register_driver(&rt61pci_driver);
2853 }
2854
2855 static void __exit rt61pci_exit(void)
2856 {
2857         pci_unregister_driver(&rt61pci_driver);
2858 }
2859
2860 module_init(rt61pci_init);
2861 module_exit(rt61pci_exit);