[MIPS] SB1: Fix interrupt disable hazard.
[linux-2.6] / include / asm-arm / arch-ixp4xx / entry-macro.S
1 /*
2  * include/asm-arm/arch-ixp4xx/entry-macro.S
3  *
4  * Low-level IRQ helper macros for IXP4xx-based platforms
5  *
6  * This file is licensed under  the terms of the GNU General Public
7  * License version 2. This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  */
10 #include <asm/hardware.h>
11
12                 .macro  disable_fiq
13                 .endm
14
15                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
16                 ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
17                 ldr     \irqstat, [\irqstat]            @ get interrupts
18                 cmp     \irqstat, #0
19                 beq     1001f                           @ upper IRQ?
20                 clz     \irqnr, \irqstat
21                 mov     \base, #31
22                 sub     \irqnr, \base, \irqnr
23                 b       1002f                           @ lower IRQ being
24                                                         @ handled
25
26 1001:
27                 /*
28                  * IXP465 has an upper IRQ status register
29                  */
30 #if defined(CONFIG_CPU_IXP46X)
31                 ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
32                 ldr     \irqstat, [\irqstat]            @ get upper interrupts
33                 mov     \irqnr, #63
34                 clz     \irqstat, \irqstat
35                 cmp     \irqstat, #32
36                 subne   \irqnr, \irqnr, \irqstat
37 #endif
38 1002:
39                 .endm
40
41