git.oblomov.eu Git - linux-2.6/blob - drivers/gpu/drm/radeon/rv515.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "radeon_reg.h"
  31 #include "radeon.h"
  32
  33 /* rv515 depends on : */
  34 void r100_hdp_reset(struct radeon_device *rdev);
  35 int r100_cp_reset(struct radeon_device *rdev);
  36 int r100_rb2d_reset(struct radeon_device *rdev);
  37 int r100_gui_wait_for_idle(struct radeon_device *rdev);
  38 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  39 int rv370_pcie_gart_enable(struct radeon_device *rdev);
  40 void rv370_pcie_gart_disable(struct radeon_device *rdev);
  41 void r420_pipes_init(struct radeon_device *rdev);
  42 void rs600_mc_disable_clients(struct radeon_device *rdev);
  43 void rs600_disable_vga(struct radeon_device *rdev);
  44
  45 /* This files gather functions specifics to:
  46  * rv515
  47  *
  48  * Some of these functions might be used by newer ASICs.
  49  */
  50 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  51 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  52 void rv515_gpu_init(struct radeon_device *rdev);
  53 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  54
  55
  56 /*
  57  * MC
  58  */
  59 int rv515_mc_init(struct radeon_device *rdev)
  60 {
  61         uint32_t tmp;
  62         int r;
  63
  64         if (r100_debugfs_rbbm_init(rdev)) {
  65                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  66         }
  67         if (rv515_debugfs_pipes_info_init(rdev)) {
  68                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  69         }
  70         if (rv515_debugfs_ga_info_init(rdev)) {
  71                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  72         }
  73
  74         rv515_gpu_init(rdev);
  75         rv370_pcie_gart_disable(rdev);
  76
  77         /* Setup GPU memory space */
  78         rdev->mc.vram_location = 0xFFFFFFFFUL;
  79         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  80         if (rdev->flags & RADEON_IS_AGP) {
  81                 r = radeon_agp_init(rdev);
  82                 if (r) {
  83                         printk(KERN_WARNING "[drm] Disabling AGP\n");
  84                         rdev->flags &= ~RADEON_IS_AGP;
  85                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  86                 } else {
  87                         rdev->mc.gtt_location = rdev->mc.agp_base;
  88                 }
  89         }
  90         r = radeon_mc_setup(rdev);
  91         if (r) {
  92                 return r;
  93         }
  94
  95         /* Program GPU memory space */
  96         rs600_mc_disable_clients(rdev);
  97         if (rv515_mc_wait_for_idle(rdev)) {
  98                 printk(KERN_WARNING "Failed to wait MC idle while "
  99                        "programming pipes. Bad things might happen.\n");
 100         }
 101         /* Write VRAM size in case we are limiting it */
 102         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
 103         tmp = REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
 104         WREG32(0x134, tmp);
 105         tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
 106         tmp = REG_SET(RV515_MC_FB_TOP, tmp >> 16);
 107         tmp |= REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
 108         WREG32_MC(RV515_MC_FB_LOCATION, tmp);
 109         WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
 110         WREG32(0x310, rdev->mc.vram_location);
 111         if (rdev->flags & RADEON_IS_AGP) {
 112                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 113                 tmp = REG_SET(RV515_MC_AGP_TOP, tmp >> 16);
 114                 tmp |= REG_SET(RV515_MC_AGP_START, rdev->mc.gtt_location >> 16);
 115                 WREG32_MC(RV515_MC_AGP_LOCATION, tmp);
 116                 WREG32_MC(RV515_MC_AGP_BASE, rdev->mc.agp_base);
 117                 WREG32_MC(RV515_MC_AGP_BASE_2, 0);
 118         } else {
 119                 WREG32_MC(RV515_MC_AGP_LOCATION, 0x0FFFFFFF);
 120                 WREG32_MC(RV515_MC_AGP_BASE, 0);
 121                 WREG32_MC(RV515_MC_AGP_BASE_2, 0);
 122         }
 123         return 0;
 124 }
 125
 126 void rv515_mc_fini(struct radeon_device *rdev)
 127 {
 128         rv370_pcie_gart_disable(rdev);
 129         radeon_gart_table_vram_free(rdev);
 130         radeon_gart_fini(rdev);
 131 }
 132
 133
 134 /*
 135  * Global GPU functions
 136  */
 137 void rv515_ring_start(struct radeon_device *rdev)
 138 {
 139         unsigned gb_tile_config;
 140         int r;
 141
 142         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 143         gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16;
 144         switch (rdev->num_gb_pipes) {
 145         case 2:
 146                 gb_tile_config |= R300_PIPE_COUNT_R300;
 147                 break;
 148         case 3:
 149                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 150                 break;
 151         case 4:
 152                 gb_tile_config |= R300_PIPE_COUNT_R420;
 153                 break;
 154         case 1:
 155         default:
 156                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 157                 break;
 158         }
 159
 160         r = radeon_ring_lock(rdev, 64);
 161         if (r) {
 162                 return;
 163         }
 164         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 165         radeon_ring_write(rdev,
 166                           RADEON_ISYNC_ANY2D_IDLE3D |
 167                           RADEON_ISYNC_ANY3D_IDLE2D |
 168                           RADEON_ISYNC_WAIT_IDLEGUI |
 169                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 170         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
 171         radeon_ring_write(rdev, gb_tile_config);
 172         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 173         radeon_ring_write(rdev,
 174                           RADEON_WAIT_2D_IDLECLEAN |
 175                           RADEON_WAIT_3D_IDLECLEAN);
 176         radeon_ring_write(rdev, PACKET0(0x170C, 0));
 177         radeon_ring_write(rdev, 1 << 31);
 178         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
 179         radeon_ring_write(rdev, 0);
 180         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
 181         radeon_ring_write(rdev, 0);
 182         radeon_ring_write(rdev, PACKET0(0x42C8, 0));
 183         radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
 184         radeon_ring_write(rdev, PACKET0(R500_VAP_INDEX_OFFSET, 0));
 185         radeon_ring_write(rdev, 0);
 186         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 187         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 188         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 189         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
 190         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 191         radeon_ring_write(rdev,
 192                           RADEON_WAIT_2D_IDLECLEAN |
 193                           RADEON_WAIT_3D_IDLECLEAN);
 194         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
 195         radeon_ring_write(rdev, 0);
 196         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 197         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 198         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 199         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
 200         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
 201         radeon_ring_write(rdev,
 202                           ((6 << R300_MS_X0_SHIFT) |
 203                            (6 << R300_MS_Y0_SHIFT) |
 204                            (6 << R300_MS_X1_SHIFT) |
 205                            (6 << R300_MS_Y1_SHIFT) |
 206                            (6 << R300_MS_X2_SHIFT) |
 207                            (6 << R300_MS_Y2_SHIFT) |
 208                            (6 << R300_MSBD0_Y_SHIFT) |
 209                            (6 << R300_MSBD0_X_SHIFT)));
 210         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
 211         radeon_ring_write(rdev,
 212                           ((6 << R300_MS_X3_SHIFT) |
 213                            (6 << R300_MS_Y3_SHIFT) |
 214                            (6 << R300_MS_X4_SHIFT) |
 215                            (6 << R300_MS_Y4_SHIFT) |
 216                            (6 << R300_MS_X5_SHIFT) |
 217                            (6 << R300_MS_Y5_SHIFT) |
 218                            (6 << R300_MSBD1_SHIFT)));
 219         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
 220         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 221         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
 222         radeon_ring_write(rdev,
 223                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 224         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
 225         radeon_ring_write(rdev,
 226                           R300_GEOMETRY_ROUND_NEAREST |
 227                           R300_COLOR_ROUND_NEAREST);
 228         radeon_ring_unlock_commit(rdev);
 229 }
 230
 231 void rv515_errata(struct radeon_device *rdev)
 232 {
 233         rdev->pll_errata = 0;
 234 }
 235
 236 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
 237 {
 238         unsigned i;
 239         uint32_t tmp;
 240
 241         for (i = 0; i < rdev->usec_timeout; i++) {
 242                 /* read MC_STATUS */
 243                 tmp = RREG32_MC(RV515_MC_STATUS);
 244                 if (tmp & RV515_MC_STATUS_IDLE) {
 245                         return 0;
 246                 }
 247                 DRM_UDELAY(1);
 248         }
 249         return -1;
 250 }
 251
 252 void rv515_gpu_init(struct radeon_device *rdev)
 253 {
 254         unsigned pipe_select_current, gb_pipe_select, tmp;
 255
 256         r100_hdp_reset(rdev);
 257         r100_rb2d_reset(rdev);
 258
 259         if (r100_gui_wait_for_idle(rdev)) {
 260                 printk(KERN_WARNING "Failed to wait GUI idle while "
 261                        "reseting GPU. Bad things might happen.\n");
 262         }
 263
 264         rs600_disable_vga(rdev);
 265
 266         r420_pipes_init(rdev);
 267         gb_pipe_select = RREG32(0x402C);
 268         tmp = RREG32(0x170C);
 269         pipe_select_current = (tmp >> 2) & 3;
 270         tmp = (1 << pipe_select_current) |
 271               (((gb_pipe_select >> 8) & 0xF) << 4);
 272         WREG32_PLL(0x000D, tmp);
 273         if (r100_gui_wait_for_idle(rdev)) {
 274                 printk(KERN_WARNING "Failed to wait GUI idle while "
 275                        "reseting GPU. Bad things might happen.\n");
 276         }
 277         if (rv515_mc_wait_for_idle(rdev)) {
 278                 printk(KERN_WARNING "Failed to wait MC idle while "
 279                        "programming pipes. Bad things might happen.\n");
 280         }
 281 }
 282
 283 int rv515_ga_reset(struct radeon_device *rdev)
 284 {
 285         uint32_t tmp;
 286         bool reinit_cp;
 287         int i;
 288
 289         reinit_cp = rdev->cp.ready;
 290         rdev->cp.ready = false;
 291         for (i = 0; i < rdev->usec_timeout; i++) {
 292                 WREG32(RADEON_CP_CSQ_MODE, 0);
 293                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 294                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
 295                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
 296                 udelay(200);
 297                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 298                 /* Wait to prevent race in RBBM_STATUS */
 299                 mdelay(1);
 300                 tmp = RREG32(RADEON_RBBM_STATUS);
 301                 if (tmp & ((1 << 20) | (1 << 26))) {
 302                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
 303                         /* GA still busy soft reset it */
 304                         WREG32(0x429C, 0x200);
 305                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 306                         WREG32(0x43E0, 0);
 307                         WREG32(0x43E4, 0);
 308                         WREG32(0x24AC, 0);
 309                 }
 310                 /* Wait to prevent race in RBBM_STATUS */
 311                 mdelay(1);
 312                 tmp = RREG32(RADEON_RBBM_STATUS);
 313                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 314                         break;
 315                 }
 316         }
 317         for (i = 0; i < rdev->usec_timeout; i++) {
 318                 tmp = RREG32(RADEON_RBBM_STATUS);
 319                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 320                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
 321                                  tmp);
 322                         DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
 323                         DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
 324                         DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
 325                         if (reinit_cp) {
 326                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 327                         }
 328                         return 0;
 329                 }
 330                 DRM_UDELAY(1);
 331         }
 332         tmp = RREG32(RADEON_RBBM_STATUS);
 333         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
 334         return -1;
 335 }
 336
 337 int rv515_gpu_reset(struct radeon_device *rdev)
 338 {
 339         uint32_t status;
 340
 341         /* reset order likely matter */
 342         status = RREG32(RADEON_RBBM_STATUS);
 343         /* reset HDP */
 344         r100_hdp_reset(rdev);
 345         /* reset rb2d */
 346         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
 347                 r100_rb2d_reset(rdev);
 348         }
 349         /* reset GA */
 350         if (status & ((1 << 20) | (1 << 26))) {
 351                 rv515_ga_reset(rdev);
 352         }
 353         /* reset CP */
 354         status = RREG32(RADEON_RBBM_STATUS);
 355         if (status & (1 << 16)) {
 356                 r100_cp_reset(rdev);
 357         }
 358         /* Check if GPU is idle */
 359         status = RREG32(RADEON_RBBM_STATUS);
 360         if (status & (1 << 31)) {
 361                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
 362                 return -1;
 363         }
 364         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
 365         return 0;
 366 }
 367
 368
 369 /*
 370  * VRAM info
 371  */
 372 static void rv515_vram_get_type(struct radeon_device *rdev)
 373 {
 374         uint32_t tmp;
 375
 376         rdev->mc.vram_width = 128;
 377         rdev->mc.vram_is_ddr = true;
 378         tmp = RREG32_MC(RV515_MC_CNTL);
 379         tmp &= RV515_MEM_NUM_CHANNELS_MASK;
 380         switch (tmp) {
 381         case 0:
 382                 rdev->mc.vram_width = 64;
 383                 break;
 384         case 1:
 385                 rdev->mc.vram_width = 128;
 386                 break;
 387         default:
 388                 rdev->mc.vram_width = 128;
 389                 break;
 390         }
 391 }
 392
 393 void rv515_vram_info(struct radeon_device *rdev)
 394 {
 395         rv515_vram_get_type(rdev);
 396         rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 397
 398         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 399         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 400 }
 401
 402
 403 /*
 404  * Indirect registers accessor
 405  */
 406 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 407 {
 408         uint32_t r;
 409
 410         WREG32(R520_MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
 411         r = RREG32(R520_MC_IND_DATA);
 412         WREG32(R520_MC_IND_INDEX, 0);
 413         return r;
 414 }
 415
 416 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 417 {
 418         WREG32(R520_MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
 419         WREG32(R520_MC_IND_DATA, (v));
 420         WREG32(R520_MC_IND_INDEX, 0);
 421 }
 422
 423 uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
 424 {
 425         uint32_t r;
 426
 427         WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
 428         (void)RREG32(RADEON_PCIE_INDEX);
 429         r = RREG32(RADEON_PCIE_DATA);
 430         return r;
 431 }
 432
 433 void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 434 {
 435         WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
 436         (void)RREG32(RADEON_PCIE_INDEX);
 437         WREG32(RADEON_PCIE_DATA, (v));
 438         (void)RREG32(RADEON_PCIE_DATA);
 439 }
 440
 441
 442 /*
 443  * Debugfs info
 444  */
 445 #if defined(CONFIG_DEBUG_FS)
 446 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
 447 {
 448         struct drm_info_node *node = (struct drm_info_node *) m->private;
 449         struct drm_device *dev = node->minor->dev;
 450         struct radeon_device *rdev = dev->dev_private;
 451         uint32_t tmp;
 452
 453         tmp = RREG32(R400_GB_PIPE_SELECT);
 454         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 455         tmp = RREG32(R500_SU_REG_DEST);
 456         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
 457         tmp = RREG32(R300_GB_TILE_CONFIG);
 458         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 459         tmp = RREG32(R300_DST_PIPE_CONFIG);
 460         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 461         return 0;
 462 }
 463
 464 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
 465 {
 466         struct drm_info_node *node = (struct drm_info_node *) m->private;
 467         struct drm_device *dev = node->minor->dev;
 468         struct radeon_device *rdev = dev->dev_private;
 469         uint32_t tmp;
 470
 471         tmp = RREG32(0x2140);
 472         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
 473         radeon_gpu_reset(rdev);
 474         tmp = RREG32(0x425C);
 475         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
 476         return 0;
 477 }
 478
 479 static struct drm_info_list rv515_pipes_info_list[] = {
 480         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
 481 };
 482
 483 static struct drm_info_list rv515_ga_info_list[] = {
 484         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
 485 };
 486 #endif
 487
 488 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
 489 {
 490 #if defined(CONFIG_DEBUG_FS)
 491         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
 492 #else
 493         return 0;
 494 #endif
 495 }
 496
 497 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
 498 {
 499 #if defined(CONFIG_DEBUG_FS)
 500         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
 501 #else
 502         return 0;
 503 #endif
 504 }