2 * Copyright (C) 2006-2007 PA Semi, Inc
4 * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/delay.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <asm/dma-mapping.h>
30 #include <linux/skbuff.h>
33 #include <linux/tcp.h>
34 #include <net/checksum.h>
35 #include <linux/inet_lro.h>
38 #include <asm/firmware.h>
39 #include <asm/pasemi_dma.h>
41 #include "pasemi_mac.h"
43 /* We have our own align, since ppc64 in general has it at 0 because
44 * of design flaws in some of the server bridge chips. However, for
45 * PWRficient doing the unaligned copies is more expensive than doing
46 * unaligned DMA, so make sure the data is aligned instead.
48 #define LOCAL_SKB_ALIGN 2
58 #define LRO_MAX_AGGR 64
61 #define PE_MAX_MTU 9000
62 #define PE_DEF_MTU ETH_DATA_LEN
64 #define DEFAULT_MSG_ENABLE \
74 MODULE_LICENSE("GPL");
75 MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
76 MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
78 static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
79 module_param(debug, int, 0);
80 MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
82 extern const struct ethtool_ops pasemi_mac_ethtool_ops;
84 static int translation_enabled(void)
86 #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
89 return firmware_has_feature(FW_FEATURE_LPAR);
93 static void write_iob_reg(unsigned int reg, unsigned int val)
95 pasemi_write_iob_reg(reg, val);
98 static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg)
100 return pasemi_read_mac_reg(mac->dma_if, reg);
103 static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg,
106 pasemi_write_mac_reg(mac->dma_if, reg, val);
109 static unsigned int read_dma_reg(unsigned int reg)
111 return pasemi_read_dma_reg(reg);
114 static void write_dma_reg(unsigned int reg, unsigned int val)
116 pasemi_write_dma_reg(reg, val);
119 static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac)
124 static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac)
129 static inline void prefetch_skb(const struct sk_buff *skb)
139 static int mac_to_intf(struct pasemi_mac *mac)
141 struct pci_dev *pdev = mac->pdev;
143 int nintf, off, i, j;
144 int devfn = pdev->devfn;
146 tmp = read_dma_reg(PAS_DMA_CAP_IFI);
147 nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S;
148 off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S;
150 /* IOFF contains the offset to the registers containing the
151 * DMA interface-to-MAC-pci-id mappings, and NIN contains number
152 * of total interfaces. Each register contains 4 devfns.
153 * Just do a linear search until we find the devfn of the MAC
154 * we're trying to look up.
157 for (i = 0; i < (nintf+3)/4; i++) {
158 tmp = read_dma_reg(off+4*i);
159 for (j = 0; j < 4; j++) {
160 if (((tmp >> (8*j)) & 0xff) == devfn)
167 static void pasemi_mac_intf_disable(struct pasemi_mac *mac)
171 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
172 flags &= ~PAS_MAC_CFG_PCFG_PE;
173 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
176 static void pasemi_mac_intf_enable(struct pasemi_mac *mac)
180 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
181 flags |= PAS_MAC_CFG_PCFG_PE;
182 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
185 static int pasemi_get_mac_addr(struct pasemi_mac *mac)
187 struct pci_dev *pdev = mac->pdev;
188 struct device_node *dn = pci_device_to_OF_node(pdev);
195 "No device node for mac, not configuring\n");
199 maddr = of_get_property(dn, "local-mac-address", &len);
201 if (maddr && len == 6) {
202 memcpy(mac->mac_addr, maddr, 6);
206 /* Some old versions of firmware mistakenly uses mac-address
207 * (and as a string) instead of a byte array in local-mac-address.
211 maddr = of_get_property(dn, "mac-address", NULL);
215 "no mac address in device tree, not configuring\n");
219 if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
220 &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
222 "can't parse mac address, not configuring\n");
226 memcpy(mac->mac_addr, addr, 6);
231 static int pasemi_mac_set_mac_addr(struct net_device *dev, void *p)
233 struct pasemi_mac *mac = netdev_priv(dev);
234 struct sockaddr *addr = p;
235 unsigned int adr0, adr1;
237 if (!is_valid_ether_addr(addr->sa_data))
240 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
242 adr0 = dev->dev_addr[2] << 24 |
243 dev->dev_addr[3] << 16 |
244 dev->dev_addr[4] << 8 |
246 adr1 = read_mac_reg(mac, PAS_MAC_CFG_ADR1);
248 adr1 |= dev->dev_addr[0] << 8 | dev->dev_addr[1];
250 pasemi_mac_intf_disable(mac);
251 write_mac_reg(mac, PAS_MAC_CFG_ADR0, adr0);
252 write_mac_reg(mac, PAS_MAC_CFG_ADR1, adr1);
253 pasemi_mac_intf_enable(mac);
258 static int get_skb_hdr(struct sk_buff *skb, void **iphdr,
259 void **tcph, u64 *hdr_flags, void *data)
261 u64 macrx = (u64) data;
265 /* IPv4 header checksum failed */
266 if ((macrx & XCT_MACRX_HTY_M) != XCT_MACRX_HTY_IPV4_OK)
270 skb_reset_network_header(skb);
272 if (iph->protocol != IPPROTO_TCP)
275 ip_len = ip_hdrlen(skb);
276 skb_set_transport_header(skb, ip_len);
277 *tcph = tcp_hdr(skb);
279 /* check if ip header and tcp header are complete */
280 if (ntohs(iph->tot_len) < ip_len + tcp_hdrlen(skb))
283 *hdr_flags = LRO_IPV4 | LRO_TCP;
289 static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
292 const dma_addr_t *dmas)
295 struct pci_dev *pdev = mac->dma_pdev;
297 pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE);
299 for (f = 0; f < nfrags; f++) {
300 skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
302 pci_unmap_page(pdev, dmas[f+1], frag->size, PCI_DMA_TODEVICE);
304 dev_kfree_skb_irq(skb);
306 /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
307 * aligned up to a power of 2
309 return (nfrags + 3) & ~1;
312 static struct pasemi_mac_csring *pasemi_mac_setup_csring(struct pasemi_mac *mac)
314 struct pasemi_mac_csring *ring;
319 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_csring),
320 offsetof(struct pasemi_mac_csring, chan));
323 dev_err(&mac->pdev->dev, "Can't allocate checksum channel\n");
327 chno = ring->chan.chno;
329 ring->size = CS_RING_SIZE;
330 ring->next_to_fill = 0;
332 /* Allocate descriptors */
333 if (pasemi_dma_alloc_ring(&ring->chan, CS_RING_SIZE))
336 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
337 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
338 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
339 val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3);
341 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
343 ring->events[0] = pasemi_dma_alloc_flag();
344 ring->events[1] = pasemi_dma_alloc_flag();
345 if (ring->events[0] < 0 || ring->events[1] < 0)
348 pasemi_dma_clear_flag(ring->events[0]);
349 pasemi_dma_clear_flag(ring->events[1]);
351 ring->fun = pasemi_dma_alloc_fun();
355 cfg = PAS_DMA_TXCHAN_CFG_TY_FUNC | PAS_DMA_TXCHAN_CFG_UP |
356 PAS_DMA_TXCHAN_CFG_TATTR(ring->fun) |
357 PAS_DMA_TXCHAN_CFG_LPSQ | PAS_DMA_TXCHAN_CFG_LPDQ;
359 if (translation_enabled())
360 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
362 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
365 pasemi_dma_start_chan(&ring->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
366 PAS_DMA_TXCHAN_TCMDSTA_DB |
367 PAS_DMA_TXCHAN_TCMDSTA_DE |
368 PAS_DMA_TXCHAN_TCMDSTA_DA);
374 if (ring->events[0] >= 0)
375 pasemi_dma_free_flag(ring->events[0]);
376 if (ring->events[1] >= 0)
377 pasemi_dma_free_flag(ring->events[1]);
378 pasemi_dma_free_ring(&ring->chan);
380 pasemi_dma_free_chan(&ring->chan);
386 static void pasemi_mac_setup_csrings(struct pasemi_mac *mac)
389 mac->cs[0] = pasemi_mac_setup_csring(mac);
390 if (mac->type == MAC_TYPE_XAUI)
391 mac->cs[1] = pasemi_mac_setup_csring(mac);
395 for (i = 0; i < MAX_CS; i++)
400 static void pasemi_mac_free_csring(struct pasemi_mac_csring *csring)
402 pasemi_dma_stop_chan(&csring->chan);
403 pasemi_dma_free_flag(csring->events[0]);
404 pasemi_dma_free_flag(csring->events[1]);
405 pasemi_dma_free_ring(&csring->chan);
406 pasemi_dma_free_chan(&csring->chan);
407 pasemi_dma_free_fun(csring->fun);
410 static int pasemi_mac_setup_rx_resources(const struct net_device *dev)
412 struct pasemi_mac_rxring *ring;
413 struct pasemi_mac *mac = netdev_priv(dev);
417 ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring),
418 offsetof(struct pasemi_mac_rxring, chan));
421 dev_err(&mac->pdev->dev, "Can't allocate RX channel\n");
424 chno = ring->chan.chno;
426 spin_lock_init(&ring->lock);
428 ring->size = RX_RING_SIZE;
429 ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
430 RX_RING_SIZE, GFP_KERNEL);
432 if (!ring->ring_info)
435 /* Allocate descriptors */
436 if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE))
439 ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
440 RX_RING_SIZE * sizeof(u64),
441 &ring->buf_dma, GFP_KERNEL);
445 memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
447 write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno),
448 PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma));
450 write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno),
451 PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) |
452 PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
454 cfg = PAS_DMA_RXCHAN_CFG_HBU(2);
456 if (translation_enabled())
457 cfg |= PAS_DMA_RXCHAN_CFG_CTR;
459 write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg);
461 write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if),
462 PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma));
464 write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if),
465 PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) |
466 PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
468 cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 |
469 PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP |
470 PAS_DMA_RXINT_CFG_HEN;
472 if (translation_enabled())
473 cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR;
475 write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg);
477 ring->next_to_fill = 0;
478 ring->next_to_clean = 0;
485 kfree(ring->ring_info);
487 pasemi_dma_free_chan(&ring->chan);
492 static struct pasemi_mac_txring *
493 pasemi_mac_setup_tx_resources(const struct net_device *dev)
495 struct pasemi_mac *mac = netdev_priv(dev);
497 struct pasemi_mac_txring *ring;
501 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring),
502 offsetof(struct pasemi_mac_txring, chan));
505 dev_err(&mac->pdev->dev, "Can't allocate TX channel\n");
509 chno = ring->chan.chno;
511 spin_lock_init(&ring->lock);
513 ring->size = TX_RING_SIZE;
514 ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
515 TX_RING_SIZE, GFP_KERNEL);
516 if (!ring->ring_info)
519 /* Allocate descriptors */
520 if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE))
523 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
524 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
525 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
526 val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
528 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
530 cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE |
531 PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
532 PAS_DMA_TXCHAN_CFG_UP |
533 PAS_DMA_TXCHAN_CFG_WT(4);
535 if (translation_enabled())
536 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
538 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
540 ring->next_to_fill = 0;
541 ring->next_to_clean = 0;
547 kfree(ring->ring_info);
549 pasemi_dma_free_chan(&ring->chan);
554 static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac)
556 struct pasemi_mac_txring *txring = tx_ring(mac);
558 struct pasemi_mac_buffer *info;
559 dma_addr_t dmas[MAX_SKB_FRAGS+1];
563 start = txring->next_to_clean;
564 limit = txring->next_to_fill;
566 /* Compensate for when fill has wrapped and clean has not */
568 limit += TX_RING_SIZE;
570 for (i = start; i < limit; i += freed) {
571 info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)];
572 if (info->dma && info->skb) {
573 nfrags = skb_shinfo(info->skb)->nr_frags;
574 for (j = 0; j <= nfrags; j++)
575 dmas[j] = txring->ring_info[(i+1+j) &
576 (TX_RING_SIZE-1)].dma;
577 freed = pasemi_mac_unmap_tx_skb(mac, nfrags,
583 kfree(txring->ring_info);
584 pasemi_dma_free_chan(&txring->chan);
588 static void pasemi_mac_free_rx_buffers(struct pasemi_mac *mac)
590 struct pasemi_mac_rxring *rx = rx_ring(mac);
592 struct pasemi_mac_buffer *info;
594 for (i = 0; i < RX_RING_SIZE; i++) {
595 info = &RX_DESC_INFO(rx, i);
596 if (info->skb && info->dma) {
597 pci_unmap_single(mac->dma_pdev,
601 dev_kfree_skb_any(info->skb);
607 for (i = 0; i < RX_RING_SIZE; i++)
611 static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac)
613 pasemi_mac_free_rx_buffers(mac);
615 dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
616 rx_ring(mac)->buffers, rx_ring(mac)->buf_dma);
618 kfree(rx_ring(mac)->ring_info);
619 pasemi_dma_free_chan(&rx_ring(mac)->chan);
623 static void pasemi_mac_replenish_rx_ring(const struct net_device *dev,
626 const struct pasemi_mac *mac = netdev_priv(dev);
627 struct pasemi_mac_rxring *rx = rx_ring(mac);
633 fill = rx_ring(mac)->next_to_fill;
634 for (count = 0; count < limit; count++) {
635 struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill);
636 u64 *buff = &RX_BUFF(rx, fill);
643 skb = dev_alloc_skb(mac->bufsz);
644 skb_reserve(skb, LOCAL_SKB_ALIGN);
649 dma = pci_map_single(mac->dma_pdev, skb->data,
650 mac->bufsz - LOCAL_SKB_ALIGN,
653 if (unlikely(pci_dma_mapping_error(mac->dma_pdev, dma))) {
654 dev_kfree_skb_irq(info->skb);
660 *buff = XCT_RXB_LEN(mac->bufsz) | XCT_RXB_ADDR(dma);
666 write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count);
668 rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) &
672 static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac)
674 struct pasemi_mac_rxring *rx = rx_ring(mac);
675 unsigned int reg, pcnt;
676 /* Re-enable packet count interrupts: finally
677 * ack the packet count interrupt we got in rx_intr.
680 pcnt = *rx->chan.status & PAS_STATUS_PCNT_M;
682 reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
684 if (*rx->chan.status & PAS_STATUS_TIMER)
685 reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
687 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg);
690 static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac)
692 unsigned int reg, pcnt;
694 /* Re-enable packet count interrupts */
695 pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M;
697 reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
699 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg);
703 static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac,
706 unsigned int rcmdsta, ccmdsta;
707 struct pasemi_dmachan *chan = &rx_ring(mac)->chan;
709 if (!netif_msg_rx_err(mac))
712 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
713 ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno));
715 printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n",
716 macrx, *chan->status);
718 printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
722 static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac,
726 struct pasemi_dmachan *chan = &tx_ring(mac)->chan;
728 if (!netif_msg_tx_err(mac))
731 cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno));
733 printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\
734 "tx status 0x%016lx\n", mactx, *chan->status);
736 printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
739 static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx,
742 const struct pasemi_dmachan *chan = &rx->chan;
743 struct pasemi_mac *mac = rx->mac;
744 struct pci_dev *pdev = mac->dma_pdev;
746 int count, buf_index, tot_bytes, packets;
747 struct pasemi_mac_buffer *info;
756 spin_lock(&rx->lock);
758 n = rx->next_to_clean;
760 prefetch(&RX_DESC(rx, n));
762 for (count = 0; count < limit; count++) {
763 macrx = RX_DESC(rx, n);
764 prefetch(&RX_DESC(rx, n+4));
766 if ((macrx & XCT_MACRX_E) ||
767 (*chan->status & PAS_STATUS_ERROR))
768 pasemi_mac_rx_error(mac, macrx);
770 if (!(macrx & XCT_MACRX_O))
775 BUG_ON(!(macrx & XCT_MACRX_RR_8BRES));
777 eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >>
781 dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M);
782 info = &RX_DESC_INFO(rx, buf_index);
788 len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
790 pci_unmap_single(pdev, dma, mac->bufsz - LOCAL_SKB_ALIGN,
793 if (macrx & XCT_MACRX_CRC) {
794 /* CRC error flagged */
795 mac->netdev->stats.rx_errors++;
796 mac->netdev->stats.rx_crc_errors++;
797 /* No need to free skb, it'll be reused */
804 if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
805 skb->ip_summed = CHECKSUM_UNNECESSARY;
806 skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
809 skb->ip_summed = CHECKSUM_NONE;
814 /* Don't include CRC */
817 skb->protocol = eth_type_trans(skb, mac->netdev);
818 lro_receive_skb(&mac->lro_mgr, skb, (void *)macrx);
822 RX_DESC(rx, n+1) = 0;
824 /* Need to zero it out since hardware doesn't, since the
825 * replenish loop uses it to tell when it's done.
827 RX_BUFF(rx, buf_index) = 0;
832 if (n > RX_RING_SIZE) {
833 /* Errata 5971 workaround: L2 target of headers */
834 write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0);
835 n &= (RX_RING_SIZE-1);
838 rx_ring(mac)->next_to_clean = n;
840 lro_flush_all(&mac->lro_mgr);
842 /* Increase is in number of 16-byte entries, and since each descriptor
843 * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with
846 write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1);
848 pasemi_mac_replenish_rx_ring(mac->netdev, count);
850 mac->netdev->stats.rx_bytes += tot_bytes;
851 mac->netdev->stats.rx_packets += packets;
853 spin_unlock(&rx_ring(mac)->lock);
858 /* Can't make this too large or we blow the kernel stack limits */
859 #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
861 static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring)
863 struct pasemi_dmachan *chan = &txring->chan;
864 struct pasemi_mac *mac = txring->mac;
866 unsigned int start, descr_count, buf_count, batch_limit;
867 unsigned int ring_limit;
868 unsigned int total_count;
870 struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
871 dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
872 int nf[TX_CLEAN_BATCHSIZE];
876 batch_limit = TX_CLEAN_BATCHSIZE;
878 spin_lock_irqsave(&txring->lock, flags);
880 start = txring->next_to_clean;
881 ring_limit = txring->next_to_fill;
883 prefetch(&TX_DESC_INFO(txring, start+1).skb);
885 /* Compensate for when fill has wrapped but clean has not */
886 if (start > ring_limit)
887 ring_limit += TX_RING_SIZE;
893 descr_count < batch_limit && i < ring_limit;
895 u64 mactx = TX_DESC(txring, i);
898 if ((mactx & XCT_MACTX_E) ||
899 (*chan->status & PAS_STATUS_ERROR))
900 pasemi_mac_tx_error(mac, mactx);
902 /* Skip over control descriptors */
903 if (!(mactx & XCT_MACTX_LLEN_M)) {
904 TX_DESC(txring, i) = 0;
905 TX_DESC(txring, i+1) = 0;
910 skb = TX_DESC_INFO(txring, i+1).skb;
911 nr_frags = TX_DESC_INFO(txring, i).dma;
913 if (unlikely(mactx & XCT_MACTX_O))
914 /* Not yet transmitted */
917 buf_count = 2 + nr_frags;
918 /* Since we always fill with an even number of entries, make
919 * sure we skip any unused one at the end as well.
924 for (j = 0; j <= nr_frags; j++)
925 dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma;
927 skbs[descr_count] = skb;
928 nf[descr_count] = nr_frags;
930 TX_DESC(txring, i) = 0;
931 TX_DESC(txring, i+1) = 0;
935 txring->next_to_clean = i & (TX_RING_SIZE-1);
937 spin_unlock_irqrestore(&txring->lock, flags);
938 netif_wake_queue(mac->netdev);
940 for (i = 0; i < descr_count; i++)
941 pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]);
943 total_count += descr_count;
945 /* If the batch was full, try to clean more */
946 if (descr_count == batch_limit)
953 static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
955 const struct pasemi_mac_rxring *rxring = data;
956 struct pasemi_mac *mac = rxring->mac;
957 struct net_device *dev = mac->netdev;
958 const struct pasemi_dmachan *chan = &rxring->chan;
961 if (!(*chan->status & PAS_STATUS_CAUSE_M))
964 /* Don't reset packet count so it won't fire again but clear
969 if (*chan->status & PAS_STATUS_SOFT)
970 reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
971 if (*chan->status & PAS_STATUS_ERROR)
972 reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
974 netif_rx_schedule(&mac->napi);
976 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg);
981 #define TX_CLEAN_INTERVAL HZ
983 static void pasemi_mac_tx_timer(unsigned long data)
985 struct pasemi_mac_txring *txring = (struct pasemi_mac_txring *)data;
986 struct pasemi_mac *mac = txring->mac;
988 pasemi_mac_clean_tx(txring);
990 mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL);
992 pasemi_mac_restart_tx_intr(mac);
995 static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
997 struct pasemi_mac_txring *txring = data;
998 const struct pasemi_dmachan *chan = &txring->chan;
999 struct pasemi_mac *mac = txring->mac;
1002 if (!(*chan->status & PAS_STATUS_CAUSE_M))
1007 if (*chan->status & PAS_STATUS_SOFT)
1008 reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
1009 if (*chan->status & PAS_STATUS_ERROR)
1010 reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
1012 mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2);
1014 netif_rx_schedule(&mac->napi);
1017 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg);
1022 static void pasemi_adjust_link(struct net_device *dev)
1024 struct pasemi_mac *mac = netdev_priv(dev);
1027 unsigned int new_flags;
1029 if (!mac->phydev->link) {
1030 /* If no link, MAC speed settings don't matter. Just report
1031 * link down and return.
1033 if (mac->link && netif_msg_link(mac))
1034 printk(KERN_INFO "%s: Link is down.\n", dev->name);
1036 netif_carrier_off(dev);
1037 pasemi_mac_intf_disable(mac);
1042 pasemi_mac_intf_enable(mac);
1043 netif_carrier_on(dev);
1046 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
1047 new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
1048 PAS_MAC_CFG_PCFG_TSR_M);
1050 if (!mac->phydev->duplex)
1051 new_flags |= PAS_MAC_CFG_PCFG_HD;
1053 switch (mac->phydev->speed) {
1055 new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
1056 PAS_MAC_CFG_PCFG_TSR_1G;
1059 new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
1060 PAS_MAC_CFG_PCFG_TSR_100M;
1063 new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
1064 PAS_MAC_CFG_PCFG_TSR_10M;
1067 printk("Unsupported speed %d\n", mac->phydev->speed);
1070 /* Print on link or speed/duplex change */
1071 msg = mac->link != mac->phydev->link || flags != new_flags;
1073 mac->duplex = mac->phydev->duplex;
1074 mac->speed = mac->phydev->speed;
1075 mac->link = mac->phydev->link;
1077 if (new_flags != flags)
1078 write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
1080 if (msg && netif_msg_link(mac))
1081 printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
1082 dev->name, mac->speed, mac->duplex ? "full" : "half");
1085 static int pasemi_mac_phy_init(struct net_device *dev)
1087 struct pasemi_mac *mac = netdev_priv(dev);
1088 struct device_node *dn, *phy_dn;
1089 struct phy_device *phydev;
1090 unsigned int phy_id;
1092 const unsigned int *prop;
1096 dn = pci_device_to_OF_node(mac->pdev);
1097 ph = of_get_property(dn, "phy-handle", NULL);
1100 phy_dn = of_find_node_by_phandle(*ph);
1102 prop = of_get_property(phy_dn, "reg", NULL);
1103 ret = of_address_to_resource(phy_dn->parent, 0, &r);
1108 snprintf(mac->phy_id, sizeof(mac->phy_id), "%x:%02x",
1109 (int)r.start, phy_id);
1111 of_node_put(phy_dn);
1117 phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII);
1119 if (IS_ERR(phydev)) {
1120 printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
1121 return PTR_ERR(phydev);
1124 mac->phydev = phydev;
1129 of_node_put(phy_dn);
1134 static int pasemi_mac_open(struct net_device *dev)
1136 struct pasemi_mac *mac = netdev_priv(dev);
1140 flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
1141 PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
1142 PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
1144 write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
1146 ret = pasemi_mac_setup_rx_resources(dev);
1148 goto out_rx_resources;
1150 mac->tx = pasemi_mac_setup_tx_resources(dev);
1155 /* We might already have allocated rings in case mtu was changed
1156 * before interface was brought up.
1158 if (dev->mtu > 1500 && !mac->num_cs) {
1159 pasemi_mac_setup_csrings(mac);
1164 /* Zero out rmon counters */
1165 for (i = 0; i < 32; i++)
1166 write_mac_reg(mac, PAS_MAC_RMON(i), 0);
1168 /* 0x3ff with 33MHz clock is about 31us */
1169 write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG,
1170 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff));
1172 write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno),
1173 PAS_IOB_DMA_RXCH_CFG_CNTTH(256));
1175 write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno),
1176 PAS_IOB_DMA_TXCH_CFG_CNTTH(32));
1178 write_mac_reg(mac, PAS_MAC_IPC_CHNL,
1179 PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) |
1180 PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno));
1183 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1184 PAS_DMA_RXINT_RCMDSTA_EN |
1185 PAS_DMA_RXINT_RCMDSTA_DROPS_M |
1186 PAS_DMA_RXINT_RCMDSTA_BP |
1187 PAS_DMA_RXINT_RCMDSTA_OO |
1188 PAS_DMA_RXINT_RCMDSTA_BT);
1190 /* enable rx channel */
1191 pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU |
1192 PAS_DMA_RXCHAN_CCMDSTA_OD |
1193 PAS_DMA_RXCHAN_CCMDSTA_FD |
1194 PAS_DMA_RXCHAN_CCMDSTA_DT);
1196 /* enable tx channel */
1197 pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
1198 PAS_DMA_TXCHAN_TCMDSTA_DB |
1199 PAS_DMA_TXCHAN_TCMDSTA_DE |
1200 PAS_DMA_TXCHAN_TCMDSTA_DA);
1202 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
1204 write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno),
1207 /* Clear out any residual packet count state from firmware */
1208 pasemi_mac_restart_rx_intr(mac);
1209 pasemi_mac_restart_tx_intr(mac);
1211 flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
1213 if (mac->type == MAC_TYPE_GMAC)
1214 flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
1216 flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
1218 /* Enable interface in MAC */
1219 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
1221 ret = pasemi_mac_phy_init(dev);
1223 /* Since we won't get link notification, just enable RX */
1224 pasemi_mac_intf_enable(mac);
1225 if (mac->type == MAC_TYPE_GMAC) {
1226 /* Warn for missing PHY on SGMII (1Gig) ports */
1227 dev_warn(&mac->pdev->dev,
1228 "PHY init failed: %d.\n", ret);
1229 dev_warn(&mac->pdev->dev,
1230 "Defaulting to 1Gbit full duplex\n");
1234 netif_start_queue(dev);
1235 napi_enable(&mac->napi);
1237 snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx",
1240 ret = request_irq(mac->tx->chan.irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
1241 mac->tx_irq_name, mac->tx);
1243 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
1244 mac->tx->chan.irq, ret);
1248 snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx",
1251 ret = request_irq(mac->rx->chan.irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
1252 mac->rx_irq_name, mac->rx);
1254 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
1255 mac->rx->chan.irq, ret);
1260 phy_start(mac->phydev);
1262 init_timer(&mac->tx->clean_timer);
1263 mac->tx->clean_timer.function = pasemi_mac_tx_timer;
1264 mac->tx->clean_timer.data = (unsigned long)mac->tx;
1265 mac->tx->clean_timer.expires = jiffies+HZ;
1266 add_timer(&mac->tx->clean_timer);
1271 free_irq(mac->tx->chan.irq, mac->tx);
1273 napi_disable(&mac->napi);
1274 netif_stop_queue(dev);
1277 pasemi_mac_free_tx_resources(mac);
1278 pasemi_mac_free_rx_resources(mac);
1284 #define MAX_RETRIES 5000
1286 static void pasemi_mac_pause_txchan(struct pasemi_mac *mac)
1288 unsigned int sta, retries;
1289 int txch = tx_ring(mac)->chan.chno;
1291 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch),
1292 PAS_DMA_TXCHAN_TCMDSTA_ST);
1294 for (retries = 0; retries < MAX_RETRIES; retries++) {
1295 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
1296 if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT))
1301 if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)
1302 dev_err(&mac->dma_pdev->dev,
1303 "Failed to stop tx channel, tcmdsta %08x\n", sta);
1305 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0);
1308 static void pasemi_mac_pause_rxchan(struct pasemi_mac *mac)
1310 unsigned int sta, retries;
1311 int rxch = rx_ring(mac)->chan.chno;
1313 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch),
1314 PAS_DMA_RXCHAN_CCMDSTA_ST);
1315 for (retries = 0; retries < MAX_RETRIES; retries++) {
1316 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
1317 if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT))
1322 if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)
1323 dev_err(&mac->dma_pdev->dev,
1324 "Failed to stop rx channel, ccmdsta 08%x\n", sta);
1325 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0);
1328 static void pasemi_mac_pause_rxint(struct pasemi_mac *mac)
1330 unsigned int sta, retries;
1332 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1333 PAS_DMA_RXINT_RCMDSTA_ST);
1334 for (retries = 0; retries < MAX_RETRIES; retries++) {
1335 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1336 if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT))
1341 if (sta & PAS_DMA_RXINT_RCMDSTA_ACT)
1342 dev_err(&mac->dma_pdev->dev,
1343 "Failed to stop rx interface, rcmdsta %08x\n", sta);
1344 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
1347 static int pasemi_mac_close(struct net_device *dev)
1349 struct pasemi_mac *mac = netdev_priv(dev);
1353 rxch = rx_ring(mac)->chan.chno;
1354 txch = tx_ring(mac)->chan.chno;
1357 phy_stop(mac->phydev);
1358 phy_disconnect(mac->phydev);
1361 del_timer_sync(&mac->tx->clean_timer);
1363 netif_stop_queue(dev);
1364 napi_disable(&mac->napi);
1366 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1367 if (sta & (PAS_DMA_RXINT_RCMDSTA_BP |
1368 PAS_DMA_RXINT_RCMDSTA_OO |
1369 PAS_DMA_RXINT_RCMDSTA_BT))
1370 printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta);
1372 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
1373 if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU |
1374 PAS_DMA_RXCHAN_CCMDSTA_OD |
1375 PAS_DMA_RXCHAN_CCMDSTA_FD |
1376 PAS_DMA_RXCHAN_CCMDSTA_DT))
1377 printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta);
1379 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
1380 if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB |
1381 PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA))
1382 printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta);
1384 /* Clean out any pending buffers */
1385 pasemi_mac_clean_tx(tx_ring(mac));
1386 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
1388 pasemi_mac_pause_txchan(mac);
1389 pasemi_mac_pause_rxint(mac);
1390 pasemi_mac_pause_rxchan(mac);
1391 pasemi_mac_intf_disable(mac);
1393 free_irq(mac->tx->chan.irq, mac->tx);
1394 free_irq(mac->rx->chan.irq, mac->rx);
1396 for (i = 0; i < mac->num_cs; i++) {
1397 pasemi_mac_free_csring(mac->cs[i]);
1403 /* Free resources */
1404 pasemi_mac_free_rx_resources(mac);
1405 pasemi_mac_free_tx_resources(mac);
1410 static void pasemi_mac_queue_csdesc(const struct sk_buff *skb,
1411 const dma_addr_t *map,
1412 const unsigned int *map_size,
1413 struct pasemi_mac_txring *txring,
1414 struct pasemi_mac_csring *csring)
1418 const int nh_off = skb_network_offset(skb);
1419 const int nh_len = skb_network_header_len(skb);
1420 const int nfrags = skb_shinfo(skb)->nr_frags;
1421 int cs_size, i, fill, hdr, cpyhdr, evt;
1424 fund = XCT_FUN_ST | XCT_FUN_RR_8BRES |
1425 XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
1426 XCT_FUN_CRM_SIG | XCT_FUN_LLEN(skb->len - nh_off) |
1427 XCT_FUN_SHL(nh_len >> 2) | XCT_FUN_SE;
1429 switch (ip_hdr(skb)->protocol) {
1431 fund |= XCT_FUN_SIG_TCP4;
1432 /* TCP checksum is 16 bytes into the header */
1433 cs_dest = map[0] + skb_transport_offset(skb) + 16;
1436 fund |= XCT_FUN_SIG_UDP4;
1437 /* UDP checksum is 6 bytes into the header */
1438 cs_dest = map[0] + skb_transport_offset(skb) + 6;
1444 /* Do the checksum offloaded */
1445 fill = csring->next_to_fill;
1448 CS_DESC(csring, fill++) = fund;
1449 /* Room for 8BRES. Checksum result is really 2 bytes into it */
1450 csdma = csring->chan.ring_dma + (fill & (CS_RING_SIZE-1)) * 8 + 2;
1451 CS_DESC(csring, fill++) = 0;
1453 CS_DESC(csring, fill) = XCT_PTR_LEN(map_size[0]-nh_off) | XCT_PTR_ADDR(map[0]+nh_off);
1454 for (i = 1; i <= nfrags; i++)
1455 CS_DESC(csring, fill+i) = XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
1461 /* Copy the result into the TCP packet */
1463 CS_DESC(csring, fill++) = XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
1464 XCT_FUN_LLEN(2) | XCT_FUN_SE;
1465 CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(cs_dest) | XCT_PTR_T;
1466 CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(csdma);
1469 evt = !csring->last_event;
1470 csring->last_event = evt;
1472 /* Event handshaking with MAC TX */
1473 CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1474 CTRL_CMD_ETYPE_SET | CTRL_CMD_REG(csring->events[evt]);
1475 CS_DESC(csring, fill++) = 0;
1476 CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1477 CTRL_CMD_ETYPE_WCLR | CTRL_CMD_REG(csring->events[!evt]);
1478 CS_DESC(csring, fill++) = 0;
1479 csring->next_to_fill = fill & (CS_RING_SIZE-1);
1481 cs_size = fill - hdr;
1482 write_dma_reg(PAS_DMA_TXCHAN_INCR(csring->chan.chno), (cs_size) >> 1);
1484 /* TX-side event handshaking */
1485 fill = txring->next_to_fill;
1486 TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1487 CTRL_CMD_ETYPE_WSET | CTRL_CMD_REG(csring->events[evt]);
1488 TX_DESC(txring, fill++) = 0;
1489 TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1490 CTRL_CMD_ETYPE_CLR | CTRL_CMD_REG(csring->events[!evt]);
1491 TX_DESC(txring, fill++) = 0;
1492 txring->next_to_fill = fill;
1494 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2);
1499 static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
1501 struct pasemi_mac * const mac = netdev_priv(dev);
1502 struct pasemi_mac_txring * const txring = tx_ring(mac);
1503 struct pasemi_mac_csring *csring;
1506 dma_addr_t map[MAX_SKB_FRAGS+1];
1507 unsigned int map_size[MAX_SKB_FRAGS+1];
1508 unsigned long flags;
1511 const int nh_off = skb_network_offset(skb);
1512 const int nh_len = skb_network_header_len(skb);
1514 prefetch(&txring->ring_info);
1516 dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
1518 nfrags = skb_shinfo(skb)->nr_frags;
1520 map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
1522 map_size[0] = skb_headlen(skb);
1523 if (pci_dma_mapping_error(mac->dma_pdev, map[0]))
1524 goto out_err_nolock;
1526 for (i = 0; i < nfrags; i++) {
1527 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1529 map[i+1] = pci_map_page(mac->dma_pdev, frag->page,
1530 frag->page_offset, frag->size,
1532 map_size[i+1] = frag->size;
1533 if (pci_dma_mapping_error(mac->dma_pdev, map[i+1])) {
1535 goto out_err_nolock;
1539 if (skb->ip_summed == CHECKSUM_PARTIAL && skb->len <= 1540) {
1540 switch (ip_hdr(skb)->protocol) {
1542 dflags |= XCT_MACTX_CSUM_TCP;
1543 dflags |= XCT_MACTX_IPH(nh_len >> 2);
1544 dflags |= XCT_MACTX_IPO(nh_off);
1547 dflags |= XCT_MACTX_CSUM_UDP;
1548 dflags |= XCT_MACTX_IPH(nh_len >> 2);
1549 dflags |= XCT_MACTX_IPO(nh_off);
1556 mactx = dflags | XCT_MACTX_LLEN(skb->len);
1558 spin_lock_irqsave(&txring->lock, flags);
1560 /* Avoid stepping on the same cache line that the DMA controller
1561 * is currently about to send, so leave at least 8 words available.
1562 * Total free space needed is mactx + fragments + 8
1564 if (RING_AVAIL(txring) < nfrags + 14) {
1565 /* no room -- stop the queue and wait for tx intr */
1566 netif_stop_queue(dev);
1570 /* Queue up checksum + event descriptors, if needed */
1571 if (mac->num_cs && skb->ip_summed == CHECKSUM_PARTIAL && skb->len > 1540) {
1572 csring = mac->cs[mac->last_cs];
1573 mac->last_cs = (mac->last_cs + 1) % mac->num_cs;
1575 pasemi_mac_queue_csdesc(skb, map, map_size, txring, csring);
1578 fill = txring->next_to_fill;
1579 TX_DESC(txring, fill) = mactx;
1580 TX_DESC_INFO(txring, fill).dma = nfrags;
1582 TX_DESC_INFO(txring, fill).skb = skb;
1583 for (i = 0; i <= nfrags; i++) {
1584 TX_DESC(txring, fill+i) =
1585 XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
1586 TX_DESC_INFO(txring, fill+i).dma = map[i];
1589 /* We have to add an even number of 8-byte entries to the ring
1590 * even if the last one is unused. That means always an odd number
1591 * of pointers + one mactx descriptor.
1596 txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1);
1598 dev->stats.tx_packets++;
1599 dev->stats.tx_bytes += skb->len;
1601 spin_unlock_irqrestore(&txring->lock, flags);
1603 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1);
1605 return NETDEV_TX_OK;
1608 spin_unlock_irqrestore(&txring->lock, flags);
1611 pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags],
1614 return NETDEV_TX_BUSY;
1617 static void pasemi_mac_set_rx_mode(struct net_device *dev)
1619 const struct pasemi_mac *mac = netdev_priv(dev);
1622 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
1624 /* Set promiscuous */
1625 if (dev->flags & IFF_PROMISC)
1626 flags |= PAS_MAC_CFG_PCFG_PR;
1628 flags &= ~PAS_MAC_CFG_PCFG_PR;
1630 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
1634 static int pasemi_mac_poll(struct napi_struct *napi, int budget)
1636 struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
1637 struct net_device *dev = mac->netdev;
1640 pasemi_mac_clean_tx(tx_ring(mac));
1641 pkts = pasemi_mac_clean_rx(rx_ring(mac), budget);
1642 if (pkts < budget) {
1643 /* all done, no more packets present */
1644 netif_rx_complete(napi);
1646 pasemi_mac_restart_rx_intr(mac);
1647 pasemi_mac_restart_tx_intr(mac);
1652 #ifdef CONFIG_NET_POLL_CONTROLLER
1654 * Polling 'interrupt' - used by things like netconsole to send skbs
1655 * without having to re-enable interrupts. It's not called while
1656 * the interrupt routine is executing.
1658 static void pasemi_mac_netpoll(struct net_device *dev)
1660 const struct pasemi_mac *mac = netdev_priv(dev);
1662 disable_irq(mac->tx->chan.irq);
1663 pasemi_mac_tx_intr(mac->tx->chan.irq, mac->tx);
1664 enable_irq(mac->tx->chan.irq);
1666 disable_irq(mac->rx->chan.irq);
1667 pasemi_mac_rx_intr(mac->rx->chan.irq, mac->rx);
1668 enable_irq(mac->rx->chan.irq);
1672 static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu)
1674 struct pasemi_mac *mac = netdev_priv(dev);
1676 unsigned int rcmdsta = 0;
1680 if (new_mtu < PE_MIN_MTU || new_mtu > PE_MAX_MTU)
1683 running = netif_running(dev);
1686 /* Need to stop the interface, clean out all already
1687 * received buffers, free all unused buffers on the RX
1688 * interface ring, then finally re-fill the rx ring with
1689 * the new-size buffers and restart.
1692 napi_disable(&mac->napi);
1693 netif_tx_disable(dev);
1694 pasemi_mac_intf_disable(mac);
1696 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1697 pasemi_mac_pause_rxint(mac);
1698 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
1699 pasemi_mac_free_rx_buffers(mac);
1703 /* Setup checksum channels if large MTU and none already allocated */
1704 if (new_mtu > 1500 && !mac->num_cs) {
1705 pasemi_mac_setup_csrings(mac);
1712 /* Change maxf, i.e. what size frames are accepted.
1713 * Need room for ethernet header and CRC word
1715 reg = read_mac_reg(mac, PAS_MAC_CFG_MACCFG);
1716 reg &= ~PAS_MAC_CFG_MACCFG_MAXF_M;
1717 reg |= PAS_MAC_CFG_MACCFG_MAXF(new_mtu + ETH_HLEN + 4);
1718 write_mac_reg(mac, PAS_MAC_CFG_MACCFG, reg);
1721 /* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
1722 mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
1726 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1727 rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN);
1729 rx_ring(mac)->next_to_fill = 0;
1730 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE-1);
1732 napi_enable(&mac->napi);
1733 netif_start_queue(dev);
1734 pasemi_mac_intf_enable(mac);
1740 static int __devinit
1741 pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1743 struct net_device *dev;
1744 struct pasemi_mac *mac;
1747 err = pci_enable_device(pdev);
1751 dev = alloc_etherdev(sizeof(struct pasemi_mac));
1754 "pasemi_mac: Could not allocate ethernet device.\n");
1756 goto out_disable_device;
1759 pci_set_drvdata(pdev, dev);
1760 SET_NETDEV_DEV(dev, &pdev->dev);
1762 mac = netdev_priv(dev);
1767 netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
1769 dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG |
1770 NETIF_F_HIGHDMA | NETIF_F_GSO;
1772 mac->lro_mgr.max_aggr = LRO_MAX_AGGR;
1773 mac->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1774 mac->lro_mgr.lro_arr = mac->lro_desc;
1775 mac->lro_mgr.get_skb_header = get_skb_hdr;
1776 mac->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1777 mac->lro_mgr.dev = mac->netdev;
1778 mac->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1779 mac->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1782 mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
1783 if (!mac->dma_pdev) {
1784 dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
1789 mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
1790 if (!mac->iob_pdev) {
1791 dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
1796 /* get mac addr from device tree */
1797 if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
1801 memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
1803 mac->dma_if = mac_to_intf(mac);
1804 if (mac->dma_if < 0) {
1805 dev_err(&mac->pdev->dev, "Can't map DMA interface\n");
1810 switch (pdev->device) {
1812 mac->type = MAC_TYPE_GMAC;
1815 mac->type = MAC_TYPE_XAUI;
1822 dev->open = pasemi_mac_open;
1823 dev->stop = pasemi_mac_close;
1824 dev->hard_start_xmit = pasemi_mac_start_tx;
1825 dev->set_multicast_list = pasemi_mac_set_rx_mode;
1826 dev->set_mac_address = pasemi_mac_set_mac_addr;
1827 dev->mtu = PE_DEF_MTU;
1828 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
1829 mac->bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
1830 #ifdef CONFIG_NET_POLL_CONTROLLER
1831 dev->poll_controller = pasemi_mac_netpoll;
1834 dev->change_mtu = pasemi_mac_change_mtu;
1835 dev->ethtool_ops = &pasemi_mac_ethtool_ops;
1840 mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1842 /* Enable most messages by default */
1843 mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1845 err = register_netdev(dev);
1848 dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
1851 } else if netif_msg_probe(mac)
1852 printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %pM\n",
1853 dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
1854 mac->dma_if, dev->dev_addr);
1860 pci_dev_put(mac->iob_pdev);
1862 pci_dev_put(mac->dma_pdev);
1866 pci_disable_device(pdev);
1871 static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
1873 struct net_device *netdev = pci_get_drvdata(pdev);
1874 struct pasemi_mac *mac;
1879 mac = netdev_priv(netdev);
1881 unregister_netdev(netdev);
1883 pci_disable_device(pdev);
1884 pci_dev_put(mac->dma_pdev);
1885 pci_dev_put(mac->iob_pdev);
1887 pasemi_dma_free_chan(&mac->tx->chan);
1888 pasemi_dma_free_chan(&mac->rx->chan);
1890 pci_set_drvdata(pdev, NULL);
1891 free_netdev(netdev);
1894 static struct pci_device_id pasemi_mac_pci_tbl[] = {
1895 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
1896 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
1900 MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
1902 static struct pci_driver pasemi_mac_driver = {
1903 .name = "pasemi_mac",
1904 .id_table = pasemi_mac_pci_tbl,
1905 .probe = pasemi_mac_probe,
1906 .remove = __devexit_p(pasemi_mac_remove),
1909 static void __exit pasemi_mac_cleanup_module(void)
1911 pci_unregister_driver(&pasemi_mac_driver);
1914 int pasemi_mac_init_module(void)
1918 err = pasemi_dma_init();
1922 return pci_register_driver(&pasemi_mac_driver);
1925 module_init(pasemi_mac_init_module);
1926 module_exit(pasemi_mac_cleanup_module);