[PATCH] Fbdev driver for IBM GXT4500P videocards
[linux-2.6] / drivers / video / gxt4500.c
1 /*
2  * Frame buffer device for IBM GXT4500P display adaptor
3  *
4  * Copyright (C) 2006 Paul Mackerras, IBM Corp. <paulus@samba.org>
5  */
6
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/fb.h>
10 #include <linux/console.h>
11 #include <linux/pci.h>
12 #include <linux/pci_ids.h>
13 #include <linux/delay.h>
14
15 #define PCI_DEVICE_ID_IBM_GXT4500P      0x21c
16
17 /* GXT4500P registers */
18
19 /* Registers in PCI config space */
20 #define CFG_ENDIAN0             0x40
21
22 /* Misc control/status registers */
23 #define STATUS                  0x1000
24 #define CTRL_REG0               0x1004
25 #define   CR0_HALT_DMA                  0x4
26 #define   CR0_RASTER_RESET              0x8
27 #define   CR0_GEOM_RESET                0x10
28 #define   CR0_MEM_CTRLER_RESET          0x20
29
30 /* Framebuffer control registers */
31 #define FB_AB_CTRL              0x1100
32 #define FB_CD_CTRL              0x1104
33 #define FB_WID_CTRL             0x1108
34 #define FB_Z_CTRL               0x110c
35 #define FB_VGA_CTRL             0x1110
36 #define REFRESH_AB_CTRL         0x1114
37 #define REFRESH_CD_CTRL         0x1118
38 #define FB_OVL_CTRL             0x111c
39 #define   FB_CTRL_TYPE                  0x80000000
40 #define   FB_CTRL_WIDTH_MASK            0x007f0000
41 #define   FB_CTRL_WIDTH_SHIFT           16
42 #define   FB_CTRL_START_SEG_MASK        0x00003fff
43
44 #define REFRESH_START           0x1098
45 #define REFRESH_SIZE            0x109c
46
47 /* "Direct" framebuffer access registers */
48 #define DFA_FB_A                0x11e0
49 #define DFA_FB_B                0x11e4
50 #define DFA_FB_C                0x11e8
51 #define DFA_FB_D                0x11ec
52 #define   DFA_FB_ENABLE                 0x80000000
53 #define   DFA_FB_BASE_MASK              0x03f00000
54 #define   DFA_FB_STRIDE_1k              0x00000000
55 #define   DFA_FB_STRIDE_2k              0x00000010
56 #define   DFA_FB_STRIDE_4k              0x00000020
57 #define   DFA_PIX_8BIT                  0x00000000
58 #define   DFA_PIX_16BIT_565             0x00000001
59 #define   DFA_PIX_16BIT_1555            0x00000002
60 #define   DFA_PIX_24BIT                 0x00000004
61 #define   DFA_PIX_32BIT                 0x00000005
62
63 /* maps DFA_PIX_* to pixel size in bytes */
64 static const unsigned char pixsize[] = {
65         1, 2, 2, 2, 4, 4
66 };
67
68 /* Display timing generator registers */
69 #define DTG_CONTROL             0x1900
70 #define   DTG_CTL_SCREEN_REFRESH        2
71 #define   DTG_CTL_ENABLE                1
72 #define DTG_HORIZ_EXTENT        0x1904
73 #define DTG_HORIZ_DISPLAY       0x1908
74 #define DTG_HSYNC_START         0x190c
75 #define DTG_HSYNC_END           0x1910
76 #define DTG_HSYNC_END_COMP      0x1914
77 #define DTG_VERT_EXTENT         0x1918
78 #define DTG_VERT_DISPLAY        0x191c
79 #define DTG_VSYNC_START         0x1920
80 #define DTG_VSYNC_END           0x1924
81 #define DTG_VERT_SHORT          0x1928
82
83 /* PLL/RAMDAC registers */
84 #define DISP_CTL                0x402c
85 #define   DISP_CTL_OFF                  2
86 #define SYNC_CTL                0x4034
87 #define   SYNC_CTL_SYNC_ON_RGB          1
88 #define   SYNC_CTL_SYNC_OFF             2
89 #define   SYNC_CTL_HSYNC_INV            8
90 #define   SYNC_CTL_VSYNC_INV            0x10
91 #define   SYNC_CTL_HSYNC_OFF            0x20
92 #define   SYNC_CTL_VSYNC_OFF            0x40
93
94 #define PLL_M                   0x4040
95 #define PLL_N                   0x4044
96 #define PLL_POSTDIV             0x4048
97
98 /* Hardware cursor */
99 #define CURSOR_X                0x4078
100 #define CURSOR_Y                0x407c
101 #define CURSOR_HOTSPOT          0x4080
102 #define CURSOR_MODE             0x4084
103 #define   CURSOR_MODE_OFF               0
104 #define   CURSOR_MODE_4BPP              1
105 #define CURSOR_PIXMAP           0x5000
106 #define CURSOR_CMAP             0x7400
107
108 /* Window attribute table */
109 #define WAT_FMT                 0x4100
110 #define   WAT_FMT_24BIT                 0
111 #define   WAT_FMT_16BIT_565             1
112 #define   WAT_FMT_16BIT_1555            2
113 #define   WAT_FMT_32BIT                 3       /* 0 vs. 3 is a guess */
114 #define   WAT_FMT_8BIT_332              9
115 #define   WAT_FMT_8BIT                  0xa
116 #define   WAT_FMT_NO_CMAP               4       /* ORd in to other values */
117 #define WAT_CMAP_OFFSET         0x4104          /* 4-bit value gets << 6 */
118 #define WAT_CTRL                0x4108
119 #define   WAT_CTRL_SEL_B                1       /* select B buffer if 1 */
120 #define   WAT_CTRL_NO_INC               2
121 #define WAT_GAMMA_CTRL          0x410c
122 #define   WAT_GAMMA_DISABLE             1       /* disables gamma cmap */
123 #define WAT_OVL_CTRL            0x430c          /* controls overlay */
124
125 /* Indexed by DFA_PIX_* values */
126 static const unsigned char watfmt[] = {
127         WAT_FMT_8BIT, WAT_FMT_16BIT_565, WAT_FMT_16BIT_1555, 0,
128         WAT_FMT_24BIT, WAT_FMT_32BIT
129 };
130
131 /* Colormap array; 1k entries of 4 bytes each */
132 #define CMAP                    0x6000
133
134 #define readreg(par, reg)       readl((par)->regs + (reg))
135 #define writereg(par, reg, val) writel((val), (par)->regs + (reg))
136
137 struct gxt4500_par {
138         void __iomem *regs;
139
140         int pixfmt;             /* pixel format, see DFA_PIX_* values */
141
142         /* PLL parameters */
143         int pll_m;              /* ref clock divisor */
144         int pll_n;              /* VCO divisor */
145         int pll_pd1;            /* first post-divisor */
146         int pll_pd2;            /* second post-divisor */
147
148         u32 pseudo_palette[16]; /* used in color blits */
149 };
150
151 /* mode requested by user */
152 static char *mode_option;
153
154 /* default mode: 1280x1024 @ 60 Hz, 8 bpp */
155 static const struct fb_videomode defaultmode __devinitdata = {
156         .refresh = 60,
157         .xres = 1280,
158         .yres = 1024,
159         .pixclock = 9295,
160         .left_margin = 248,
161         .right_margin = 48,
162         .upper_margin = 38,
163         .lower_margin = 1,
164         .hsync_len = 112,
165         .vsync_len = 3,
166         .vmode = FB_VMODE_NONINTERLACED
167 };
168
169 /*
170  * The refclk and VCO dividers appear to use a linear feedback shift
171  * register, which gets reloaded when it reaches a terminal value, at
172  * which point the divider output is toggled.  Thus one can obtain
173  * whatever divisor is required by putting the appropriate value into
174  * the reload register.  For a divisor of N, one puts the value from
175  * the LFSR sequence that comes N-1 places before the terminal value
176  * into the reload register.
177  */
178
179 static const unsigned char mdivtab[] = {
180 /* 1 */               0x3f, 0x00, 0x20, 0x10, 0x28, 0x14, 0x2a, 0x15, 0x0a,
181 /* 10 */        0x25, 0x32, 0x19, 0x0c, 0x26, 0x13, 0x09, 0x04, 0x22, 0x11,
182 /* 20 */        0x08, 0x24, 0x12, 0x29, 0x34, 0x1a, 0x2d, 0x36, 0x1b, 0x0d,
183 /* 30 */        0x06, 0x23, 0x31, 0x38, 0x1c, 0x2e, 0x17, 0x0b, 0x05, 0x02,
184 /* 40 */        0x21, 0x30, 0x18, 0x2c, 0x16, 0x2b, 0x35, 0x3a, 0x1d, 0x0e,
185 /* 50 */        0x27, 0x33, 0x39, 0x3c, 0x1e, 0x2f, 0x37, 0x3b, 0x3d, 0x3e,
186 /* 60 */        0x1f, 0x0f, 0x07, 0x03, 0x01,
187 };
188
189 static const unsigned char ndivtab[] = {
190 /* 2 */                     0x00, 0x80, 0xc0, 0xe0, 0xf0, 0x78, 0xbc, 0x5e,
191 /* 10 */        0x2f, 0x17, 0x0b, 0x85, 0xc2, 0xe1, 0x70, 0x38, 0x9c, 0x4e,
192 /* 20 */        0xa7, 0xd3, 0xe9, 0xf4, 0xfa, 0xfd, 0xfe, 0x7f, 0xbf, 0xdf,
193 /* 30 */        0xef, 0x77, 0x3b, 0x1d, 0x8e, 0xc7, 0xe3, 0x71, 0xb8, 0xdc,
194 /* 40 */        0x6e, 0xb7, 0x5b, 0x2d, 0x16, 0x8b, 0xc5, 0xe2, 0xf1, 0xf8,
195 /* 50 */        0xfc, 0x7e, 0x3f, 0x9f, 0xcf, 0x67, 0xb3, 0xd9, 0x6c, 0xb6,
196 /* 60 */        0xdb, 0x6d, 0x36, 0x9b, 0x4d, 0x26, 0x13, 0x89, 0xc4, 0x62,
197 /* 70 */        0xb1, 0xd8, 0xec, 0xf6, 0xfb, 0x7d, 0xbe, 0x5f, 0xaf, 0x57,
198 /* 80 */        0x2b, 0x95, 0x4a, 0x25, 0x92, 0x49, 0xa4, 0x52, 0x29, 0x94,
199 /* 90 */        0xca, 0x65, 0xb2, 0x59, 0x2c, 0x96, 0xcb, 0xe5, 0xf2, 0x79,
200 /* 100 */       0x3c, 0x1e, 0x0f, 0x07, 0x83, 0x41, 0x20, 0x90, 0x48, 0x24,
201 /* 110 */       0x12, 0x09, 0x84, 0x42, 0xa1, 0x50, 0x28, 0x14, 0x8a, 0x45,
202 /* 120 */       0xa2, 0xd1, 0xe8, 0x74, 0xba, 0xdd, 0xee, 0xf7, 0x7b, 0x3d,
203 /* 130 */       0x9e, 0x4f, 0x27, 0x93, 0xc9, 0xe4, 0x72, 0x39, 0x1c, 0x0e,
204 /* 140 */       0x87, 0xc3, 0x61, 0x30, 0x18, 0x8c, 0xc6, 0x63, 0x31, 0x98,
205 /* 150 */       0xcc, 0xe6, 0x73, 0xb9, 0x5c, 0x2e, 0x97, 0x4b, 0xa5, 0xd2,
206 /* 160 */       0x69, 0xb4, 0xda, 0xed, 0x76, 0xbb, 0x5d, 0xae, 0xd7, 0x6b,
207 /* 170 */       0xb5, 0x5a, 0xad, 0x56, 0xab, 0xd5, 0x6a, 0x35, 0x1a, 0x8d,
208 /* 180 */       0x46, 0x23, 0x11, 0x88, 0x44, 0x22, 0x91, 0xc8, 0x64, 0x32,
209 /* 190 */       0x19, 0x0c, 0x86, 0x43, 0x21, 0x10, 0x08, 0x04, 0x02, 0x81,
210 /* 200 */       0x40, 0xa0, 0xd0, 0x68, 0x34, 0x9a, 0xcd, 0x66, 0x33, 0x99,
211 /* 210 */       0x4c, 0xa6, 0x53, 0xa9, 0xd4, 0xea, 0x75, 0x3a, 0x9d, 0xce,
212 /* 220 */       0xe7, 0xf3, 0xf9, 0x7c, 0x3e, 0x1f, 0x8f, 0x47, 0xa3, 0x51,
213 /* 230 */       0xa8, 0x54, 0xaa, 0x55, 0x2a, 0x15, 0x0a, 0x05, 0x82, 0xc1,
214 /* 240 */       0x60, 0xb0, 0x58, 0xac, 0xd6, 0xeb, 0xf5, 0x7a, 0xbd, 0xde,
215 /* 250 */       0x6f, 0x37, 0x1b, 0x0d, 0x06, 0x03, 0x01,
216 };
217
218 #define REF_PERIOD_PS   9259    /* period of reference clock in ps */
219
220 static int calc_pll(int period_ps, struct gxt4500_par *par)
221 {
222         int m, n, pdiv1, pdiv2, postdiv;
223         int pll_period, best_error, t;
224
225         /* only deal with range 1MHz - 400MHz */
226         if (period_ps < 2500 || period_ps > 1000000)
227                 return -1;
228
229         best_error = 1000000;
230         for (pdiv1 = 1; pdiv1 <= 8; ++pdiv1) {
231                 for (pdiv2 = 1; pdiv2 <= pdiv1; ++pdiv2) {
232                         postdiv = pdiv1 * pdiv2;
233                         pll_period = (period_ps + postdiv - 1) / postdiv;
234                         /* keep pll in range 500..1250 MHz */
235                         if (pll_period < 800 || pll_period > 2000)
236                                 continue;
237                         for (m = 3; m <= 40; ++m) {
238                                 n = REF_PERIOD_PS * m * postdiv / period_ps;
239                                 if (n < 5 || n > 256)
240                                         continue;
241                                 t = REF_PERIOD_PS * m * postdiv / n;
242                                 t -= period_ps;
243                                 if (t >= 0 && t < best_error) {
244                                         par->pll_m = m;
245                                         par->pll_n = n;
246                                         par->pll_pd1 = pdiv1;
247                                         par->pll_pd2 = pdiv2;
248                                         best_error = t;
249                                 }
250                         }
251                 }
252         }
253         if (best_error == 1000000)
254                 return -1;
255         return 0;
256 }
257
258 static int calc_pixclock(struct gxt4500_par *par)
259 {
260         return REF_PERIOD_PS * par->pll_m * par->pll_pd1 * par->pll_pd2
261                 / par->pll_n;
262 }
263
264 static int gxt4500_var_to_par(struct fb_var_screeninfo *var,
265                               struct gxt4500_par *par)
266 {
267         if (var->xres + var->xoffset > var->xres_virtual ||
268             var->yres + var->yoffset > var->yres_virtual ||
269             var->xres_virtual > 4096)
270                 return -EINVAL;
271         if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
272                 return -EINVAL;
273
274         if (calc_pll(var->pixclock, par) < 0)
275                 return -EINVAL;
276
277         switch (var->bits_per_pixel) {
278         case 32:
279                 if (var->transp.length)
280                         par->pixfmt = DFA_PIX_32BIT;
281                 else
282                         par->pixfmt = DFA_PIX_24BIT;
283                 break;
284         case 24:
285                 par->pixfmt = DFA_PIX_24BIT;
286                 break;
287         case 16:
288                 if (var->green.length == 5)
289                         par->pixfmt = DFA_PIX_16BIT_1555;
290                 else
291                         par->pixfmt = DFA_PIX_16BIT_565;
292                 break;
293         case 8:
294                 par->pixfmt = DFA_PIX_8BIT;
295                 break;
296         default:
297                 return -EINVAL;
298         }
299
300         return 0;
301 }
302
303 static const struct fb_bitfield eightbits = {0, 8};
304 static const struct fb_bitfield nobits = {0, 0};
305
306 static void gxt4500_unpack_pixfmt(struct fb_var_screeninfo *var,
307                                   int pixfmt)
308 {
309         var->bits_per_pixel = pixsize[pixfmt] * 8;
310         var->red = eightbits;
311         var->green = eightbits;
312         var->blue = eightbits;
313         var->transp = nobits;
314
315         switch (pixfmt) {
316         case DFA_PIX_16BIT_565:
317                 var->red.length = 5;
318                 var->green.length = 6;
319                 var->blue.length = 5;
320                 break;
321         case DFA_PIX_16BIT_1555:
322                 var->red.length = 5;
323                 var->green.length = 5;
324                 var->blue.length = 5;
325                 var->transp.length = 1;
326                 break;
327         case DFA_PIX_32BIT:
328                 var->transp.length = 8;
329                 break;
330         }
331         if (pixfmt != DFA_PIX_8BIT) {
332                 var->green.offset = var->red.length;
333                 var->blue.offset = var->green.offset + var->green.length;
334                 if (var->transp.length)
335                         var->transp.offset =
336                                 var->blue.offset + var->blue.length;
337         }
338 }
339
340 static int gxt4500_check_var(struct fb_var_screeninfo *var,
341                              struct fb_info *info)
342 {
343         struct gxt4500_par par;
344         int err;
345
346         par = *(struct gxt4500_par *)info->par;
347         err = gxt4500_var_to_par(var, &par);
348         if (!err) {
349                 var->pixclock = calc_pixclock(&par);
350                 gxt4500_unpack_pixfmt(var, par.pixfmt);
351         }
352         return err;
353 }
354
355 static int gxt4500_set_par(struct fb_info *info)
356 {
357         struct gxt4500_par *par = info->par;
358         struct fb_var_screeninfo *var = &info->var;
359         int err;
360         u32 ctrlreg;
361         unsigned int dfa_ctl, pixfmt, stride;
362         unsigned int wid_tiles, i;
363         unsigned int prefetch_pix, htot;
364         struct gxt4500_par save_par;
365
366         save_par = *par;
367         err = gxt4500_var_to_par(var, par);
368         if (err) {
369                 *par = save_par;
370                 return err;
371         }
372
373         /* turn off DTG for now */
374         ctrlreg = readreg(par, DTG_CONTROL);
375         ctrlreg &= ~(DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH);
376         writereg(par, DTG_CONTROL, ctrlreg);
377
378         /* set PLL registers */
379         writereg(par, PLL_M, mdivtab[par->pll_m - 1]);
380         writereg(par, PLL_N, ndivtab[par->pll_n - 2]);
381         writereg(par, PLL_POSTDIV,
382                  ((8 - par->pll_pd1) << 3) | (8 - par->pll_pd2));
383         msleep(20);
384
385         /* turn off hardware cursor */
386         writereg(par, CURSOR_MODE, CURSOR_MODE_OFF);
387
388         /* reset raster engine */
389         writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16));
390         udelay(10);
391         writereg(par, CTRL_REG0, CR0_RASTER_RESET << 16);
392
393         /* set display timing generator registers */
394         htot = var->xres + var->left_margin + var->right_margin +
395                 var->hsync_len;
396         writereg(par, DTG_HORIZ_EXTENT, htot - 1);
397         writereg(par, DTG_HORIZ_DISPLAY, var->xres - 1);
398         writereg(par, DTG_HSYNC_START, var->xres + var->right_margin - 1);
399         writereg(par, DTG_HSYNC_END,
400                  var->xres + var->right_margin + var->hsync_len - 1);
401         writereg(par, DTG_HSYNC_END_COMP,
402                  var->xres + var->right_margin + var->hsync_len - 1);
403         writereg(par, DTG_VERT_EXTENT,
404                  var->yres + var->upper_margin + var->lower_margin +
405                  var->vsync_len - 1);
406         writereg(par, DTG_VERT_DISPLAY, var->yres - 1);
407         writereg(par, DTG_VSYNC_START, var->yres + var->lower_margin - 1);
408         writereg(par, DTG_VSYNC_END,
409                  var->yres + var->lower_margin + var->vsync_len - 1);
410         prefetch_pix = 3300000 / var->pixclock;
411         if (prefetch_pix >= htot)
412                 prefetch_pix = htot - 1;
413         writereg(par, DTG_VERT_SHORT, htot - prefetch_pix - 1);
414         ctrlreg |= DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH;
415         writereg(par, DTG_CONTROL, ctrlreg);
416
417         /* calculate stride in DFA aperture */
418         if (var->xres_virtual > 2048) {
419                 stride = 4096;
420                 dfa_ctl = DFA_FB_STRIDE_4k;
421         } else if (var->xres_virtual > 1024) {
422                 stride = 2048;
423                 dfa_ctl = DFA_FB_STRIDE_2k;
424         } else {
425                 stride = 1024;
426                 dfa_ctl = DFA_FB_STRIDE_1k;
427         }
428
429         /* Set up framebuffer definition */
430         wid_tiles = (var->xres_virtual + 63) >> 6;
431
432         /* XXX add proper FB allocation here someday */
433         writereg(par, FB_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
434         writereg(par, REFRESH_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
435         writereg(par, FB_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
436         writereg(par, REFRESH_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
437         writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
438         writereg(par, REFRESH_SIZE, (var->xres << 16) | var->yres);
439
440         /* Set up framebuffer access by CPU */
441
442         pixfmt = par->pixfmt;
443         dfa_ctl |= DFA_FB_ENABLE | pixfmt;
444         writereg(par, DFA_FB_A, dfa_ctl);
445
446         /*
447          * Set up window attribute table.
448          * We set all WAT entries the same so it doesn't matter what the
449          * window ID (WID) plane contains.
450          */
451         for (i = 0; i < 32; ++i) {
452                 writereg(par, WAT_FMT + (i << 4), watfmt[pixfmt]);
453                 writereg(par, WAT_CMAP_OFFSET + (i << 4), 0);
454                 writereg(par, WAT_CTRL + (i << 4), 0);
455                 writereg(par, WAT_GAMMA_CTRL + (i << 4), WAT_GAMMA_DISABLE);
456         }
457
458         /* Set sync polarity etc. */
459         ctrlreg = readreg(par, SYNC_CTL) &
460                 ~(SYNC_CTL_SYNC_ON_RGB | SYNC_CTL_HSYNC_INV |
461                   SYNC_CTL_VSYNC_INV);
462         if (var->sync & FB_SYNC_ON_GREEN)
463                 ctrlreg |= SYNC_CTL_SYNC_ON_RGB;
464         if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
465                 ctrlreg |= SYNC_CTL_HSYNC_INV;
466         if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
467                 ctrlreg |= SYNC_CTL_VSYNC_INV;
468         writereg(par, SYNC_CTL, ctrlreg);
469
470         info->fix.line_length = stride * pixsize[pixfmt];
471         info->fix.visual = (pixfmt == DFA_PIX_8BIT)? FB_VISUAL_PSEUDOCOLOR:
472                 FB_VISUAL_DIRECTCOLOR;
473
474         return 0;
475 }
476
477 static int gxt4500_setcolreg(unsigned int reg, unsigned int red,
478                              unsigned int green, unsigned int blue,
479                              unsigned int transp, struct fb_info *info)
480 {
481         u32 cmap_entry;
482         struct gxt4500_par *par = info->par;
483
484         if (reg > 1023)
485                 return 1;
486         cmap_entry = ((transp & 0xff00) << 16) | ((blue & 0xff00) << 8) |
487                 (green & 0xff00) | (red >> 8);
488         writereg(par, CMAP + reg * 4, cmap_entry);
489
490         if (reg < 16 && par->pixfmt != DFA_PIX_8BIT) {
491                 u32 *pal = info->pseudo_palette;
492                 u32 val = reg;
493                 switch (par->pixfmt) {
494                 case DFA_PIX_16BIT_565:
495                         val |= (reg << 11) | (reg << 6);
496                         break;
497                 case DFA_PIX_16BIT_1555:
498                         val |= (reg << 10) | (reg << 5);
499                         break;
500                 case DFA_PIX_32BIT:
501                         val |= (reg << 24);
502                         /* fall through */
503                 case DFA_PIX_24BIT:
504                         val |= (reg << 16) | (reg << 8);
505                         break;
506                 }
507                 pal[reg] = val;
508         }
509
510         return 0;
511 }
512
513 static int gxt4500_pan_display(struct fb_var_screeninfo *var,
514                                struct fb_info *info)
515 {
516         struct gxt4500_par *par = info->par;
517
518         if (var->xoffset & 7)
519                 return -EINVAL;
520         if (var->xoffset + var->xres > var->xres_virtual ||
521             var->yoffset + var->yres > var->yres_virtual)
522                 return -EINVAL;
523
524         writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
525         return 0;
526 }
527
528 static int gxt4500_blank(int blank, struct fb_info *info)
529 {
530         struct gxt4500_par *par = info->par;
531         int ctrl, dctl;
532
533         ctrl = readreg(par, SYNC_CTL);
534         ctrl &= ~(SYNC_CTL_SYNC_OFF | SYNC_CTL_HSYNC_OFF | SYNC_CTL_VSYNC_OFF);
535         dctl = readreg(par, DISP_CTL);
536         dctl |= DISP_CTL_OFF;
537         switch (blank) {
538         case FB_BLANK_UNBLANK:
539                 dctl &= ~DISP_CTL_OFF;
540                 break;
541         case FB_BLANK_POWERDOWN:
542                 ctrl |= SYNC_CTL_SYNC_OFF;
543                 break;
544         case FB_BLANK_HSYNC_SUSPEND:
545                 ctrl |= SYNC_CTL_HSYNC_OFF;
546                 break;
547         case FB_BLANK_VSYNC_SUSPEND:
548                 ctrl |= SYNC_CTL_VSYNC_OFF;
549                 break;
550         default: ;
551         }
552         writereg(par, SYNC_CTL, ctrl);
553         writereg(par, DISP_CTL, dctl);
554
555         return 0;
556 }
557
558 static const struct fb_fix_screeninfo gxt4500_fix __devinitdata = {
559         .id = "IBM GXT4500P",
560         .type = FB_TYPE_PACKED_PIXELS,
561         .visual = FB_VISUAL_PSEUDOCOLOR,
562         .xpanstep = 8,
563         .ypanstep = 1,
564         .mmio_len = 0x20000,
565 };
566
567 static struct fb_ops gxt4500_ops = {
568         .owner = THIS_MODULE,
569         .fb_check_var = gxt4500_check_var,
570         .fb_set_par = gxt4500_set_par,
571         .fb_setcolreg = gxt4500_setcolreg,
572         .fb_pan_display = gxt4500_pan_display,
573         .fb_blank = gxt4500_blank,
574         .fb_fillrect = cfb_fillrect,
575         .fb_copyarea = cfb_copyarea,
576         .fb_imageblit = cfb_imageblit,
577 };
578
579 /* PCI functions */
580 static int __devinit gxt4500_probe(struct pci_dev *pdev,
581                                    const struct pci_device_id *ent)
582 {
583         int err;
584         unsigned long reg_phys, fb_phys;
585         struct gxt4500_par *par;
586         struct fb_info *info;
587         struct fb_var_screeninfo var;
588
589         err = pci_enable_device(pdev);
590         if (err) {
591                 dev_err(&pdev->dev, "gxt4500: cannot enable PCI device: %d\n",
592                         err);
593                 return err;
594         }
595
596         reg_phys = pci_resource_start(pdev, 0);
597         if (!request_mem_region(reg_phys, pci_resource_len(pdev, 0),
598                                 "gxt4500 regs")) {
599                 dev_err(&pdev->dev, "gxt4500: cannot get registers\n");
600                 goto err_nodev;
601         }
602
603         fb_phys = pci_resource_start(pdev, 1);
604         if (!request_mem_region(fb_phys, pci_resource_len(pdev, 1),
605                                 "gxt4500 FB")) {
606                 dev_err(&pdev->dev, "gxt4500: cannot get framebuffer\n");
607                 goto err_free_regs;
608         }
609
610         info = framebuffer_alloc(sizeof(struct gxt4500_par), &pdev->dev);
611         if (!info) {
612                 dev_err(&pdev->dev, "gxt4500: cannot alloc FB info record");
613                 goto err_free_fb;
614         }
615         par = info->par;
616         info->fix = gxt4500_fix;
617         info->pseudo_palette = par->pseudo_palette;
618
619         info->fix.mmio_start = reg_phys;
620         par->regs = ioremap(reg_phys, pci_resource_len(pdev, 0));
621         if (!par->regs) {
622                 dev_err(&pdev->dev, "gxt4500: cannot map registers\n");
623                 goto err_free_all;
624         }
625
626         info->fix.smem_start = fb_phys;
627         info->fix.smem_len = pci_resource_len(pdev, 1);
628         info->screen_base = ioremap(fb_phys, pci_resource_len(pdev, 1));
629         if (!info->screen_base) {
630                 dev_err(&pdev->dev, "gxt4500: cannot map framebuffer\n");
631                 goto err_unmap_regs;
632         }
633
634         pci_set_drvdata(pdev, info);
635
636         /* Set byte-swapping for DFA aperture for all pixel sizes */
637         pci_write_config_dword(pdev, CFG_ENDIAN0, 0x333300);
638
639         info->fbops = &gxt4500_ops;
640         info->flags = FBINFO_FLAG_DEFAULT;
641
642         err = fb_alloc_cmap(&info->cmap, 256, 0);
643         if (err) {
644                 dev_err(&pdev->dev, "gxt4500: cannot allocate cmap\n");
645                 goto err_unmap_all;
646         }
647
648         gxt4500_blank(FB_BLANK_UNBLANK, info);
649
650         if (!fb_find_mode(&var, info, mode_option, NULL, 0, &defaultmode, 8)) {
651                 dev_err(&pdev->dev, "gxt4500: cannot find valid video mode\n");
652                 goto err_free_cmap;
653         }
654         info->var = var;
655         if (gxt4500_set_par(info)) {
656                 printk(KERN_ERR "gxt4500: cannot set video mode\n");
657                 goto err_free_cmap;
658         }
659
660         if (register_framebuffer(info) < 0) {
661                 dev_err(&pdev->dev, "gxt4500: cannot register framebuffer\n");
662                 goto err_free_cmap;
663         }
664         printk(KERN_INFO "fb%d: %s frame buffer device\n",
665                info->node, info->fix.id);
666
667         return 0;
668
669  err_free_cmap:
670         fb_dealloc_cmap(&info->cmap);
671  err_unmap_all:
672         iounmap(info->screen_base);
673  err_unmap_regs:
674         iounmap(par->regs);
675  err_free_all:
676         framebuffer_release(info);
677  err_free_fb:
678         release_mem_region(fb_phys, pci_resource_len(pdev, 1));
679  err_free_regs:
680         release_mem_region(reg_phys, pci_resource_len(pdev, 0));
681  err_nodev:
682         return -ENODEV;
683 }
684
685 static void __devexit gxt4500_remove(struct pci_dev *pdev)
686 {
687         struct fb_info *info = pci_get_drvdata(pdev);
688         struct gxt4500_par *par;
689
690         if (!info)
691                 return;
692         par = info->par;
693         unregister_framebuffer(info);
694         fb_dealloc_cmap(&info->cmap);
695         iounmap(par->regs);
696         iounmap(info->screen_base);
697         release_mem_region(pci_resource_start(pdev, 0),
698                            pci_resource_len(pdev, 0));
699         release_mem_region(pci_resource_start(pdev, 1),
700                            pci_resource_len(pdev, 1));
701         framebuffer_release(info);
702 }
703
704 /* supported chipsets */
705 static const struct pci_device_id gxt4500_pci_tbl[] = {
706         { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT4500P,
707           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
708         { 0 }
709 };
710
711 MODULE_DEVICE_TABLE(pci, gxt4500_pci_tbl);
712
713 static struct pci_driver gxt4500_driver = {
714         .name = "gxt4500",
715         .id_table = gxt4500_pci_tbl,
716         .probe = gxt4500_probe,
717         .remove = __devexit_p(gxt4500_remove),
718 };
719
720 static int __devinit gxt4500_init(void)
721 {
722 #ifndef MODULE
723         if (fb_get_options("gxt4500", &mode_option))
724                 return -ENODEV;
725 #endif
726
727         return pci_register_driver(&gxt4500_driver);
728 }
729 module_init(gxt4500_init);
730
731 static void __exit gxt4500_exit(void)
732 {
733         pci_unregister_driver(&gxt4500_driver);
734 }
735 module_exit(gxt4500_exit);
736
737 MODULE_AUTHOR("Paul Mackerras <paulus@samba.org>");
738 MODULE_DESCRIPTION("FBDev driver for IBM GXT4500P");
739 MODULE_LICENSE("GPL");
740 module_param(mode_option, charp, 0);
741 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\"");