2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #include <linux/types.h>
26 #include <linux/mii.h>
31 /* function prototype */
32 void atl1c_phy_disable(struct atl1c_hw *hw);
33 void atl1c_hw_set_mac_addr(struct atl1c_hw *hw);
34 int atl1c_phy_reset(struct atl1c_hw *hw);
35 int atl1c_read_mac_addr(struct atl1c_hw *hw);
36 int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex);
37 u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr);
38 void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value);
39 int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
40 int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data);
41 bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value);
42 int atl1c_phy_init(struct atl1c_hw *hw);
43 int atl1c_check_eeprom_exist(struct atl1c_hw *hw);
44 int atl1c_restart_autoneg(struct atl1c_hw *hw);
46 /* register definition */
47 #define REG_DEVICE_CAP 0x5C
48 #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
49 #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
51 #define REG_DEVICE_CTRL 0x60
52 #define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
53 #define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
54 #define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
55 #define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
57 #define REG_LINK_CTRL 0x68
58 #define LINK_CTRL_L0S_EN 0x01
59 #define LINK_CTRL_L1_EN 0x02
61 #define REG_VPD_CAP 0x6C
62 #define VPD_CAP_ID_MASK 0xff
63 #define VPD_CAP_ID_SHIFT 0
64 #define VPD_CAP_NEXT_PTR_MASK 0xFF
65 #define VPD_CAP_NEXT_PTR_SHIFT 8
66 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
67 #define VPD_CAP_VPD_ADDR_SHIFT 16
68 #define VPD_CAP_VPD_FLAG 0x80000000
70 #define REG_VPD_DATA 0x70
72 #define REG_PCIE_UC_SEVERITY 0x10C
73 #define PCIE_UC_SERVRITY_TRN 0x00000001
74 #define PCIE_UC_SERVRITY_DLP 0x00000010
75 #define PCIE_UC_SERVRITY_PSN_TLP 0x00001000
76 #define PCIE_UC_SERVRITY_FCP 0x00002000
77 #define PCIE_UC_SERVRITY_CPL_TO 0x00004000
78 #define PCIE_UC_SERVRITY_CA 0x00008000
79 #define PCIE_UC_SERVRITY_UC 0x00010000
80 #define PCIE_UC_SERVRITY_ROV 0x00020000
81 #define PCIE_UC_SERVRITY_MLFP 0x00040000
82 #define PCIE_UC_SERVRITY_ECRC 0x00080000
83 #define PCIE_UC_SERVRITY_UR 0x00100000
85 #define REG_DEV_SERIALNUM_CTRL 0x200
86 #define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */
87 #define REG_DEV_MAC_SEL_SHIFT 0
88 #define REG_DEV_SERIAL_NUM_EN_MASK 0x1
89 #define REG_DEV_SERIAL_NUM_EN_SHIFT 1
91 #define REG_TWSI_CTRL 0x218
92 #define TWSI_CTRL_LD_OFFSET_MASK 0xFF
93 #define TWSI_CTRL_LD_OFFSET_SHIFT 0
94 #define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
95 #define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
96 #define TWSI_CTRL_SW_LDSTART 0x800
97 #define TWSI_CTRL_HW_LDSTART 0x1000
98 #define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
99 #define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
100 #define TWSI_CTRL_LD_EXIST 0x400000
101 #define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
102 #define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
103 #define TWSI_CTRL_FREQ_SEL_100K 0
104 #define TWSI_CTRL_FREQ_SEL_200K 1
105 #define TWSI_CTRL_FREQ_SEL_300K 2
106 #define TWSI_CTRL_FREQ_SEL_400K 3
107 #define TWSI_CTRL_SMB_SLV_ADDR
108 #define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
109 #define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
112 #define REG_PCIE_DEV_MISC_CTRL 0x21C
113 #define PCIE_DEV_MISC_EXT_PIPE 0x2
114 #define PCIE_DEV_MISC_RETRY_BUFDIS 0x1
115 #define PCIE_DEV_MISC_SPIROM_EXIST 0x4
116 #define PCIE_DEV_MISC_SERDES_ENDIAN 0x8
117 #define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10
119 #define REG_PCIE_PHYMISC 0x1000
120 #define PCIE_PHYMISC_FORCE_RCV_DET 0x4
122 #define REG_TWSI_DEBUG 0x1108
123 #define TWSI_DEBUG_DEV_EXIST 0x20000000
125 #define REG_EEPROM_CTRL 0x12C0
126 #define EEPROM_CTRL_DATA_HI_MASK 0xFFFF
127 #define EEPROM_CTRL_DATA_HI_SHIFT 0
128 #define EEPROM_CTRL_ADDR_MASK 0x3FF
129 #define EEPROM_CTRL_ADDR_SHIFT 16
130 #define EEPROM_CTRL_ACK 0x40000000
131 #define EEPROM_CTRL_RW 0x80000000
133 #define REG_EEPROM_DATA_LO 0x12C4
135 #define REG_OTP_CTRL 0x12F0
136 #define OTP_CTRL_CLK_EN 0x0002
138 #define REG_PM_CTRL 0x12F8
139 #define PM_CTRL_SDES_EN 0x00000001
140 #define PM_CTRL_RBER_EN 0x00000002
141 #define PM_CTRL_CLK_REQ_EN 0x00000004
142 #define PM_CTRL_ASPM_L1_EN 0x00000008
143 #define PM_CTRL_SERDES_L1_EN 0x00000010
144 #define PM_CTRL_SERDES_PLL_L1_EN 0x00000020
145 #define PM_CTRL_SERDES_PD_EX_L1 0x00000040
146 #define PM_CTRL_SERDES_BUDS_RX_L1_EN 0x00000080
147 #define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xF
148 #define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8
149 #define PM_CTRL_ASPM_L0S_EN 0x00001000
150 #define PM_CTRL_CLK_SWH_L1 0x00002000
151 #define PM_CTRL_CLK_PWM_VER1_1 0x00004000
152 #define PM_CTRL_PCIE_RECV 0x00008000
153 #define PM_CTRL_L1_ENTRY_TIMER_MASK 0xF
154 #define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16
155 #define PM_CTRL_PM_REQ_TIMER_MASK 0xF
156 #define PM_CTRL_PM_REQ_TIMER_SHIFT 20
157 #define PM_CTRL_LCKDET_TIMER_MASK 0x3F
158 #define PM_CTRL_LCKDET_TIMER_SHIFT 24
159 #define PM_CTRL_MAC_ASPM_CHK 0x40000000
160 #define PM_CTRL_HOTRST 0x80000000
162 /* Selene Master Control Register */
163 #define REG_MASTER_CTRL 0x1400
164 #define MASTER_CTRL_SOFT_RST 0x1
165 #define MASTER_CTRL_TEST_MODE_MASK 0x3
166 #define MASTER_CTRL_TEST_MODE_SHIFT 2
167 #define MASTER_CTRL_BERT_START 0x10
168 #define MASTER_CTRL_MTIMER_EN 0x100
169 #define MASTER_CTRL_MANUAL_INT 0x200
170 #define MASTER_CTRL_TX_ITIMER_EN 0x400
171 #define MASTER_CTRL_RX_ITIMER_EN 0x800
172 #define MASTER_CTRL_CLK_SEL_DIS 0x1000
173 #define MASTER_CTRL_CLK_SWH_MODE 0x2000
174 #define MASTER_CTRL_INT_RDCLR 0x4000
175 #define MASTER_CTRL_REV_NUM_SHIFT 16
176 #define MASTER_CTRL_REV_NUM_MASK 0xff
177 #define MASTER_CTRL_DEV_ID_SHIFT 24
178 #define MASTER_CTRL_DEV_ID_MASK 0x7f
179 #define MASTER_CTRL_OTP_SEL 0x80000000
181 /* Timer Initial Value Register */
182 #define REG_MANUAL_TIMER_INIT 0x1404
184 /* IRQ ModeratorTimer Initial Value Register */
185 #define REG_IRQ_MODRT_TIMER_INIT 0x1408
186 #define IRQ_MODRT_TIMER_MASK 0xffff
187 #define IRQ_MODRT_TX_TIMER_SHIFT 0
188 #define IRQ_MODRT_RX_TIMER_SHIFT 16
190 #define REG_GPHY_CTRL 0x140C
191 #define GPHY_CTRL_EXT_RESET 0x1
192 #define GPHY_CTRL_RTL_MODE 0x2
193 #define GPHY_CTRL_LED_MODE 0x4
194 #define GPHY_CTRL_ANEG_NOW 0x8
195 #define GPHY_CTRL_REV_ANEG 0x10
196 #define GPHY_CTRL_GATE_25M_EN 0x20
197 #define GPHY_CTRL_LPW_EXIT 0x40
198 #define GPHY_CTRL_PHY_IDDQ 0x80
199 #define GPHY_CTRL_PHY_IDDQ_DIS 0x100
200 #define GPHY_CTRL_GIGA_DIS 0x200
201 #define GPHY_CTRL_HIB_EN 0x400
202 #define GPHY_CTRL_HIB_PULSE 0x800
203 #define GPHY_CTRL_SEL_ANA_RST 0x1000
204 #define GPHY_CTRL_PHY_PLL_ON 0x2000
205 #define GPHY_CTRL_PWDOWN_HW 0x4000
206 #define GPHY_CTRL_PHY_PLL_BYPASS 0x8000
208 #define GPHY_CTRL_DEFAULT ( \
209 GPHY_CTRL_SEL_ANA_RST |\
210 GPHY_CTRL_HIB_PULSE |\
213 #define GPHY_CTRL_PW_WOL_DIS ( \
214 GPHY_CTRL_SEL_ANA_RST |\
215 GPHY_CTRL_HIB_PULSE |\
217 GPHY_CTRL_PWDOWN_HW |\
220 /* Block IDLE Status Register */
221 #define REG_IDLE_STATUS 0x1410
222 #define IDLE_STATUS_MASK 0x00FF
223 #define IDLE_STATUS_RXMAC_NO_IDLE 0x1
224 #define IDLE_STATUS_TXMAC_NO_IDLE 0x2
225 #define IDLE_STATUS_RXQ_NO_IDLE 0x4
226 #define IDLE_STATUS_TXQ_NO_IDLE 0x8
227 #define IDLE_STATUS_DMAR_NO_IDLE 0x10
228 #define IDLE_STATUS_DMAW_NO_IDLE 0x20
229 #define IDLE_STATUS_SMB_NO_IDLE 0x40
230 #define IDLE_STATUS_CMB_NO_IDLE 0x80
232 /* MDIO Control Register */
233 #define REG_MDIO_CTRL 0x1414
234 #define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit
235 * control data to write to PHY
236 * MII management register */
237 #define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit
238 * status data that was read
239 * from the PHY MII management register */
240 #define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
241 #define MDIO_REG_ADDR_SHIFT 16
242 #define MDIO_RW 0x200000 /* 1: read, 0: write */
243 #define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
244 #define MDIO_START 0x800000 /* Write 1 to initiate the MDIO
245 * master. And this bit is self
246 * cleared after one cycle */
247 #define MDIO_CLK_SEL_SHIFT 24
248 #define MDIO_CLK_25_4 0
249 #define MDIO_CLK_25_6 2
250 #define MDIO_CLK_25_8 3
251 #define MDIO_CLK_25_10 4
252 #define MDIO_CLK_25_14 5
253 #define MDIO_CLK_25_20 6
254 #define MDIO_CLK_25_28 7
255 #define MDIO_BUSY 0x8000000
256 #define MDIO_AP_EN 0x10000000
257 #define MDIO_WAIT_TIMES 10
259 /* MII PHY Status Register */
260 #define REG_PHY_STATUS 0x1418
261 #define PHY_GENERAL_STATUS_MASK 0xFFFF
262 #define PHY_STATUS_RECV_ENABLE 0x0001
263 #define PHY_OE_PWSP_STATUS_MASK 0x07FF
264 #define PHY_OE_PWSP_STATUS_SHIFT 16
265 #define PHY_STATUS_LPW_STATE 0x80000000
266 /* BIST Control and Status Register0 (for the Packet Memory) */
267 #define REG_BIST0_CTRL 0x141c
268 #define BIST0_NOW 0x1
269 #define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is
270 * un-repairable because
271 * it has address decoder
272 * failure or more than 1 cell
273 * stuck-to-x failure */
274 #define BIST0_FUSE_FLAG 0x4
276 /* BIST Control and Status Register1(for the retry buffer of PCI Express) */
277 #define REG_BIST1_CTRL 0x1420
278 #define BIST1_NOW 0x1
279 #define BIST1_SRAM_FAIL 0x2
280 #define BIST1_FUSE_FLAG 0x4
282 /* SerDes Lock Detect Control and Status Register */
283 #define REG_SERDES_LOCK 0x1424
284 #define SERDES_LOCK_DETECT 0x1 /* SerDes lock detected. This signal
285 * comes from Analog SerDes */
286 #define SERDES_LOCK_DETECT_EN 0x2 /* 1: Enable SerDes Lock detect function */
288 /* MAC Control Register */
289 #define REG_MAC_CTRL 0x1480
290 #define MAC_CTRL_TX_EN 0x1
291 #define MAC_CTRL_RX_EN 0x2
292 #define MAC_CTRL_TX_FLOW 0x4
293 #define MAC_CTRL_RX_FLOW 0x8
294 #define MAC_CTRL_LOOPBACK 0x10
295 #define MAC_CTRL_DUPLX 0x20
296 #define MAC_CTRL_ADD_CRC 0x40
297 #define MAC_CTRL_PAD 0x80
298 #define MAC_CTRL_LENCHK 0x100
299 #define MAC_CTRL_HUGE_EN 0x200
300 #define MAC_CTRL_PRMLEN_SHIFT 10
301 #define MAC_CTRL_PRMLEN_MASK 0xf
302 #define MAC_CTRL_RMV_VLAN 0x4000
303 #define MAC_CTRL_PROMIS_EN 0x8000
304 #define MAC_CTRL_TX_PAUSE 0x10000
305 #define MAC_CTRL_SCNT 0x20000
306 #define MAC_CTRL_SRST_TX 0x40000
307 #define MAC_CTRL_TX_SIMURST 0x80000
308 #define MAC_CTRL_SPEED_SHIFT 20
309 #define MAC_CTRL_SPEED_MASK 0x3
310 #define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
311 #define MAC_CTRL_TX_HUGE 0x800000
312 #define MAC_CTRL_RX_CHKSUM_EN 0x1000000
313 #define MAC_CTRL_MC_ALL_EN 0x2000000
314 #define MAC_CTRL_BC_EN 0x4000000
315 #define MAC_CTRL_DBG 0x8000000
316 #define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000
318 /* MAC IPG/IFG Control Register */
319 #define REG_MAC_IPG_IFG 0x1484
320 #define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back
321 * inter-packet gap. The
322 * default is 96-bit time */
323 #define MAC_IPG_IFG_IPGT_MASK 0x7f
324 #define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to
325 * enforce in between RX frames */
326 #define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
327 #define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
328 #define MAC_IPG_IFG_IPGR1_MASK 0x7f
329 #define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
330 #define MAC_IPG_IFG_IPGR2_MASK 0x7f
332 /* MAC STATION ADDRESS */
333 #define REG_MAC_STA_ADDR 0x1488
335 /* Hash table for multicast address */
336 #define REG_RX_HASH_TABLE 0x1490
338 /* MAC Half-Duplex Control Register */
339 #define REG_MAC_HALF_DUPLX_CTRL 0x1498
340 #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
341 #define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
342 #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
343 #define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
344 #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
345 #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
346 #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure,
347 * immediately start the
348 * transmission after back pressure */
349 #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
350 #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
351 #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
352 #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
353 #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
355 /* Maximum Frame Length Control Register */
356 #define REG_MTU 0x149c
358 /* Wake-On-Lan control register */
359 #define REG_WOL_CTRL 0x14a0
360 #define WOL_PATTERN_EN 0x00000001
361 #define WOL_PATTERN_PME_EN 0x00000002
362 #define WOL_MAGIC_EN 0x00000004
363 #define WOL_MAGIC_PME_EN 0x00000008
364 #define WOL_LINK_CHG_EN 0x00000010
365 #define WOL_LINK_CHG_PME_EN 0x00000020
366 #define WOL_PATTERN_ST 0x00000100
367 #define WOL_MAGIC_ST 0x00000200
368 #define WOL_LINKCHG_ST 0x00000400
369 #define WOL_CLK_SWITCH_EN 0x00008000
370 #define WOL_PT0_EN 0x00010000
371 #define WOL_PT1_EN 0x00020000
372 #define WOL_PT2_EN 0x00040000
373 #define WOL_PT3_EN 0x00080000
374 #define WOL_PT4_EN 0x00100000
375 #define WOL_PT5_EN 0x00200000
376 #define WOL_PT6_EN 0x00400000
378 /* WOL Length ( 2 DWORD ) */
379 #define REG_WOL_PATTERN_LEN 0x14a4
380 #define WOL_PT_LEN_MASK 0x7f
381 #define WOL_PT0_LEN_SHIFT 0
382 #define WOL_PT1_LEN_SHIFT 8
383 #define WOL_PT2_LEN_SHIFT 16
384 #define WOL_PT3_LEN_SHIFT 24
385 #define WOL_PT4_LEN_SHIFT 0
386 #define WOL_PT5_LEN_SHIFT 8
387 #define WOL_PT6_LEN_SHIFT 16
389 /* Internal SRAM Partition Register */
390 #define RFDX_HEAD_ADDR_MASK 0x03FF
391 #define RFDX_HARD_ADDR_SHIFT 0
392 #define RFDX_TAIL_ADDR_MASK 0x03FF
393 #define RFDX_TAIL_ADDR_SHIFT 16
395 #define REG_SRAM_RFD0_INFO 0x1500
396 #define REG_SRAM_RFD1_INFO 0x1504
397 #define REG_SRAM_RFD2_INFO 0x1508
398 #define REG_SRAM_RFD3_INFO 0x150C
400 #define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */
401 #define RFD_NIC_LEN_MASK 0x03FF
403 #define REG_SRAM_TRD_ADDR 0x1518
404 #define TPD_HEAD_ADDR_MASK 0x03FF
405 #define TPD_HEAD_ADDR_SHIFT 0
406 #define TPD_TAIL_ADDR_MASK 0x03FF
407 #define TPD_TAIL_ADDR_SHIFT 16
409 #define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */
410 #define TPD_NIC_LEN_MASK 0x03FF
412 #define REG_SRAM_RXF_ADDR 0x1520
413 #define REG_SRAM_RXF_LEN 0x1524
414 #define REG_SRAM_TXF_ADDR 0x1528
415 #define REG_SRAM_TXF_LEN 0x152C
416 #define REG_SRAM_TCPH_ADDR 0x1530
417 #define REG_SRAM_PKTH_ADDR 0x1532
421 * Software sets this bit after the initialization of the head and tail */
422 #define REG_LOAD_PTR 0x1534
425 * addresses of all descriptors, as well as the following descriptor
426 * control register, which triggers each function block to load the head
427 * pointer to prepare for the operation. This bit is then self-cleared
430 #define REG_RX_BASE_ADDR_HI 0x1540
431 #define REG_TX_BASE_ADDR_HI 0x1544
432 #define REG_SMB_BASE_ADDR_HI 0x1548
433 #define REG_SMB_BASE_ADDR_LO 0x154C
434 #define REG_RFD0_HEAD_ADDR_LO 0x1550
435 #define REG_RFD1_HEAD_ADDR_LO 0x1554
436 #define REG_RFD2_HEAD_ADDR_LO 0x1558
437 #define REG_RFD3_HEAD_ADDR_LO 0x155C
438 #define REG_RFD_RING_SIZE 0x1560
439 #define RFD_RING_SIZE_MASK 0x0FFF
440 #define REG_RX_BUF_SIZE 0x1564
441 #define RX_BUF_SIZE_MASK 0xFFFF
442 #define REG_RRD0_HEAD_ADDR_LO 0x1568
443 #define REG_RRD1_HEAD_ADDR_LO 0x156C
444 #define REG_RRD2_HEAD_ADDR_LO 0x1570
445 #define REG_RRD3_HEAD_ADDR_LO 0x1574
446 #define REG_RRD_RING_SIZE 0x1578
447 #define RRD_RING_SIZE_MASK 0x0FFF
448 #define REG_HTPD_HEAD_ADDR_LO 0x157C
449 #define REG_NTPD_HEAD_ADDR_LO 0x1580
450 #define REG_TPD_RING_SIZE 0x1584
451 #define TPD_RING_SIZE_MASK 0xFFFF
452 #define REG_CMB_BASE_ADDR_LO 0x1588
455 #define REG_RSS_KEY0 0x14B0
456 #define REG_RSS_KEY1 0x14B4
457 #define REG_RSS_KEY2 0x14B8
458 #define REG_RSS_KEY3 0x14BC
459 #define REG_RSS_KEY4 0x14C0
460 #define REG_RSS_KEY5 0x14C4
461 #define REG_RSS_KEY6 0x14C8
462 #define REG_RSS_KEY7 0x14CC
463 #define REG_RSS_KEY8 0x14D0
464 #define REG_RSS_KEY9 0x14D4
465 #define REG_IDT_TABLE0 0x14E0
466 #define REG_IDT_TABLE1 0x14E4
467 #define REG_IDT_TABLE2 0x14E8
468 #define REG_IDT_TABLE3 0x14EC
469 #define REG_IDT_TABLE4 0x14F0
470 #define REG_IDT_TABLE5 0x14F4
471 #define REG_IDT_TABLE6 0x14F8
472 #define REG_IDT_TABLE7 0x14FC
473 #define REG_IDT_TABLE REG_IDT_TABLE0
474 #define REG_RSS_HASH_VALUE 0x15B0
475 #define REG_RSS_HASH_FLAG 0x15B4
476 #define REG_BASE_CPU_NUMBER 0x15B8
478 /* TXQ Control Register */
479 #define REG_TXQ_CTRL 0x1590
480 #define TXQ_NUM_TPD_BURST_MASK 0xF
481 #define TXQ_NUM_TPD_BURST_SHIFT 0
482 #define TXQ_CTRL_IP_OPTION_EN 0x10
483 #define TXQ_CTRL_EN 0x20
484 #define TXQ_CTRL_ENH_MODE 0x40
485 #define TXQ_CTRL_LS_8023_EN 0x80
486 #define TXQ_TXF_BURST_NUM_SHIFT 16
487 #define TXQ_TXF_BURST_NUM_MASK 0xFFFF
489 /* Jumbo packet Threshold for task offload */
490 #define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */
491 #define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF
493 #define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */
494 #define TXF_WATER_MARK_MASK 0x0FFF
495 #define TXF_LOW_WATER_MARK_SHIFT 0
496 #define TXF_HIGH_WATER_MARK_SHIFT 16
497 #define TXQ_CTRL_BURST_MODE_EN 0x80000000
499 #define REG_THRUPUT_MON_CTRL 0x159C
500 #define THRUPUT_MON_RATE_MASK 0x3
501 #define THRUPUT_MON_RATE_SHIFT 0
502 #define THRUPUT_MON_EN 0x80
504 /* RXQ Control Register */
505 #define REG_RXQ_CTRL 0x15A0
506 #define ASPM_THRUPUT_LIMIT_MASK 0x3
507 #define ASPM_THRUPUT_LIMIT_SHIFT 0
508 #define ASPM_THRUPUT_LIMIT_NO 0x00
509 #define ASPM_THRUPUT_LIMIT_1M 0x01
510 #define ASPM_THRUPUT_LIMIT_10M 0x02
511 #define ASPM_THRUPUT_LIMIT_100M 0x04
512 #define RXQ1_CTRL_EN 0x10
513 #define RXQ2_CTRL_EN 0x20
514 #define RXQ3_CTRL_EN 0x40
515 #define IPV6_CHKSUM_CTRL_EN 0x80
516 #define RSS_HASH_BITS_MASK 0x00FF
517 #define RSS_HASH_BITS_SHIFT 8
518 #define RSS_HASH_IPV4 0x10000
519 #define RSS_HASH_IPV4_TCP 0x20000
520 #define RSS_HASH_IPV6 0x40000
521 #define RSS_HASH_IPV6_TCP 0x80000
522 #define RXQ_RFD_BURST_NUM_MASK 0x003F
523 #define RXQ_RFD_BURST_NUM_SHIFT 20
524 #define RSS_MODE_MASK 0x0003
525 #define RSS_MODE_SHIFT 26
526 #define RSS_NIP_QUEUE_SEL_MASK 0x1
527 #define RSS_NIP_QUEUE_SEL_SHIFT 28
528 #define RRS_HASH_CTRL_EN 0x20000000
529 #define RX_CUT_THRU_EN 0x40000000
530 #define RXQ_CTRL_EN 0x80000000
532 #define REG_RFD_FREE_THRESH 0x15A4
533 #define RFD_FREE_THRESH_MASK 0x003F
534 #define RFD_FREE_HI_THRESH_SHIFT 0
535 #define RFD_FREE_LO_THRESH_SHIFT 6
537 /* RXF flow control register */
538 #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
539 #define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
540 #define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF
541 #define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
542 #define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF
544 #define REG_RXD_DMA_CTRL 0x15AC
545 #define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */
546 #define RXD_DMA_THRESH_SHIFT 0
547 #define RXD_DMA_DOWN_TIMER_MASK 0xFFFF
548 #define RXD_DMA_DOWN_TIMER_SHIFT 16
550 /* DMA Engine Control Register */
551 #define REG_DMA_CTRL 0x15C0
552 #define DMA_CTRL_DMAR_IN_ORDER 0x1
553 #define DMA_CTRL_DMAR_ENH_ORDER 0x2
554 #define DMA_CTRL_DMAR_OUT_ORDER 0x4
555 #define DMA_CTRL_RCB_VALUE 0x8
556 #define DMA_CTRL_DMAR_BURST_LEN_MASK 0x0007
557 #define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
558 #define DMA_CTRL_DMAW_BURST_LEN_MASK 0x0007
559 #define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
560 #define DMA_CTRL_DMAR_REQ_PRI 0x400
561 #define DMA_CTRL_DMAR_DLY_CNT_MASK 0x001F
562 #define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
563 #define DMA_CTRL_DMAW_DLY_CNT_MASK 0x000F
564 #define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
565 #define DMA_CTRL_CMB_EN 0x100000
566 #define DMA_CTRL_SMB_EN 0x200000
567 #define DMA_CTRL_CMB_NOW 0x400000
568 #define MAC_CTRL_SMB_DIS 0x1000000
569 #define DMA_CTRL_SMB_NOW 0x80000000
571 /* CMB/SMB Control Register */
572 #define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */
573 #define SMB_STAT_TIMER_MASK 0xFFFFFF
574 #define REG_CMB_TPD_THRESH 0x15C8
575 #define CMB_TPD_THRESH_MASK 0xFFFF
576 #define REG_CMB_TX_TIMER 0x15CC /* 2us resolution */
577 #define CMB_TX_TIMER_MASK 0xFFFF
580 #define MB_RFDX_PROD_IDX_MASK 0xFFFF
581 #define REG_MB_RFD0_PROD_IDX 0x15E0
582 #define REG_MB_RFD1_PROD_IDX 0x15E4
583 #define REG_MB_RFD2_PROD_IDX 0x15E8
584 #define REG_MB_RFD3_PROD_IDX 0x15EC
586 #define MB_PRIO_PROD_IDX_MASK 0xFFFF
587 #define REG_MB_PRIO_PROD_IDX 0x15F0
588 #define MB_HTPD_PROD_IDX_SHIFT 0
589 #define MB_NTPD_PROD_IDX_SHIFT 16
591 #define MB_PRIO_CONS_IDX_MASK 0xFFFF
592 #define REG_MB_PRIO_CONS_IDX 0x15F4
593 #define MB_HTPD_CONS_IDX_SHIFT 0
594 #define MB_NTPD_CONS_IDX_SHIFT 16
596 #define REG_MB_RFD01_CONS_IDX 0x15F8
597 #define MB_RFD0_CONS_IDX_MASK 0x0000FFFF
598 #define MB_RFD1_CONS_IDX_MASK 0xFFFF0000
599 #define REG_MB_RFD23_CONS_IDX 0x15FC
600 #define MB_RFD2_CONS_IDX_MASK 0x0000FFFF
601 #define MB_RFD3_CONS_IDX_MASK 0xFFFF0000
603 /* Interrupt Status Register */
604 #define REG_ISR 0x1600
605 #define ISR_SMB 0x00000001
606 #define ISR_TIMER 0x00000002
608 * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
609 * in Table 51 Selene Master Control Register (Offset 0x1400).
611 #define ISR_MANUAL 0x00000004
612 #define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */
613 #define ISR_RFD0_UR 0x00000010 /* RFD0 under run */
614 #define ISR_RFD1_UR 0x00000020
615 #define ISR_RFD2_UR 0x00000040
616 #define ISR_RFD3_UR 0x00000080
617 #define ISR_TXF_UR 0x00000100
618 #define ISR_DMAR_TO_RST 0x00000200
619 #define ISR_DMAW_TO_RST 0x00000400
620 #define ISR_TX_CREDIT 0x00000800
621 #define ISR_GPHY 0x00001000
622 /* GPHY low power state interrupt */
623 #define ISR_GPHY_LPW 0x00002000
624 #define ISR_TXQ_TO_RST 0x00004000
625 #define ISR_TX_PKT 0x00008000
626 #define ISR_RX_PKT_0 0x00010000
627 #define ISR_RX_PKT_1 0x00020000
628 #define ISR_RX_PKT_2 0x00040000
629 #define ISR_RX_PKT_3 0x00080000
630 #define ISR_MAC_RX 0x00100000
631 #define ISR_MAC_TX 0x00200000
632 #define ISR_UR_DETECTED 0x00400000
633 #define ISR_FERR_DETECTED 0x00800000
634 #define ISR_NFERR_DETECTED 0x01000000
635 #define ISR_CERR_DETECTED 0x02000000
636 #define ISR_PHY_LINKDOWN 0x04000000
637 #define ISR_DIS_INT 0x80000000
639 /* Interrupt Mask Register */
640 #define REG_IMR 0x1604
642 #define IMR_NORMAL_MASK (\
656 #define ISR_RX_PKT (\
676 #define REG_INT_RETRIG_TIMER 0x1608
677 #define INT_RETRIG_TIMER_MASK 0xFFFF
679 #define REG_HDS_CTRL 0x160C
680 #define HDS_CTRL_EN 0x0001
681 #define HDS_CTRL_BACKFILLSIZE_SHIFT 8
682 #define HDS_CTRL_BACKFILLSIZE_MASK 0x0FFF
683 #define HDS_CTRL_MAX_HDRSIZE_SHIFT 20
684 #define HDS_CTRL_MAC_HDRSIZE_MASK 0x0FFF
686 #define REG_MAC_RX_STATUS_BIN 0x1700
687 #define REG_MAC_RX_STATUS_END 0x175c
688 #define REG_MAC_TX_STATUS_BIN 0x1760
689 #define REG_MAC_TX_STATUS_END 0x17c0
692 #define REG_DEBUG_DATA0 0x1900
693 #define REG_DEBUG_DATA1 0x1904
695 /* PHY Control Register */
696 #define MII_BMCR 0x00
697 #define BMCR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
698 #define BMCR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
699 #define BMCR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
700 #define BMCR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
701 #define BMCR_ISOLATE 0x0400 /* Isolate PHY from MII */
702 #define BMCR_POWER_DOWN 0x0800 /* Power down */
703 #define BMCR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
704 #define BMCR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
705 #define BMCR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
706 #define BMCR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
707 #define BMCR_SPEED_MASK 0x2040
708 #define BMCR_SPEED_1000 0x0040
709 #define BMCR_SPEED_100 0x2000
710 #define BMCR_SPEED_10 0x0000
712 /* PHY Status Register */
713 #define MII_BMSR 0x01
714 #define BMMSR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
715 #define BMSR_JABBER_DETECT 0x0002 /* Jabber Detected */
716 #define BMSR_LINK_STATUS 0x0004 /* Link Status 1 = link */
717 #define BMSR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
718 #define BMSR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
719 #define BMSR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
720 #define BMSR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
721 #define BMSR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
722 #define BMSR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
723 #define BMSR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
724 #define BMSR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
725 #define BMSR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
726 #define BMSR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
727 #define BMMII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
728 #define BMMII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
730 #define MII_PHYSID1 0x02
731 #define MII_PHYSID2 0x03
733 /* Autoneg Advertisement Register */
734 #define MII_ADVERTISE 0x04
735 #define ADVERTISE_SPEED_MASK 0x01E0
736 #define ADVERTISE_DEFAULT_CAP 0x0DE0
738 /* 1000BASE-T Control Register */
739 #define MII_GIGA_CR 0x09
740 #define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */
742 #define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
743 #define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
744 #define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
745 #define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
746 #define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
747 #define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
748 #define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
749 #define GIGA_CR_1000T_SPEED_MASK 0x0300
750 #define GIGA_CR_1000T_DEFAULT_CAP 0x0300
752 /* PHY Specific Status Register */
753 #define MII_GIGA_PSSR 0x11
754 #define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
755 #define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
756 #define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
757 #define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */
758 #define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */
759 #define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
761 /* PHY Interrupt Enable Register */
763 #define IER_LINK_UP 0x0400
764 #define IER_LINK_DOWN 0x0800
766 /* PHY Interrupt Status Register */
768 #define ISR_LINK_UP 0x0400
769 #define ISR_LINK_DOWN 0x0800
771 /* Cable-Detect-Test Control Register */
772 #define MII_CDTC 0x16
773 #define CDTC_EN_OFF 0 /* sc */
774 #define CDTC_EN_BITS 1
775 #define CDTC_PAIR_OFF 8
776 #define CDTC_PAIR_BIT 2
778 /* Cable-Detect-Test Status Register */
779 #define MII_CDTS 0x1C
780 #define CDTS_STATUS_OFF 8
781 #define CDTS_STATUS_BITS 2
782 #define CDTS_STATUS_NORMAL 0
783 #define CDTS_STATUS_SHORT 1
784 #define CDTS_STATUS_OPEN 2
785 #define CDTS_STATUS_INVALID 3
787 #define MII_DBG_ADDR 0x1D
788 #define MII_DBG_DATA 0x1E
790 #define MII_ANA_CTRL_0 0x0
791 #define ANA_RESTART_CAL 0x0001
792 #define ANA_MANUL_SWICH_ON_SHIFT 0x1
793 #define ANA_MANUL_SWICH_ON_MASK 0xF
794 #define ANA_MAN_ENABLE 0x0020
795 #define ANA_SEL_HSP 0x0040
796 #define ANA_EN_HB 0x0080
797 #define ANA_EN_HBIAS 0x0100
798 #define ANA_OEN_125M 0x0200
799 #define ANA_EN_LCKDT 0x0400
800 #define ANA_LCKDT_PHY 0x0800
801 #define ANA_AFE_MODE 0x1000
802 #define ANA_VCO_SLOW 0x2000
803 #define ANA_VCO_FAST 0x4000
804 #define ANA_SEL_CLK125M_DSP 0x8000
806 #define MII_ANA_CTRL_4 0x4
807 #define ANA_IECHO_ADJ_MASK 0xF
808 #define ANA_IECHO_ADJ_3_SHIFT 0
809 #define ANA_IECHO_ADJ_2_SHIFT 4
810 #define ANA_IECHO_ADJ_1_SHIFT 8
811 #define ANA_IECHO_ADJ_0_SHIFT 12
813 #define MII_ANA_CTRL_5 0x5
814 #define ANA_SERDES_CDR_BW_SHIFT 0
815 #define ANA_SERDES_CDR_BW_MASK 0x3
816 #define ANA_MS_PAD_DBG 0x0004
817 #define ANA_SPEEDUP_DBG 0x0008
818 #define ANA_SERDES_TH_LOS_SHIFT 4
819 #define ANA_SERDES_TH_LOS_MASK 0x3
820 #define ANA_SERDES_EN_DEEM 0x0040
821 #define ANA_SERDES_TXELECIDLE 0x0080
822 #define ANA_SERDES_BEACON 0x0100
823 #define ANA_SERDES_HALFTXDR 0x0200
824 #define ANA_SERDES_SEL_HSP 0x0400
825 #define ANA_SERDES_EN_PLL 0x0800
826 #define ANA_SERDES_EN 0x1000
827 #define ANA_SERDES_EN_LCKDT 0x2000
829 #define MII_ANA_CTRL_11 0xB
830 #define ANA_PS_HIB_EN 0x8000
832 #define MII_ANA_CTRL_18 0x12
833 #define ANA_TEST_MODE_10BT_01SHIFT 0
834 #define ANA_TEST_MODE_10BT_01MASK 0x3
835 #define ANA_LOOP_SEL_10BT 0x0004
836 #define ANA_RGMII_MODE_SW 0x0008
837 #define ANA_EN_LONGECABLE 0x0010
838 #define ANA_TEST_MODE_10BT_2 0x0020
839 #define ANA_EN_10BT_IDLE 0x0400
840 #define ANA_EN_MASK_TB 0x0800
841 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12
842 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3
843 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14
844 #define ANA_INTERVAL_SEL_TIMER_MASK 0x3
846 #define MII_ANA_CTRL_41 0x29
847 #define ANA_TOP_PS_EN 0x8000
849 #define MII_ANA_CTRL_54 0x36
850 #define ANA_LONG_CABLE_TH_100_SHIFT 0
851 #define ANA_LONG_CABLE_TH_100_MASK 0x3F
852 #define ANA_DESERVED 0x0040
853 #define ANA_EN_LIT_CH 0x0080
854 #define ANA_SHORT_CABLE_TH_100_SHIFT 8
855 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F
856 #define ANA_BP_BAD_LINK_ACCUM 0x4000
857 #define ANA_BP_SMALL_BW 0x8000
859 #endif /*_ATL1C_HW_H_*/
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