2 * au1550_spi.c - au1550 psc spi controller driver
3 * may work also with au1200, au1210, au1250
4 * will not work on au1000, au1100 and au1500 (no full spi controller there)
6 * Copyright (c) 2006 ATRON electronic GmbH
7 * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/errno.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi/spi_bitbang.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/completion.h>
33 #include <asm/mach-au1x00/au1000.h>
34 #include <asm/mach-au1x00/au1xxx_psc.h>
35 #include <asm/mach-au1x00/au1xxx_dbdma.h>
37 #include <asm/mach-au1x00/au1550_spi.h>
39 static unsigned usedma = 1;
40 module_param(usedma, uint, 0644);
43 #define AU1550_SPI_DEBUG_LOOPBACK
47 #define AU1550_SPI_DBDMA_DESCRIPTORS 1
48 #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
51 struct spi_bitbang bitbang;
53 volatile psc_spi_t __iomem *regs;
64 void (*rx_word)(struct au1550_spi *hw);
65 void (*tx_word)(struct au1550_spi *hw);
66 int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
67 irqreturn_t (*irq_callback)(struct au1550_spi *hw);
69 struct completion master_done;
78 unsigned dma_rx_tmpbuf_size;
79 u32 dma_rx_tmpbuf_addr;
81 struct spi_master *master;
83 struct au1550_spi_info *pdata;
87 /* we use an 8-bit memory device for dma transfers to/from spi fifo */
88 static dbdev_tab_t au1550_spi_mem_dbdev =
90 .dev_id = DBDMA_MEM_CHAN,
91 .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
94 .dev_physaddr = 0x00000000,
99 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
103 * compute BRG and DIV bits to setup spi clock based on main input clock rate
104 * that was specified in platform data structure
105 * according to au1550 datasheet:
106 * psc_tempclk = psc_mainclk / (2 << DIV)
107 * spiclk = psc_tempclk / (2 * (BRG + 1))
108 * BRG valid range is 4..63
109 * DIV valid range is 0..3
111 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
113 u32 mainclk_hz = hw->pdata->mainclk_hz;
116 for (div = 0; div < 4; div++) {
117 brg = mainclk_hz / speed_hz / (4 << div);
118 /* now we have BRG+1 in brg, so count with that */
120 brg = (4 + 1); /* speed_hz too big */
121 break; /* set lowest brg (div is == 0) */
124 break; /* we have valid brg and div */
127 div = 3; /* speed_hz too small */
128 brg = (63 + 1); /* set highest brg and div */
131 return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
134 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
136 hw->regs->psc_spimsk =
137 PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
138 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
139 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
142 hw->regs->psc_spievent =
143 PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
144 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
145 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
149 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
153 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
156 pcr = hw->regs->psc_spipcr;
162 * dma transfers are used for the most common spi word size of 8-bits
163 * we cannot easily change already set up dma channels' width, so if we wanted
164 * dma support for more than 8-bit words (up to 24 bits), we would need to
165 * setup dma channels from scratch on each spi transfer, based on bits_per_word
166 * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
167 * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
168 * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
170 static void au1550_spi_chipsel(struct spi_device *spi, int value)
172 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
173 unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
177 case BITBANG_CS_INACTIVE:
178 if (hw->pdata->deactivate_cs)
179 hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
183 case BITBANG_CS_ACTIVE:
184 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
186 cfg = hw->regs->psc_spicfg;
188 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
191 if (spi->mode & SPI_CPOL)
192 cfg |= PSC_SPICFG_BI;
194 cfg &= ~PSC_SPICFG_BI;
195 if (spi->mode & SPI_CPHA)
196 cfg &= ~PSC_SPICFG_CDE;
198 cfg |= PSC_SPICFG_CDE;
200 if (spi->mode & SPI_LSB_FIRST)
201 cfg |= PSC_SPICFG_MLF;
203 cfg &= ~PSC_SPICFG_MLF;
205 if (hw->usedma && spi->bits_per_word <= 8)
206 cfg &= ~PSC_SPICFG_DD_DISABLE;
208 cfg |= PSC_SPICFG_DD_DISABLE;
209 cfg = PSC_SPICFG_CLR_LEN(cfg);
210 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
212 cfg = PSC_SPICFG_CLR_BAUD(cfg);
213 cfg &= ~PSC_SPICFG_SET_DIV(3);
214 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
216 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
219 stat = hw->regs->psc_spistat;
221 } while ((stat & PSC_SPISTAT_DR) == 0);
223 if (hw->pdata->activate_cs)
224 hw->pdata->activate_cs(hw->pdata, spi->chip_select,
230 static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
232 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
236 bpw = t ? t->bits_per_word : spi->bits_per_word;
237 hz = t ? t->speed_hz : spi->max_speed_hz;
239 if (bpw < 4 || bpw > 24) {
240 dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n",
244 if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
245 dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
250 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
252 cfg = hw->regs->psc_spicfg;
254 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
257 if (hw->usedma && bpw <= 8)
258 cfg &= ~PSC_SPICFG_DD_DISABLE;
260 cfg |= PSC_SPICFG_DD_DISABLE;
261 cfg = PSC_SPICFG_CLR_LEN(cfg);
262 cfg |= PSC_SPICFG_SET_LEN(bpw);
264 cfg = PSC_SPICFG_CLR_BAUD(cfg);
265 cfg &= ~PSC_SPICFG_SET_DIV(3);
266 cfg |= au1550_spi_baudcfg(hw, hz);
268 hw->regs->psc_spicfg = cfg;
271 if (cfg & PSC_SPICFG_DE_ENABLE) {
273 stat = hw->regs->psc_spistat;
275 } while ((stat & PSC_SPISTAT_DR) == 0);
278 au1550_spi_reset_fifos(hw);
279 au1550_spi_mask_ack_all(hw);
283 static int au1550_spi_setup(struct spi_device *spi)
285 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
287 if (spi->bits_per_word == 0)
288 spi->bits_per_word = 8;
289 if (spi->bits_per_word < 4 || spi->bits_per_word > 24) {
290 dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n",
295 if (spi->max_speed_hz == 0)
296 spi->max_speed_hz = hw->freq_max;
297 if (spi->max_speed_hz > hw->freq_max
298 || spi->max_speed_hz < hw->freq_min)
301 * NOTE: cannot change speed and other hw settings immediately,
302 * otherwise sharing of spi bus is not possible,
303 * so do not call setupxfer(spi, NULL) here
309 * for dma spi transfers, we have to setup rx channel, otherwise there is
310 * no reliable way how to recognize that spi transfer is done
311 * dma complete callbacks are called before real spi transfer is finished
312 * and if only tx dma channel is set up (and rx fifo overflow event masked)
313 * spi master done event irq is not generated unless rx fifo is empty (emptied)
314 * so we need rx tmp buffer to use for rx dma if user does not provide one
316 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
318 hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
319 if (!hw->dma_rx_tmpbuf)
321 hw->dma_rx_tmpbuf_size = size;
322 hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
323 size, DMA_FROM_DEVICE);
324 if (dma_mapping_error(hw->dma_rx_tmpbuf_addr)) {
325 kfree(hw->dma_rx_tmpbuf);
326 hw->dma_rx_tmpbuf = 0;
327 hw->dma_rx_tmpbuf_size = 0;
333 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
335 dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
336 hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
337 kfree(hw->dma_rx_tmpbuf);
338 hw->dma_rx_tmpbuf = 0;
339 hw->dma_rx_tmpbuf_size = 0;
342 static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
344 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
345 dma_addr_t dma_tx_addr;
346 dma_addr_t dma_rx_addr;
355 dma_tx_addr = t->tx_dma;
356 dma_rx_addr = t->rx_dma;
359 * check if buffers are already dma mapped, map them otherwise
360 * use rx buffer in place of tx if tx buffer was not provided
361 * use temp rx buffer (preallocated or realloc to fit) for rx dma
364 if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
365 dma_rx_addr = dma_map_single(hw->dev,
367 t->len, DMA_FROM_DEVICE);
368 if (dma_mapping_error(dma_rx_addr))
369 dev_err(hw->dev, "rx dma map error\n");
372 if (t->len > hw->dma_rx_tmpbuf_size) {
375 au1550_spi_dma_rxtmp_free(hw);
376 ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
377 AU1550_SPI_DMA_RXTMP_MINSIZE));
381 hw->rx = hw->dma_rx_tmpbuf;
382 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
383 dma_sync_single_for_device(hw->dev, dma_rx_addr,
384 t->len, DMA_FROM_DEVICE);
387 if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
388 dma_tx_addr = dma_map_single(hw->dev,
390 t->len, DMA_TO_DEVICE);
391 if (dma_mapping_error(dma_tx_addr))
392 dev_err(hw->dev, "tx dma map error\n");
395 dma_sync_single_for_device(hw->dev, dma_rx_addr,
396 t->len, DMA_BIDIRECTIONAL);
400 /* put buffers on the ring */
401 res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, hw->rx, t->len);
403 dev_err(hw->dev, "rx dma put dest error\n");
405 res = au1xxx_dbdma_put_source(hw->dma_tx_ch, (void *)hw->tx, t->len);
407 dev_err(hw->dev, "tx dma put source error\n");
409 au1xxx_dbdma_start(hw->dma_rx_ch);
410 au1xxx_dbdma_start(hw->dma_tx_ch);
412 /* by default enable nearly all events interrupt */
413 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
416 /* start the transfer */
417 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
420 wait_for_completion(&hw->master_done);
422 au1xxx_dbdma_stop(hw->dma_tx_ch);
423 au1xxx_dbdma_stop(hw->dma_rx_ch);
426 /* using the temporal preallocated and premapped buffer */
427 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
430 /* unmap buffers if mapped above */
431 if (t->rx_buf && t->rx_dma == 0 )
432 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
434 if (t->tx_buf && t->tx_dma == 0 )
435 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
438 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
441 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
445 stat = hw->regs->psc_spistat;
446 evnt = hw->regs->psc_spievent;
448 if ((stat & PSC_SPISTAT_DI) == 0) {
449 dev_err(hw->dev, "Unexpected IRQ!\n");
453 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
454 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
455 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
458 * due to an spi error we consider transfer as done,
459 * so mask all events until before next transfer start
460 * and stop the possibly running dma immediatelly
462 au1550_spi_mask_ack_all(hw);
463 au1xxx_dbdma_stop(hw->dma_rx_ch);
464 au1xxx_dbdma_stop(hw->dma_tx_ch);
466 /* get number of transfered bytes */
467 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
468 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
470 au1xxx_dbdma_reset(hw->dma_rx_ch);
471 au1xxx_dbdma_reset(hw->dma_tx_ch);
472 au1550_spi_reset_fifos(hw);
475 "Unexpected SPI error: event=0x%x stat=0x%x!\n",
478 complete(&hw->master_done);
482 if ((evnt & PSC_SPIEVNT_MD) != 0) {
483 /* transfer completed successfully */
484 au1550_spi_mask_ack_all(hw);
485 hw->rx_count = hw->len;
486 hw->tx_count = hw->len;
487 complete(&hw->master_done);
493 /* routines to handle different word sizes in pio mode */
494 #define AU1550_SPI_RX_WORD(size, mask) \
495 static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
497 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
500 *(u##size *)hw->rx = (u##size)fifoword; \
501 hw->rx += (size) / 8; \
503 hw->rx_count += (size) / 8; \
506 #define AU1550_SPI_TX_WORD(size, mask) \
507 static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
511 fifoword = *(u##size *)hw->tx & (u32)(mask); \
512 hw->tx += (size) / 8; \
514 hw->tx_count += (size) / 8; \
515 if (hw->tx_count >= hw->len) \
516 fifoword |= PSC_SPITXRX_LC; \
517 hw->regs->psc_spitxrx = fifoword; \
521 AU1550_SPI_RX_WORD(8,0xff)
522 AU1550_SPI_RX_WORD(16,0xffff)
523 AU1550_SPI_RX_WORD(32,0xffffff)
524 AU1550_SPI_TX_WORD(8,0xff)
525 AU1550_SPI_TX_WORD(16,0xffff)
526 AU1550_SPI_TX_WORD(32,0xffffff)
528 static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
531 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
539 /* by default enable nearly all events after filling tx fifo */
540 mask = PSC_SPIMSK_SD;
542 /* fill the transmit FIFO */
543 while (hw->tx_count < hw->len) {
547 if (hw->tx_count >= hw->len) {
548 /* mask tx fifo request interrupt as we are done */
549 mask |= PSC_SPIMSK_TR;
552 stat = hw->regs->psc_spistat;
554 if (stat & PSC_SPISTAT_TF)
558 /* enable event interrupts */
559 hw->regs->psc_spimsk = mask;
562 /* start the transfer */
563 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
566 wait_for_completion(&hw->master_done);
568 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
571 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
576 stat = hw->regs->psc_spistat;
577 evnt = hw->regs->psc_spievent;
579 if ((stat & PSC_SPISTAT_DI) == 0) {
580 dev_err(hw->dev, "Unexpected IRQ!\n");
584 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
585 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
586 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
589 "Unexpected SPI error: event=0x%x stat=0x%x!\n",
592 * due to an error we consider transfer as done,
593 * so mask all events until before next transfer start
595 au1550_spi_mask_ack_all(hw);
596 au1550_spi_reset_fifos(hw);
597 complete(&hw->master_done);
602 * while there is something to read from rx fifo
603 * or there is a space to write to tx fifo:
607 stat = hw->regs->psc_spistat;
610 if ((stat & PSC_SPISTAT_RE) == 0 && hw->rx_count < hw->len) {
612 /* ack the receive request event */
613 hw->regs->psc_spievent = PSC_SPIEVNT_RR;
618 if ((stat & PSC_SPISTAT_TF) == 0 && hw->tx_count < hw->len) {
620 /* ack the transmit request event */
621 hw->regs->psc_spievent = PSC_SPIEVNT_TR;
627 evnt = hw->regs->psc_spievent;
630 if (hw->rx_count >= hw->len || (evnt & PSC_SPIEVNT_MD) != 0) {
631 /* transfer completed successfully */
632 au1550_spi_mask_ack_all(hw);
633 complete(&hw->master_done);
638 static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
640 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
641 return hw->txrx_bufs(spi, t);
644 static irqreturn_t au1550_spi_irq(int irq, void *dev, struct pt_regs *regs)
646 struct au1550_spi *hw = dev;
647 return hw->irq_callback(hw);
650 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
654 hw->txrx_bufs = &au1550_spi_dma_txrxb;
655 hw->irq_callback = &au1550_spi_dma_irq_callback;
657 hw->rx_word = &au1550_spi_rx_word_8;
658 hw->tx_word = &au1550_spi_tx_word_8;
659 hw->txrx_bufs = &au1550_spi_pio_txrxb;
660 hw->irq_callback = &au1550_spi_pio_irq_callback;
662 } else if (bpw <= 16) {
663 hw->rx_word = &au1550_spi_rx_word_16;
664 hw->tx_word = &au1550_spi_tx_word_16;
665 hw->txrx_bufs = &au1550_spi_pio_txrxb;
666 hw->irq_callback = &au1550_spi_pio_irq_callback;
668 hw->rx_word = &au1550_spi_rx_word_32;
669 hw->tx_word = &au1550_spi_tx_word_32;
670 hw->txrx_bufs = &au1550_spi_pio_txrxb;
671 hw->irq_callback = &au1550_spi_pio_irq_callback;
675 static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
679 /* set up the PSC for SPI mode */
680 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
682 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
685 hw->regs->psc_spicfg = 0;
688 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
692 stat = hw->regs->psc_spistat;
694 } while ((stat & PSC_SPISTAT_SR) == 0);
697 cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
698 cfg |= PSC_SPICFG_SET_LEN(8);
699 cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
700 /* use minimal allowed brg and div values as initial setting: */
701 cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
703 #ifdef AU1550_SPI_DEBUG_LOOPBACK
704 cfg |= PSC_SPICFG_LB;
707 hw->regs->psc_spicfg = cfg;
710 au1550_spi_mask_ack_all(hw);
712 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
716 stat = hw->regs->psc_spistat;
718 } while ((stat & PSC_SPISTAT_DR) == 0);
722 static int __init au1550_spi_probe(struct platform_device *pdev)
724 struct au1550_spi *hw;
725 struct spi_master *master;
728 master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
729 if (master == NULL) {
730 dev_err(&pdev->dev, "No memory for spi_master\n");
735 hw = spi_master_get_devdata(master);
737 hw->master = spi_master_get(master);
738 hw->pdata = pdev->dev.platform_data;
739 hw->dev = &pdev->dev;
741 if (hw->pdata == NULL) {
742 dev_err(&pdev->dev, "No platform data supplied\n");
747 platform_set_drvdata(pdev, hw);
749 init_completion(&hw->master_done);
751 hw->bitbang.master = hw->master;
752 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
753 hw->bitbang.chipselect = au1550_spi_chipsel;
754 hw->bitbang.master->setup = au1550_spi_setup;
755 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
757 switch (hw->pdata->bus_num) {
759 hw->irq = AU1550_PSC0_INT;
760 hw->regs = (volatile psc_spi_t *)PSC0_BASE_ADDR;
761 hw->dma_rx_id = DSCR_CMD0_PSC0_RX;
762 hw->dma_tx_id = DSCR_CMD0_PSC0_TX;
765 hw->irq = AU1550_PSC1_INT;
766 hw->regs = (volatile psc_spi_t *)PSC1_BASE_ADDR;
767 hw->dma_rx_id = DSCR_CMD0_PSC1_RX;
768 hw->dma_tx_id = DSCR_CMD0_PSC1_TX;
771 hw->irq = AU1550_PSC2_INT;
772 hw->regs = (volatile psc_spi_t *)PSC2_BASE_ADDR;
773 hw->dma_rx_id = DSCR_CMD0_PSC2_RX;
774 hw->dma_tx_id = DSCR_CMD0_PSC2_TX;
777 hw->irq = AU1550_PSC3_INT;
778 hw->regs = (volatile psc_spi_t *)PSC3_BASE_ADDR;
779 hw->dma_rx_id = DSCR_CMD0_PSC3_RX;
780 hw->dma_tx_id = DSCR_CMD0_PSC3_TX;
783 dev_err(&pdev->dev, "Wrong bus_num of SPI\n");
788 if (request_mem_region((unsigned long)hw->regs, sizeof(psc_spi_t),
789 pdev->name) == NULL) {
790 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
797 if (pdev->dev.dma_mask == NULL)
798 dev_warn(&pdev->dev, "no dma mask\n");
805 * create memory device with 8 bits dev_devwidth
806 * needed for proper byte ordering to spi fifo
808 int memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
811 "Cannot create dma 8 bit mem device\n");
813 goto err_dma_add_dev;
816 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(memid,
817 hw->dma_tx_id, NULL, (void *)hw);
818 if (hw->dma_tx_ch == 0) {
820 "Cannot allocate tx dma channel\n");
824 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
825 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
826 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
828 "Cannot allocate tx dma descriptors\n");
830 goto err_no_txdma_descr;
834 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
835 memid, NULL, (void *)hw);
836 if (hw->dma_rx_ch == 0) {
838 "Cannot allocate rx dma channel\n");
842 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
843 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
844 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
846 "Cannot allocate rx dma descriptors\n");
848 goto err_no_rxdma_descr;
851 err = au1550_spi_dma_rxtmp_alloc(hw,
852 AU1550_SPI_DMA_RXTMP_MINSIZE);
855 "Cannot allocate initial rx dma tmp buffer\n");
856 goto err_dma_rxtmp_alloc;
860 au1550_spi_bits_handlers_set(hw, 8);
862 err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
864 dev_err(&pdev->dev, "Cannot claim IRQ\n");
868 master->bus_num = hw->pdata->bus_num;
869 master->num_chipselect = hw->pdata->num_chipselect;
872 * precompute valid range for spi freq - from au1550 datasheet:
873 * psc_tempclk = psc_mainclk / (2 << DIV)
874 * spiclk = psc_tempclk / (2 * (BRG + 1))
875 * BRG valid range is 4..63
876 * DIV valid range is 0..3
877 * round the min and max frequencies to values that would still
878 * produce valid brg and div
881 int min_div = (2 << 0) * (2 * (4 + 1));
882 int max_div = (2 << 3) * (2 * (63 + 1));
883 hw->freq_max = hw->pdata->mainclk_hz / min_div;
884 hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1;
887 au1550_spi_setup_psc_as_spi(hw);
889 err = spi_bitbang_start(&hw->bitbang);
891 dev_err(&pdev->dev, "Failed to register SPI master\n");
896 "spi master registered: bus_num=%d num_chipselect=%d\n",
897 master->bus_num, master->num_chipselect);
902 free_irq(hw->irq, hw);
905 au1550_spi_dma_rxtmp_free(hw);
910 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
915 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
919 release_mem_region((unsigned long)hw->regs, sizeof(psc_spi_t));
923 spi_master_put(hw->master);
929 static int __exit au1550_spi_remove(struct platform_device *pdev)
931 struct au1550_spi *hw = platform_get_drvdata(pdev);
933 dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
934 hw->master->bus_num);
936 spi_bitbang_stop(&hw->bitbang);
937 free_irq(hw->irq, hw);
938 release_mem_region((unsigned long)hw->regs, sizeof(psc_spi_t));
941 au1550_spi_dma_rxtmp_free(hw);
942 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
943 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
946 platform_set_drvdata(pdev, NULL);
948 spi_master_put(hw->master);
952 static struct platform_driver au1550_spi_drv = {
953 .remove = __exit_p(au1550_spi_remove),
955 .name = "au1550-spi",
956 .owner = THIS_MODULE,
960 static int __init au1550_spi_init(void)
962 return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe);
964 module_init(au1550_spi_init);
966 static void __exit au1550_spi_exit(void)
968 platform_driver_unregister(&au1550_spi_drv);
970 module_exit(au1550_spi_exit);
972 MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
973 MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
974 MODULE_LICENSE("GPL");