2 * VIA AGPGART routines.
5 #include <linux/types.h>
6 #include <linux/module.h>
8 #include <linux/init.h>
9 #include <linux/agp_backend.h>
12 static const struct pci_device_id agp_via_pci_table[];
14 #define VIA_GARTCTRL 0x80
15 #define VIA_APSIZE 0x84
16 #define VIA_ATTBASE 0x88
18 #define VIA_AGP3_GARTCTRL 0x90
19 #define VIA_AGP3_APSIZE 0x94
20 #define VIA_AGP3_ATTBASE 0x98
21 #define VIA_AGPSEL 0xfd
23 static int via_fetch_size(void)
27 struct aper_size_info_8 *values;
29 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
30 pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);
31 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
32 if (temp == values[i].size_value) {
33 agp_bridge->previous_size =
34 agp_bridge->current_size = (void *) (values + i);
35 agp_bridge->aperture_size_idx = i;
36 return values[i].size;
39 printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp);
44 static int via_configure(void)
47 struct aper_size_info_8 *current_size;
49 current_size = A_SIZE_8(agp_bridge->current_size);
51 pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
52 current_size->size_value);
53 /* address to map too */
54 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
55 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
57 /* GART control register */
58 pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
60 /* attbase - aperture GATT base */
61 pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,
62 (agp_bridge->gatt_bus_addr & 0xfffff000) | 3);
67 static void via_cleanup(void)
69 struct aper_size_info_8 *previous_size;
71 previous_size = A_SIZE_8(agp_bridge->previous_size);
72 pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
73 previous_size->size_value);
74 /* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
75 * during reinitialization.
80 static void via_tlbflush(struct agp_memory *mem)
84 pci_read_config_dword(agp_bridge->dev, VIA_GARTCTRL, &temp);
86 pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
88 pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
92 static const struct aper_size_info_8 via_generic_sizes[9] =
106 static int via_fetch_size_agp3(void)
110 struct aper_size_info_16 *values;
112 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
113 pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp);
116 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
117 if (temp == values[i].size_value) {
118 agp_bridge->previous_size =
119 agp_bridge->current_size = (void *) (values + i);
120 agp_bridge->aperture_size_idx = i;
121 return values[i].size;
128 static int via_configure_agp3(void)
131 struct aper_size_info_16 *current_size;
133 current_size = A_SIZE_16(agp_bridge->current_size);
135 /* address to map too */
136 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
137 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
139 /* attbase - aperture GATT base */
140 pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
141 agp_bridge->gatt_bus_addr & 0xfffff000);
143 /* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch
144 * translation table first.
145 * 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the
146 * graphics AGP aperture for the AGP3.0 port.
148 pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
149 pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp | (3<<7));
154 static void via_cleanup_agp3(void)
156 struct aper_size_info_16 *previous_size;
158 previous_size = A_SIZE_16(agp_bridge->previous_size);
159 pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value);
163 static void via_tlbflush_agp3(struct agp_memory *mem)
167 pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
168 pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
169 pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp);
173 static const struct agp_bridge_driver via_agp3_driver = {
174 .owner = THIS_MODULE,
175 .aperture_sizes = agp3_generic_sizes,
176 .size_type = U8_APER_SIZE,
177 .num_aperture_sizes = 10,
178 .configure = via_configure_agp3,
179 .fetch_size = via_fetch_size_agp3,
180 .cleanup = via_cleanup_agp3,
181 .tlb_flush = via_tlbflush_agp3,
182 .mask_memory = agp_generic_mask_memory,
184 .agp_enable = agp_generic_enable,
185 .cache_flush = global_cache_flush,
186 .create_gatt_table = agp_generic_create_gatt_table,
187 .free_gatt_table = agp_generic_free_gatt_table,
188 .insert_memory = agp_generic_insert_memory,
189 .remove_memory = agp_generic_remove_memory,
190 .alloc_by_type = agp_generic_alloc_by_type,
191 .free_by_type = agp_generic_free_by_type,
192 .agp_alloc_page = agp_generic_alloc_page,
193 .agp_destroy_page = agp_generic_destroy_page,
194 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
197 static const struct agp_bridge_driver via_driver = {
198 .owner = THIS_MODULE,
199 .aperture_sizes = via_generic_sizes,
200 .size_type = U8_APER_SIZE,
201 .num_aperture_sizes = 9,
202 .configure = via_configure,
203 .fetch_size = via_fetch_size,
204 .cleanup = via_cleanup,
205 .tlb_flush = via_tlbflush,
206 .mask_memory = agp_generic_mask_memory,
208 .agp_enable = agp_generic_enable,
209 .cache_flush = global_cache_flush,
210 .create_gatt_table = agp_generic_create_gatt_table,
211 .free_gatt_table = agp_generic_free_gatt_table,
212 .insert_memory = agp_generic_insert_memory,
213 .remove_memory = agp_generic_remove_memory,
214 .alloc_by_type = agp_generic_alloc_by_type,
215 .free_by_type = agp_generic_free_by_type,
216 .agp_alloc_page = agp_generic_alloc_page,
217 .agp_destroy_page = agp_generic_destroy_page,
218 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
221 static struct agp_device_ids via_agp_device_ids[] __devinitdata =
224 .device_id = PCI_DEVICE_ID_VIA_82C597_0,
225 .chipset_name = "Apollo VP3",
229 .device_id = PCI_DEVICE_ID_VIA_82C598_0,
230 .chipset_name = "Apollo MVP3",
234 .device_id = PCI_DEVICE_ID_VIA_8501_0,
235 .chipset_name = "Apollo MVP4",
240 .device_id = PCI_DEVICE_ID_VIA_8601_0,
241 .chipset_name = "Apollo ProMedia/PLE133Ta",
244 /* VT82C693A / VT28C694T */
246 .device_id = PCI_DEVICE_ID_VIA_82C691_0,
247 .chipset_name = "Apollo Pro 133",
251 .device_id = PCI_DEVICE_ID_VIA_8371_0,
252 .chipset_name = "KX133",
257 .device_id = PCI_DEVICE_ID_VIA_8633_0,
258 .chipset_name = "Pro 266",
262 .device_id = PCI_DEVICE_ID_VIA_XN266,
263 .chipset_name = "Apollo Pro266",
268 .device_id = PCI_DEVICE_ID_VIA_8361,
269 .chipset_name = "KLE133",
272 /* VT8365 / VT8362 */
274 .device_id = PCI_DEVICE_ID_VIA_8363_0,
275 .chipset_name = "Twister-K/KT133x/KM133",
280 .device_id = PCI_DEVICE_ID_VIA_8753_0,
281 .chipset_name = "P4X266",
286 .device_id = PCI_DEVICE_ID_VIA_8367_0,
287 .chipset_name = "KT266/KY266x/KT333",
290 /* VT8633 (for CuMine/ Celeron) */
292 .device_id = PCI_DEVICE_ID_VIA_8653_0,
293 .chipset_name = "Pro266T",
298 .device_id = PCI_DEVICE_ID_VIA_XM266,
299 .chipset_name = "PM266/KM266",
304 .device_id = PCI_DEVICE_ID_VIA_862X_0,
305 .chipset_name = "CLE266",
309 .device_id = PCI_DEVICE_ID_VIA_8377_0,
310 .chipset_name = "KT400/KT400A/KT600",
313 /* VT8604 / VT8605 / VT8603
314 * (Apollo Pro133A chipset with S3 Savage4) */
316 .device_id = PCI_DEVICE_ID_VIA_8605_0,
317 .chipset_name = "ProSavage PM133/PL133/PN133"
322 .device_id = PCI_DEVICE_ID_VIA_8703_51_0,
323 .chipset_name = "P4M266x/P4N266",
328 .device_id = PCI_DEVICE_ID_VIA_8754C_0,
329 .chipset_name = "PT800",
334 .device_id = PCI_DEVICE_ID_VIA_8763_0,
335 .chipset_name = "P4X600"
340 .device_id = PCI_DEVICE_ID_VIA_8378_0,
341 .chipset_name = "KM400/KM400A",
346 .device_id = PCI_DEVICE_ID_VIA_PT880,
347 .chipset_name = "PT880",
352 .device_id = PCI_DEVICE_ID_VIA_PT880ULTRA,
353 .chipset_name = "PT880 Ultra",
358 .device_id = PCI_DEVICE_ID_VIA_8783_0,
359 .chipset_name = "PT890",
362 /* PM800/PN800/PM880/PN880 */
364 .device_id = PCI_DEVICE_ID_VIA_PX8X0_0,
365 .chipset_name = "PM800/PN800/PM880/PN880",
369 .device_id = PCI_DEVICE_ID_VIA_3269_0,
370 .chipset_name = "KT880",
374 .device_id = PCI_DEVICE_ID_VIA_83_87XX_1,
375 .chipset_name = "VT83xx/VT87xx/KTxxx/Px8xx",
379 .device_id = PCI_DEVICE_ID_VIA_3296_0,
380 .chipset_name = "P4M800",
384 .device_id = PCI_DEVICE_ID_VIA_P4M800CE,
385 .chipset_name = "VT3314",
389 .device_id = PCI_DEVICE_ID_VIA_CX700,
390 .chipset_name = "CX700",
394 .device_id = PCI_DEVICE_ID_VIA_VT3336,
395 .chipset_name = "VT3336",
399 .device_id = PCI_DEVICE_ID_VIA_P4M890,
400 .chipset_name = "P4M890",
402 { }, /* dummy final entry, always present */
407 * VIA's AGP3 chipsets do magick to put the AGP bridge compliant
408 * with the same standards version as the graphics card.
410 static void check_via_agp3 (struct agp_bridge_data *bridge)
414 pci_read_config_byte(bridge->dev, VIA_AGPSEL, ®);
415 /* Check AGP 2.0 compatibility mode. */
416 if ((reg & (1<<1))==0)
417 bridge->driver = &via_agp3_driver;
421 static int __devinit agp_via_probe(struct pci_dev *pdev,
422 const struct pci_device_id *ent)
424 struct agp_device_ids *devs = via_agp_device_ids;
425 struct agp_bridge_data *bridge;
429 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
433 j = ent - agp_via_pci_table;
434 printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name);
436 bridge = agp_alloc_bridge();
441 bridge->capndx = cap_ptr;
442 bridge->driver = &via_driver;
445 * Garg, there are KT400s with KT266 IDs.
447 if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
448 /* Is there a KT400 subsystem ? */
449 if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) {
450 printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
451 check_via_agp3(bridge);
455 /* If this is an AGP3 bridge, check which mode its in and adjust. */
456 get_agp_version(bridge);
457 if (bridge->major_version >= 3)
458 check_via_agp3(bridge);
460 /* Fill in the mode register */
461 pci_read_config_dword(pdev,
462 bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
464 pci_set_drvdata(pdev, bridge);
465 return agp_add_bridge(bridge);
468 static void __devexit agp_via_remove(struct pci_dev *pdev)
470 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
472 agp_remove_bridge(bridge);
473 agp_put_bridge(bridge);
478 static int agp_via_suspend(struct pci_dev *pdev, pm_message_t state)
480 pci_save_state (pdev);
481 pci_set_power_state (pdev, PCI_D3hot);
486 static int agp_via_resume(struct pci_dev *pdev)
488 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
490 pci_set_power_state (pdev, PCI_D0);
491 pci_restore_state(pdev);
493 if (bridge->driver == &via_agp3_driver)
494 return via_configure_agp3();
495 else if (bridge->driver == &via_driver)
496 return via_configure();
501 #endif /* CONFIG_PM */
503 /* must be the same order as name table above */
504 static const struct pci_device_id agp_via_pci_table[] = {
507 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
509 .vendor = PCI_VENDOR_ID_VIA, \
511 .subvendor = PCI_ANY_ID, \
512 .subdevice = PCI_ANY_ID, \
514 ID(PCI_DEVICE_ID_VIA_82C597_0),
515 ID(PCI_DEVICE_ID_VIA_82C598_0),
516 ID(PCI_DEVICE_ID_VIA_8501_0),
517 ID(PCI_DEVICE_ID_VIA_8601_0),
518 ID(PCI_DEVICE_ID_VIA_82C691_0),
519 ID(PCI_DEVICE_ID_VIA_8371_0),
520 ID(PCI_DEVICE_ID_VIA_8633_0),
521 ID(PCI_DEVICE_ID_VIA_XN266),
522 ID(PCI_DEVICE_ID_VIA_8361),
523 ID(PCI_DEVICE_ID_VIA_8363_0),
524 ID(PCI_DEVICE_ID_VIA_8753_0),
525 ID(PCI_DEVICE_ID_VIA_8367_0),
526 ID(PCI_DEVICE_ID_VIA_8653_0),
527 ID(PCI_DEVICE_ID_VIA_XM266),
528 ID(PCI_DEVICE_ID_VIA_862X_0),
529 ID(PCI_DEVICE_ID_VIA_8377_0),
530 ID(PCI_DEVICE_ID_VIA_8605_0),
531 ID(PCI_DEVICE_ID_VIA_8703_51_0),
532 ID(PCI_DEVICE_ID_VIA_8754C_0),
533 ID(PCI_DEVICE_ID_VIA_8763_0),
534 ID(PCI_DEVICE_ID_VIA_8378_0),
535 ID(PCI_DEVICE_ID_VIA_PT880),
536 ID(PCI_DEVICE_ID_VIA_PT880ULTRA),
537 ID(PCI_DEVICE_ID_VIA_8783_0),
538 ID(PCI_DEVICE_ID_VIA_PX8X0_0),
539 ID(PCI_DEVICE_ID_VIA_3269_0),
540 ID(PCI_DEVICE_ID_VIA_83_87XX_1),
541 ID(PCI_DEVICE_ID_VIA_3296_0),
542 ID(PCI_DEVICE_ID_VIA_P4M800CE),
543 ID(PCI_DEVICE_ID_VIA_CX700),
544 ID(PCI_DEVICE_ID_VIA_VT3336),
545 ID(PCI_DEVICE_ID_VIA_P4M890),
549 MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
552 static struct pci_driver agp_via_pci_driver = {
553 .name = "agpgart-via",
554 .id_table = agp_via_pci_table,
555 .probe = agp_via_probe,
556 .remove = agp_via_remove,
558 .suspend = agp_via_suspend,
559 .resume = agp_via_resume,
564 static int __init agp_via_init(void)
568 return pci_register_driver(&agp_via_pci_driver);
571 static void __exit agp_via_cleanup(void)
573 pci_unregister_driver(&agp_via_pci_driver);
576 module_init(agp_via_init);
577 module_exit(agp_via_cleanup);
579 MODULE_LICENSE("GPL");
580 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");