2 * arch/m68k/q40/config.c
4 * Copyright (C) 1999 Richard Zidlicky
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file README.legal in the main directory of this archive
15 #include <linux/types.h>
16 #include <linux/kernel.h>
18 #include <linux/tty.h>
19 #include <linux/console.h>
20 #include <linux/linkage.h>
21 #include <linux/init.h>
22 #include <linux/major.h>
23 #include <linux/serial_reg.h>
24 #include <linux/rtc.h>
25 #include <linux/vt_kern.h>
29 #include <asm/bootinfo.h>
30 #include <asm/system.h>
31 #include <asm/pgtable.h>
32 #include <asm/setup.h>
34 #include <asm/traps.h>
35 #include <asm/machdep.h>
36 #include <asm/q40_master.h>
38 extern irqreturn_t q40_process_int (int level, struct pt_regs *regs);
39 extern void q40_init_IRQ (void);
40 static void q40_get_model(char *model);
41 static int q40_get_hardware_list(char *buffer);
42 extern void q40_sched_init(irqreturn_t (*handler)(int, void *, struct pt_regs *));
44 extern unsigned long q40_gettimeoffset (void);
45 extern int q40_hwclk (int, struct rtc_time *);
46 extern unsigned int q40_get_ss (void);
47 extern int q40_set_clock_mmss (unsigned long);
48 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
49 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
50 extern void q40_reset (void);
52 extern void q40_waitbut(void);
53 void q40_set_vectors (void);
55 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/ );
57 extern char m68k_debug_device[];
58 static void q40_mem_console_write(struct console *co, const char *b,
63 static struct console q40_console_driver = {
65 .flags = CON_PRINTBUFFER,
70 /* early debugging function:*/
71 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
74 static void q40_mem_console_write(struct console *co, const char *s,
87 void printq40(char *str)
92 while (l-- >0 && _cpleft-- >0)
103 #ifdef CONFIG_HEARTBEAT
104 static void q40_heartbeat(int on)
118 printk ("\n\n*******************************************\n"
119 "Called q40_reset : press the RESET button!! \n"
120 "*******************************************\n");
127 printk ("\n\n*******************\n"
129 "*******************\n");
134 static void q40_get_model(char *model)
136 sprintf(model, "Q40");
139 /* No hardware options on Q40? */
141 static int q40_get_hardware_list(char *buffer)
147 static unsigned int serports[]={0x3f8,0x2f8,0x3e8,0x2e8,0};
148 void q40_disable_irqs(void)
153 while((i=serports[j++])) outb(0,i+UART_IER);
154 master_outb(0,EXT_ENABLE_REG);
155 master_outb(0,KEY_IRQ_ENABLE_REG);
158 void __init config_q40(void)
160 mach_sched_init = q40_sched_init;
162 mach_init_IRQ = q40_init_IRQ;
163 mach_gettimeoffset = q40_gettimeoffset;
164 mach_hwclk = q40_hwclk;
165 mach_get_ss = q40_get_ss;
166 mach_get_rtc_pll = q40_get_rtc_pll;
167 mach_set_rtc_pll = q40_set_rtc_pll;
168 mach_set_clock_mmss = q40_set_clock_mmss;
170 mach_reset = q40_reset;
171 mach_get_model = q40_get_model;
172 mach_get_hardware_list = q40_get_hardware_list;
174 #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE)
175 mach_beep = q40_mksound;
177 #ifdef CONFIG_HEARTBEAT
178 mach_heartbeat = q40_heartbeat;
180 mach_halt = q40_halt;
182 /* disable a few things that SMSQ might have left enabled */
185 /* no DMA at all, but ide-scsi requires it.. make sure
186 * all physical RAM fits into the boundary - otherwise
187 * allocator may play costly and useless tricks */
188 mach_max_dma_address = 1024*1024*1024;
190 /* useful for early debugging stages - writes kernel messages into SRAM */
191 if (!strncmp( m68k_debug_device,"mem",3 ))
193 /*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
194 _cpleft=2000-((long)q40_mem_cptr-0xff020000)/4;
195 q40_console_driver.write = q40_mem_console_write;
196 register_console(&q40_console_driver);
201 int q40_parse_bootinfo(const struct bi_record *rec)
207 static inline unsigned char bcd2bin (unsigned char b)
209 return ((b>>4)*10 + (b&15));
212 static inline unsigned char bin2bcd (unsigned char b)
214 return (((b/10)*16) + (b%10));
218 unsigned long q40_gettimeoffset (void)
220 return 5000*(ql_ticks!=0);
225 * Looks like op is non-zero for setting the clock, and zero for
228 * struct hwclk_time {
229 * unsigned sec; 0..59
230 * unsigned min; 0..59
231 * unsigned hour; 0..23
232 * unsigned day; 1..31
233 * unsigned mon; 0..11
234 * unsigned year; 00...
235 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set
239 int q40_hwclk(int op, struct rtc_time *t)
243 Q40_RTC_CTRL |= Q40_RTC_WRITE;
245 Q40_RTC_SECS = bin2bcd(t->tm_sec);
246 Q40_RTC_MINS = bin2bcd(t->tm_min);
247 Q40_RTC_HOUR = bin2bcd(t->tm_hour);
248 Q40_RTC_DATE = bin2bcd(t->tm_mday);
249 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
250 Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
252 Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
254 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
258 Q40_RTC_CTRL |= Q40_RTC_READ;
260 t->tm_year = bcd2bin (Q40_RTC_YEAR);
261 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1;
262 t->tm_mday = bcd2bin (Q40_RTC_DATE);
263 t->tm_hour = bcd2bin (Q40_RTC_HOUR);
264 t->tm_min = bcd2bin (Q40_RTC_MINS);
265 t->tm_sec = bcd2bin (Q40_RTC_SECS);
267 Q40_RTC_CTRL &= ~(Q40_RTC_READ);
271 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
278 unsigned int q40_get_ss(void)
280 return bcd2bin(Q40_RTC_SECS);
284 * Set the minutes and seconds from seconds value 'nowtime'. Fail if
285 * clock is out by > 30 minutes. Logic lifted from atari code.
288 int q40_set_clock_mmss (unsigned long nowtime)
291 short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60;
296 rtc_minutes = bcd2bin (Q40_RTC_MINS);
298 if ((rtc_minutes < real_minutes
299 ? real_minutes - rtc_minutes
300 : rtc_minutes - real_minutes) < 30)
302 Q40_RTC_CTRL |= Q40_RTC_WRITE;
303 Q40_RTC_MINS = bin2bcd(real_minutes);
304 Q40_RTC_SECS = bin2bcd(real_seconds);
305 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
315 /* get and set PLL calibration of RTC clock */
316 #define Q40_RTC_PLL_MASK ((1<<5)-1)
317 #define Q40_RTC_PLL_SIGN (1<<5)
319 static int q40_get_rtc_pll(struct rtc_pll_info *pll)
321 int tmp=Q40_RTC_CTRL;
322 pll->pll_value = tmp & Q40_RTC_PLL_MASK;
323 if (tmp & Q40_RTC_PLL_SIGN)
324 pll->pll_value = -pll->pll_value;
327 pll->pll_posmult=512;
328 pll->pll_negmult=256;
329 pll->pll_clock=125829120;
333 static int q40_set_rtc_pll(struct rtc_pll_info *pll)
336 /* the docs are a bit unclear so I am doublesetting */
337 /* RTC_WRITE here ... */
338 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
340 Q40_RTC_CTRL |= Q40_RTC_WRITE;
342 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);