git.oblomov.eu Git - linux-2.6/blob - arch/x86/kernel/genx2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpu.h>
  14 #include <linux/cpumask.h>
  15 #include <linux/string.h>
  16 #include <linux/ctype.h>
  17 #include <linux/init.h>
  18 #include <linux/sched.h>
  19 #include <linux/module.h>
  20 #include <linux/hardirq.h>
  21 #include <linux/timer.h>
  22 #include <linux/proc_fs.h>
  23 #include <asm/current.h>
  24 #include <asm/smp.h>
  25 #include <asm/ipi.h>
  26 #include <asm/genapic.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/uv/uv_mmrs.h>
  29 #include <asm/uv/uv_hub.h>
  30 #include <asm/uv/bios.h>
  31
  32 DEFINE_PER_CPU(int, x2apic_extra_bits);
  33
  34 static enum uv_system_type uv_system_type;
  35
  36 static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  37 {
  38         if (!strcmp(oem_id, "SGI")) {
  39                 if (!strcmp(oem_table_id, "UVL"))
  40                         uv_system_type = UV_LEGACY_APIC;
  41                 else if (!strcmp(oem_table_id, "UVX"))
  42                         uv_system_type = UV_X2APIC;
  43                 else if (!strcmp(oem_table_id, "UVH")) {
  44                         uv_system_type = UV_NON_UNIQUE_APIC;
  45                         return 1;
  46                 }
  47         }
  48         return 0;
  49 }
  50
  51 enum uv_system_type get_uv_system_type(void)
  52 {
  53         return uv_system_type;
  54 }
  55
  56 int is_uv_system(void)
  57 {
  58         return uv_system_type != UV_NONE;
  59 }
  60 EXPORT_SYMBOL_GPL(is_uv_system);
  61
  62 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  63 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  64
  65 struct uv_blade_info *uv_blade_info;
  66 EXPORT_SYMBOL_GPL(uv_blade_info);
  67
  68 short *uv_node_to_blade;
  69 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  70
  71 short *uv_cpu_to_blade;
  72 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  73
  74 short uv_possible_blades;
  75 EXPORT_SYMBOL_GPL(uv_possible_blades);
  76
  77 unsigned long sn_rtc_cycles_per_second;
  78 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  79
  80 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  81
  82 static cpumask_t uv_target_cpus(void)
  83 {
  84         return cpumask_of_cpu(0);
  85 }
  86
  87 static cpumask_t uv_vector_allocation_domain(int cpu)
  88 {
  89         cpumask_t domain = CPU_MASK_NONE;
  90         cpu_set(cpu, domain);
  91         return domain;
  92 }
  93
  94 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
  95 {
  96         unsigned long val;
  97         int pnode;
  98
  99         pnode = uv_apicid_to_pnode(phys_apicid);
 100         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 101             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 102             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 103             APIC_DM_INIT;
 104         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 105         mdelay(10);
 106
 107         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 108             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 109             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 110             APIC_DM_STARTUP;
 111         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 112         return 0;
 113 }
 114
 115 static void uv_send_IPI_one(int cpu, int vector)
 116 {
 117         unsigned long val, apicid, lapicid;
 118         int pnode;
 119
 120         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 121         lapicid = apicid & 0x3f;                /* ZZZ macro needed */
 122         pnode = uv_apicid_to_pnode(apicid);
 123         val =
 124             (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
 125                                               UVH_IPI_INT_APIC_ID_SHFT) |
 126             (vector << UVH_IPI_INT_VECTOR_SHFT);
 127         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 128 }
 129
 130 static void uv_send_IPI_mask(cpumask_t mask, int vector)
 131 {
 132         unsigned int cpu;
 133
 134         for_each_possible_cpu(cpu)
 135                 if (cpu_isset(cpu, mask))
 136                         uv_send_IPI_one(cpu, vector);
 137 }
 138
 139 static void uv_send_IPI_allbutself(int vector)
 140 {
 141         cpumask_t mask = cpu_online_map;
 142
 143         cpu_clear(smp_processor_id(), mask);
 144
 145         if (!cpus_empty(mask))
 146                 uv_send_IPI_mask(mask, vector);
 147 }
 148
 149 static void uv_send_IPI_all(int vector)
 150 {
 151         uv_send_IPI_mask(cpu_online_map, vector);
 152 }
 153
 154 static int uv_apic_id_registered(void)
 155 {
 156         return 1;
 157 }
 158
 159 static void uv_init_apic_ldr(void)
 160 {
 161 }
 162
 163 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
 164 {
 165         int cpu;
 166
 167         /*
 168          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 169          * May as well be the first.
 170          */
 171         cpu = first_cpu(cpumask);
 172         if ((unsigned)cpu < nr_cpu_ids)
 173                 return per_cpu(x86_cpu_to_apicid, cpu);
 174         else
 175                 return BAD_APICID;
 176 }
 177
 178 static unsigned int get_apic_id(unsigned long x)
 179 {
 180         unsigned int id;
 181
 182         WARN_ON(preemptible() && num_online_cpus() > 1);
 183         id = x | __get_cpu_var(x2apic_extra_bits);
 184
 185         return id;
 186 }
 187
 188 static unsigned long set_apic_id(unsigned int id)
 189 {
 190         unsigned long x;
 191
 192         /* maskout x2apic_extra_bits ? */
 193         x = id;
 194         return x;
 195 }
 196
 197 static unsigned int uv_read_apic_id(void)
 198 {
 199
 200         return get_apic_id(apic_read(APIC_ID));
 201 }
 202
 203 static unsigned int phys_pkg_id(int index_msb)
 204 {
 205         return uv_read_apic_id() >> index_msb;
 206 }
 207
 208 static void uv_send_IPI_self(int vector)
 209 {
 210         apic_write(APIC_SELF_IPI, vector);
 211 }
 212
 213 struct genapic apic_x2apic_uv_x = {
 214         .name = "UV large system",
 215         .acpi_madt_oem_check = uv_acpi_madt_oem_check,
 216         .int_delivery_mode = dest_Fixed,
 217         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 218         .target_cpus = uv_target_cpus,
 219         .vector_allocation_domain = uv_vector_allocation_domain,
 220         .apic_id_registered = uv_apic_id_registered,
 221         .init_apic_ldr = uv_init_apic_ldr,
 222         .send_IPI_all = uv_send_IPI_all,
 223         .send_IPI_allbutself = uv_send_IPI_allbutself,
 224         .send_IPI_mask = uv_send_IPI_mask,
 225         .send_IPI_self = uv_send_IPI_self,
 226         .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
 227         .phys_pkg_id = phys_pkg_id,
 228         .get_apic_id = get_apic_id,
 229         .set_apic_id = set_apic_id,
 230         .apic_id_mask = (0xFFFFFFFFu),
 231 };
 232
 233 static __cpuinit void set_x2apic_extra_bits(int pnode)
 234 {
 235         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 236 }
 237
 238 /*
 239  * Called on boot cpu.
 240  */
 241 static __init int boot_pnode_to_blade(int pnode)
 242 {
 243         int blade;
 244
 245         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 246                 if (pnode == uv_blade_info[blade].pnode)
 247                         return blade;
 248         BUG();
 249 }
 250
 251 struct redir_addr {
 252         unsigned long redirect;
 253         unsigned long alias;
 254 };
 255
 256 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 257
 258 static __initdata struct redir_addr redir_addrs[] = {
 259         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 260         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 261         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 262 };
 263
 264 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 265 {
 266         union uvh_si_alias0_overlay_config_u alias;
 267         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 268         int i;
 269
 270         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 271                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 272                 if (alias.s.base == 0) {
 273                         *size = (1UL << alias.s.m_alias);
 274                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 275                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 276                         return;
 277                 }
 278         }
 279         BUG();
 280 }
 281
 282 static __init void map_low_mmrs(void)
 283 {
 284         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 285         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 286 }
 287
 288 enum map_type {map_wb, map_uc};
 289
 290 static __init void map_high(char *id, unsigned long base, int shift,
 291                             int max_pnode, enum map_type map_type)
 292 {
 293         unsigned long bytes, paddr;
 294
 295         paddr = base << shift;
 296         bytes = (1UL << shift) * (max_pnode + 1);
 297         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 298                                                 paddr + bytes);
 299         if (map_type == map_uc)
 300                 init_extra_mapping_uc(paddr, bytes);
 301         else
 302                 init_extra_mapping_wb(paddr, bytes);
 303
 304 }
 305 static __init void map_gru_high(int max_pnode)
 306 {
 307         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 308         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 309
 310         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 311         if (gru.s.enable)
 312                 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
 313 }
 314
 315 static __init void map_config_high(int max_pnode)
 316 {
 317         union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
 318         int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
 319
 320         cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
 321         if (cfg.s.enable)
 322                 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
 323 }
 324
 325 static __init void map_mmr_high(int max_pnode)
 326 {
 327         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 328         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 329
 330         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 331         if (mmr.s.enable)
 332                 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
 333 }
 334
 335 static __init void map_mmioh_high(int max_pnode)
 336 {
 337         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 338         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 339
 340         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 341         if (mmioh.s.enable)
 342                 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
 343 }
 344
 345 static __init void uv_rtc_init(void)
 346 {
 347         long status;
 348         u64 ticks_per_sec;
 349
 350         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 351                                         &ticks_per_sec);
 352         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 353                 printk(KERN_WARNING
 354                         "unable to determine platform RTC clock frequency, "
 355                         "guessing.\n");
 356                 /* BIOS gives wrong value for clock freq. so guess */
 357                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 358         } else
 359                 sn_rtc_cycles_per_second = ticks_per_sec;
 360 }
 361
 362 /*
 363  * percpu heartbeat timer
 364  */
 365 static void uv_heartbeat(unsigned long ignored)
 366 {
 367         struct timer_list *timer = &uv_hub_info->scir.timer;
 368         unsigned char bits = uv_hub_info->scir.state;
 369
 370         /* flip heartbeat bit */
 371         bits ^= SCIR_CPU_HEARTBEAT;
 372
 373         /* is this cpu idle? */
 374         if (idle_cpu(raw_smp_processor_id()))
 375                 bits &= ~SCIR_CPU_ACTIVITY;
 376         else
 377                 bits |= SCIR_CPU_ACTIVITY;
 378
 379         /* update system controller interface reg */
 380         uv_set_scir_bits(bits);
 381
 382         /* enable next timer period */
 383         mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 384 }
 385
 386 static void __cpuinit uv_heartbeat_enable(int cpu)
 387 {
 388         if (!uv_cpu_hub_info(cpu)->scir.enabled) {
 389                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 390
 391                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 392                 setup_timer(timer, uv_heartbeat, cpu);
 393                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 394                 add_timer_on(timer, cpu);
 395                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 396         }
 397
 398         /* check boot cpu */
 399         if (!uv_cpu_hub_info(0)->scir.enabled)
 400                 uv_heartbeat_enable(0);
 401 }
 402
 403 #ifdef CONFIG_HOTPLUG_CPU
 404 static void __cpuinit uv_heartbeat_disable(int cpu)
 405 {
 406         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 407                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 408                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 409         }
 410         uv_set_cpu_scir_bits(cpu, 0xff);
 411 }
 412
 413 /*
 414  * cpu hotplug notifier
 415  */
 416 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 417                                        unsigned long action, void *hcpu)
 418 {
 419         long cpu = (long)hcpu;
 420
 421         switch (action) {
 422         case CPU_ONLINE:
 423                 uv_heartbeat_enable(cpu);
 424                 break;
 425         case CPU_DOWN_PREPARE:
 426                 uv_heartbeat_disable(cpu);
 427                 break;
 428         default:
 429                 break;
 430         }
 431         return NOTIFY_OK;
 432 }
 433
 434 static __init void uv_scir_register_cpu_notifier(void)
 435 {
 436         hotcpu_notifier(uv_scir_cpu_notify, 0);
 437 }
 438
 439 #else /* !CONFIG_HOTPLUG_CPU */
 440
 441 static __init void uv_scir_register_cpu_notifier(void)
 442 {
 443 }
 444
 445 static __init int uv_init_heartbeat(void)
 446 {
 447         int cpu;
 448
 449         if (is_uv_system())
 450                 for_each_online_cpu(cpu)
 451                         uv_heartbeat_enable(cpu);
 452         return 0;
 453 }
 454
 455 late_initcall(uv_init_heartbeat);
 456
 457 #endif /* !CONFIG_HOTPLUG_CPU */
 458
 459 /*
 460  * Called on each cpu to initialize the per_cpu UV data area.
 461  *      ZZZ hotplug not supported yet
 462  */
 463 void __cpuinit uv_cpu_init(void)
 464 {
 465         /* CPU 0 initilization will be done via uv_system_init. */
 466         if (!uv_blade_info)
 467                 return;
 468
 469         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 470
 471         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 472                 set_x2apic_extra_bits(uv_hub_info->pnode);
 473 }
 474
 475
 476 void __init uv_system_init(void)
 477 {
 478         union uvh_si_addr_map_config_u m_n_config;
 479         union uvh_node_id_u node_id;
 480         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 481         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 482         int max_pnode = 0;
 483         unsigned long mmr_base, present;
 484
 485         map_low_mmrs();
 486
 487         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 488         m_val = m_n_config.s.m_skt;
 489         n_val = m_n_config.s.n_skt;
 490         mmr_base =
 491             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 492             ~UV_MMR_ENABLE;
 493         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 494
 495         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 496                 uv_possible_blades +=
 497                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 498         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 499
 500         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 501         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 502
 503         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 504
 505         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 506         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 507         memset(uv_node_to_blade, 255, bytes);
 508
 509         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 510         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 511         memset(uv_cpu_to_blade, 255, bytes);
 512
 513         blade = 0;
 514         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 515                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 516                 for (j = 0; j < 64; j++) {
 517                         if (!test_bit(j, &present))
 518                                 continue;
 519                         uv_blade_info[blade].pnode = (i * 64 + j);
 520                         uv_blade_info[blade].nr_possible_cpus = 0;
 521                         uv_blade_info[blade].nr_online_cpus = 0;
 522                         blade++;
 523                 }
 524         }
 525
 526         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 527         gnode_upper = (((unsigned long)node_id.s.node_id) &
 528                        ~((1 << n_val) - 1)) << m_val;
 529
 530         uv_bios_init();
 531         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 532                             &sn_coherency_id, &sn_region_size);
 533         uv_rtc_init();
 534
 535         for_each_present_cpu(cpu) {
 536                 nid = cpu_to_node(cpu);
 537                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 538                 blade = boot_pnode_to_blade(pnode);
 539                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 540                 uv_blade_info[blade].nr_possible_cpus++;
 541
 542                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 543                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 544                 uv_cpu_hub_info(cpu)->m_val = m_val;
 545                 uv_cpu_hub_info(cpu)->n_val = m_val;
 546                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 547                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 548                 uv_cpu_hub_info(cpu)->pnode = pnode;
 549                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 550                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 551                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 552                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 553                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 554                 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
 555                 uv_node_to_blade[nid] = blade;
 556                 uv_cpu_to_blade[cpu] = blade;
 557                 max_pnode = max(pnode, max_pnode);
 558
 559                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 560                         "lcpu %d, blade %d\n",
 561                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 562                         lcpu, blade);
 563         }
 564
 565         map_gru_high(max_pnode);
 566         map_mmr_high(max_pnode);
 567         map_config_high(max_pnode);
 568         map_mmioh_high(max_pnode);
 569
 570         uv_cpu_init();
 571         uv_scir_register_cpu_notifier();
 572         proc_mkdir("sgi_uv", NULL);
 573 }