2 * MPC8544 DS Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
14 compatible = "MPC8544DS", "MPC85xxDS";
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>;
32 clock-frequency = <0>;
38 device_type = "memory";
39 reg = <00000000 00000000>; // Filled by U-Boot
45 #interrupt-cells = <2>;
47 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00100000>; // CCSRBAR 1M
49 bus-frequency = <0>; // Filled out by uboot.
51 memory-controller@2000 {
52 compatible = "fsl,8544-memory-controller";
54 interrupt-parent = <&mpic>;
58 l2-cache-controller@20000 {
59 compatible = "fsl,8544-l2-cache-controller";
61 cache-line-size = <20>; // 32 bytes
62 cache-size = <40000>; // L2, 256K
63 interrupt-parent = <&mpic>;
69 compatible = "fsl-i2c";
72 interrupt-parent = <&mpic>;
80 compatible = "gianfar";
82 phy0: ethernet-phy@0 {
83 interrupt-parent = <&mpic>;
86 device_type = "ethernet-phy";
88 phy1: ethernet-phy@1 {
89 interrupt-parent = <&mpic>;
92 device_type = "ethernet-phy";
99 device_type = "network";
101 compatible = "gianfar";
103 local-mac-address = [ 00 00 00 00 00 00 ];
104 interrupts = <1d 2 1e 2 22 2>;
105 interrupt-parent = <&mpic>;
106 phy-handle = <&phy0>;
110 #address-cells = <1>;
112 device_type = "network";
114 compatible = "gianfar";
116 local-mac-address = [ 00 00 00 00 00 00 ];
117 interrupts = <1f 2 20 2 21 2>;
118 interrupt-parent = <&mpic>;
119 phy-handle = <&phy1>;
123 device_type = "serial";
124 compatible = "ns16550";
126 clock-frequency = <0>;
128 interrupt-parent = <&mpic>;
132 device_type = "serial";
133 compatible = "ns16550";
135 clock-frequency = <0>;
137 interrupt-parent = <&mpic>;
141 compatible = "fsl,mpc8540-pci";
143 interrupt-map-mask = <f800 0 0 7>;
146 /* IDSEL 0x11 J17 Slot 1 */
152 /* IDSEL 0x12 J16 Slot 2 */
157 9000 0 0 4 &mpic 1 1>;
159 interrupt-parent = <&mpic>;
162 ranges = <02000000 0 80000000 80000000 0 10000000
163 01000000 0 00000000 e2000000 0 00800000>;
164 clock-frequency = <3f940aa>;
165 #interrupt-cells = <1>;
167 #address-cells = <3>;
172 compatible = "fsl,mpc8548-pcie";
174 #interrupt-cells = <1>;
176 #address-cells = <3>;
179 ranges = <02000000 0 90000000 90000000 0 10000000
180 01000000 0 00000000 e3000000 0 00800000>;
181 clock-frequency = <1fca055>;
182 interrupt-parent = <&mpic>;
184 interrupt-map-mask = <f800 0 0 7>;
195 compatible = "fsl,mpc8548-pcie";
197 #interrupt-cells = <1>;
199 #address-cells = <3>;
202 ranges = <02000000 0 a0000000 a0000000 0 10000000
203 01000000 0 00000000 e2800000 0 00800000>;
204 clock-frequency = <1fca055>;
205 interrupt-parent = <&mpic>;
207 interrupt-map-mask = <f800 0 0 7>;
218 compatible = "fsl,mpc8548-pcie";
220 #interrupt-cells = <1>;
222 #address-cells = <3>;
225 ranges = <02000000 0 b0000000 b0000000 0 10000000
226 01000000 0 00000000 e3800000 0 00800000>;
227 clock-frequency = <1fca055>;
228 interrupt-parent = <&mpic>;
230 interrupt-map-mask = <f800 0 0 7>;
234 d000 0 0 1 &i8259 6 2
235 d000 0 0 2 &i8259 3 2
236 d000 0 0 3 &i8259 4 2
237 d000 0 0 4 &i8259 5 2
240 d800 0 0 1 &i8259 5 2
241 d800 0 0 2 &i8259 0 0
242 d800 0 0 3 &i8259 0 0
243 d800 0 0 4 &i8259 0 0
246 e000 0 0 1 &i8259 9 2
247 e000 0 0 2 &i8259 a 2
248 e000 0 0 3 &i8259 c 2
249 e000 0 0 4 &i8259 7 2
252 e800 0 0 1 &i8259 9 2
253 e800 0 0 2 &i8259 a 2
254 e800 0 0 3 &i8259 b 2
255 e800 0 0 4 &i8259 0 0
258 f000 0 0 1 &i8259 c 2
259 f000 0 0 2 &i8259 0 0
260 f000 0 0 3 &i8259 0 0
261 f000 0 0 4 &i8259 0 0
263 // IDSEL 0x1f IDE/SATA
264 f800 0 0 1 &i8259 6 2
265 f800 0 0 2 &i8259 0 0
266 f800 0 0 3 &i8259 0 0
267 f800 0 0 4 &i8259 0 0
272 #address-cells = <3>;
273 ranges = <02000000 0 b0000000
283 #address-cells = <3>;
284 ranges = <02000000 0 b0000000
293 #interrupt-cells = <2>;
295 #address-cells = <2>;
296 reg = <f000 0 0 0 0>;
297 ranges = <1 0 01000000 0 0
299 interrupt-parent = <&i8259>;
301 i8259: interrupt-controller@20 {
305 clock-frequency = <0>;
306 interrupt-controller;
307 device_type = "interrupt-controller";
308 #address-cells = <0>;
309 #interrupt-cells = <2>;
311 compatible = "chrp,iic";
319 #address-cells = <1>;
320 reg = <1 60 1 1 64 1>;
321 interrupts = <1 3 c 3>;
327 compatible = "pnpPNP,303";
332 compatible = "pnpPNP,f03";
352 clock-frequency = <0>;
353 interrupt-controller;
354 #address-cells = <0>;
355 #interrupt-cells = <2>;
358 compatible = "chrp,open-pic";
359 device_type = "open-pic";