2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
37 #include "rt2x00pci.h"
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
51 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
56 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
57 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, ®);
58 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
60 udelay(REGISTER_BUSY_DELAY);
66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
67 const unsigned int word, const u8 value)
72 * Wait until the BBP becomes ready.
74 reg = rt61pci_bbp_check(rt2x00dev);
75 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
76 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
81 * Write the data into the BBP.
84 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
85 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
86 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
87 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
89 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
92 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
93 const unsigned int word, u8 *value)
98 * Wait until the BBP becomes ready.
100 reg = rt61pci_bbp_check(rt2x00dev);
101 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
102 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
107 * Write the request into the BBP.
110 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
111 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
112 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
114 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
117 * Wait until the BBP becomes ready.
119 reg = rt61pci_bbp_check(rt2x00dev);
120 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
121 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
126 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
129 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
130 const unsigned int word, const u32 value)
138 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
139 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®);
140 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
142 udelay(REGISTER_BUSY_DELAY);
145 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
150 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
151 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
152 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
153 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
155 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
156 rt2x00_rf_write(rt2x00dev, word, value);
159 #ifdef CONFIG_RT61PCI_LEDS
161 * This function is only called from rt61pci_led_brightness()
162 * make gcc happy by placing this function inside the
163 * same ifdef statement as the caller.
165 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
166 const u8 command, const u8 token,
167 const u8 arg0, const u8 arg1)
171 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®);
173 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
174 ERROR(rt2x00dev, "mcu request error. "
175 "Request 0x%02x failed for token 0x%02x.\n",
180 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
181 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
182 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
183 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
184 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
186 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
187 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
188 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
189 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
191 #endif /* CONFIG_RT61PCI_LEDS */
193 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
195 struct rt2x00_dev *rt2x00dev = eeprom->data;
198 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
200 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
201 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
202 eeprom->reg_data_clock =
203 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
204 eeprom->reg_chip_select =
205 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
208 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
210 struct rt2x00_dev *rt2x00dev = eeprom->data;
213 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
214 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
215 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
216 !!eeprom->reg_data_clock);
217 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
218 !!eeprom->reg_chip_select);
220 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
223 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
224 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
226 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
227 const unsigned int word, u32 *data)
229 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
232 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
233 const unsigned int word, u32 data)
235 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
238 static const struct rt2x00debug rt61pci_rt2x00debug = {
239 .owner = THIS_MODULE,
241 .read = rt61pci_read_csr,
242 .write = rt61pci_write_csr,
243 .word_size = sizeof(u32),
244 .word_count = CSR_REG_SIZE / sizeof(u32),
247 .read = rt2x00_eeprom_read,
248 .write = rt2x00_eeprom_write,
249 .word_size = sizeof(u16),
250 .word_count = EEPROM_SIZE / sizeof(u16),
253 .read = rt61pci_bbp_read,
254 .write = rt61pci_bbp_write,
255 .word_size = sizeof(u8),
256 .word_count = BBP_SIZE / sizeof(u8),
259 .read = rt2x00_rf_read,
260 .write = rt61pci_rf_write,
261 .word_size = sizeof(u32),
262 .word_count = RF_SIZE / sizeof(u32),
265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
267 #ifdef CONFIG_RT61PCI_RFKILL
268 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
272 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
273 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
276 #define rt61pci_rfkill_poll NULL
277 #endif /* CONFIG_RT61PCI_RFKILL */
279 #ifdef CONFIG_RT61PCI_LEDS
280 static void rt61pci_led_brightness(struct led_classdev *led_cdev,
281 enum led_brightness brightness)
283 struct rt2x00_led *led =
284 container_of(led_cdev, struct rt2x00_led, led_dev);
285 unsigned int enabled = brightness != LED_OFF;
286 unsigned int a_mode =
287 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
288 unsigned int bg_mode =
289 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
291 if (led->type == LED_TYPE_RADIO) {
292 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
293 MCU_LEDCS_RADIO_STATUS, enabled);
295 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
296 (led->rt2x00dev->led_mcu_reg & 0xff),
297 ((led->rt2x00dev->led_mcu_reg >> 8)));
298 } else if (led->type == LED_TYPE_ASSOC) {
299 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
300 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
301 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
302 MCU_LEDCS_LINK_A_STATUS, a_mode);
304 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
305 (led->rt2x00dev->led_mcu_reg & 0xff),
306 ((led->rt2x00dev->led_mcu_reg >> 8)));
307 } else if (led->type == LED_TYPE_QUALITY) {
309 * The brightness is divided into 6 levels (0 - 5),
310 * this means we need to convert the brightness
311 * argument into the matching level within that range.
313 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
314 brightness / (LED_FULL / 6), 0);
318 #define rt61pci_led_brightness NULL
319 #endif /* CONFIG_RT61PCI_LEDS */
322 * Configuration handlers.
324 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
325 struct rt2x00_intf *intf,
326 struct rt2x00intf_conf *conf,
327 const unsigned int flags)
329 unsigned int beacon_base;
332 if (flags & CONFIG_UPDATE_TYPE) {
334 * Clear current synchronisation setup.
335 * For the Beacon base registers we only need to clear
336 * the first byte since that byte contains the VALID and OWNER
337 * bits which (when set to 0) will invalidate the entire beacon.
339 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
340 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
343 * Enable synchronisation.
345 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
346 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync);
347 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
350 if (flags & CONFIG_UPDATE_MAC) {
351 reg = le32_to_cpu(conf->mac[1]);
352 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
353 conf->mac[1] = cpu_to_le32(reg);
355 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
356 conf->mac, sizeof(conf->mac));
359 if (flags & CONFIG_UPDATE_BSSID) {
360 reg = le32_to_cpu(conf->bssid[1]);
361 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3);
362 conf->bssid[1] = cpu_to_le32(reg);
364 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
365 conf->bssid, sizeof(conf->bssid));
369 static int rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
370 const int short_preamble,
371 const int ack_timeout,
372 const int ack_consume_time)
376 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
377 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
378 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
380 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
381 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
383 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
388 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
389 const int basic_rate_mask)
391 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
394 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
395 struct rf_channel *rf, const int txpower)
401 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
402 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
404 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
405 rt2x00_rf(&rt2x00dev->chip, RF2527));
407 rt61pci_bbp_read(rt2x00dev, 3, &r3);
408 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
409 rt61pci_bbp_write(rt2x00dev, 3, r3);
412 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
413 r94 += txpower - MAX_TXPOWER;
414 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
416 rt61pci_bbp_write(rt2x00dev, 94, r94);
418 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
419 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
420 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
421 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
425 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
426 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
427 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
428 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
432 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
433 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
434 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
435 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
440 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
443 struct rf_channel rf;
445 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
446 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
447 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
448 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
450 rt61pci_config_channel(rt2x00dev, &rf, txpower);
453 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
454 struct antenna_setup *ant)
460 rt61pci_bbp_read(rt2x00dev, 3, &r3);
461 rt61pci_bbp_read(rt2x00dev, 4, &r4);
462 rt61pci_bbp_read(rt2x00dev, 77, &r77);
464 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
465 rt2x00_rf(&rt2x00dev->chip, RF5325));
468 * Configure the RX antenna.
471 case ANTENNA_HW_DIVERSITY:
472 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
473 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
474 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
477 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
478 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
479 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
480 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
482 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
486 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
487 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
488 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
489 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
491 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
495 rt61pci_bbp_write(rt2x00dev, 77, r77);
496 rt61pci_bbp_write(rt2x00dev, 3, r3);
497 rt61pci_bbp_write(rt2x00dev, 4, r4);
500 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
501 struct antenna_setup *ant)
507 rt61pci_bbp_read(rt2x00dev, 3, &r3);
508 rt61pci_bbp_read(rt2x00dev, 4, &r4);
509 rt61pci_bbp_read(rt2x00dev, 77, &r77);
511 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
512 rt2x00_rf(&rt2x00dev->chip, RF2529));
513 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
514 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
517 * Configure the RX antenna.
520 case ANTENNA_HW_DIVERSITY:
521 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
524 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
525 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
529 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
530 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
534 rt61pci_bbp_write(rt2x00dev, 77, r77);
535 rt61pci_bbp_write(rt2x00dev, 3, r3);
536 rt61pci_bbp_write(rt2x00dev, 4, r4);
539 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
540 const int p1, const int p2)
544 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
546 rt2x00_set_field32(®, MAC_CSR13_BIT4, p1);
547 rt2x00_set_field32(®, MAC_CSR13_BIT12, 0);
549 rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2);
550 rt2x00_set_field32(®, MAC_CSR13_BIT11, 0);
552 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
555 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
556 struct antenna_setup *ant)
562 rt61pci_bbp_read(rt2x00dev, 3, &r3);
563 rt61pci_bbp_read(rt2x00dev, 4, &r4);
564 rt61pci_bbp_read(rt2x00dev, 77, &r77);
567 * Configure the RX antenna.
571 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
572 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
573 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
575 case ANTENNA_HW_DIVERSITY:
577 * FIXME: Antenna selection for the rf 2529 is very confusing
578 * in the legacy driver. Just default to antenna B until the
579 * legacy code can be properly translated into rt2x00 code.
583 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
584 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
585 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
589 rt61pci_bbp_write(rt2x00dev, 77, r77);
590 rt61pci_bbp_write(rt2x00dev, 3, r3);
591 rt61pci_bbp_write(rt2x00dev, 4, r4);
597 * value[0] -> non-LNA
603 static const struct antenna_sel antenna_sel_a[] = {
604 { 96, { 0x58, 0x78 } },
605 { 104, { 0x38, 0x48 } },
606 { 75, { 0xfe, 0x80 } },
607 { 86, { 0xfe, 0x80 } },
608 { 88, { 0xfe, 0x80 } },
609 { 35, { 0x60, 0x60 } },
610 { 97, { 0x58, 0x58 } },
611 { 98, { 0x58, 0x58 } },
614 static const struct antenna_sel antenna_sel_bg[] = {
615 { 96, { 0x48, 0x68 } },
616 { 104, { 0x2c, 0x3c } },
617 { 75, { 0xfe, 0x80 } },
618 { 86, { 0xfe, 0x80 } },
619 { 88, { 0xfe, 0x80 } },
620 { 35, { 0x50, 0x50 } },
621 { 97, { 0x48, 0x48 } },
622 { 98, { 0x48, 0x48 } },
625 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
626 struct antenna_setup *ant)
628 const struct antenna_sel *sel;
634 * We should never come here because rt2x00lib is supposed
635 * to catch this and send us the correct antenna explicitely.
637 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
638 ant->tx == ANTENNA_SW_DIVERSITY);
640 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
642 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
644 sel = antenna_sel_bg;
645 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
648 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
649 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
651 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
653 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
654 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
655 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
656 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
658 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
660 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
661 rt2x00_rf(&rt2x00dev->chip, RF5325))
662 rt61pci_config_antenna_5x(rt2x00dev, ant);
663 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
664 rt61pci_config_antenna_2x(rt2x00dev, ant);
665 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
666 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
667 rt61pci_config_antenna_2x(rt2x00dev, ant);
669 rt61pci_config_antenna_2529(rt2x00dev, ant);
673 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
674 struct rt2x00lib_conf *libconf)
678 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
679 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
680 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
682 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
683 rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
684 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
685 rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
686 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
688 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
689 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
690 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
692 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
693 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
694 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
696 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
697 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
698 libconf->conf->beacon_int * 16);
699 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
702 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
703 struct rt2x00lib_conf *libconf,
704 const unsigned int flags)
706 if (flags & CONFIG_UPDATE_PHYMODE)
707 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
708 if (flags & CONFIG_UPDATE_CHANNEL)
709 rt61pci_config_channel(rt2x00dev, &libconf->rf,
710 libconf->conf->power_level);
711 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
712 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
713 if (flags & CONFIG_UPDATE_ANTENNA)
714 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
715 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
716 rt61pci_config_duration(rt2x00dev, libconf);
722 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
723 struct link_qual *qual)
728 * Update FCS error count from register.
730 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
731 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
734 * Update False CCA count from register.
736 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
737 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
740 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
742 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
743 rt2x00dev->link.vgc_level = 0x20;
746 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
748 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
753 rt61pci_bbp_read(rt2x00dev, 17, &r17);
756 * Determine r17 bounds.
758 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
761 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
768 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
775 * If we are not associated, we should go straight to the
776 * dynamic CCA tuning.
778 if (!rt2x00dev->intf_associated)
779 goto dynamic_cca_tune;
782 * Special big-R17 for very short distance
786 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
791 * Special big-R17 for short distance
795 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
800 * Special big-R17 for middle-short distance
804 if (r17 != low_bound)
805 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
810 * Special mid-R17 for middle distance
814 if (r17 != low_bound)
815 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
820 * Special case: Change up_bound based on the rssi.
821 * Lower up_bound when rssi is weaker then -74 dBm.
823 up_bound -= 2 * (-74 - rssi);
824 if (low_bound > up_bound)
825 up_bound = low_bound;
827 if (r17 > up_bound) {
828 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
835 * r17 does not yet exceed upper limit, continue and base
836 * the r17 tuning on the false CCA count.
838 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
839 if (++r17 > up_bound)
841 rt61pci_bbp_write(rt2x00dev, 17, r17);
842 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
843 if (--r17 < low_bound)
845 rt61pci_bbp_write(rt2x00dev, 17, r17);
852 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
856 switch (rt2x00dev->chip.rt) {
858 fw_name = FIRMWARE_RT2561;
861 fw_name = FIRMWARE_RT2561s;
864 fw_name = FIRMWARE_RT2661;
874 static u16 rt61pci_get_firmware_crc(void *data, const size_t len)
879 * Use the crc itu-t algorithm.
880 * The last 2 bytes in the firmware array are the crc checksum itself,
881 * this means that we should never pass those 2 bytes to the crc
884 crc = crc_itu_t(0, data, len - 2);
885 crc = crc_itu_t_byte(crc, 0);
886 crc = crc_itu_t_byte(crc, 0);
891 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
898 * Wait for stable hardware.
900 for (i = 0; i < 100; i++) {
901 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
908 ERROR(rt2x00dev, "Unstable hardware.\n");
913 * Prepare MCU and mailbox for firmware loading.
916 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
917 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
918 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
919 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
920 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
923 * Write firmware to device.
926 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
927 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
928 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
930 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
933 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
934 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
936 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
937 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
939 for (i = 0; i < 100; i++) {
940 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
941 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
947 ERROR(rt2x00dev, "MCU Control register not ready.\n");
952 * Reset MAC and BBP registers.
955 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
956 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
957 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
959 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
960 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
961 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
962 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
964 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
965 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
966 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
972 * Initialization functions.
974 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
975 struct queue_entry *entry)
977 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
980 rt2x00_desc_read(priv_rx->desc, 5, &word);
981 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
983 rt2x00_desc_write(priv_rx->desc, 5, word);
985 rt2x00_desc_read(priv_rx->desc, 0, &word);
986 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
987 rt2x00_desc_write(priv_rx->desc, 0, word);
990 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
991 struct queue_entry *entry)
993 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
996 rt2x00_desc_read(priv_tx->desc, 1, &word);
997 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
998 rt2x00_desc_write(priv_tx->desc, 1, word);
1000 rt2x00_desc_read(priv_tx->desc, 5, &word);
1001 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1002 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
1003 rt2x00_desc_write(priv_tx->desc, 5, word);
1005 rt2x00_desc_read(priv_tx->desc, 6, &word);
1006 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1008 rt2x00_desc_write(priv_tx->desc, 6, word);
1010 rt2x00_desc_read(priv_tx->desc, 0, &word);
1011 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1012 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1013 rt2x00_desc_write(priv_tx->desc, 0, word);
1016 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1018 struct queue_entry_priv_pci_rx *priv_rx;
1019 struct queue_entry_priv_pci_tx *priv_tx;
1023 * Initialize registers.
1025 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
1026 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
1027 rt2x00dev->tx[0].limit);
1028 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
1029 rt2x00dev->tx[1].limit);
1030 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
1031 rt2x00dev->tx[2].limit);
1032 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
1033 rt2x00dev->tx[3].limit);
1034 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1036 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
1037 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
1038 rt2x00dev->tx[0].desc_size / 4);
1039 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1041 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
1042 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
1043 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
1045 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1047 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
1048 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
1049 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
1051 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1053 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
1054 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
1055 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
1057 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1059 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
1060 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
1061 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
1063 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1065 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
1066 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1067 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
1068 rt2x00dev->rx->desc_size / 4);
1069 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1070 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1072 priv_rx = rt2x00dev->rx->entries[0].priv_data;
1073 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
1074 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
1076 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1078 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
1079 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
1080 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
1081 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
1082 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
1083 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1085 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
1086 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1087 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1088 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1089 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1090 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1092 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1093 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
1094 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1099 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1103 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1104 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
1105 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
1106 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1107 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1109 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
1110 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1111 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
1112 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1113 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
1114 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1115 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
1116 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1117 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
1118 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1121 * CCK TXD BBP registers
1123 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
1124 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
1125 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
1126 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
1127 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
1128 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
1129 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
1130 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
1131 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
1132 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1135 * OFDM TXD BBP registers
1137 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
1138 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
1139 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
1140 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
1141 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
1142 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
1143 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
1144 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1146 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
1147 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1148 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1149 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1150 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1151 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1153 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
1154 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1155 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1156 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1157 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1158 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1160 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1162 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1164 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
1165 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1166 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1168 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1170 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1173 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1175 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, ®);
1176 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
1177 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
1178 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
1181 * Invalidate all Shared Keys (SEC_CSR0),
1182 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1184 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1185 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1186 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1188 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1189 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1190 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1191 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1193 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1195 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1197 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1199 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
1200 rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
1201 rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
1202 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1204 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
1205 rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
1206 rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
1207 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1211 * For the Beacon base registers we only need to clear
1212 * the first byte since that byte contains the VALID and OWNER
1213 * bits which (when set to 0) will invalidate the entire beacon.
1215 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1216 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1217 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1218 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1221 * We must clear the error counters.
1222 * These registers are cleared on read,
1223 * so we may pass a useless variable to store the value.
1225 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1226 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1227 rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
1230 * Reset MAC and BBP registers.
1232 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1233 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1234 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1235 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1237 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1238 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1239 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1240 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1242 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1243 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1244 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1249 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1256 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1257 rt61pci_bbp_read(rt2x00dev, 0, &value);
1258 if ((value != 0xff) && (value != 0x00))
1259 goto continue_csr_init;
1260 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1261 udelay(REGISTER_BUSY_DELAY);
1264 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1268 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1269 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1270 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1271 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1272 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1273 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1274 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1275 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1276 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1277 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1278 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1279 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1280 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1281 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1282 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1283 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1284 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1285 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1286 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1287 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1288 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1289 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1290 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1291 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1293 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1294 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1296 if (eeprom != 0xffff && eeprom != 0x0000) {
1297 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1298 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1299 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1307 * Device state switch handlers.
1309 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1310 enum dev_state state)
1314 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1315 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1316 state == STATE_RADIO_RX_OFF);
1317 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1320 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1321 enum dev_state state)
1323 int mask = (state == STATE_RADIO_IRQ_OFF);
1327 * When interrupts are being enabled, the interrupt registers
1328 * should clear the register to assure a clean state.
1330 if (state == STATE_RADIO_IRQ_ON) {
1331 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1332 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1334 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
1335 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1339 * Only toggle the interrupts bits we are going to use.
1340 * Non-checked interrupt bits are disabled by default.
1342 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
1343 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
1344 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
1345 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1346 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1347 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1349 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
1350 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
1351 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
1352 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
1353 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
1354 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
1355 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
1356 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
1357 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
1358 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1361 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1366 * Initialize all registers.
1368 if (rt61pci_init_queues(rt2x00dev) ||
1369 rt61pci_init_registers(rt2x00dev) ||
1370 rt61pci_init_bbp(rt2x00dev)) {
1371 ERROR(rt2x00dev, "Register initialization failed.\n");
1376 * Enable interrupts.
1378 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1383 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1384 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1385 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1390 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1394 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1397 * Disable synchronisation.
1399 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1404 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1405 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1406 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1407 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1408 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1409 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1412 * Disable interrupts.
1414 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1417 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1424 put_to_sleep = (state != STATE_AWAKE);
1426 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1427 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1428 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1429 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1432 * Device is not guaranteed to be in the requested state yet.
1433 * We must wait until the register indicates that the
1434 * device has entered the correct state.
1436 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1437 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1439 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1440 if (current_state == !put_to_sleep)
1445 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1446 "current device state %d.\n", !put_to_sleep, current_state);
1451 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1452 enum dev_state state)
1457 case STATE_RADIO_ON:
1458 retval = rt61pci_enable_radio(rt2x00dev);
1460 case STATE_RADIO_OFF:
1461 rt61pci_disable_radio(rt2x00dev);
1463 case STATE_RADIO_RX_ON:
1464 case STATE_RADIO_RX_ON_LINK:
1465 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1467 case STATE_RADIO_RX_OFF:
1468 case STATE_RADIO_RX_OFF_LINK:
1469 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1471 case STATE_DEEP_SLEEP:
1475 retval = rt61pci_set_state(rt2x00dev, state);
1486 * TX descriptor initialization
1488 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1489 struct sk_buff *skb,
1490 struct txentry_desc *txdesc,
1491 struct ieee80211_tx_control *control)
1493 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1494 __le32 *txd = skbdesc->desc;
1498 * Start writing the descriptor words.
1500 rt2x00_desc_read(txd, 1, &word);
1501 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1502 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1503 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1504 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1505 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1506 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1507 rt2x00_desc_write(txd, 1, word);
1509 rt2x00_desc_read(txd, 2, &word);
1510 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1511 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1512 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1513 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1514 rt2x00_desc_write(txd, 2, word);
1516 rt2x00_desc_read(txd, 5, &word);
1517 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1518 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1519 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1520 rt2x00_desc_write(txd, 5, word);
1522 if (skbdesc->desc_len > TXINFO_SIZE) {
1523 rt2x00_desc_read(txd, 11, &word);
1524 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1525 rt2x00_desc_write(txd, 11, word);
1528 rt2x00_desc_read(txd, 0, &word);
1529 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1530 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1531 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1532 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1533 rt2x00_set_field32(&word, TXD_W0_ACK,
1534 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1535 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1536 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1537 rt2x00_set_field32(&word, TXD_W0_OFDM,
1538 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1539 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1540 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1542 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1543 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1544 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1545 rt2x00_set_field32(&word, TXD_W0_BURST,
1546 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1547 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1548 rt2x00_desc_write(txd, 0, word);
1552 * TX data initialization
1554 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1555 const unsigned int queue)
1559 if (queue == RT2X00_BCN_QUEUE_BEACON) {
1561 * For Wi-Fi faily generated beacons between participating
1562 * stations. Set TBTT phase adaptive adjustment step to 8us.
1564 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1566 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1567 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1568 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
1569 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
1570 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1571 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1576 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1577 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0,
1578 (queue == IEEE80211_TX_QUEUE_DATA0));
1579 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1,
1580 (queue == IEEE80211_TX_QUEUE_DATA1));
1581 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2,
1582 (queue == IEEE80211_TX_QUEUE_DATA2));
1583 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3,
1584 (queue == IEEE80211_TX_QUEUE_DATA3));
1585 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1589 * RX control handlers
1591 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1597 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1612 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1613 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1616 if (lna == 3 || lna == 2)
1619 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1620 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1622 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1625 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1626 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1629 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1632 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1633 struct rxdone_entry_desc *rxdesc)
1635 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1639 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1640 rt2x00_desc_read(priv_rx->desc, 1, &word1);
1643 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1644 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1647 * Obtain the status about this packet.
1649 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1650 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1651 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1652 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1653 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1657 * Interrupt functions.
1659 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1661 struct data_queue *queue;
1662 struct queue_entry *entry;
1663 struct queue_entry *entry_done;
1664 struct queue_entry_priv_pci_tx *priv_tx;
1665 struct txdone_entry_desc txdesc;
1673 * During each loop we will compare the freshly read
1674 * STA_CSR4 register value with the value read from
1675 * the previous loop. If the 2 values are equal then
1676 * we should stop processing because the chance it
1677 * quite big that the device has been unplugged and
1678 * we risk going into an endless loop.
1683 rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
1684 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1692 * Skip this entry when it contains an invalid
1693 * queue identication number.
1695 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1696 queue = rt2x00queue_get_queue(rt2x00dev, type);
1697 if (unlikely(!queue))
1701 * Skip this entry when it contains an invalid
1704 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1705 if (unlikely(index >= queue->limit))
1708 entry = &queue->entries[index];
1709 priv_tx = entry->priv_data;
1710 rt2x00_desc_read(priv_tx->desc, 0, &word);
1712 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1713 !rt2x00_get_field32(word, TXD_W0_VALID))
1716 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1717 while (entry != entry_done) {
1719 * Just report any entries we missed as failed.
1722 "TX status report missed for entry %d\n",
1723 entry_done->entry_idx);
1725 txdesc.status = TX_FAIL_OTHER;
1728 rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1729 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1733 * Obtain the status about this packet.
1735 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1736 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1738 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1742 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1744 struct rt2x00_dev *rt2x00dev = dev_instance;
1749 * Get the interrupt sources & saved to local variable.
1750 * Write register value back to clear pending interrupts.
1752 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
1753 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1755 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1756 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1758 if (!reg && !reg_mcu)
1761 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1765 * Handle interrupts, walk through all bits
1766 * and run the tasks, the bits are checked in order of
1771 * 1 - Rx ring done interrupt.
1773 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1774 rt2x00pci_rxdone(rt2x00dev);
1777 * 2 - Tx ring done interrupt.
1779 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1780 rt61pci_txdone(rt2x00dev);
1783 * 3 - Handle MCU command done.
1786 rt2x00pci_register_write(rt2x00dev,
1787 M2H_CMD_DONE_CSR, 0xffffffff);
1793 * Device probe functions.
1795 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1797 struct eeprom_93cx6 eeprom;
1803 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
1805 eeprom.data = rt2x00dev;
1806 eeprom.register_read = rt61pci_eepromregister_read;
1807 eeprom.register_write = rt61pci_eepromregister_write;
1808 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1809 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1810 eeprom.reg_data_in = 0;
1811 eeprom.reg_data_out = 0;
1812 eeprom.reg_data_clock = 0;
1813 eeprom.reg_chip_select = 0;
1815 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1816 EEPROM_SIZE / sizeof(u16));
1819 * Start validation of the data that has been read.
1821 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1822 if (!is_valid_ether_addr(mac)) {
1823 DECLARE_MAC_BUF(macbuf);
1825 random_ether_addr(mac);
1826 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1829 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1830 if (word == 0xffff) {
1831 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1832 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1834 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1836 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1837 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1838 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1839 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1840 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1841 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1844 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1845 if (word == 0xffff) {
1846 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1847 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1848 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1849 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1850 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1851 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1852 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1853 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1856 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1857 if (word == 0xffff) {
1858 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1860 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1861 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1864 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1865 if (word == 0xffff) {
1866 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1867 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1868 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1869 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1872 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1873 if (word == 0xffff) {
1874 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1875 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1876 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1877 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1879 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1880 if (value < -10 || value > 10)
1881 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1882 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1883 if (value < -10 || value > 10)
1884 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1885 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1888 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1889 if (word == 0xffff) {
1890 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1891 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1892 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1893 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1895 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1896 if (value < -10 || value > 10)
1897 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1898 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1899 if (value < -10 || value > 10)
1900 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1901 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1907 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1915 * Read EEPROM word for configuration.
1917 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1920 * Identify RF chipset.
1921 * To determine the RT chip we have to read the
1922 * PCI header of the device.
1924 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1925 PCI_CONFIG_HEADER_DEVICE, &device);
1926 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1927 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
1928 rt2x00_set_chip(rt2x00dev, device, value, reg);
1930 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1931 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1932 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1933 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1934 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1939 * Determine number of antenna's.
1941 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1942 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1945 * Identify default antenna configuration.
1947 rt2x00dev->default_ant.tx =
1948 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1949 rt2x00dev->default_ant.rx =
1950 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1953 * Read the Frame type.
1955 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1956 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1959 * Detect if this device has an hardware controlled radio.
1961 #ifdef CONFIG_RT61PCI_RFKILL
1962 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1963 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1964 #endif /* CONFIG_RT61PCI_RFKILL */
1967 * Read frequency offset and RF programming sequence.
1969 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1970 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
1971 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
1973 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1976 * Read external LNA informations.
1978 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1980 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1981 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1982 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1983 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1986 * When working with a RF2529 chip without double antenna
1987 * the antenna settings should be gathered from the NIC
1990 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
1991 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
1992 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
1994 rt2x00dev->default_ant.tx = ANTENNA_B;
1995 rt2x00dev->default_ant.rx = ANTENNA_A;
1998 rt2x00dev->default_ant.tx = ANTENNA_B;
1999 rt2x00dev->default_ant.rx = ANTENNA_B;
2002 rt2x00dev->default_ant.tx = ANTENNA_A;
2003 rt2x00dev->default_ant.rx = ANTENNA_A;
2006 rt2x00dev->default_ant.tx = ANTENNA_A;
2007 rt2x00dev->default_ant.rx = ANTENNA_B;
2011 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2012 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2013 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2014 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2018 * Store led settings, for correct led behaviour.
2019 * If the eeprom value is invalid,
2020 * switch to default led mode.
2022 #ifdef CONFIG_RT61PCI_LEDS
2023 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2025 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2028 case LED_MODE_TXRX_ACTIVITY:
2030 case LED_MODE_ALPHA:
2031 case LED_MODE_DEFAULT:
2032 rt2x00dev->led_flags =
2033 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
2035 case LED_MODE_SIGNAL_STRENGTH:
2036 rt2x00dev->led_flags =
2037 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
2038 LED_SUPPORT_QUALITY;
2042 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2043 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2044 rt2x00_get_field16(eeprom,
2045 EEPROM_LED_POLARITY_GPIO_0));
2046 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2047 rt2x00_get_field16(eeprom,
2048 EEPROM_LED_POLARITY_GPIO_1));
2049 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2050 rt2x00_get_field16(eeprom,
2051 EEPROM_LED_POLARITY_GPIO_2));
2052 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2053 rt2x00_get_field16(eeprom,
2054 EEPROM_LED_POLARITY_GPIO_3));
2055 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2056 rt2x00_get_field16(eeprom,
2057 EEPROM_LED_POLARITY_GPIO_4));
2058 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2059 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2060 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2061 rt2x00_get_field16(eeprom,
2062 EEPROM_LED_POLARITY_RDY_G));
2063 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2064 rt2x00_get_field16(eeprom,
2065 EEPROM_LED_POLARITY_RDY_A));
2066 #endif /* CONFIG_RT61PCI_LEDS */
2072 * RF value list for RF5225 & RF5325
2073 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2075 static const struct rf_channel rf_vals_noseq[] = {
2076 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2077 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2078 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2079 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2080 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2081 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2082 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2083 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2084 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2085 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2086 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2087 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2088 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2089 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2091 /* 802.11 UNI / HyperLan 2 */
2092 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2093 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2094 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2095 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2096 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2097 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2098 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2099 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2101 /* 802.11 HyperLan 2 */
2102 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2103 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2104 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2105 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2106 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2107 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2108 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2109 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2110 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2111 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2114 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2115 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2116 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2117 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2118 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2119 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2121 /* MMAC(Japan)J52 ch 34,38,42,46 */
2122 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2123 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2124 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2125 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2129 * RF value list for RF5225 & RF5325
2130 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2132 static const struct rf_channel rf_vals_seq[] = {
2133 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2134 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2135 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2136 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2137 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2138 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2139 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2140 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2141 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2142 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2143 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2144 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2145 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2146 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2148 /* 802.11 UNI / HyperLan 2 */
2149 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2150 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2151 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2152 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2153 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2154 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2155 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2156 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2158 /* 802.11 HyperLan 2 */
2159 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2160 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2161 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2162 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2163 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2164 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2165 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2166 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2167 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2168 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2171 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2172 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2173 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2174 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2175 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2176 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2178 /* MMAC(Japan)J52 ch 34,38,42,46 */
2179 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2180 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2181 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2182 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2185 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2187 struct hw_mode_spec *spec = &rt2x00dev->spec;
2192 * Initialize all hw fields.
2194 rt2x00dev->hw->flags =
2195 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2196 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2197 rt2x00dev->hw->extra_tx_headroom = 0;
2198 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2199 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2200 rt2x00dev->hw->queues = 4;
2202 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2203 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2204 rt2x00_eeprom_addr(rt2x00dev,
2205 EEPROM_MAC_ADDR_0));
2208 * Convert tx_power array in eeprom.
2210 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2211 for (i = 0; i < 14; i++)
2212 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2215 * Initialize hw_mode information.
2217 spec->supported_bands = SUPPORT_BAND_2GHZ;
2218 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2219 spec->tx_power_a = NULL;
2220 spec->tx_power_bg = txpower;
2221 spec->tx_power_default = DEFAULT_TXPOWER;
2223 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2224 spec->num_channels = 14;
2225 spec->channels = rf_vals_noseq;
2227 spec->num_channels = 14;
2228 spec->channels = rf_vals_seq;
2231 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2232 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2233 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2234 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2236 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2237 for (i = 0; i < 14; i++)
2238 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2240 spec->tx_power_a = txpower;
2244 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2249 * Allocate eeprom data.
2251 retval = rt61pci_validate_eeprom(rt2x00dev);
2255 retval = rt61pci_init_eeprom(rt2x00dev);
2260 * Initialize hw specifications.
2262 rt61pci_probe_hw_mode(rt2x00dev);
2265 * This device requires firmware.
2267 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2270 * Set the rssi offset.
2272 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2278 * IEEE80211 stack callback functions.
2280 static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2281 unsigned int changed_flags,
2282 unsigned int *total_flags,
2284 struct dev_addr_list *mc_list)
2286 struct rt2x00_dev *rt2x00dev = hw->priv;
2290 * Mask off any flags we are going to ignore from
2291 * the total_flags field.
2302 * Apply some rules to the filters:
2303 * - Some filters imply different filters to be set.
2304 * - Some things we can't filter out at all.
2307 *total_flags |= FIF_ALLMULTI;
2308 if (*total_flags & FIF_OTHER_BSS ||
2309 *total_flags & FIF_PROMISC_IN_BSS)
2310 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2313 * Check if there is any work left for us.
2315 if (rt2x00dev->packet_filter == *total_flags)
2317 rt2x00dev->packet_filter = *total_flags;
2320 * Start configuration steps.
2321 * Note that the version error will always be dropped
2322 * and broadcast frames will always be accepted since
2323 * there is no filter for it at this time.
2325 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
2326 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
2327 !(*total_flags & FIF_FCSFAIL));
2328 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
2329 !(*total_flags & FIF_PLCPFAIL));
2330 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
2331 !(*total_flags & FIF_CONTROL));
2332 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
2333 !(*total_flags & FIF_PROMISC_IN_BSS));
2334 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
2335 !(*total_flags & FIF_PROMISC_IN_BSS));
2336 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2337 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
2338 !(*total_flags & FIF_ALLMULTI));
2339 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
2340 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS,
2341 !(*total_flags & FIF_CONTROL));
2342 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2345 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2346 u32 short_retry, u32 long_retry)
2348 struct rt2x00_dev *rt2x00dev = hw->priv;
2351 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
2352 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2353 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2354 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2359 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2361 struct rt2x00_dev *rt2x00dev = hw->priv;
2365 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
2366 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2367 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);
2368 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2373 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2374 struct ieee80211_tx_control *control)
2376 struct rt2x00_dev *rt2x00dev = hw->priv;
2377 struct rt2x00_intf *intf = vif_to_intf(control->vif);
2378 struct skb_frame_desc *skbdesc;
2379 unsigned int beacon_base;
2382 if (unlikely(!intf->beacon))
2386 * We need to append the descriptor in front of the
2389 if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
2390 if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
2398 * Add the descriptor in front of the skb.
2400 skb_push(skb, intf->beacon->queue->desc_size);
2401 memset(skb->data, 0, intf->beacon->queue->desc_size);
2404 * Fill in skb descriptor
2406 skbdesc = get_skb_frame_desc(skb);
2407 memset(skbdesc, 0, sizeof(*skbdesc));
2408 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2409 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2410 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
2411 skbdesc->desc = skb->data;
2412 skbdesc->desc_len = intf->beacon->queue->desc_size;
2413 skbdesc->entry = intf->beacon;
2416 * Disable beaconing while we are reloading the beacon data,
2417 * otherwise we might be sending out invalid data.
2419 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
2420 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
2421 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
2422 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
2423 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2426 * mac80211 doesn't provide the control->queue variable
2427 * for beacons. Set our own queue identification so
2428 * it can be used during descriptor initialization.
2430 control->queue = RT2X00_BCN_QUEUE_BEACON;
2431 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2434 * Write entire beacon with descriptor to register,
2435 * and kick the beacon generator.
2437 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2438 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2439 skb->data, skb->len);
2440 rt61pci_kick_tx_queue(rt2x00dev, control->queue);
2445 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2447 .start = rt2x00mac_start,
2448 .stop = rt2x00mac_stop,
2449 .add_interface = rt2x00mac_add_interface,
2450 .remove_interface = rt2x00mac_remove_interface,
2451 .config = rt2x00mac_config,
2452 .config_interface = rt2x00mac_config_interface,
2453 .configure_filter = rt61pci_configure_filter,
2454 .get_stats = rt2x00mac_get_stats,
2455 .set_retry_limit = rt61pci_set_retry_limit,
2456 .bss_info_changed = rt2x00mac_bss_info_changed,
2457 .conf_tx = rt2x00mac_conf_tx,
2458 .get_tx_stats = rt2x00mac_get_tx_stats,
2459 .get_tsf = rt61pci_get_tsf,
2460 .beacon_update = rt61pci_beacon_update,
2463 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2464 .irq_handler = rt61pci_interrupt,
2465 .probe_hw = rt61pci_probe_hw,
2466 .get_firmware_name = rt61pci_get_firmware_name,
2467 .get_firmware_crc = rt61pci_get_firmware_crc,
2468 .load_firmware = rt61pci_load_firmware,
2469 .initialize = rt2x00pci_initialize,
2470 .uninitialize = rt2x00pci_uninitialize,
2471 .init_rxentry = rt61pci_init_rxentry,
2472 .init_txentry = rt61pci_init_txentry,
2473 .set_device_state = rt61pci_set_device_state,
2474 .rfkill_poll = rt61pci_rfkill_poll,
2475 .link_stats = rt61pci_link_stats,
2476 .reset_tuner = rt61pci_reset_tuner,
2477 .link_tuner = rt61pci_link_tuner,
2478 .led_brightness = rt61pci_led_brightness,
2479 .write_tx_desc = rt61pci_write_tx_desc,
2480 .write_tx_data = rt2x00pci_write_tx_data,
2481 .kick_tx_queue = rt61pci_kick_tx_queue,
2482 .fill_rxdone = rt61pci_fill_rxdone,
2483 .config_intf = rt61pci_config_intf,
2484 .config_preamble = rt61pci_config_preamble,
2485 .config = rt61pci_config,
2488 static const struct data_queue_desc rt61pci_queue_rx = {
2489 .entry_num = RX_ENTRIES,
2490 .data_size = DATA_FRAME_SIZE,
2491 .desc_size = RXD_DESC_SIZE,
2492 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
2495 static const struct data_queue_desc rt61pci_queue_tx = {
2496 .entry_num = TX_ENTRIES,
2497 .data_size = DATA_FRAME_SIZE,
2498 .desc_size = TXD_DESC_SIZE,
2499 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2502 static const struct data_queue_desc rt61pci_queue_bcn = {
2503 .entry_num = 4 * BEACON_ENTRIES,
2504 .data_size = MGMT_FRAME_SIZE,
2505 .desc_size = TXINFO_SIZE,
2506 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2509 static const struct rt2x00_ops rt61pci_ops = {
2510 .name = KBUILD_MODNAME,
2513 .eeprom_size = EEPROM_SIZE,
2515 .rx = &rt61pci_queue_rx,
2516 .tx = &rt61pci_queue_tx,
2517 .bcn = &rt61pci_queue_bcn,
2518 .lib = &rt61pci_rt2x00_ops,
2519 .hw = &rt61pci_mac80211_ops,
2520 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2521 .debugfs = &rt61pci_rt2x00debug,
2522 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2526 * RT61pci module information.
2528 static struct pci_device_id rt61pci_device_table[] = {
2530 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2532 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2534 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2538 MODULE_AUTHOR(DRV_PROJECT);
2539 MODULE_VERSION(DRV_VERSION);
2540 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2541 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2542 "PCI & PCMCIA chipset based cards");
2543 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2544 MODULE_FIRMWARE(FIRMWARE_RT2561);
2545 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2546 MODULE_FIRMWARE(FIRMWARE_RT2661);
2547 MODULE_LICENSE("GPL");
2549 static struct pci_driver rt61pci_driver = {
2550 .name = KBUILD_MODNAME,
2551 .id_table = rt61pci_device_table,
2552 .probe = rt2x00pci_probe,
2553 .remove = __devexit_p(rt2x00pci_remove),
2554 .suspend = rt2x00pci_suspend,
2555 .resume = rt2x00pci_resume,
2558 static int __init rt61pci_init(void)
2560 return pci_register_driver(&rt61pci_driver);
2563 static void __exit rt61pci_exit(void)
2565 pci_unregister_driver(&rt61pci_driver);
2568 module_init(rt61pci_init);
2569 module_exit(rt61pci_exit);