2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
118 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
119 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
121 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
122 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
124 #define MUSB_VERSION "6.0"
126 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
128 #define MUSB_DRIVER_NAME "musb_hdrc"
129 const char musb_driver_name[] = MUSB_DRIVER_NAME;
131 MODULE_DESCRIPTION(DRIVER_INFO);
132 MODULE_AUTHOR(DRIVER_AUTHOR);
133 MODULE_LICENSE("GPL");
134 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
137 /*-------------------------------------------------------------------------*/
139 static inline struct musb *dev_to_musb(struct device *dev)
141 #ifdef CONFIG_USB_MUSB_HDRC_HCD
142 /* usbcore insists dev->driver_data is a "struct hcd *" */
143 return hcd_to_musb(dev_get_drvdata(dev));
145 return dev_get_drvdata(dev);
149 /*-------------------------------------------------------------------------*/
151 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
154 * Load an endpoint's FIFO
156 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
158 void __iomem *fifo = hw_ep->fifo;
162 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
163 'T', hw_ep->epnum, fifo, len, src);
165 /* we can't assume unaligned reads work */
166 if (likely((0x01 & (unsigned long) src) == 0)) {
169 /* best case is 32bit-aligned source address */
170 if ((0x02 & (unsigned long) src) == 0) {
172 writesl(fifo, src + index, len >> 2);
173 index += len & ~0x03;
176 musb_writew(fifo, 0, *(u16 *)&src[index]);
181 writesw(fifo, src + index, len >> 1);
182 index += len & ~0x01;
186 musb_writeb(fifo, 0, src[index]);
189 writesb(fifo, src, len);
194 * Unload an endpoint's FIFO
196 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
198 void __iomem *fifo = hw_ep->fifo;
200 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
201 'R', hw_ep->epnum, fifo, len, dst);
203 /* we can't assume unaligned writes work */
204 if (likely((0x01 & (unsigned long) dst) == 0)) {
207 /* best case is 32bit-aligned destination address */
208 if ((0x02 & (unsigned long) dst) == 0) {
210 readsl(fifo, dst, len >> 2);
214 *(u16 *)&dst[index] = musb_readw(fifo, 0);
219 readsw(fifo, dst, len >> 1);
224 dst[index] = musb_readb(fifo, 0);
227 readsb(fifo, dst, len);
231 #endif /* normal PIO */
234 /*-------------------------------------------------------------------------*/
236 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
237 static const u8 musb_test_packet[53] = {
238 /* implicit SYNC then DATA0 to start */
241 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
243 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
245 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
246 /* JJJJJJJKKKKKKK x8 */
247 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
249 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
250 /* JKKKKKKK x10, JK */
251 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
253 /* implicit CRC16 then EOP to end */
256 void musb_load_testpacket(struct musb *musb)
258 void __iomem *regs = musb->endpoints[0].regs;
260 musb_ep_select(musb->mregs, 0);
261 musb_write_fifo(musb->control_ep,
262 sizeof(musb_test_packet), musb_test_packet);
263 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
266 /*-------------------------------------------------------------------------*/
268 const char *otg_state_string(struct musb *musb)
270 switch (musb->xceiv.state) {
271 case OTG_STATE_A_IDLE: return "a_idle";
272 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
273 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
274 case OTG_STATE_A_HOST: return "a_host";
275 case OTG_STATE_A_SUSPEND: return "a_suspend";
276 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
277 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
278 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
279 case OTG_STATE_B_IDLE: return "b_idle";
280 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
281 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
282 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
283 case OTG_STATE_B_HOST: return "b_host";
284 default: return "UNDEFINED";
288 #ifdef CONFIG_USB_MUSB_OTG
291 * See also USB_OTG_1-3.pdf 6.6.5 Timers
292 * REVISIT: Are the other timers done in the hardware?
294 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
297 * Handles OTG hnp timeouts, such as b_ase0_brst
299 void musb_otg_timer_func(unsigned long data)
301 struct musb *musb = (struct musb *)data;
304 spin_lock_irqsave(&musb->lock, flags);
305 switch (musb->xceiv.state) {
306 case OTG_STATE_B_WAIT_ACON:
307 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
308 musb_g_disconnect(musb);
309 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
312 case OTG_STATE_A_WAIT_BCON:
313 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
317 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
319 musb->ignore_disconnect = 0;
320 spin_unlock_irqrestore(&musb->lock, flags);
323 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
326 * Stops the B-device HNP state. Caller must take care of locking.
328 void musb_hnp_stop(struct musb *musb)
330 struct usb_hcd *hcd = musb_to_hcd(musb);
331 void __iomem *mbase = musb->mregs;
334 switch (musb->xceiv.state) {
335 case OTG_STATE_A_PERIPHERAL:
336 case OTG_STATE_A_WAIT_VFALL:
337 case OTG_STATE_A_WAIT_BCON:
338 DBG(1, "HNP: Switching back to A-host\n");
339 musb_g_disconnect(musb);
340 musb->xceiv.state = OTG_STATE_A_IDLE;
344 case OTG_STATE_B_HOST:
345 DBG(1, "HNP: Disabling HR\n");
346 hcd->self.is_b_host = 0;
347 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
349 reg = musb_readb(mbase, MUSB_POWER);
350 reg |= MUSB_POWER_SUSPENDM;
351 musb_writeb(mbase, MUSB_POWER, reg);
352 /* REVISIT: Start SESSION_REQUEST here? */
355 DBG(1, "HNP: Stopping in unknown state %s\n",
356 otg_state_string(musb));
360 * When returning to A state after HNP, avoid hub_port_rebounce(),
361 * which cause occasional OPT A "Did not receive reset after connect"
364 musb->port1_status &=
365 ~(1 << USB_PORT_FEAT_C_CONNECTION);
371 * Interrupt Service Routine to record USB "global" interrupts.
372 * Since these do not happen often and signify things of
373 * paramount importance, it seems OK to check them individually;
374 * the order of the tests is specified in the manual
376 * @param musb instance pointer
377 * @param int_usb register contents
382 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
383 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
386 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
389 irqreturn_t handled = IRQ_NONE;
390 void __iomem *mbase = musb->mregs;
392 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
395 /* in host mode, the peripheral may issue remote wakeup.
396 * in peripheral mode, the host may resume the link.
397 * spurious RESUME irqs happen too, paired with SUSPEND.
399 if (int_usb & MUSB_INTR_RESUME) {
400 handled = IRQ_HANDLED;
401 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
403 if (devctl & MUSB_DEVCTL_HM) {
404 #ifdef CONFIG_USB_MUSB_HDRC_HCD
405 switch (musb->xceiv.state) {
406 case OTG_STATE_A_SUSPEND:
407 /* remote wakeup? later, GetPortStatus
408 * will stop RESUME signaling
411 if (power & MUSB_POWER_SUSPENDM) {
413 musb->int_usb &= ~MUSB_INTR_SUSPEND;
414 DBG(2, "Spurious SUSPENDM\n");
418 power &= ~MUSB_POWER_SUSPENDM;
419 musb_writeb(mbase, MUSB_POWER,
420 power | MUSB_POWER_RESUME);
422 musb->port1_status |=
423 (USB_PORT_STAT_C_SUSPEND << 16)
424 | MUSB_PORT_STAT_RESUME;
425 musb->rh_timer = jiffies
426 + msecs_to_jiffies(20);
428 musb->xceiv.state = OTG_STATE_A_HOST;
430 usb_hcd_resume_root_hub(musb_to_hcd(musb));
432 case OTG_STATE_B_WAIT_ACON:
433 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
438 WARNING("bogus %s RESUME (%s)\n",
440 otg_state_string(musb));
444 switch (musb->xceiv.state) {
445 #ifdef CONFIG_USB_MUSB_HDRC_HCD
446 case OTG_STATE_A_SUSPEND:
447 /* possibly DISCONNECT is upcoming */
448 musb->xceiv.state = OTG_STATE_A_HOST;
449 usb_hcd_resume_root_hub(musb_to_hcd(musb));
452 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
453 case OTG_STATE_B_WAIT_ACON:
454 case OTG_STATE_B_PERIPHERAL:
455 /* disconnect while suspended? we may
456 * not get a disconnect irq...
458 if ((devctl & MUSB_DEVCTL_VBUS)
459 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
461 musb->int_usb |= MUSB_INTR_DISCONNECT;
462 musb->int_usb &= ~MUSB_INTR_SUSPEND;
467 case OTG_STATE_B_IDLE:
468 musb->int_usb &= ~MUSB_INTR_SUSPEND;
472 WARNING("bogus %s RESUME (%s)\n",
474 otg_state_string(musb));
479 #ifdef CONFIG_USB_MUSB_HDRC_HCD
480 /* see manual for the order of the tests */
481 if (int_usb & MUSB_INTR_SESSREQ) {
482 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
484 /* IRQ arrives from ID pin sense or (later, if VBUS power
485 * is removed) SRP. responses are time critical:
486 * - turn on VBUS (with silicon-specific mechanism)
487 * - go through A_WAIT_VRISE
488 * - ... to A_WAIT_BCON.
489 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
491 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
492 musb->ep0_stage = MUSB_EP0_START;
493 musb->xceiv.state = OTG_STATE_A_IDLE;
495 musb_set_vbus(musb, 1);
497 handled = IRQ_HANDLED;
500 if (int_usb & MUSB_INTR_VBUSERROR) {
503 /* During connection as an A-Device, we may see a short
504 * current spikes causing voltage drop, because of cable
505 * and peripheral capacitance combined with vbus draw.
506 * (So: less common with truly self-powered devices, where
507 * vbus doesn't act like a power supply.)
509 * Such spikes are short; usually less than ~500 usec, max
510 * of ~2 msec. That is, they're not sustained overcurrent
511 * errors, though they're reported using VBUSERROR irqs.
513 * Workarounds: (a) hardware: use self powered devices.
514 * (b) software: ignore non-repeated VBUS errors.
516 * REVISIT: do delays from lots of DEBUG_KERNEL checks
517 * make trouble here, keeping VBUS < 4.4V ?
519 switch (musb->xceiv.state) {
520 case OTG_STATE_A_HOST:
521 /* recovery is dicey once we've gotten past the
522 * initial stages of enumeration, but if VBUS
523 * stayed ok at the other end of the link, and
524 * another reset is due (at least for high speed,
525 * to redo the chirp etc), it might work OK...
527 case OTG_STATE_A_WAIT_BCON:
528 case OTG_STATE_A_WAIT_VRISE:
529 if (musb->vbuserr_retry) {
530 musb->vbuserr_retry--;
532 devctl |= MUSB_DEVCTL_SESSION;
533 musb_writeb(mbase, MUSB_DEVCTL, devctl);
535 musb->port1_status |=
536 (1 << USB_PORT_FEAT_OVER_CURRENT)
537 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
544 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
545 otg_state_string(musb),
548 switch (devctl & MUSB_DEVCTL_VBUS) {
549 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
550 s = "<SessEnd"; break;
551 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
552 s = "<AValid"; break;
553 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
554 s = "<VBusValid"; break;
555 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
559 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
562 /* go through A_WAIT_VFALL then start a new session */
564 musb_set_vbus(musb, 0);
565 handled = IRQ_HANDLED;
568 if (int_usb & MUSB_INTR_CONNECT) {
569 struct usb_hcd *hcd = musb_to_hcd(musb);
571 handled = IRQ_HANDLED;
573 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
575 musb->ep0_stage = MUSB_EP0_START;
577 #ifdef CONFIG_USB_MUSB_OTG
578 /* flush endpoints when transitioning from Device Mode */
579 if (is_peripheral_active(musb)) {
580 /* REVISIT HNP; just force disconnect */
582 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
583 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
584 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
586 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
587 |USB_PORT_STAT_HIGH_SPEED
588 |USB_PORT_STAT_ENABLE
590 musb->port1_status |= USB_PORT_STAT_CONNECTION
591 |(USB_PORT_STAT_C_CONNECTION << 16);
593 /* high vs full speed is just a guess until after reset */
594 if (devctl & MUSB_DEVCTL_LSDEV)
595 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
598 usb_hcd_poll_rh_status(hcd);
600 usb_hcd_resume_root_hub(hcd);
604 /* indicate new connection to OTG machine */
605 switch (musb->xceiv.state) {
606 case OTG_STATE_B_PERIPHERAL:
607 if (int_usb & MUSB_INTR_SUSPEND) {
608 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
609 musb->xceiv.state = OTG_STATE_B_HOST;
610 hcd->self.is_b_host = 1;
611 int_usb &= ~MUSB_INTR_SUSPEND;
613 DBG(1, "CONNECT as b_peripheral???\n");
615 case OTG_STATE_B_WAIT_ACON:
616 DBG(1, "HNP: Waiting to switch to b_host state\n");
617 musb->xceiv.state = OTG_STATE_B_HOST;
618 hcd->self.is_b_host = 1;
621 if ((devctl & MUSB_DEVCTL_VBUS)
622 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
623 musb->xceiv.state = OTG_STATE_A_HOST;
624 hcd->self.is_b_host = 0;
628 DBG(1, "CONNECT (%s) devctl %02x\n",
629 otg_state_string(musb), devctl);
631 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
633 /* mentor saves a bit: bus reset and babble share the same irq.
634 * only host sees babble; only peripheral sees bus reset.
636 if (int_usb & MUSB_INTR_RESET) {
637 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
639 * Looks like non-HS BABBLE can be ignored, but
640 * HS BABBLE is an error condition. For HS the solution
641 * is to avoid babble in the first place and fix what
642 * caused BABBLE. When HS BABBLE happens we can only
645 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
646 DBG(1, "BABBLE devctl: %02x\n", devctl);
648 ERR("Stopping host session -- babble\n");
649 musb_writeb(mbase, MUSB_DEVCTL, 0);
651 } else if (is_peripheral_capable()) {
652 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
653 switch (musb->xceiv.state) {
654 #ifdef CONFIG_USB_OTG
655 case OTG_STATE_A_SUSPEND:
656 /* We need to ignore disconnect on suspend
657 * otherwise tusb 2.0 won't reconnect after a
658 * power cycle, which breaks otg compliance.
660 musb->ignore_disconnect = 1;
663 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
664 DBG(1, "HNP: Setting timer as %s\n",
665 otg_state_string(musb));
666 musb_otg_timer.data = (unsigned long)musb;
667 mod_timer(&musb_otg_timer, jiffies
668 + msecs_to_jiffies(100));
670 case OTG_STATE_A_PERIPHERAL:
673 case OTG_STATE_B_WAIT_ACON:
674 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
675 otg_state_string(musb));
676 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
680 case OTG_STATE_B_IDLE:
681 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
683 case OTG_STATE_B_PERIPHERAL:
687 DBG(1, "Unhandled BUS RESET as %s\n",
688 otg_state_string(musb));
692 handled = IRQ_HANDLED;
694 schedule_work(&musb->irq_work);
700 * Interrupt Service Routine to record USB "global" interrupts.
701 * Since these do not happen often and signify things of
702 * paramount importance, it seems OK to check them individually;
703 * the order of the tests is specified in the manual
705 * @param musb instance pointer
706 * @param int_usb register contents
710 static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
713 irqreturn_t handled = IRQ_NONE;
716 /* REVISIT ... this would be for multiplexing periodic endpoints, or
717 * supporting transfer phasing to prevent exceeding ISO bandwidth
718 * limits of a given frame or microframe.
720 * It's not needed for peripheral side, which dedicates endpoints;
721 * though it _might_ use SOF irqs for other purposes.
723 * And it's not currently needed for host side, which also dedicates
724 * endpoints, relies on TX/RX interval registers, and isn't claimed
725 * to support ISO transfers yet.
727 if (int_usb & MUSB_INTR_SOF) {
728 void __iomem *mbase = musb->mregs;
729 struct musb_hw_ep *ep;
733 DBG(6, "START_OF_FRAME\n");
734 handled = IRQ_HANDLED;
736 /* start any periodic Tx transfers waiting for current frame */
737 frame = musb_readw(mbase, MUSB_FRAME);
738 ep = musb->endpoints;
739 for (epnum = 1; (epnum < musb->nr_endpoints)
740 && (musb->epmask >= (1 << epnum));
743 * FIXME handle framecounter wraps (12 bits)
744 * eliminate duplicated StartUrb logic
746 if (ep->dwWaitFrame >= frame) {
748 pr_debug("SOF --> periodic TX%s on %d\n",
749 ep->tx_channel ? " DMA" : "",
752 musb_h_tx_start(musb, epnum);
754 cppi_hostdma_start(musb, epnum);
756 } /* end of for loop */
760 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
761 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
762 otg_state_string(musb),
763 MUSB_MODE(musb), devctl);
764 handled = IRQ_HANDLED;
766 switch (musb->xceiv.state) {
767 #ifdef CONFIG_USB_MUSB_HDRC_HCD
768 case OTG_STATE_A_HOST:
769 case OTG_STATE_A_SUSPEND:
770 usb_hcd_resume_root_hub(musb_to_hcd(musb));
771 musb_root_disconnect(musb);
772 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
773 musb_platform_try_idle(musb, jiffies
774 + msecs_to_jiffies(musb->a_wait_bcon));
777 #ifdef CONFIG_USB_MUSB_OTG
778 case OTG_STATE_B_HOST:
781 case OTG_STATE_A_PERIPHERAL:
783 musb_root_disconnect(musb);
785 case OTG_STATE_B_WAIT_ACON:
788 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
789 case OTG_STATE_B_PERIPHERAL:
790 case OTG_STATE_B_IDLE:
791 musb_g_disconnect(musb);
795 WARNING("unhandled DISCONNECT transition (%s)\n",
796 otg_state_string(musb));
800 schedule_work(&musb->irq_work);
803 if (int_usb & MUSB_INTR_SUSPEND) {
804 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
805 otg_state_string(musb), devctl, power);
806 handled = IRQ_HANDLED;
808 switch (musb->xceiv.state) {
809 #ifdef CONFIG_USB_MUSB_OTG
810 case OTG_STATE_A_PERIPHERAL:
812 * We cannot stop HNP here, devctl BDEVICE might be
817 case OTG_STATE_B_PERIPHERAL:
818 musb_g_suspend(musb);
819 musb->is_active = is_otg_enabled(musb)
820 && musb->xceiv.gadget->b_hnp_enable;
821 if (musb->is_active) {
822 #ifdef CONFIG_USB_MUSB_OTG
823 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
824 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
825 musb_otg_timer.data = (unsigned long)musb;
826 mod_timer(&musb_otg_timer, jiffies
827 + msecs_to_jiffies(TB_ASE0_BRST));
831 case OTG_STATE_A_WAIT_BCON:
832 if (musb->a_wait_bcon != 0)
833 musb_platform_try_idle(musb, jiffies
834 + msecs_to_jiffies(musb->a_wait_bcon));
836 case OTG_STATE_A_HOST:
837 musb->xceiv.state = OTG_STATE_A_SUSPEND;
838 musb->is_active = is_otg_enabled(musb)
839 && musb->xceiv.host->b_hnp_enable;
841 case OTG_STATE_B_HOST:
842 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
843 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
846 /* "should not happen" */
850 schedule_work(&musb->irq_work);
857 /*-------------------------------------------------------------------------*/
860 * Program the HDRC to start (enable interrupts, dma, etc.).
862 void musb_start(struct musb *musb)
864 void __iomem *regs = musb->mregs;
865 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
867 DBG(2, "<== devctl %02x\n", devctl);
869 /* Set INT enable registers, enable interrupts */
870 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
871 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
872 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
874 musb_writeb(regs, MUSB_TESTMODE, 0);
876 /* put into basic highspeed mode and start session */
877 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
878 | MUSB_POWER_SOFTCONN
880 /* ENSUSPEND wedges tusb */
881 /* | MUSB_POWER_ENSUSPEND */
885 devctl = musb_readb(regs, MUSB_DEVCTL);
886 devctl &= ~MUSB_DEVCTL_SESSION;
888 if (is_otg_enabled(musb)) {
889 /* session started after:
890 * (a) ID-grounded irq, host mode;
891 * (b) vbus present/connect IRQ, peripheral mode;
892 * (c) peripheral initiates, using SRP
894 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
897 devctl |= MUSB_DEVCTL_SESSION;
899 } else if (is_host_enabled(musb)) {
900 /* assume ID pin is hard-wired to ground */
901 devctl |= MUSB_DEVCTL_SESSION;
903 } else /* peripheral is enabled */ {
904 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
907 musb_platform_enable(musb);
908 musb_writeb(regs, MUSB_DEVCTL, devctl);
912 static void musb_generic_disable(struct musb *musb)
914 void __iomem *mbase = musb->mregs;
917 /* disable interrupts */
918 musb_writeb(mbase, MUSB_INTRUSBE, 0);
919 musb_writew(mbase, MUSB_INTRTXE, 0);
920 musb_writew(mbase, MUSB_INTRRXE, 0);
923 musb_writeb(mbase, MUSB_DEVCTL, 0);
925 /* flush pending interrupts */
926 temp = musb_readb(mbase, MUSB_INTRUSB);
927 temp = musb_readw(mbase, MUSB_INTRTX);
928 temp = musb_readw(mbase, MUSB_INTRRX);
933 * Make the HDRC stop (disable interrupts, etc.);
934 * reversible by musb_start
935 * called on gadget driver unregister
936 * with controller locked, irqs blocked
937 * acts as a NOP unless some role activated the hardware
939 void musb_stop(struct musb *musb)
941 /* stop IRQs, timers, ... */
942 musb_platform_disable(musb);
943 musb_generic_disable(musb);
944 DBG(3, "HDRC disabled\n");
947 * - mark host and/or peripheral drivers unusable/inactive
948 * - disable DMA (and enable it in HdrcStart)
949 * - make sure we can musb_start() after musb_stop(); with
950 * OTG mode, gadget driver module rmmod/modprobe cycles that
953 musb_platform_try_idle(musb, 0);
956 static void musb_shutdown(struct platform_device *pdev)
958 struct musb *musb = dev_to_musb(&pdev->dev);
961 spin_lock_irqsave(&musb->lock, flags);
962 musb_platform_disable(musb);
963 musb_generic_disable(musb);
965 clk_put(musb->clock);
968 spin_unlock_irqrestore(&musb->lock, flags);
970 /* FIXME power down */
974 /*-------------------------------------------------------------------------*/
977 * The silicon either has hard-wired endpoint configurations, or else
978 * "dynamic fifo" sizing. The driver has support for both, though at this
979 * writing only the dynamic sizing is very well tested. Since we switched
980 * away from compile-time hardware parameters, we can no longer rely on
981 * dead code elimination to leave only the relevant one in the object file.
983 * We don't currently use dynamic fifo setup capability to do anything
984 * more than selecting one of a bunch of predefined configurations.
986 #if defined(CONFIG_USB_TUSB6010) || \
987 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
988 static ushort __initdata fifo_mode = 4;
990 static ushort __initdata fifo_mode = 2;
993 /* "modprobe ... fifo_mode=1" etc */
994 module_param(fifo_mode, ushort, 0);
995 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
998 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
999 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1003 enum fifo_style style;
1009 * tables defining fifo_mode values. define more if you like.
1010 * for host side, make sure both halves of ep1 are set up.
1013 /* mode 0 - fits in 2KB */
1014 static struct fifo_cfg __initdata mode_0_cfg[] = {
1015 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1016 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1017 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1018 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1019 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1022 /* mode 1 - fits in 4KB */
1023 static struct fifo_cfg __initdata mode_1_cfg[] = {
1024 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1025 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1026 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1027 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1028 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1031 /* mode 2 - fits in 4KB */
1032 static struct fifo_cfg __initdata mode_2_cfg[] = {
1033 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1034 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1035 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1036 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1037 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1038 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1041 /* mode 3 - fits in 4KB */
1042 static struct fifo_cfg __initdata mode_3_cfg[] = {
1043 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1044 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1045 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1046 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1047 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1048 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1051 /* mode 4 - fits in 16KB */
1052 static struct fifo_cfg __initdata mode_4_cfg[] = {
1053 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1054 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1055 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1056 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1057 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1058 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1059 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1060 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1061 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1062 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1063 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1064 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1065 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1066 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1067 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1068 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1069 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1070 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1071 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1072 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1073 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1074 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1075 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1076 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1077 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1078 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1079 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1080 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1085 * configure a fifo; for non-shared endpoints, this may be called
1086 * once for a tx fifo and once for an rx fifo.
1088 * returns negative errno or offset for next fifo.
1091 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1092 const struct fifo_cfg *cfg, u16 offset)
1094 void __iomem *mbase = musb->mregs;
1096 u16 maxpacket = cfg->maxpacket;
1097 u16 c_off = offset >> 3;
1100 /* expect hw_ep has already been zero-initialized */
1102 size = ffs(max(maxpacket, (u16) 8)) - 1;
1103 maxpacket = 1 << size;
1106 if (cfg->mode == BUF_DOUBLE) {
1107 if ((offset + (maxpacket << 1)) >
1108 (1 << (musb->config->ram_bits + 2)))
1110 c_size |= MUSB_FIFOSZ_DPB;
1112 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1116 /* configure the FIFO */
1117 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1119 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1120 /* EP0 reserved endpoint for control, bidirectional;
1121 * EP1 reserved for bulk, two unidirection halves.
1123 if (hw_ep->epnum == 1)
1124 musb->bulk_ep = hw_ep;
1125 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1127 switch (cfg->style) {
1129 musb_write_txfifosz(mbase, c_size);
1130 musb_write_txfifoadd(mbase, c_off);
1131 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1132 hw_ep->max_packet_sz_tx = maxpacket;
1135 musb_write_rxfifosz(mbase, c_size);
1136 musb_write_rxfifoadd(mbase, c_off);
1137 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1138 hw_ep->max_packet_sz_rx = maxpacket;
1141 musb_write_txfifosz(mbase, c_size);
1142 musb_write_txfifoadd(mbase, c_off);
1143 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1144 hw_ep->max_packet_sz_rx = maxpacket;
1146 musb_write_rxfifosz(mbase, c_size);
1147 musb_write_rxfifoadd(mbase, c_off);
1148 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1149 hw_ep->max_packet_sz_tx = maxpacket;
1151 hw_ep->is_shared_fifo = true;
1155 /* NOTE rx and tx endpoint irqs aren't managed separately,
1156 * which happens to be ok
1158 musb->epmask |= (1 << hw_ep->epnum);
1160 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1163 static struct fifo_cfg __initdata ep0_cfg = {
1164 .style = FIFO_RXTX, .maxpacket = 64,
1167 static int __init ep_config_from_table(struct musb *musb)
1169 const struct fifo_cfg *cfg;
1172 struct musb_hw_ep *hw_ep = musb->endpoints;
1174 switch (fifo_mode) {
1180 n = ARRAY_SIZE(mode_0_cfg);
1184 n = ARRAY_SIZE(mode_1_cfg);
1188 n = ARRAY_SIZE(mode_2_cfg);
1192 n = ARRAY_SIZE(mode_3_cfg);
1196 n = ARRAY_SIZE(mode_4_cfg);
1200 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1201 musb_driver_name, fifo_mode);
1204 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1205 /* assert(offset > 0) */
1207 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1208 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1211 for (i = 0; i < n; i++) {
1212 u8 epn = cfg->hw_ep_num;
1214 if (epn >= musb->config->num_eps) {
1215 pr_debug("%s: invalid ep %d\n",
1216 musb_driver_name, epn);
1219 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1221 pr_debug("%s: mem overrun, ep %d\n",
1222 musb_driver_name, epn);
1226 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1229 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1231 n + 1, musb->config->num_eps * 2 - 1,
1232 offset, (1 << (musb->config->ram_bits + 2)));
1234 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1235 if (!musb->bulk_ep) {
1236 pr_debug("%s: missing bulk\n", musb_driver_name);
1246 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1247 * @param musb the controller
1249 static int __init ep_config_from_hw(struct musb *musb)
1252 struct musb_hw_ep *hw_ep;
1253 void *mbase = musb->mregs;
1256 DBG(2, "<== static silicon ep config\n");
1258 /* FIXME pick up ep0 maxpacket size */
1260 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1261 musb_ep_select(mbase, epnum);
1262 hw_ep = musb->endpoints + epnum;
1264 ret = musb_read_fifosize(musb, hw_ep, epnum);
1268 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1270 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1271 /* pick an RX/TX endpoint for bulk */
1272 if (hw_ep->max_packet_sz_tx < 512
1273 || hw_ep->max_packet_sz_rx < 512)
1276 /* REVISIT: this algorithm is lazy, we should at least
1277 * try to pick a double buffered endpoint.
1281 musb->bulk_ep = hw_ep;
1285 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1286 if (!musb->bulk_ep) {
1287 pr_debug("%s: missing bulk\n", musb_driver_name);
1295 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1297 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1298 * configure endpoints, or take their config from silicon
1300 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1307 u16 hwvers, rev_major, rev_minor;
1308 char aInfo[78], aRevision[32], aDate[12];
1309 void __iomem *mbase = musb->mregs;
1313 /* log core options (read using indexed model) */
1314 musb_ep_select(mbase, 0);
1315 reg = musb_read_configdata(mbase);
1317 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1318 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1319 strcat(aInfo, ", dyn FIFOs");
1320 if (reg & MUSB_CONFIGDATA_MPRXE) {
1321 strcat(aInfo, ", bulk combine");
1323 musb->bulk_combine = true;
1325 strcat(aInfo, " (X)"); /* no driver support */
1328 if (reg & MUSB_CONFIGDATA_MPTXE) {
1329 strcat(aInfo, ", bulk split");
1331 musb->bulk_split = true;
1333 strcat(aInfo, " (X)"); /* no driver support */
1336 if (reg & MUSB_CONFIGDATA_HBRXE) {
1337 strcat(aInfo, ", HB-ISO Rx");
1338 strcat(aInfo, " (X)"); /* no driver support */
1340 if (reg & MUSB_CONFIGDATA_HBTXE) {
1341 strcat(aInfo, ", HB-ISO Tx");
1342 strcat(aInfo, " (X)"); /* no driver support */
1344 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1345 strcat(aInfo, ", SoftConn");
1347 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1348 musb_driver_name, reg, aInfo);
1351 data = musb_readl(mbase, 0x404);
1352 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1353 (data >> 16) & 0xff, (data >> 24) & 0xff);
1354 /* FIXME ID2 and ID3 are unused */
1355 data = musb_readl(mbase, 0x408);
1356 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1357 data = musb_readl(mbase, 0x40c);
1358 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1359 reg = musb_readb(mbase, 0x400);
1360 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1364 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1365 musb->is_multipoint = 1;
1368 musb->is_multipoint = 0;
1370 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1371 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1373 "%s: kernel must blacklist external hubs\n",
1379 /* log release info */
1380 hwvers = musb_read_hwvers(mbase);
1381 rev_major = (hwvers >> 10) & 0x1f;
1382 rev_minor = hwvers & 0x3ff;
1383 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1384 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1385 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1386 musb_driver_name, type, aRevision, aDate);
1389 musb_configure_ep0(musb);
1391 /* discover endpoint configuration */
1392 musb->nr_endpoints = 1;
1395 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1396 if (musb->config->dyn_fifo)
1397 status = ep_config_from_table(musb);
1399 ERR("reconfigure software for Dynamic FIFOs\n");
1403 if (!musb->config->dyn_fifo)
1404 status = ep_config_from_hw(musb);
1406 ERR("reconfigure software for static FIFOs\n");
1414 /* finish init, and print endpoint config */
1415 for (i = 0; i < musb->nr_endpoints; i++) {
1416 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1418 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1419 #ifdef CONFIG_USB_TUSB6010
1420 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1421 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1422 hw_ep->fifo_sync_va =
1423 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1426 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1428 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1431 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1432 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1433 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1434 hw_ep->rx_reinit = 1;
1435 hw_ep->tx_reinit = 1;
1438 if (hw_ep->max_packet_sz_tx) {
1440 "%s: hw_ep %d%s, %smax %d\n",
1441 musb_driver_name, i,
1442 hw_ep->is_shared_fifo ? "shared" : "tx",
1443 hw_ep->tx_double_buffered
1444 ? "doublebuffer, " : "",
1445 hw_ep->max_packet_sz_tx);
1447 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1449 "%s: hw_ep %d%s, %smax %d\n",
1450 musb_driver_name, i,
1452 hw_ep->rx_double_buffered
1453 ? "doublebuffer, " : "",
1454 hw_ep->max_packet_sz_rx);
1456 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1457 DBG(1, "hw_ep %d not configured\n", i);
1463 /*-------------------------------------------------------------------------*/
1465 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1467 static irqreturn_t generic_interrupt(int irq, void *__hci)
1469 unsigned long flags;
1470 irqreturn_t retval = IRQ_NONE;
1471 struct musb *musb = __hci;
1473 spin_lock_irqsave(&musb->lock, flags);
1475 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1476 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1477 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1479 if (musb->int_usb || musb->int_tx || musb->int_rx)
1480 retval = musb_interrupt(musb);
1482 spin_unlock_irqrestore(&musb->lock, flags);
1488 #define generic_interrupt NULL
1492 * handle all the irqs defined by the HDRC core. for now we expect: other
1493 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1494 * will be assigned, and the irq will already have been acked.
1496 * called in irq context with spinlock held, irqs blocked
1498 irqreturn_t musb_interrupt(struct musb *musb)
1500 irqreturn_t retval = IRQ_NONE;
1505 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1506 power = musb_readb(musb->mregs, MUSB_POWER);
1508 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1509 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1510 musb->int_usb, musb->int_tx, musb->int_rx);
1512 /* the core can interrupt us for multiple reasons; docs have
1513 * a generic interrupt flowchart to follow
1515 if (musb->int_usb & STAGE0_MASK)
1516 retval |= musb_stage0_irq(musb, musb->int_usb,
1519 /* "stage 1" is handling endpoint irqs */
1521 /* handle endpoint 0 first */
1522 if (musb->int_tx & 1) {
1523 if (devctl & MUSB_DEVCTL_HM)
1524 retval |= musb_h_ep0_irq(musb);
1526 retval |= musb_g_ep0_irq(musb);
1529 /* RX on endpoints 1-15 */
1530 reg = musb->int_rx >> 1;
1534 /* musb_ep_select(musb->mregs, ep_num); */
1535 /* REVISIT just retval = ep->rx_irq(...) */
1536 retval = IRQ_HANDLED;
1537 if (devctl & MUSB_DEVCTL_HM) {
1538 if (is_host_capable())
1539 musb_host_rx(musb, ep_num);
1541 if (is_peripheral_capable())
1542 musb_g_rx(musb, ep_num);
1550 /* TX on endpoints 1-15 */
1551 reg = musb->int_tx >> 1;
1555 /* musb_ep_select(musb->mregs, ep_num); */
1556 /* REVISIT just retval |= ep->tx_irq(...) */
1557 retval = IRQ_HANDLED;
1558 if (devctl & MUSB_DEVCTL_HM) {
1559 if (is_host_capable())
1560 musb_host_tx(musb, ep_num);
1562 if (is_peripheral_capable())
1563 musb_g_tx(musb, ep_num);
1570 /* finish handling "global" interrupts after handling fifos */
1572 retval |= musb_stage2_irq(musb,
1573 musb->int_usb, devctl, power);
1579 #ifndef CONFIG_MUSB_PIO_ONLY
1580 static int __initdata use_dma = 1;
1582 /* "modprobe ... use_dma=0" etc */
1583 module_param(use_dma, bool, 0);
1584 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1586 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1588 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1590 /* called with controller lock already held */
1593 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1594 if (!is_cppi_enabled()) {
1596 if (devctl & MUSB_DEVCTL_HM)
1597 musb_h_ep0_irq(musb);
1599 musb_g_ep0_irq(musb);
1603 /* endpoints 1..15 */
1605 if (devctl & MUSB_DEVCTL_HM) {
1606 if (is_host_capable())
1607 musb_host_tx(musb, epnum);
1609 if (is_peripheral_capable())
1610 musb_g_tx(musb, epnum);
1614 if (devctl & MUSB_DEVCTL_HM) {
1615 if (is_host_capable())
1616 musb_host_rx(musb, epnum);
1618 if (is_peripheral_capable())
1619 musb_g_rx(musb, epnum);
1629 /*-------------------------------------------------------------------------*/
1634 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1636 struct musb *musb = dev_to_musb(dev);
1637 unsigned long flags;
1640 spin_lock_irqsave(&musb->lock, flags);
1641 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1642 spin_unlock_irqrestore(&musb->lock, flags);
1648 musb_mode_store(struct device *dev, struct device_attribute *attr,
1649 const char *buf, size_t n)
1651 struct musb *musb = dev_to_musb(dev);
1652 unsigned long flags;
1655 spin_lock_irqsave(&musb->lock, flags);
1656 if (sysfs_streq(buf, "host"))
1657 status = musb_platform_set_mode(musb, MUSB_HOST);
1658 else if (sysfs_streq(buf, "peripheral"))
1659 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1660 else if (sysfs_streq(buf, "otg"))
1661 status = musb_platform_set_mode(musb, MUSB_OTG);
1664 spin_unlock_irqrestore(&musb->lock, flags);
1666 return (status == 0) ? n : status;
1668 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1671 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1672 const char *buf, size_t n)
1674 struct musb *musb = dev_to_musb(dev);
1675 unsigned long flags;
1678 if (sscanf(buf, "%lu", &val) < 1) {
1679 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1683 spin_lock_irqsave(&musb->lock, flags);
1684 musb->a_wait_bcon = val;
1685 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1686 musb->is_active = 0;
1687 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1688 spin_unlock_irqrestore(&musb->lock, flags);
1694 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1696 struct musb *musb = dev_to_musb(dev);
1697 unsigned long flags;
1701 spin_lock_irqsave(&musb->lock, flags);
1702 val = musb->a_wait_bcon;
1703 vbus = musb_platform_get_vbus_status(musb);
1704 spin_unlock_irqrestore(&musb->lock, flags);
1706 return sprintf(buf, "Vbus %s, timeout %lu\n",
1707 vbus ? "on" : "off", val);
1709 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1711 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1713 /* Gadget drivers can't know that a host is connected so they might want
1714 * to start SRP, but users can. This allows userspace to trigger SRP.
1717 musb_srp_store(struct device *dev, struct device_attribute *attr,
1718 const char *buf, size_t n)
1720 struct musb *musb = dev_to_musb(dev);
1723 if (sscanf(buf, "%hu", &srp) != 1
1725 printk(KERN_ERR "SRP: Value must be 1\n");
1730 musb_g_wakeup(musb);
1734 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1736 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1740 /* Only used to provide driver mode change events */
1741 static void musb_irq_work(struct work_struct *data)
1743 struct musb *musb = container_of(data, struct musb, irq_work);
1744 static int old_state;
1746 if (musb->xceiv.state != old_state) {
1747 old_state = musb->xceiv.state;
1748 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1752 /* --------------------------------------------------------------------------
1756 static struct musb *__init
1757 allocate_instance(struct device *dev,
1758 struct musb_hdrc_config *config, void __iomem *mbase)
1761 struct musb_hw_ep *ep;
1763 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1764 struct usb_hcd *hcd;
1766 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1769 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1771 musb = hcd_to_musb(hcd);
1772 INIT_LIST_HEAD(&musb->control);
1773 INIT_LIST_HEAD(&musb->in_bulk);
1774 INIT_LIST_HEAD(&musb->out_bulk);
1776 hcd->uses_new_polling = 1;
1778 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1780 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1783 dev_set_drvdata(dev, musb);
1787 musb->mregs = mbase;
1788 musb->ctrl_base = mbase;
1789 musb->nIrq = -ENODEV;
1790 musb->config = config;
1791 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1792 for (epnum = 0, ep = musb->endpoints;
1793 epnum < musb->config->num_eps;
1799 musb->controller = dev;
1803 static void musb_free(struct musb *musb)
1805 /* this has multiple entry modes. it handles fault cleanup after
1806 * probe(), where things may be partially set up, as well as rmmod
1807 * cleanup after everything's been de-activated.
1811 device_remove_file(musb->controller, &dev_attr_mode);
1812 device_remove_file(musb->controller, &dev_attr_vbus);
1813 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1814 device_remove_file(musb->controller, &dev_attr_srp);
1818 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1819 musb_gadget_cleanup(musb);
1822 if (musb->nIrq >= 0) {
1824 disable_irq_wake(musb->nIrq);
1825 free_irq(musb->nIrq, musb);
1827 if (is_dma_capable() && musb->dma_controller) {
1828 struct dma_controller *c = musb->dma_controller;
1831 dma_controller_destroy(c);
1834 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1835 musb_platform_exit(musb);
1836 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1839 clk_disable(musb->clock);
1840 clk_put(musb->clock);
1843 #ifdef CONFIG_USB_MUSB_OTG
1844 put_device(musb->xceiv.dev);
1847 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1848 usb_put_hcd(musb_to_hcd(musb));
1855 * Perform generic per-controller initialization.
1857 * @pDevice: the controller (already clocked, etc)
1859 * @mregs: virtual address of controller registers,
1860 * not yet corrected for platform-specific offsets
1863 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1867 struct musb_hdrc_platform_data *plat = dev->platform_data;
1869 /* The driver might handle more features than the board; OK.
1870 * Fail when the board needs a feature that's not enabled.
1873 dev_dbg(dev, "no platform_data?\n");
1876 switch (plat->mode) {
1878 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1883 case MUSB_PERIPHERAL:
1884 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1890 #ifdef CONFIG_USB_MUSB_OTG
1896 dev_err(dev, "incompatible Kconfig role setting\n");
1901 musb = allocate_instance(dev, plat->config, ctrl);
1905 spin_lock_init(&musb->lock);
1906 musb->board_mode = plat->mode;
1907 musb->board_set_power = plat->set_power;
1908 musb->set_clock = plat->set_clock;
1909 musb->min_power = plat->min_power;
1911 /* Clock usage is chip-specific ... functional clock (DaVinci,
1912 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1913 * code does is make sure a clock handle is available; platform
1914 * code manages it during start/stop and suspend/resume.
1917 musb->clock = clk_get(dev, plat->clock);
1918 if (IS_ERR(musb->clock)) {
1919 status = PTR_ERR(musb->clock);
1925 /* assume vbus is off */
1927 /* platform adjusts musb->mregs and musb->isr if needed,
1928 * and activates clocks
1930 musb->isr = generic_interrupt;
1931 status = musb_platform_init(musb);
1940 #ifndef CONFIG_MUSB_PIO_ONLY
1941 if (use_dma && dev->dma_mask) {
1942 struct dma_controller *c;
1944 c = dma_controller_create(musb, musb->mregs);
1945 musb->dma_controller = c;
1950 /* ideally this would be abstracted in platform setup */
1951 if (!is_dma_capable() || !musb->dma_controller)
1952 dev->dma_mask = NULL;
1954 /* be sure interrupts are disabled before connecting ISR */
1955 musb_platform_disable(musb);
1956 musb_generic_disable(musb);
1958 /* setup musb parts of the core (especially endpoints) */
1959 status = musb_core_init(plat->config->multipoint
1960 ? MUSB_CONTROLLER_MHDRC
1961 : MUSB_CONTROLLER_HDRC, musb);
1965 /* Init IRQ workqueue before request_irq */
1966 INIT_WORK(&musb->irq_work, musb_irq_work);
1968 /* attach to the IRQ */
1969 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1970 dev_err(dev, "request_irq %d failed!\n", nIrq);
1975 /* FIXME this handles wakeup irqs wrong */
1976 if (enable_irq_wake(nIrq) == 0) {
1978 device_init_wakeup(dev, 1);
1983 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1986 switch (musb->board_mode) {
1987 case MUSB_HOST: s = "Host"; break;
1988 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1989 default: s = "OTG"; break;
1992 (is_dma_capable() && musb->dma_controller)
1996 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1997 /* host side needs more setup, except for no-host modes */
1998 if (musb->board_mode != MUSB_PERIPHERAL) {
1999 struct usb_hcd *hcd = musb_to_hcd(musb);
2001 if (musb->board_mode == MUSB_OTG)
2002 hcd->self.otg_port = 1;
2003 musb->xceiv.host = &hcd->self;
2004 hcd->power_budget = 2 * (plat->power ? : 250);
2006 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
2008 /* For the host-only role, we can activate right away.
2009 * (We expect the ID pin to be forcibly grounded!!)
2010 * Otherwise, wait till the gadget driver hooks up.
2012 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2013 MUSB_HST_MODE(musb);
2014 musb->xceiv.default_a = 1;
2015 musb->xceiv.state = OTG_STATE_A_IDLE;
2017 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2021 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2023 musb_readb(musb->mregs, MUSB_DEVCTL),
2024 (musb_readb(musb->mregs, MUSB_DEVCTL)
2025 & MUSB_DEVCTL_BDEVICE
2028 } else /* peripheral is enabled */ {
2029 MUSB_DEV_MODE(musb);
2030 musb->xceiv.default_a = 0;
2031 musb->xceiv.state = OTG_STATE_B_IDLE;
2033 status = musb_gadget_setup(musb);
2037 DBG(1, "%s mode, status %d, dev%02x\n",
2038 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2040 musb_readb(musb->mregs, MUSB_DEVCTL));
2045 status = device_create_file(dev, &dev_attr_mode);
2046 status = device_create_file(dev, &dev_attr_vbus);
2047 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2048 status = device_create_file(dev, &dev_attr_srp);
2049 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2059 device_remove_file(musb->controller, &dev_attr_mode);
2060 device_remove_file(musb->controller, &dev_attr_vbus);
2061 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2062 device_remove_file(musb->controller, &dev_attr_srp);
2065 musb_platform_exit(musb);
2067 dev_err(musb->controller,
2068 "musb_init_controller failed with status %d\n", status);
2071 clk_put(musb->clock);
2072 device_init_wakeup(dev, 0);
2079 /*-------------------------------------------------------------------------*/
2081 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2082 * bridge to a platform device; this driver then suffices.
2085 #ifndef CONFIG_MUSB_PIO_ONLY
2086 static u64 *orig_dma_mask;
2089 static int __init musb_probe(struct platform_device *pdev)
2091 struct device *dev = &pdev->dev;
2092 int irq = platform_get_irq(pdev, 0);
2093 struct resource *iomem;
2096 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2097 if (!iomem || irq == 0)
2100 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2102 dev_err(dev, "ioremap failed\n");
2106 #ifndef CONFIG_MUSB_PIO_ONLY
2107 /* clobbered by use_dma=n */
2108 orig_dma_mask = dev->dma_mask;
2110 return musb_init_controller(dev, irq, base);
2113 static int __devexit musb_remove(struct platform_device *pdev)
2115 struct musb *musb = dev_to_musb(&pdev->dev);
2116 void __iomem *ctrl_base = musb->ctrl_base;
2118 /* this gets called on rmmod.
2119 * - Host mode: host may still be active
2120 * - Peripheral mode: peripheral is deactivated (or never-activated)
2121 * - OTG mode: both roles are deactivated (or never-activated)
2123 musb_shutdown(pdev);
2124 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2125 if (musb->board_mode == MUSB_HOST)
2126 usb_remove_hcd(musb_to_hcd(musb));
2130 device_init_wakeup(&pdev->dev, 0);
2131 #ifndef CONFIG_MUSB_PIO_ONLY
2132 pdev->dev.dma_mask = orig_dma_mask;
2139 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2141 unsigned long flags;
2142 struct musb *musb = dev_to_musb(&pdev->dev);
2147 spin_lock_irqsave(&musb->lock, flags);
2149 if (is_peripheral_active(musb)) {
2150 /* FIXME force disconnect unless we know USB will wake
2151 * the system up quickly enough to respond ...
2153 } else if (is_host_active(musb)) {
2154 /* we know all the children are suspended; sometimes
2155 * they will even be wakeup-enabled.
2159 if (musb->set_clock)
2160 musb->set_clock(musb->clock, 0);
2162 clk_disable(musb->clock);
2163 spin_unlock_irqrestore(&musb->lock, flags);
2167 static int musb_resume_early(struct platform_device *pdev)
2169 struct musb *musb = dev_to_musb(&pdev->dev);
2174 if (musb->set_clock)
2175 musb->set_clock(musb->clock, 1);
2177 clk_enable(musb->clock);
2179 /* for static cmos like DaVinci, register values were preserved
2180 * unless for some reason the whole soc powered down or the USB
2181 * module got reset through the PSC (vs just being disabled).
2187 #define musb_suspend NULL
2188 #define musb_resume_early NULL
2191 static struct platform_driver musb_driver = {
2193 .name = (char *)musb_driver_name,
2194 .bus = &platform_bus_type,
2195 .owner = THIS_MODULE,
2197 .remove = __devexit_p(musb_remove),
2198 .shutdown = musb_shutdown,
2199 .suspend = musb_suspend,
2200 .resume_early = musb_resume_early,
2203 /*-------------------------------------------------------------------------*/
2205 static int __init musb_init(void)
2207 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2212 pr_info("%s: version " MUSB_VERSION ", "
2213 #ifdef CONFIG_MUSB_PIO_ONLY
2215 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2217 #elif defined(CONFIG_USB_INVENTRA_DMA)
2219 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2225 #ifdef CONFIG_USB_MUSB_OTG
2226 "otg (peripheral+host)"
2227 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2229 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2233 musb_driver_name, musb_debug);
2234 return platform_driver_probe(&musb_driver, musb_probe);
2237 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2238 * and before usb gadget and host-side drivers start to register
2240 fs_initcall(musb_init);
2242 static void __exit musb_cleanup(void)
2244 platform_driver_unregister(&musb_driver);
2246 module_exit(musb_cleanup);