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   1 /*****************************************************************************
   2  *                                                                           *
   3  * File: common.h                                                            *
   4  * $Revision: 1.5 $                                                          *
   5  * $Date: 2005/03/23 07:41:27 $                                              *
   6  * Description:                                                              *
   7  *  part of the Chelsio 10Gb Ethernet Driver.                                *
   8  *                                                                           *
   9  * This program is free software; you can redistribute it and/or modify      *
  10  * it under the terms of the GNU General Public License, version 2, as       *
  11  * published by the Free Software Foundation.                                *
  12  *                                                                           *
  13  * You should have received a copy of the GNU General Public License along   *
  14  * with this program; if not, write to the Free Software Foundation, Inc.,   *
  15  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
  16  *                                                                           *
  17  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
  18  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
  19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
  20  *                                                                           *
  21  * http://www.chelsio.com                                                    *
  22  *                                                                           *
  23  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
  24  * All rights reserved.                                                      *
  25  *                                                                           *
  26  * Maintainers: maintainers@chelsio.com                                      *
  27  *                                                                           *
  28  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
  29  *          Tina Yang               <tainay@chelsio.com>                     *
  30  *          Felix Marti             <felix@chelsio.com>                      *
  31  *          Scott Bardone           <sbardone@chelsio.com>                   *
  32  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
  33  *          Frank DiMambro          <frank@chelsio.com>                      *
  34  *                                                                           *
  35  * History:                                                                  *
  36  *                                                                           *
  37  ****************************************************************************/
  38
  39 #ifndef CHELSIO_COMMON_H
  40 #define CHELSIO_COMMON_H
  41
  42 #define DIMOF(x) (sizeof(x)/sizeof(x[0]))
  43
  44 #define NMTUS      8
  45 #define MAX_NPORTS 4
  46 #define TCB_SIZE   128
  47
  48 enum {
  49         CHBT_BOARD_7500,
  50         CHBT_BOARD_8000,
  51         CHBT_BOARD_CHT101,
  52         CHBT_BOARD_CHT110,
  53         CHBT_BOARD_CHT210,
  54         CHBT_BOARD_CHT204,
  55         CHBT_BOARD_N110,
  56         CHBT_BOARD_N210,
  57         CHBT_BOARD_COUGAR,
  58         CHBT_BOARD_6800,
  59         CHBT_BOARD_SIMUL
  60 };
  61
  62 enum {
  63         CHBT_TERM_FPGA,
  64         CHBT_TERM_T1,
  65         CHBT_TERM_T2,
  66         CHBT_TERM_T3
  67 };
  68
  69 enum {
  70         CHBT_MAC_CHELSIO_A,
  71         CHBT_MAC_IXF1010,
  72         CHBT_MAC_PM3393,
  73         CHBT_MAC_VSC7321,
  74         CHBT_MAC_DUMMY
  75 };
  76
  77 enum {
  78         CHBT_PHY_88E1041,
  79         CHBT_PHY_88E1111,
  80         CHBT_PHY_88X2010,
  81         CHBT_PHY_XPAK,
  82         CHBT_PHY_MY3126,
  83         CHBT_PHY_DUMMY
  84 };
  85
  86 enum {
  87         PAUSE_RX = 1,
  88         PAUSE_TX = 2,
  89         PAUSE_AUTONEG = 4
  90 };
  91
  92 /* Revisions of T1 chip */
  93 #define TERM_T1A     0
  94 #define TERM_T1B     1
  95 #define TERM_T2      3
  96
  97 struct tp_params {
  98         unsigned int pm_size;
  99         unsigned int cm_size;
 100         unsigned int pm_rx_base;
 101         unsigned int pm_tx_base;
 102         unsigned int pm_rx_pg_size;
 103         unsigned int pm_tx_pg_size;
 104         unsigned int pm_rx_num_pgs;
 105         unsigned int pm_tx_num_pgs;
 106         unsigned int use_5tuple_mode;
 107 };
 108
 109 struct sge_params {
 110         unsigned int cmdQ_size[2];
 111         unsigned int freelQ_size[2];
 112         unsigned int large_buf_capacity;
 113         unsigned int rx_coalesce_usecs;
 114         unsigned int last_rx_coalesce_raw;
 115         unsigned int default_rx_coalesce_usecs;
 116         unsigned int sample_interval_usecs;
 117         unsigned int coalesce_enable;
 118         unsigned int polling;
 119 };
 120
 121 struct mc5_params {
 122         unsigned int mode;      /* selects MC5 width */
 123         unsigned int nservers;  /* size of server region */
 124         unsigned int nroutes;   /* size of routing region */
 125 };
 126
 127 /* Default MC5 region sizes */
 128 #define DEFAULT_SERVER_REGION_LEN 256
 129 #define DEFAULT_RT_REGION_LEN 1024
 130
 131 struct pci_params {
 132         unsigned short speed;
 133         unsigned char  width;
 134         unsigned char  is_pcix;
 135 };
 136
 137 struct adapter_params {
 138         struct sge_params sge;
 139         struct mc5_params mc5;
 140         struct tp_params  tp;
 141         struct pci_params pci;
 142
 143         const struct board_info *brd_info;
 144
 145         unsigned short mtus[NMTUS];
 146         unsigned int   nports;         /* # of ethernet ports */
 147         unsigned int   stats_update_period;
 148         unsigned short chip_revision;
 149         unsigned char  chip_version;
 150         unsigned char  is_asic;
 151 };
 152
 153 struct pci_err_cnt {
 154         unsigned int master_parity_err;
 155         unsigned int sig_target_abort;
 156         unsigned int rcv_target_abort;
 157         unsigned int rcv_master_abort;
 158         unsigned int sig_sys_err;
 159         unsigned int det_parity_err;
 160         unsigned int pio_parity_err;
 161         unsigned int wf_parity_err;
 162         unsigned int rf_parity_err;
 163         unsigned int cf_parity_err;
 164 };
 165
 166 struct link_config {
 167         unsigned int   supported;        /* link capabilities */
 168         unsigned int   advertising;      /* advertised capabilities */
 169         unsigned short requested_speed;  /* speed user has requested */
 170         unsigned short speed;            /* actual link speed */
 171         unsigned char  requested_duplex; /* duplex user has requested */
 172         unsigned char  duplex;           /* actual link duplex */
 173         unsigned char  requested_fc;     /* flow control user has requested */
 174         unsigned char  fc;               /* actual link flow control */
 175         unsigned char  autoneg;          /* autonegotiating? */
 176 };
 177
 178 #define SPEED_INVALID   0xffff
 179 #define DUPLEX_INVALID  0xff
 180
 181 struct mdio_ops;
 182 struct gmac;
 183 struct gphy;
 184
 185 struct board_info {
 186         unsigned char           board;
 187         unsigned char           port_number;
 188         unsigned long           caps;
 189         unsigned char           chip_term;
 190         unsigned char           chip_mac;
 191         unsigned char           chip_phy;
 192         unsigned int            clock_core;
 193         unsigned int            clock_mc3;
 194         unsigned int            clock_mc4;
 195         unsigned int            espi_nports;
 196         unsigned int            clock_cspi;
 197         unsigned int            clock_elmer0;
 198         unsigned char           mdio_mdien;
 199         unsigned char           mdio_mdiinv;
 200         unsigned char           mdio_mdc;
 201         unsigned char           mdio_phybaseaddr;
 202         struct gmac            *gmac;
 203         struct gphy            *gphy;
 204         struct mdio_ops        *mdio_ops;
 205         const char             *desc;
 206 };
 207
 208 #include "osdep.h"
 209
 210 #ifndef PCI_VENDOR_ID_CHELSIO
 211 #define PCI_VENDOR_ID_CHELSIO 0x1425
 212 #endif
 213
 214 extern struct pci_device_id t1_pci_tbl[];
 215
 216 static inline int t1_is_asic(const adapter_t *adapter)
 217 {
 218         return adapter->params.is_asic;
 219 }
 220
 221 static inline int adapter_matches_type(const adapter_t *adapter,
 222                                        int version, int revision)
 223 {
 224         return adapter->params.chip_version == version &&
 225                adapter->params.chip_revision == revision;
 226 }
 227
 228 #define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
 229 #define is_T2(adap)     adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
 230
 231 /* Returns true if an adapter supports VLAN acceleration and TSO */
 232 static inline int vlan_tso_capable(const adapter_t *adapter)
 233 {
 234         return !t1_is_T1B(adapter);
 235 }
 236
 237 #define for_each_port(adapter, iter) \
 238         for (iter = 0; iter < (adapter)->params.nports; ++iter)
 239
 240 #define board_info(adapter) ((adapter)->params.brd_info)
 241 #define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
 242
 243 static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
 244 {
 245         return board_info(adap)->clock_core / 1000000;
 246 }
 247
 248 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
 249 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
 250
 251 void t1_interrupts_enable(adapter_t *adapter);
 252 void t1_interrupts_disable(adapter_t *adapter);
 253 void t1_interrupts_clear(adapter_t *adapter);
 254 int elmer0_ext_intr_handler(adapter_t *adapter);
 255 int t1_slow_intr_handler(adapter_t *adapter);
 256
 257 int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
 258 const struct board_info *t1_get_board_info(unsigned int board_id);
 259 const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
 260                                                     unsigned short ssid);
 261 int t1_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
 262 int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
 263                      struct adapter_params *p);
 264 int t1_init_hw_modules(adapter_t *adapter);
 265 int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
 266 void t1_free_sw_modules(adapter_t *adapter);
 267 void t1_fatal_err(adapter_t *adapter);
 268 #endif
 269