git.oblomov.eu Git - linux-2.6/blob - drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  43                       uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  57                           uint32_t supported_device);
  58
  59 /* old legacy ATI BIOS routines */
  60
  61 /* COMBIOS table offsets */
  62 enum radeon_combios_table_offset {
  63         /* absolute offset tables */
  64         COMBIOS_ASIC_INIT_1_TABLE,
  65         COMBIOS_BIOS_SUPPORT_TABLE,
  66         COMBIOS_DAC_PROGRAMMING_TABLE,
  67         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  68         COMBIOS_CRTC_INFO_TABLE,
  69         COMBIOS_PLL_INFO_TABLE,
  70         COMBIOS_TV_INFO_TABLE,
  71         COMBIOS_DFP_INFO_TABLE,
  72         COMBIOS_HW_CONFIG_INFO_TABLE,
  73         COMBIOS_MULTIMEDIA_INFO_TABLE,
  74         COMBIOS_TV_STD_PATCH_TABLE,
  75         COMBIOS_LCD_INFO_TABLE,
  76         COMBIOS_MOBILE_INFO_TABLE,
  77         COMBIOS_PLL_INIT_TABLE,
  78         COMBIOS_MEM_CONFIG_TABLE,
  79         COMBIOS_SAVE_MASK_TABLE,
  80         COMBIOS_HARDCODED_EDID_TABLE,
  81         COMBIOS_ASIC_INIT_2_TABLE,
  82         COMBIOS_CONNECTOR_INFO_TABLE,
  83         COMBIOS_DYN_CLK_1_TABLE,
  84         COMBIOS_RESERVED_MEM_TABLE,
  85         COMBIOS_EXT_TMDS_INFO_TABLE,
  86         COMBIOS_MEM_CLK_INFO_TABLE,
  87         COMBIOS_EXT_DAC_INFO_TABLE,
  88         COMBIOS_MISC_INFO_TABLE,
  89         COMBIOS_CRT_INFO_TABLE,
  90         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  91         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  92         COMBIOS_FAN_SPEED_INFO_TABLE,
  93         COMBIOS_OVERDRIVE_INFO_TABLE,
  94         COMBIOS_OEM_INFO_TABLE,
  95         COMBIOS_DYN_CLK_2_TABLE,
  96         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  97         COMBIOS_I2C_INFO_TABLE,
  98         /* relative offset tables */
  99         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 100         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 101         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 102         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 103         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 104         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 105         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 106         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 107         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 108         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 109         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 110 };
 111
 112 enum radeon_combios_ddc {
 113         DDC_NONE_DETECTED,
 114         DDC_MONID,
 115         DDC_DVI,
 116         DDC_VGA,
 117         DDC_CRT2,
 118         DDC_LCD,
 119         DDC_GPIO,
 120 };
 121
 122 enum radeon_combios_connector {
 123         CONNECTOR_NONE_LEGACY,
 124         CONNECTOR_PROPRIETARY_LEGACY,
 125         CONNECTOR_CRT_LEGACY,
 126         CONNECTOR_DVI_I_LEGACY,
 127         CONNECTOR_DVI_D_LEGACY,
 128         CONNECTOR_CTV_LEGACY,
 129         CONNECTOR_STV_LEGACY,
 130         CONNECTOR_UNSUPPORTED_LEGACY
 131 };
 132
 133 const int legacy_connector_convert[] = {
 134         DRM_MODE_CONNECTOR_Unknown,
 135         DRM_MODE_CONNECTOR_DVID,
 136         DRM_MODE_CONNECTOR_VGA,
 137         DRM_MODE_CONNECTOR_DVII,
 138         DRM_MODE_CONNECTOR_DVID,
 139         DRM_MODE_CONNECTOR_Composite,
 140         DRM_MODE_CONNECTOR_SVIDEO,
 141         DRM_MODE_CONNECTOR_Unknown,
 142 };
 143
 144 static uint16_t combios_get_table_offset(struct drm_device *dev,
 145                                          enum radeon_combios_table_offset table)
 146 {
 147         struct radeon_device *rdev = dev->dev_private;
 148         int rev;
 149         uint16_t offset = 0, check_offset;
 150
 151         switch (table) {
 152                 /* absolute offset tables */
 153         case COMBIOS_ASIC_INIT_1_TABLE:
 154                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 155                 if (check_offset)
 156                         offset = check_offset;
 157                 break;
 158         case COMBIOS_BIOS_SUPPORT_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_DAC_PROGRAMMING_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_CRTC_INFO_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_PLL_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_TV_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_DFP_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_HW_CONFIG_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_TV_STD_PATCH_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_LCD_INFO_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_MOBILE_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_PLL_INIT_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_MEM_CONFIG_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_SAVE_MASK_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_HARDCODED_EDID_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_ASIC_INIT_2_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_CONNECTOR_INFO_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_DYN_CLK_1_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_RESERVED_MEM_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_EXT_TMDS_INFO_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_MEM_CLK_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_EXT_DAC_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_MISC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_CRT_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_FAN_SPEED_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_OVERDRIVE_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OEM_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_DYN_CLK_2_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_I2C_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323                 /* relative offset tables */
 324         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 325                 check_offset =
 326                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 327                 if (check_offset) {
 328                         rev = RBIOS8(check_offset);
 329                         if (rev > 0) {
 330                                 check_offset = RBIOS16(check_offset + 0x3);
 331                                 if (check_offset)
 332                                         offset = check_offset;
 333                         }
 334                 }
 335                 break;
 336         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 337                 check_offset =
 338                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 339                 if (check_offset) {
 340                         rev = RBIOS8(check_offset);
 341                         if (rev > 0) {
 342                                 check_offset = RBIOS16(check_offset + 0x5);
 343                                 if (check_offset)
 344                                         offset = check_offset;
 345                         }
 346                 }
 347                 break;
 348         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 349                 check_offset =
 350                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 351                 if (check_offset) {
 352                         rev = RBIOS8(check_offset);
 353                         if (rev > 0) {
 354                                 check_offset = RBIOS16(check_offset + 0x7);
 355                                 if (check_offset)
 356                                         offset = check_offset;
 357                         }
 358                 }
 359                 break;
 360         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 361                 check_offset =
 362                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 363                 if (check_offset) {
 364                         rev = RBIOS8(check_offset);
 365                         if (rev == 2) {
 366                                 check_offset = RBIOS16(check_offset + 0x9);
 367                                 if (check_offset)
 368                                         offset = check_offset;
 369                         }
 370                 }
 371                 break;
 372         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 373                 check_offset =
 374                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 375                 if (check_offset) {
 376                         while (RBIOS8(check_offset++));
 377                         check_offset += 2;
 378                         if (check_offset)
 379                                 offset = check_offset;
 380                 }
 381                 break;
 382         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 383                 check_offset =
 384                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 385                 if (check_offset) {
 386                         check_offset = RBIOS16(check_offset + 0x11);
 387                         if (check_offset)
 388                                 offset = check_offset;
 389                 }
 390                 break;
 391         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 392                 check_offset =
 393                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 394                 if (check_offset) {
 395                         check_offset = RBIOS16(check_offset + 0x13);
 396                         if (check_offset)
 397                                 offset = check_offset;
 398                 }
 399                 break;
 400         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 401                 check_offset =
 402                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 403                 if (check_offset) {
 404                         check_offset = RBIOS16(check_offset + 0x15);
 405                         if (check_offset)
 406                                 offset = check_offset;
 407                 }
 408                 break;
 409         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 410                 check_offset =
 411                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 412                 if (check_offset) {
 413                         check_offset = RBIOS16(check_offset + 0x17);
 414                         if (check_offset)
 415                                 offset = check_offset;
 416                 }
 417                 break;
 418         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 419                 check_offset =
 420                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 421                 if (check_offset) {
 422                         check_offset = RBIOS16(check_offset + 0x2);
 423                         if (check_offset)
 424                                 offset = check_offset;
 425                 }
 426                 break;
 427         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 428                 check_offset =
 429                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 430                 if (check_offset) {
 431                         check_offset = RBIOS16(check_offset + 0x4);
 432                         if (check_offset)
 433                                 offset = check_offset;
 434                 }
 435                 break;
 436         default:
 437                 break;
 438         }
 439
 440         return offset;
 441
 442 }
 443
 444 struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
 445 {
 446         struct radeon_i2c_bus_rec i2c;
 447
 448         i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 449         i2c.mask_data_mask = RADEON_GPIO_EN_0;
 450         i2c.a_clk_mask = RADEON_GPIO_A_1;
 451         i2c.a_data_mask = RADEON_GPIO_A_0;
 452         i2c.put_clk_mask = RADEON_GPIO_EN_1;
 453         i2c.put_data_mask = RADEON_GPIO_EN_0;
 454         i2c.get_clk_mask = RADEON_GPIO_Y_1;
 455         i2c.get_data_mask = RADEON_GPIO_Y_0;
 456         if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
 457             (ddc_line == RADEON_MDGPIO_EN_REG)) {
 458                 i2c.mask_clk_reg = ddc_line;
 459                 i2c.mask_data_reg = ddc_line;
 460                 i2c.a_clk_reg = ddc_line;
 461                 i2c.a_data_reg = ddc_line;
 462                 i2c.put_clk_reg = ddc_line;
 463                 i2c.put_data_reg = ddc_line;
 464                 i2c.get_clk_reg = ddc_line + 4;
 465                 i2c.get_data_reg = ddc_line + 4;
 466         } else {
 467                 i2c.mask_clk_reg = ddc_line;
 468                 i2c.mask_data_reg = ddc_line;
 469                 i2c.a_clk_reg = ddc_line;
 470                 i2c.a_data_reg = ddc_line;
 471                 i2c.put_clk_reg = ddc_line;
 472                 i2c.put_data_reg = ddc_line;
 473                 i2c.get_clk_reg = ddc_line;
 474                 i2c.get_data_reg = ddc_line;
 475         }
 476
 477         if (ddc_line)
 478                 i2c.valid = true;
 479         else
 480                 i2c.valid = false;
 481
 482         return i2c;
 483 }
 484
 485 bool radeon_combios_get_clock_info(struct drm_device *dev)
 486 {
 487         struct radeon_device *rdev = dev->dev_private;
 488         uint16_t pll_info;
 489         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 490         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 491         struct radeon_pll *spll = &rdev->clock.spll;
 492         struct radeon_pll *mpll = &rdev->clock.mpll;
 493         int8_t rev;
 494         uint16_t sclk, mclk;
 495
 496         if (rdev->bios == NULL)
 497                 return NULL;
 498
 499         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 500         if (pll_info) {
 501                 rev = RBIOS8(pll_info);
 502
 503                 /* pixel clocks */
 504                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 505                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 506                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 507                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 508
 509                 if (rev > 9) {
 510                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 511                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 512                 } else {
 513                         p1pll->pll_in_min = 40;
 514                         p1pll->pll_in_max = 500;
 515                 }
 516                 *p2pll = *p1pll;
 517
 518                 /* system clock */
 519                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 520                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 521                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 522                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 523
 524                 if (rev > 10) {
 525                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 526                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 527                 } else {
 528                         /* ??? */
 529                         spll->pll_in_min = 40;
 530                         spll->pll_in_max = 500;
 531                 }
 532
 533                 /* memory clock */
 534                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 535                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 536                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 537                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 538
 539                 if (rev > 10) {
 540                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 541                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 542                 } else {
 543                         /* ??? */
 544                         mpll->pll_in_min = 40;
 545                         mpll->pll_in_max = 500;
 546                 }
 547
 548                 /* default sclk/mclk */
 549                 sclk = RBIOS16(pll_info + 0xa);
 550                 mclk = RBIOS16(pll_info + 0x8);
 551                 if (sclk == 0)
 552                         sclk = 200 * 100;
 553                 if (mclk == 0)
 554                         mclk = 200 * 100;
 555
 556                 rdev->clock.default_sclk = sclk;
 557                 rdev->clock.default_mclk = mclk;
 558
 559                 return true;
 560         }
 561         return false;
 562 }
 563
 564 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 565                                                                        radeon_encoder
 566                                                                        *encoder)
 567 {
 568         struct drm_device *dev = encoder->base.dev;
 569         struct radeon_device *rdev = dev->dev_private;
 570         uint16_t dac_info;
 571         uint8_t rev, bg, dac;
 572         struct radeon_encoder_primary_dac *p_dac = NULL;
 573
 574         if (rdev->bios == NULL)
 575                 return NULL;
 576
 577         /* check CRT table */
 578         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 579         if (dac_info) {
 580                 p_dac =
 581                     kzalloc(sizeof(struct radeon_encoder_primary_dac),
 582                             GFP_KERNEL);
 583
 584                 if (!p_dac)
 585                         return NULL;
 586
 587                 rev = RBIOS8(dac_info) & 0x3;
 588                 if (rev < 2) {
 589                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 590                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 591                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 592                 } else {
 593                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 594                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 595                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 596                 }
 597
 598         }
 599
 600         return p_dac;
 601 }
 602
 603 static enum radeon_tv_std
 604 radeon_combios_get_tv_info(struct radeon_encoder *encoder)
 605 {
 606         struct drm_device *dev = encoder->base.dev;
 607         struct radeon_device *rdev = dev->dev_private;
 608         uint16_t tv_info;
 609         enum radeon_tv_std tv_std = TV_STD_NTSC;
 610
 611         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 612         if (tv_info) {
 613                 if (RBIOS8(tv_info + 6) == 'T') {
 614                         switch (RBIOS8(tv_info + 7) & 0xf) {
 615                         case 1:
 616                                 tv_std = TV_STD_NTSC;
 617                                 DRM_INFO("Default TV standard: NTSC\n");
 618                                 break;
 619                         case 2:
 620                                 tv_std = TV_STD_PAL;
 621                                 DRM_INFO("Default TV standard: PAL\n");
 622                                 break;
 623                         case 3:
 624                                 tv_std = TV_STD_PAL_M;
 625                                 DRM_INFO("Default TV standard: PAL-M\n");
 626                                 break;
 627                         case 4:
 628                                 tv_std = TV_STD_PAL_60;
 629                                 DRM_INFO("Default TV standard: PAL-60\n");
 630                                 break;
 631                         case 5:
 632                                 tv_std = TV_STD_NTSC_J;
 633                                 DRM_INFO("Default TV standard: NTSC-J\n");
 634                                 break;
 635                         case 6:
 636                                 tv_std = TV_STD_SCART_PAL;
 637                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 638                                 break;
 639                         default:
 640                                 tv_std = TV_STD_NTSC;
 641                                 DRM_INFO
 642                                     ("Unknown TV standard; defaulting to NTSC\n");
 643                                 break;
 644                         }
 645
 646                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 647                         case 0:
 648                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 649                                 break;
 650                         case 1:
 651                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 652                                 break;
 653                         case 2:
 654                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 655                                 break;
 656                         case 3:
 657                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 658                                 break;
 659                         default:
 660                                 break;
 661                         }
 662                 }
 663         }
 664         return tv_std;
 665 }
 666
 667 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 668         0x00000000,             /* r100  */
 669         0x00280000,             /* rv100 */
 670         0x00000000,             /* rs100 */
 671         0x00880000,             /* rv200 */
 672         0x00000000,             /* rs200 */
 673         0x00000000,             /* r200  */
 674         0x00770000,             /* rv250 */
 675         0x00290000,             /* rs300 */
 676         0x00560000,             /* rv280 */
 677         0x00780000,             /* r300  */
 678         0x00770000,             /* r350  */
 679         0x00780000,             /* rv350 */
 680         0x00780000,             /* rv380 */
 681         0x01080000,             /* r420  */
 682         0x01080000,             /* r423  */
 683         0x01080000,             /* rv410 */
 684         0x00780000,             /* rs400 */
 685         0x00780000,             /* rs480 */
 686 };
 687
 688 static struct radeon_encoder_tv_dac
 689     *radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev)
 690 {
 691         struct radeon_encoder_tv_dac *tv_dac = NULL;
 692
 693         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 694
 695         if (!tv_dac)
 696                 return NULL;
 697
 698         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
 699         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
 700                 tv_dac->ps2_tvdac_adj = 0x00880000;
 701         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 702         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 703
 704         return tv_dac;
 705 }
 706
 707 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
 708                                                              radeon_encoder
 709                                                              *encoder)
 710 {
 711         struct drm_device *dev = encoder->base.dev;
 712         struct radeon_device *rdev = dev->dev_private;
 713         uint16_t dac_info;
 714         uint8_t rev, bg, dac;
 715         struct radeon_encoder_tv_dac *tv_dac = NULL;
 716
 717         if (rdev->bios == NULL)
 718                 return radeon_legacy_get_tv_dac_info_from_table(rdev);
 719
 720         /* first check TV table */
 721         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 722         if (dac_info) {
 723                 tv_dac =
 724                     kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 725
 726                 if (!tv_dac)
 727                         return NULL;
 728
 729                 rev = RBIOS8(dac_info + 0x3);
 730                 if (rev > 4) {
 731                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 732                         dac = RBIOS8(dac_info + 0xd) & 0xf;
 733                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 734
 735                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 736                         dac = RBIOS8(dac_info + 0xf) & 0xf;
 737                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 738
 739                         bg = RBIOS8(dac_info + 0x10) & 0xf;
 740                         dac = RBIOS8(dac_info + 0x11) & 0xf;
 741                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 742                 } else if (rev > 1) {
 743                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 744                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
 745                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 746
 747                         bg = RBIOS8(dac_info + 0xd) & 0xf;
 748                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
 749                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 750
 751                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 752                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
 753                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 754                 }
 755
 756                 tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
 757
 758         } else {
 759                 /* then check CRT table */
 760                 dac_info =
 761                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 762                 if (dac_info) {
 763                         tv_dac =
 764                             kzalloc(sizeof(struct radeon_encoder_tv_dac),
 765                                     GFP_KERNEL);
 766
 767                         if (!tv_dac)
 768                                 return NULL;
 769
 770                         rev = RBIOS8(dac_info) & 0x3;
 771                         if (rev < 2) {
 772                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
 773                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
 774                                 tv_dac->ps2_tvdac_adj =
 775                                     (bg << 16) | (dac << 20);
 776                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 777                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 778                         } else {
 779                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
 780                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
 781                                 tv_dac->ps2_tvdac_adj =
 782                                     (bg << 16) | (dac << 20);
 783                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 784                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 785                         }
 786                 } else {
 787                         DRM_INFO("No TV DAC info found in BIOS\n");
 788                         return radeon_legacy_get_tv_dac_info_from_table(rdev);
 789                 }
 790         }
 791
 792         return tv_dac;
 793 }
 794
 795 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
 796                                                                          radeon_device
 797                                                                          *rdev)
 798 {
 799         struct radeon_encoder_lvds *lvds = NULL;
 800         uint32_t fp_vert_stretch, fp_horz_stretch;
 801         uint32_t ppll_div_sel, ppll_val;
 802
 803         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 804
 805         if (!lvds)
 806                 return NULL;
 807
 808         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
 809         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
 810
 811         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
 812                 lvds->native_mode.panel_yres =
 813                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
 814                      RADEON_VERT_PANEL_SHIFT) + 1;
 815         else
 816                 lvds->native_mode.panel_yres =
 817                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
 818
 819         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
 820                 lvds->native_mode.panel_xres =
 821                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
 822                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
 823         else
 824                 lvds->native_mode.panel_xres =
 825                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
 826
 827         if ((lvds->native_mode.panel_xres < 640) ||
 828             (lvds->native_mode.panel_yres < 480)) {
 829                 lvds->native_mode.panel_xres = 640;
 830                 lvds->native_mode.panel_yres = 480;
 831         }
 832
 833         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
 834         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
 835         if ((ppll_val & 0x000707ff) == 0x1bb)
 836                 lvds->use_bios_dividers = false;
 837         else {
 838                 lvds->panel_ref_divider =
 839                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
 840                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
 841                 lvds->panel_fb_divider = ppll_val & 0x7ff;
 842
 843                 if ((lvds->panel_ref_divider != 0) &&
 844                     (lvds->panel_fb_divider > 3))
 845                         lvds->use_bios_dividers = true;
 846         }
 847         lvds->panel_vcc_delay = 200;
 848
 849         DRM_INFO("Panel info derived from registers\n");
 850         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
 851                  lvds->native_mode.panel_yres);
 852
 853         return lvds;
 854 }
 855
 856 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
 857                                                          *encoder)
 858 {
 859         struct drm_device *dev = encoder->base.dev;
 860         struct radeon_device *rdev = dev->dev_private;
 861         uint16_t lcd_info;
 862         uint32_t panel_setup;
 863         char stmp[30];
 864         int tmp, i;
 865         struct radeon_encoder_lvds *lvds = NULL;
 866
 867         if (rdev->bios == NULL)
 868                 return radeon_legacy_get_lvds_info_from_regs(rdev);
 869
 870         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 871
 872         if (lcd_info) {
 873                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 874
 875                 if (!lvds)
 876                         return NULL;
 877
 878                 for (i = 0; i < 24; i++)
 879                         stmp[i] = RBIOS8(lcd_info + i + 1);
 880                 stmp[24] = 0;
 881
 882                 DRM_INFO("Panel ID String: %s\n", stmp);
 883
 884                 lvds->native_mode.panel_xres = RBIOS16(lcd_info + 0x19);
 885                 lvds->native_mode.panel_yres = RBIOS16(lcd_info + 0x1b);
 886
 887                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
 888                          lvds->native_mode.panel_yres);
 889
 890                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
 891                 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
 892                         lvds->panel_vcc_delay = 2000;
 893
 894                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
 895                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
 896                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
 897
 898                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
 899                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
 900                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
 901                 if ((lvds->panel_ref_divider != 0) &&
 902                     (lvds->panel_fb_divider > 3))
 903                         lvds->use_bios_dividers = true;
 904
 905                 panel_setup = RBIOS32(lcd_info + 0x39);
 906                 lvds->lvds_gen_cntl = 0xff00;
 907                 if (panel_setup & 0x1)
 908                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
 909
 910                 if ((panel_setup >> 4) & 0x1)
 911                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
 912
 913                 switch ((panel_setup >> 8) & 0x7) {
 914                 case 0:
 915                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
 916                         break;
 917                 case 1:
 918                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
 919                         break;
 920                 case 2:
 921                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
 922                         break;
 923                 default:
 924                         break;
 925                 }
 926
 927                 if ((panel_setup >> 16) & 0x1)
 928                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
 929
 930                 if ((panel_setup >> 17) & 0x1)
 931                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
 932
 933                 if ((panel_setup >> 18) & 0x1)
 934                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
 935
 936                 if ((panel_setup >> 23) & 0x1)
 937                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
 938
 939                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
 940
 941                 for (i = 0; i < 32; i++) {
 942                         tmp = RBIOS16(lcd_info + 64 + i * 2);
 943                         if (tmp == 0)
 944                                 break;
 945
 946                         if ((RBIOS16(tmp) == lvds->native_mode.panel_xres) &&
 947                             (RBIOS16(tmp + 2) ==
 948                              lvds->native_mode.panel_yres)) {
 949                                 lvds->native_mode.hblank =
 950                                     (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
 951                                 lvds->native_mode.hoverplus =
 952                                     (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) -
 953                                      1) * 8;
 954                                 lvds->native_mode.hsync_width =
 955                                     RBIOS8(tmp + 23) * 8;
 956
 957                                 lvds->native_mode.vblank = (RBIOS16(tmp + 24) -
 958                                                             RBIOS16(tmp + 26));
 959                                 lvds->native_mode.voverplus =
 960                                     ((RBIOS16(tmp + 28) & 0x7ff) -
 961                                      RBIOS16(tmp + 26));
 962                                 lvds->native_mode.vsync_width =
 963                                     ((RBIOS16(tmp + 28) & 0xf800) >> 11);
 964                                 lvds->native_mode.dotclock =
 965                                     RBIOS16(tmp + 9) * 10;
 966                                 lvds->native_mode.flags = 0;
 967                         }
 968                 }
 969                 encoder->native_mode = lvds->native_mode;
 970         } else {
 971                 DRM_INFO("No panel info found in BIOS\n");
 972                 return radeon_legacy_get_lvds_info_from_regs(rdev);
 973         }
 974         return lvds;
 975 }
 976
 977 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
 978         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
 979         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
 980         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
 981         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
 982         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
 983         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
 984         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
 985         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
 986         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
 987         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
 988         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
 989         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
 990         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
 991         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
 992         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
 993         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
 994         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RS400 */
 995         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RS480 */
 996 };
 997
 998 static struct radeon_encoder_int_tmds
 999     *radeon_legacy_get_tmds_info_from_table(struct radeon_device *rdev)
1000 {
1001         int i;
1002         struct radeon_encoder_int_tmds *tmds = NULL;
1003
1004         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1005
1006         if (!tmds)
1007                 return NULL;
1008
1009         for (i = 0; i < 4; i++) {
1010                 tmds->tmds_pll[i].value =
1011                     default_tmds_pll[rdev->family][i].value;
1012                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1013         }
1014
1015         return tmds;
1016 }
1017
1018 struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct
1019                                                              radeon_encoder
1020                                                              *encoder)
1021 {
1022         struct drm_device *dev = encoder->base.dev;
1023         struct radeon_device *rdev = dev->dev_private;
1024         uint16_t tmds_info;
1025         int i, n;
1026         uint8_t ver;
1027         struct radeon_encoder_int_tmds *tmds = NULL;
1028
1029         if (rdev->bios == NULL)
1030                 return radeon_legacy_get_tmds_info_from_table(rdev);
1031
1032         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1033
1034         if (tmds_info) {
1035                 tmds =
1036                     kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1037
1038                 if (!tmds)
1039                         return NULL;
1040
1041                 ver = RBIOS8(tmds_info);
1042                 DRM_INFO("DFP table revision: %d\n", ver);
1043                 if (ver == 3) {
1044                         n = RBIOS8(tmds_info + 5) + 1;
1045                         if (n > 4)
1046                                 n = 4;
1047                         for (i = 0; i < n; i++) {
1048                                 tmds->tmds_pll[i].value =
1049                                     RBIOS32(tmds_info + i * 10 + 0x08);
1050                                 tmds->tmds_pll[i].freq =
1051                                     RBIOS16(tmds_info + i * 10 + 0x10);
1052                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1053                                           tmds->tmds_pll[i].freq,
1054                                           tmds->tmds_pll[i].value);
1055                         }
1056                 } else if (ver == 4) {
1057                         int stride = 0;
1058                         n = RBIOS8(tmds_info + 5) + 1;
1059                         if (n > 4)
1060                                 n = 4;
1061                         for (i = 0; i < n; i++) {
1062                                 tmds->tmds_pll[i].value =
1063                                     RBIOS32(tmds_info + stride + 0x08);
1064                                 tmds->tmds_pll[i].freq =
1065                                     RBIOS16(tmds_info + stride + 0x10);
1066                                 if (i == 0)
1067                                         stride += 10;
1068                                 else
1069                                         stride += 6;
1070                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1071                                           tmds->tmds_pll[i].freq,
1072                                           tmds->tmds_pll[i].value);
1073                         }
1074                 }
1075         } else
1076                 DRM_INFO("No TMDS info found in BIOS\n");
1077         return tmds;
1078 }
1079
1080 void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder)
1081 {
1082         struct drm_device *dev = encoder->base.dev;
1083         struct radeon_device *rdev = dev->dev_private;
1084         uint16_t ext_tmds_info;
1085         uint8_t ver;
1086
1087         if (rdev->bios == NULL)
1088                 return;
1089
1090         ext_tmds_info =
1091             combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1092         if (ext_tmds_info) {
1093                 ver = RBIOS8(ext_tmds_info);
1094                 DRM_INFO("External TMDS Table revision: %d\n", ver);
1095                 // TODO
1096         }
1097 }
1098
1099 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1100 {
1101         struct radeon_device *rdev = dev->dev_private;
1102         struct radeon_i2c_bus_rec ddc_i2c;
1103
1104         rdev->mode_info.connector_table = radeon_connector_table;
1105         if (rdev->mode_info.connector_table == CT_NONE) {
1106 #ifdef CONFIG_PPC_PMAC
1107                 if (machine_is_compatible("PowerBook3,3")) {
1108                         /* powerbook with VGA */
1109                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1110                 } else if (machine_is_compatible("PowerBook3,4") ||
1111                            machine_is_compatible("PowerBook3,5")) {
1112                         /* powerbook with internal tmds */
1113                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1114                 } else if (machine_is_compatible("PowerBook5,1") ||
1115                            machine_is_compatible("PowerBook5,2") ||
1116                            machine_is_compatible("PowerBook5,3") ||
1117                            machine_is_compatible("PowerBook5,4") ||
1118                            machine_is_compatible("PowerBook5,5")) {
1119                         /* powerbook with external single link tmds (sil164) */
1120                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1121                 } else if (machine_is_compatible("PowerBook5,6")) {
1122                         /* powerbook with external dual or single link tmds */
1123                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1124                 } else if (machine_is_compatible("PowerBook5,7") ||
1125                            machine_is_compatible("PowerBook5,8") ||
1126                            machine_is_compatible("PowerBook5,9")) {
1127                         /* PowerBook6,2 ? */
1128                         /* powerbook with external dual link tmds (sil1178?) */
1129                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1130                 } else if (machine_is_compatible("PowerBook4,1") ||
1131                            machine_is_compatible("PowerBook4,2") ||
1132                            machine_is_compatible("PowerBook4,3") ||
1133                            machine_is_compatible("PowerBook6,3") ||
1134                            machine_is_compatible("PowerBook6,5") ||
1135                            machine_is_compatible("PowerBook6,7")) {
1136                         /* ibook */
1137                         rdev->mode_info.connector_table = CT_IBOOK;
1138                 } else if (machine_is_compatible("PowerMac4,4")) {
1139                         /* emac */
1140                         rdev->mode_info.connector_table = CT_EMAC;
1141                 } else if (machine_is_compatible("PowerMac10,1")) {
1142                         /* mini with internal tmds */
1143                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1144                 } else if (machine_is_compatible("PowerMac10,2")) {
1145                         /* mini with external tmds */
1146                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1147                 } else if (machine_is_compatible("PowerMac12,1")) {
1148                         /* PowerMac8,1 ? */
1149                         /* imac g5 isight */
1150                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1151                 } else
1152 #endif /* CONFIG_PPC_PMAC */
1153                         rdev->mode_info.connector_table = CT_GENERIC;
1154         }
1155
1156         switch (rdev->mode_info.connector_table) {
1157         case CT_GENERIC:
1158                 DRM_INFO("Connector Table: %d (generic)\n",
1159                          rdev->mode_info.connector_table);
1160                 /* these are the most common settings */
1161                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1162                         /* VGA - primary dac */
1163                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1164                         radeon_add_legacy_encoder(dev,
1165                                                   radeon_get_encoder_id(dev,
1166                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1167                                                                         1),
1168                                                   ATOM_DEVICE_CRT1_SUPPORT);
1169                         radeon_add_legacy_connector(dev, 0,
1170                                                     ATOM_DEVICE_CRT1_SUPPORT,
1171                                                     DRM_MODE_CONNECTOR_VGA,
1172                                                     &ddc_i2c);
1173                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1174                         /* LVDS */
1175                         ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
1176                         radeon_add_legacy_encoder(dev,
1177                                                   radeon_get_encoder_id(dev,
1178                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1179                                                                         0),
1180                                                   ATOM_DEVICE_LCD1_SUPPORT);
1181                         radeon_add_legacy_connector(dev, 0,
1182                                                     ATOM_DEVICE_LCD1_SUPPORT,
1183                                                     DRM_MODE_CONNECTOR_LVDS,
1184                                                     &ddc_i2c);
1185
1186                         /* VGA - primary dac */
1187                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1188                         radeon_add_legacy_encoder(dev,
1189                                                   radeon_get_encoder_id(dev,
1190                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1191                                                                         1),
1192                                                   ATOM_DEVICE_CRT1_SUPPORT);
1193                         radeon_add_legacy_connector(dev, 1,
1194                                                     ATOM_DEVICE_CRT1_SUPPORT,
1195                                                     DRM_MODE_CONNECTOR_VGA,
1196                                                     &ddc_i2c);
1197                 } else {
1198                         /* DVI-I - tv dac, int tmds */
1199                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1200                         radeon_add_legacy_encoder(dev,
1201                                                   radeon_get_encoder_id(dev,
1202                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1203                                                                         0),
1204                                                   ATOM_DEVICE_DFP1_SUPPORT);
1205                         radeon_add_legacy_encoder(dev,
1206                                                   radeon_get_encoder_id(dev,
1207                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1208                                                                         2),
1209                                                   ATOM_DEVICE_CRT2_SUPPORT);
1210                         radeon_add_legacy_connector(dev, 0,
1211                                                     ATOM_DEVICE_DFP1_SUPPORT |
1212                                                     ATOM_DEVICE_CRT2_SUPPORT,
1213                                                     DRM_MODE_CONNECTOR_DVII,
1214                                                     &ddc_i2c);
1215
1216                         /* VGA - primary dac */
1217                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1218                         radeon_add_legacy_encoder(dev,
1219                                                   radeon_get_encoder_id(dev,
1220                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1221                                                                         1),
1222                                                   ATOM_DEVICE_CRT1_SUPPORT);
1223                         radeon_add_legacy_connector(dev, 1,
1224                                                     ATOM_DEVICE_CRT1_SUPPORT,
1225                                                     DRM_MODE_CONNECTOR_VGA,
1226                                                     &ddc_i2c);
1227                 }
1228
1229                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1230                         /* TV - tv dac */
1231                         radeon_add_legacy_encoder(dev,
1232                                                   radeon_get_encoder_id(dev,
1233                                                                         ATOM_DEVICE_TV1_SUPPORT,
1234                                                                         2),
1235                                                   ATOM_DEVICE_TV1_SUPPORT);
1236                         radeon_add_legacy_connector(dev, 2,
1237                                                     ATOM_DEVICE_TV1_SUPPORT,
1238                                                     DRM_MODE_CONNECTOR_SVIDEO,
1239                                                     &ddc_i2c);
1240                 }
1241                 break;
1242         case CT_IBOOK:
1243                 DRM_INFO("Connector Table: %d (ibook)\n",
1244                          rdev->mode_info.connector_table);
1245                 /* LVDS */
1246                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1247                 radeon_add_legacy_encoder(dev,
1248                                           radeon_get_encoder_id(dev,
1249                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1250                                                                 0),
1251                                           ATOM_DEVICE_LCD1_SUPPORT);
1252                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1253                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1254                 /* VGA - TV DAC */
1255                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1256                 radeon_add_legacy_encoder(dev,
1257                                           radeon_get_encoder_id(dev,
1258                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1259                                                                 2),
1260                                           ATOM_DEVICE_CRT2_SUPPORT);
1261                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1262                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1263                 /* TV - TV DAC */
1264                 radeon_add_legacy_encoder(dev,
1265                                           radeon_get_encoder_id(dev,
1266                                                                 ATOM_DEVICE_TV1_SUPPORT,
1267                                                                 2),
1268                                           ATOM_DEVICE_TV1_SUPPORT);
1269                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1270                                             DRM_MODE_CONNECTOR_SVIDEO,
1271                                             &ddc_i2c);
1272                 break;
1273         case CT_POWERBOOK_EXTERNAL:
1274                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1275                          rdev->mode_info.connector_table);
1276                 /* LVDS */
1277                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1278                 radeon_add_legacy_encoder(dev,
1279                                           radeon_get_encoder_id(dev,
1280                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1281                                                                 0),
1282                                           ATOM_DEVICE_LCD1_SUPPORT);
1283                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1284                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1285                 /* DVI-I - primary dac, ext tmds */
1286                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1287                 radeon_add_legacy_encoder(dev,
1288                                           radeon_get_encoder_id(dev,
1289                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1290                                                                 0),
1291                                           ATOM_DEVICE_DFP2_SUPPORT);
1292                 radeon_add_legacy_encoder(dev,
1293                                           radeon_get_encoder_id(dev,
1294                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1295                                                                 1),
1296                                           ATOM_DEVICE_CRT1_SUPPORT);
1297                 radeon_add_legacy_connector(dev, 1,
1298                                             ATOM_DEVICE_DFP2_SUPPORT |
1299                                             ATOM_DEVICE_CRT1_SUPPORT,
1300                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1301                 /* TV - TV DAC */
1302                 radeon_add_legacy_encoder(dev,
1303                                           radeon_get_encoder_id(dev,
1304                                                                 ATOM_DEVICE_TV1_SUPPORT,
1305                                                                 2),
1306                                           ATOM_DEVICE_TV1_SUPPORT);
1307                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1308                                             DRM_MODE_CONNECTOR_SVIDEO,
1309                                             &ddc_i2c);
1310                 break;
1311         case CT_POWERBOOK_INTERNAL:
1312                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1313                          rdev->mode_info.connector_table);
1314                 /* LVDS */
1315                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1316                 radeon_add_legacy_encoder(dev,
1317                                           radeon_get_encoder_id(dev,
1318                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1319                                                                 0),
1320                                           ATOM_DEVICE_LCD1_SUPPORT);
1321                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1322                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1323                 /* DVI-I - primary dac, int tmds */
1324                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1325                 radeon_add_legacy_encoder(dev,
1326                                           radeon_get_encoder_id(dev,
1327                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1328                                                                 0),
1329                                           ATOM_DEVICE_DFP1_SUPPORT);
1330                 radeon_add_legacy_encoder(dev,
1331                                           radeon_get_encoder_id(dev,
1332                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1333                                                                 1),
1334                                           ATOM_DEVICE_CRT1_SUPPORT);
1335                 radeon_add_legacy_connector(dev, 1,
1336                                             ATOM_DEVICE_DFP1_SUPPORT |
1337                                             ATOM_DEVICE_CRT1_SUPPORT,
1338                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1339                 /* TV - TV DAC */
1340                 radeon_add_legacy_encoder(dev,
1341                                           radeon_get_encoder_id(dev,
1342                                                                 ATOM_DEVICE_TV1_SUPPORT,
1343                                                                 2),
1344                                           ATOM_DEVICE_TV1_SUPPORT);
1345                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1346                                             DRM_MODE_CONNECTOR_SVIDEO,
1347                                             &ddc_i2c);
1348                 break;
1349         case CT_POWERBOOK_VGA:
1350                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1351                          rdev->mode_info.connector_table);
1352                 /* LVDS */
1353                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1354                 radeon_add_legacy_encoder(dev,
1355                                           radeon_get_encoder_id(dev,
1356                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1357                                                                 0),
1358                                           ATOM_DEVICE_LCD1_SUPPORT);
1359                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1360                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1361                 /* VGA - primary dac */
1362                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1363                 radeon_add_legacy_encoder(dev,
1364                                           radeon_get_encoder_id(dev,
1365                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1366                                                                 1),
1367                                           ATOM_DEVICE_CRT1_SUPPORT);
1368                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1369                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1370                 /* TV - TV DAC */
1371                 radeon_add_legacy_encoder(dev,
1372                                           radeon_get_encoder_id(dev,
1373                                                                 ATOM_DEVICE_TV1_SUPPORT,
1374                                                                 2),
1375                                           ATOM_DEVICE_TV1_SUPPORT);
1376                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1377                                             DRM_MODE_CONNECTOR_SVIDEO,
1378                                             &ddc_i2c);
1379                 break;
1380         case CT_MINI_EXTERNAL:
1381                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1382                          rdev->mode_info.connector_table);
1383                 /* DVI-I - tv dac, ext tmds */
1384                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1385                 radeon_add_legacy_encoder(dev,
1386                                           radeon_get_encoder_id(dev,
1387                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1388                                                                 0),
1389                                           ATOM_DEVICE_DFP2_SUPPORT);
1390                 radeon_add_legacy_encoder(dev,
1391                                           radeon_get_encoder_id(dev,
1392                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1393                                                                 2),
1394                                           ATOM_DEVICE_CRT2_SUPPORT);
1395                 radeon_add_legacy_connector(dev, 0,
1396                                             ATOM_DEVICE_DFP2_SUPPORT |
1397                                             ATOM_DEVICE_CRT2_SUPPORT,
1398                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1399                 /* TV - TV DAC */
1400                 radeon_add_legacy_encoder(dev,
1401                                           radeon_get_encoder_id(dev,
1402                                                                 ATOM_DEVICE_TV1_SUPPORT,
1403                                                                 2),
1404                                           ATOM_DEVICE_TV1_SUPPORT);
1405                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1406                                             DRM_MODE_CONNECTOR_SVIDEO,
1407                                             &ddc_i2c);
1408                 break;
1409         case CT_MINI_INTERNAL:
1410                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1411                          rdev->mode_info.connector_table);
1412                 /* DVI-I - tv dac, int tmds */
1413                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1414                 radeon_add_legacy_encoder(dev,
1415                                           radeon_get_encoder_id(dev,
1416                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1417                                                                 0),
1418                                           ATOM_DEVICE_DFP1_SUPPORT);
1419                 radeon_add_legacy_encoder(dev,
1420                                           radeon_get_encoder_id(dev,
1421                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1422                                                                 2),
1423                                           ATOM_DEVICE_CRT2_SUPPORT);
1424                 radeon_add_legacy_connector(dev, 0,
1425                                             ATOM_DEVICE_DFP1_SUPPORT |
1426                                             ATOM_DEVICE_CRT2_SUPPORT,
1427                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1428                 /* TV - TV DAC */
1429                 radeon_add_legacy_encoder(dev,
1430                                           radeon_get_encoder_id(dev,
1431                                                                 ATOM_DEVICE_TV1_SUPPORT,
1432                                                                 2),
1433                                           ATOM_DEVICE_TV1_SUPPORT);
1434                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1435                                             DRM_MODE_CONNECTOR_SVIDEO,
1436                                             &ddc_i2c);
1437                 break;
1438         case CT_IMAC_G5_ISIGHT:
1439                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1440                          rdev->mode_info.connector_table);
1441                 /* DVI-D - int tmds */
1442                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1443                 radeon_add_legacy_encoder(dev,
1444                                           radeon_get_encoder_id(dev,
1445                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1446                                                                 0),
1447                                           ATOM_DEVICE_DFP1_SUPPORT);
1448                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1449                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c);
1450                 /* VGA - tv dac */
1451                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1452                 radeon_add_legacy_encoder(dev,
1453                                           radeon_get_encoder_id(dev,
1454                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1455                                                                 2),
1456                                           ATOM_DEVICE_CRT2_SUPPORT);
1457                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1458                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1459                 /* TV - TV DAC */
1460                 radeon_add_legacy_encoder(dev,
1461                                           radeon_get_encoder_id(dev,
1462                                                                 ATOM_DEVICE_TV1_SUPPORT,
1463                                                                 2),
1464                                           ATOM_DEVICE_TV1_SUPPORT);
1465                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1466                                             DRM_MODE_CONNECTOR_SVIDEO,
1467                                             &ddc_i2c);
1468                 break;
1469         case CT_EMAC:
1470                 DRM_INFO("Connector Table: %d (emac)\n",
1471                          rdev->mode_info.connector_table);
1472                 /* VGA - primary dac */
1473                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1474                 radeon_add_legacy_encoder(dev,
1475                                           radeon_get_encoder_id(dev,
1476                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1477                                                                 1),
1478                                           ATOM_DEVICE_CRT1_SUPPORT);
1479                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1480                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1481                 /* VGA - tv dac */
1482                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1483                 radeon_add_legacy_encoder(dev,
1484                                           radeon_get_encoder_id(dev,
1485                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1486                                                                 2),
1487                                           ATOM_DEVICE_CRT2_SUPPORT);
1488                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1489                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1490                 /* TV - TV DAC */
1491                 radeon_add_legacy_encoder(dev,
1492                                           radeon_get_encoder_id(dev,
1493                                                                 ATOM_DEVICE_TV1_SUPPORT,
1494                                                                 2),
1495                                           ATOM_DEVICE_TV1_SUPPORT);
1496                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1497                                             DRM_MODE_CONNECTOR_SVIDEO,
1498                                             &ddc_i2c);
1499                 break;
1500         default:
1501                 DRM_INFO("Connector table: %d (invalid)\n",
1502                          rdev->mode_info.connector_table);
1503                 return false;
1504         }
1505
1506         radeon_link_encoder_connector(dev);
1507
1508         return true;
1509 }
1510
1511 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1512                                        int bios_index,
1513                                        enum radeon_combios_connector
1514                                        *legacy_connector,
1515                                        struct radeon_i2c_bus_rec *ddc_i2c)
1516 {
1517         struct radeon_device *rdev = dev->dev_private;
1518
1519         /* XPRESS DDC quirks */
1520         if ((rdev->family == CHIP_RS400 ||
1521              rdev->family == CHIP_RS480) &&
1522             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1523                 *ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1524         else if ((rdev->family == CHIP_RS400 ||
1525                   rdev->family == CHIP_RS480) &&
1526                  ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1527                 ddc_i2c->valid = true;
1528                 ddc_i2c->mask_clk_mask = (0x20 << 8);
1529                 ddc_i2c->mask_data_mask = 0x80;
1530                 ddc_i2c->a_clk_mask = (0x20 << 8);
1531                 ddc_i2c->a_data_mask = 0x80;
1532                 ddc_i2c->put_clk_mask = (0x20 << 8);
1533                 ddc_i2c->put_data_mask = 0x80;
1534                 ddc_i2c->get_clk_mask = (0x20 << 8);
1535                 ddc_i2c->get_data_mask = 0x80;
1536                 ddc_i2c->mask_clk_reg = RADEON_GPIOPAD_MASK;
1537                 ddc_i2c->mask_data_reg = RADEON_GPIOPAD_MASK;
1538                 ddc_i2c->a_clk_reg = RADEON_GPIOPAD_A;
1539                 ddc_i2c->a_data_reg = RADEON_GPIOPAD_A;
1540                 ddc_i2c->put_clk_reg = RADEON_GPIOPAD_EN;
1541                 ddc_i2c->put_data_reg = RADEON_GPIOPAD_EN;
1542                 ddc_i2c->get_clk_reg = RADEON_LCD_GPIO_Y_REG;
1543                 ddc_i2c->get_data_reg = RADEON_LCD_GPIO_Y_REG;
1544         }
1545
1546         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1547            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1548         if (dev->pdev->device == 0x515e &&
1549             dev->pdev->subsystem_vendor == 0x1014) {
1550                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1551                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1552                         return false;
1553         }
1554
1555         /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1556         if (dev->pdev->device == 0x5159 &&
1557             dev->pdev->subsystem_vendor == 0x1002 &&
1558             dev->pdev->subsystem_device == 0x013a) {
1559                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1560                         *legacy_connector = CONNECTOR_CRT_LEGACY;
1561
1562         }
1563
1564         /* X300 card with extra non-existent DVI port */
1565         if (dev->pdev->device == 0x5B60 &&
1566             dev->pdev->subsystem_vendor == 0x17af &&
1567             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1568                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1569                         return false;
1570         }
1571
1572         return true;
1573 }
1574
1575 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1576 {
1577         struct radeon_device *rdev = dev->dev_private;
1578         uint32_t conn_info, entry, devices;
1579         uint16_t tmp;
1580         enum radeon_combios_ddc ddc_type;
1581         enum radeon_combios_connector connector;
1582         int i = 0;
1583         struct radeon_i2c_bus_rec ddc_i2c;
1584
1585         if (rdev->bios == NULL)
1586                 return false;
1587
1588         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1589         if (conn_info) {
1590                 for (i = 0; i < 4; i++) {
1591                         entry = conn_info + 2 + i * 2;
1592
1593                         if (!RBIOS16(entry))
1594                                 break;
1595
1596                         tmp = RBIOS16(entry);
1597
1598                         connector = (tmp >> 12) & 0xf;
1599
1600                         ddc_type = (tmp >> 8) & 0xf;
1601                         switch (ddc_type) {
1602                         case DDC_MONID:
1603                                 ddc_i2c =
1604                                     combios_setup_i2c_bus(RADEON_GPIO_MONID);
1605                                 break;
1606                         case DDC_DVI:
1607                                 ddc_i2c =
1608                                     combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1609                                 break;
1610                         case DDC_VGA:
1611                                 ddc_i2c =
1612                                     combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1613                                 break;
1614                         case DDC_CRT2:
1615                                 ddc_i2c =
1616                                     combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1617                                 break;
1618                         default:
1619                                 break;
1620                         }
1621
1622                         radeon_apply_legacy_quirks(dev, i, &connector,
1623                                                    &ddc_i2c);
1624
1625                         switch (connector) {
1626                         case CONNECTOR_PROPRIETARY_LEGACY:
1627                                 if ((tmp >> 4) & 0x1)
1628                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
1629                                 else
1630                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
1631                                 radeon_add_legacy_encoder(dev,
1632                                                           radeon_get_encoder_id
1633                                                           (dev, devices, 0),
1634                                                           devices);
1635                                 radeon_add_legacy_connector(dev, i, devices,
1636                                                             legacy_connector_convert
1637                                                             [connector],
1638                                                             &ddc_i2c);
1639                                 break;
1640                         case CONNECTOR_CRT_LEGACY:
1641                                 if (tmp & 0x1) {
1642                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
1643                                         radeon_add_legacy_encoder(dev,
1644                                                                   radeon_get_encoder_id
1645                                                                   (dev,
1646                                                                    ATOM_DEVICE_CRT2_SUPPORT,
1647                                                                    2),
1648                                                                   ATOM_DEVICE_CRT2_SUPPORT);
1649                                 } else {
1650                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
1651                                         radeon_add_legacy_encoder(dev,
1652                                                                   radeon_get_encoder_id
1653                                                                   (dev,
1654                                                                    ATOM_DEVICE_CRT1_SUPPORT,
1655                                                                    1),
1656                                                                   ATOM_DEVICE_CRT1_SUPPORT);
1657                                 }
1658                                 radeon_add_legacy_connector(dev,
1659                                                             i,
1660                                                             devices,
1661                                                             legacy_connector_convert
1662                                                             [connector],
1663                                                             &ddc_i2c);
1664                                 break;
1665                         case CONNECTOR_DVI_I_LEGACY:
1666                                 devices = 0;
1667                                 if (tmp & 0x1) {
1668                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
1669                                         radeon_add_legacy_encoder(dev,
1670                                                                   radeon_get_encoder_id
1671                                                                   (dev,
1672                                                                    ATOM_DEVICE_CRT2_SUPPORT,
1673                                                                    2),
1674                                                                   ATOM_DEVICE_CRT2_SUPPORT);
1675                                 } else {
1676                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
1677                                         radeon_add_legacy_encoder(dev,
1678                                                                   radeon_get_encoder_id
1679                                                                   (dev,
1680                                                                    ATOM_DEVICE_CRT1_SUPPORT,
1681                                                                    1),
1682                                                                   ATOM_DEVICE_CRT1_SUPPORT);
1683                                 }
1684                                 if ((tmp >> 4) & 0x1) {
1685                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
1686                                         radeon_add_legacy_encoder(dev,
1687                                                                   radeon_get_encoder_id
1688                                                                   (dev,
1689                                                                    ATOM_DEVICE_DFP2_SUPPORT,
1690                                                                    0),
1691                                                                   ATOM_DEVICE_DFP2_SUPPORT);
1692                                 } else {
1693                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
1694                                         radeon_add_legacy_encoder(dev,
1695                                                                   radeon_get_encoder_id
1696                                                                   (dev,
1697                                                                    ATOM_DEVICE_DFP1_SUPPORT,
1698                                                                    0),
1699                                                                   ATOM_DEVICE_DFP1_SUPPORT);
1700                                 }
1701                                 radeon_add_legacy_connector(dev,
1702                                                             i,
1703                                                             devices,
1704                                                             legacy_connector_convert
1705                                                             [connector],
1706                                                             &ddc_i2c);
1707                                 break;
1708                         case CONNECTOR_DVI_D_LEGACY:
1709                                 if ((tmp >> 4) & 0x1)
1710                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
1711                                 else
1712                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
1713                                 radeon_add_legacy_encoder(dev,
1714                                                           radeon_get_encoder_id
1715                                                           (dev, devices, 0),
1716                                                           devices);
1717                                 radeon_add_legacy_connector(dev, i, devices,
1718                                                             legacy_connector_convert
1719                                                             [connector],
1720                                                             &ddc_i2c);
1721                                 break;
1722                         case CONNECTOR_CTV_LEGACY:
1723                         case CONNECTOR_STV_LEGACY:
1724                                 radeon_add_legacy_encoder(dev,
1725                                                           radeon_get_encoder_id
1726                                                           (dev,
1727                                                            ATOM_DEVICE_TV1_SUPPORT,
1728                                                            2),
1729                                                           ATOM_DEVICE_TV1_SUPPORT);
1730                                 radeon_add_legacy_connector(dev, i,
1731                                                             ATOM_DEVICE_TV1_SUPPORT,
1732                                                             legacy_connector_convert
1733                                                             [connector],
1734                                                             &ddc_i2c);
1735                                 break;
1736                         default:
1737                                 DRM_ERROR("Unknown connector type: %d\n",
1738                                           connector);
1739                                 continue;
1740                         }
1741
1742                 }
1743         } else {
1744                 uint16_t tmds_info =
1745                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1746                 if (tmds_info) {
1747                         DRM_DEBUG("Found DFP table, assuming DVI connector\n");
1748
1749                         radeon_add_legacy_encoder(dev,
1750                                                   radeon_get_encoder_id(dev,
1751                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1752                                                                         1),
1753                                                   ATOM_DEVICE_CRT1_SUPPORT);
1754                         radeon_add_legacy_encoder(dev,
1755                                                   radeon_get_encoder_id(dev,
1756                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1757                                                                         0),
1758                                                   ATOM_DEVICE_DFP1_SUPPORT);
1759
1760                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1761                         radeon_add_legacy_connector(dev,
1762                                                     0,
1763                                                     ATOM_DEVICE_CRT1_SUPPORT |
1764                                                     ATOM_DEVICE_DFP1_SUPPORT,
1765                                                     DRM_MODE_CONNECTOR_DVII,
1766                                                     &ddc_i2c);
1767                 } else {
1768                         DRM_DEBUG("No connector info found\n");
1769                         return false;
1770                 }
1771         }
1772
1773         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
1774                 uint16_t lcd_info =
1775                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1776                 if (lcd_info) {
1777                         uint16_t lcd_ddc_info =
1778                             combios_get_table_offset(dev,
1779                                                      COMBIOS_LCD_DDC_INFO_TABLE);
1780
1781                         radeon_add_legacy_encoder(dev,
1782                                                   radeon_get_encoder_id(dev,
1783                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1784                                                                         0),
1785                                                   ATOM_DEVICE_LCD1_SUPPORT);
1786
1787                         if (lcd_ddc_info) {
1788                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
1789                                 switch (ddc_type) {
1790                                 case DDC_MONID:
1791                                         ddc_i2c =
1792                                             combios_setup_i2c_bus
1793                                             (RADEON_GPIO_MONID);
1794                                         break;
1795                                 case DDC_DVI:
1796                                         ddc_i2c =
1797                                             combios_setup_i2c_bus
1798                                             (RADEON_GPIO_DVI_DDC);
1799                                         break;
1800                                 case DDC_VGA:
1801                                         ddc_i2c =
1802                                             combios_setup_i2c_bus
1803                                             (RADEON_GPIO_VGA_DDC);
1804                                         break;
1805                                 case DDC_CRT2:
1806                                         ddc_i2c =
1807                                             combios_setup_i2c_bus
1808                                             (RADEON_GPIO_CRT2_DDC);
1809                                         break;
1810                                 case DDC_LCD:
1811                                         ddc_i2c =
1812                                             combios_setup_i2c_bus
1813                                             (RADEON_LCD_GPIO_MASK);
1814                                         ddc_i2c.mask_clk_mask =
1815                                             RBIOS32(lcd_ddc_info + 3);
1816                                         ddc_i2c.mask_data_mask =
1817                                             RBIOS32(lcd_ddc_info + 7);
1818                                         ddc_i2c.a_clk_mask =
1819                                             RBIOS32(lcd_ddc_info + 3);
1820                                         ddc_i2c.a_data_mask =
1821                                             RBIOS32(lcd_ddc_info + 7);
1822                                         ddc_i2c.put_clk_mask =
1823                                             RBIOS32(lcd_ddc_info + 3);
1824                                         ddc_i2c.put_data_mask =
1825                                             RBIOS32(lcd_ddc_info + 7);
1826                                         ddc_i2c.get_clk_mask =
1827                                             RBIOS32(lcd_ddc_info + 3);
1828                                         ddc_i2c.get_data_mask =
1829                                             RBIOS32(lcd_ddc_info + 7);
1830                                         break;
1831                                 case DDC_GPIO:
1832                                         ddc_i2c =
1833                                             combios_setup_i2c_bus
1834                                             (RADEON_MDGPIO_EN_REG);
1835                                         ddc_i2c.mask_clk_mask =
1836                                             RBIOS32(lcd_ddc_info + 3);
1837                                         ddc_i2c.mask_data_mask =
1838                                             RBIOS32(lcd_ddc_info + 7);
1839                                         ddc_i2c.a_clk_mask =
1840                                             RBIOS32(lcd_ddc_info + 3);
1841                                         ddc_i2c.a_data_mask =
1842                                             RBIOS32(lcd_ddc_info + 7);
1843                                         ddc_i2c.put_clk_mask =
1844                                             RBIOS32(lcd_ddc_info + 3);
1845                                         ddc_i2c.put_data_mask =
1846                                             RBIOS32(lcd_ddc_info + 7);
1847                                         ddc_i2c.get_clk_mask =
1848                                             RBIOS32(lcd_ddc_info + 3);
1849                                         ddc_i2c.get_data_mask =
1850                                             RBIOS32(lcd_ddc_info + 7);
1851                                         break;
1852                                 default:
1853                                         ddc_i2c.valid = false;
1854                                         break;
1855                                 }
1856                                 DRM_DEBUG("LCD DDC Info Table found!\n");
1857                         } else
1858                                 ddc_i2c.valid = false;
1859
1860                         radeon_add_legacy_connector(dev,
1861                                                     5,
1862                                                     ATOM_DEVICE_LCD1_SUPPORT,
1863                                                     DRM_MODE_CONNECTOR_LVDS,
1864                                                     &ddc_i2c);
1865                 }
1866         }
1867
1868         /* check TV table */
1869         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1870                 uint32_t tv_info =
1871                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1872                 if (tv_info) {
1873                         if (RBIOS8(tv_info + 6) == 'T') {
1874                                 radeon_add_legacy_encoder(dev,
1875                                                           radeon_get_encoder_id
1876                                                           (dev,
1877                                                            ATOM_DEVICE_TV1_SUPPORT,
1878                                                            2),
1879                                                           ATOM_DEVICE_TV1_SUPPORT);
1880                                 radeon_add_legacy_connector(dev, 6,
1881                                                             ATOM_DEVICE_TV1_SUPPORT,
1882                                                             DRM_MODE_CONNECTOR_SVIDEO,
1883                                                             &ddc_i2c);
1884                         }
1885                 }
1886         }
1887
1888         radeon_link_encoder_connector(dev);
1889
1890         return true;
1891 }
1892
1893 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
1894 {
1895         struct radeon_device *rdev = dev->dev_private;
1896
1897         if (offset) {
1898                 while (RBIOS16(offset)) {
1899                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
1900                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
1901                         uint32_t val, and_mask, or_mask;
1902                         uint32_t tmp;
1903
1904                         offset += 2;
1905                         switch (cmd) {
1906                         case 0:
1907                                 val = RBIOS32(offset);
1908                                 offset += 4;
1909                                 WREG32(addr, val);
1910                                 break;
1911                         case 1:
1912                                 val = RBIOS32(offset);
1913                                 offset += 4;
1914                                 WREG32(addr, val);
1915                                 break;
1916                         case 2:
1917                                 and_mask = RBIOS32(offset);
1918                                 offset += 4;
1919                                 or_mask = RBIOS32(offset);
1920                                 offset += 4;
1921                                 tmp = RREG32(addr);
1922                                 tmp &= and_mask;
1923                                 tmp |= or_mask;
1924                                 WREG32(addr, tmp);
1925                                 break;
1926                         case 3:
1927                                 and_mask = RBIOS32(offset);
1928                                 offset += 4;
1929                                 or_mask = RBIOS32(offset);
1930                                 offset += 4;
1931                                 tmp = RREG32(addr);
1932                                 tmp &= and_mask;
1933                                 tmp |= or_mask;
1934                                 WREG32(addr, tmp);
1935                                 break;
1936                         case 4:
1937                                 val = RBIOS16(offset);
1938                                 offset += 2;
1939                                 udelay(val);
1940                                 break;
1941                         case 5:
1942                                 val = RBIOS16(offset);
1943                                 offset += 2;
1944                                 switch (addr) {
1945                                 case 8:
1946                                         while (val--) {
1947                                                 if (!
1948                                                     (RREG32_PLL
1949                                                      (RADEON_CLK_PWRMGT_CNTL) &
1950                                                      RADEON_MC_BUSY))
1951                                                         break;
1952                                         }
1953                                         break;
1954                                 case 9:
1955                                         while (val--) {
1956                                                 if ((RREG32(RADEON_MC_STATUS) &
1957                                                      RADEON_MC_IDLE))
1958                                                         break;
1959                                         }
1960                                         break;
1961                                 default:
1962                                         break;
1963                                 }
1964                                 break;
1965                         default:
1966                                 break;
1967                         }
1968                 }
1969         }
1970 }
1971
1972 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
1973 {
1974         struct radeon_device *rdev = dev->dev_private;
1975
1976         if (offset) {
1977                 while (RBIOS8(offset)) {
1978                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
1979                         uint8_t addr = (RBIOS8(offset) & 0x3f);
1980                         uint32_t val, shift, tmp;
1981                         uint32_t and_mask, or_mask;
1982
1983                         offset++;
1984                         switch (cmd) {
1985                         case 0:
1986                                 val = RBIOS32(offset);
1987                                 offset += 4;
1988                                 WREG32_PLL(addr, val);
1989                                 break;
1990                         case 1:
1991                                 shift = RBIOS8(offset) * 8;
1992                                 offset++;
1993                                 and_mask = RBIOS8(offset) << shift;
1994                                 and_mask |= ~(0xff << shift);
1995                                 offset++;
1996                                 or_mask = RBIOS8(offset) << shift;
1997                                 offset++;
1998                                 tmp = RREG32_PLL(addr);
1999                                 tmp &= and_mask;
2000                                 tmp |= or_mask;
2001                                 WREG32_PLL(addr, tmp);
2002                                 break;
2003                         case 2:
2004                         case 3:
2005                                 tmp = 1000;
2006                                 switch (addr) {
2007                                 case 1:
2008                                         udelay(150);
2009                                         break;
2010                                 case 2:
2011                                         udelay(1000);
2012                                         break;
2013                                 case 3:
2014                                         while (tmp--) {
2015                                                 if (!
2016                                                     (RREG32_PLL
2017                                                      (RADEON_CLK_PWRMGT_CNTL) &
2018                                                      RADEON_MC_BUSY))
2019                                                         break;
2020                                         }
2021                                         break;
2022                                 case 4:
2023                                         while (tmp--) {
2024                                                 if (RREG32_PLL
2025                                                     (RADEON_CLK_PWRMGT_CNTL) &
2026                                                     RADEON_DLL_READY)
2027                                                         break;
2028                                         }
2029                                         break;
2030                                 case 5:
2031                                         tmp =
2032                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2033                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
2034 #if 0
2035                                                 uint32_t mclk_cntl =
2036                                                     RREG32_PLL
2037                                                     (RADEON_MCLK_CNTL);
2038                                                 mclk_cntl &= 0xffff0000;
2039                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
2040                                                 WREG32_PLL(RADEON_MCLK_CNTL,
2041                                                            mclk_cntl);
2042                                                 udelay(10000);
2043 #endif
2044                                                 WREG32_PLL
2045                                                     (RADEON_CLK_PWRMGT_CNTL,
2046                                                      tmp &
2047                                                      ~RADEON_CG_NO1_DEBUG_0);
2048                                                 udelay(10000);
2049                                         }
2050                                         break;
2051                                 default:
2052                                         break;
2053                                 }
2054                                 break;
2055                         default:
2056                                 break;
2057                         }
2058                 }
2059         }
2060 }
2061
2062 static void combios_parse_ram_reset_table(struct drm_device *dev,
2063                                           uint16_t offset)
2064 {
2065         struct radeon_device *rdev = dev->dev_private;
2066         uint32_t tmp;
2067
2068         if (offset) {
2069                 uint8_t val = RBIOS8(offset);
2070                 while (val != 0xff) {
2071                         offset++;
2072
2073                         if (val == 0x0f) {
2074                                 uint32_t channel_complete_mask;
2075
2076                                 if (ASIC_IS_R300(rdev))
2077                                         channel_complete_mask =
2078                                             R300_MEM_PWRUP_COMPLETE;
2079                                 else
2080                                         channel_complete_mask =
2081                                             RADEON_MEM_PWRUP_COMPLETE;
2082                                 tmp = 20000;
2083                                 while (tmp--) {
2084                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
2085                                              channel_complete_mask) ==
2086                                             channel_complete_mask)
2087                                                 break;
2088                                 }
2089                         } else {
2090                                 uint32_t or_mask = RBIOS16(offset);
2091                                 offset += 2;
2092
2093                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2094                                 tmp &= RADEON_SDRAM_MODE_MASK;
2095                                 tmp |= or_mask;
2096                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2097
2098                                 or_mask = val << 24;
2099                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2100                                 tmp &= RADEON_B3MEM_RESET_MASK;
2101                                 tmp |= or_mask;
2102                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2103                         }
2104                         val = RBIOS8(offset);
2105                 }
2106         }
2107 }
2108
2109 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2110                                    int mem_addr_mapping)
2111 {
2112         struct radeon_device *rdev = dev->dev_private;
2113         uint32_t mem_cntl;
2114         uint32_t mem_size;
2115         uint32_t addr = 0;
2116
2117         mem_cntl = RREG32(RADEON_MEM_CNTL);
2118         if (mem_cntl & RV100_HALF_MODE)
2119                 ram /= 2;
2120         mem_size = ram;
2121         mem_cntl &= ~(0xff << 8);
2122         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2123         WREG32(RADEON_MEM_CNTL, mem_cntl);
2124         RREG32(RADEON_MEM_CNTL);
2125
2126         /* sdram reset ? */
2127
2128         /* something like this????  */
2129         while (ram--) {
2130                 addr = ram * 1024 * 1024;
2131                 /* write to each page */
2132                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2133                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2134                 /* read back and verify */
2135                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2136                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2137                         return 0;
2138         }
2139
2140         return mem_size;
2141 }
2142
2143 static void combios_write_ram_size(struct drm_device *dev)
2144 {
2145         struct radeon_device *rdev = dev->dev_private;
2146         uint8_t rev;
2147         uint16_t offset;
2148         uint32_t mem_size = 0;
2149         uint32_t mem_cntl = 0;
2150
2151         /* should do something smarter here I guess... */
2152         if (rdev->flags & RADEON_IS_IGP)
2153                 return;
2154
2155         /* first check detected mem table */
2156         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2157         if (offset) {
2158                 rev = RBIOS8(offset);
2159                 if (rev < 3) {
2160                         mem_cntl = RBIOS32(offset + 1);
2161                         mem_size = RBIOS16(offset + 5);
2162                         if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2163                             ((dev->pdev->device != 0x515e)
2164                              && (dev->pdev->device != 0x5969)))
2165                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
2166                 }
2167         }
2168
2169         if (!mem_size) {
2170                 offset =
2171                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2172                 if (offset) {
2173                         rev = RBIOS8(offset - 1);
2174                         if (rev < 1) {
2175                                 if (((rdev->flags & RADEON_FAMILY_MASK) <
2176                                      CHIP_R200)
2177                                     && ((dev->pdev->device != 0x515e)
2178                                         && (dev->pdev->device != 0x5969))) {
2179                                         int ram = 0;
2180                                         int mem_addr_mapping = 0;
2181
2182                                         while (RBIOS8(offset)) {
2183                                                 ram = RBIOS8(offset);
2184                                                 mem_addr_mapping =
2185                                                     RBIOS8(offset + 1);
2186                                                 if (mem_addr_mapping != 0x25)
2187                                                         ram *= 2;
2188                                                 mem_size =
2189                                                     combios_detect_ram(dev, ram,
2190                                                                        mem_addr_mapping);
2191                                                 if (mem_size)
2192                                                         break;
2193                                                 offset += 2;
2194                                         }
2195                                 } else
2196                                         mem_size = RBIOS8(offset);
2197                         } else {
2198                                 mem_size = RBIOS8(offset);
2199                                 mem_size *= 2;  /* convert to MB */
2200                         }
2201                 }
2202         }
2203
2204         mem_size *= (1024 * 1024);      /* convert to bytes */
2205         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2206 }
2207
2208 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2209 {
2210         uint16_t dyn_clk_info =
2211             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2212
2213         if (dyn_clk_info)
2214                 combios_parse_pll_table(dev, dyn_clk_info);
2215 }
2216
2217 void radeon_combios_asic_init(struct drm_device *dev)
2218 {
2219         struct radeon_device *rdev = dev->dev_private;
2220         uint16_t table;
2221
2222         /* port hardcoded mac stuff from radeonfb */
2223         if (rdev->bios == NULL)
2224                 return;
2225
2226         /* ASIC INIT 1 */
2227         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2228         if (table)
2229                 combios_parse_mmio_table(dev, table);
2230
2231         /* PLL INIT */
2232         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2233         if (table)
2234                 combios_parse_pll_table(dev, table);
2235
2236         /* ASIC INIT 2 */
2237         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2238         if (table)
2239                 combios_parse_mmio_table(dev, table);
2240
2241         if (!(rdev->flags & RADEON_IS_IGP)) {
2242                 /* ASIC INIT 4 */
2243                 table =
2244                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2245                 if (table)
2246                         combios_parse_mmio_table(dev, table);
2247
2248                 /* RAM RESET */
2249                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2250                 if (table)
2251                         combios_parse_ram_reset_table(dev, table);
2252
2253                 /* ASIC INIT 3 */
2254                 table =
2255                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2256                 if (table)
2257                         combios_parse_mmio_table(dev, table);
2258
2259                 /* write CONFIG_MEMSIZE */
2260                 combios_write_ram_size(dev);
2261         }
2262
2263         /* DYN CLK 1 */
2264         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2265         if (table)
2266                 combios_parse_pll_table(dev, table);
2267
2268 }
2269
2270 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2271 {
2272         struct radeon_device *rdev = dev->dev_private;
2273         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2274
2275         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2276         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2277         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2278
2279         /* let the bios control the backlight */
2280         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2281
2282         /* tell the bios not to handle mode switching */
2283         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2284                            RADEON_ACC_MODE_CHANGE);
2285
2286         /* tell the bios a driver is loaded */
2287         bios_7_scratch |= RADEON_DRV_LOADED;
2288
2289         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2290         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2291         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2292 }
2293
2294 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2295 {
2296         struct drm_device *dev = encoder->dev;
2297         struct radeon_device *rdev = dev->dev_private;
2298         uint32_t bios_6_scratch;
2299
2300         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2301
2302         if (lock)
2303                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2304         else
2305                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2306
2307         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2308 }
2309
2310 void
2311 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2312                                       struct drm_encoder *encoder,
2313                                       bool connected)
2314 {
2315         struct drm_device *dev = connector->dev;
2316         struct radeon_device *rdev = dev->dev_private;
2317         struct radeon_connector *radeon_connector =
2318             to_radeon_connector(connector);
2319         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2320         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2321         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2322
2323         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2324             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2325                 if (connected) {
2326                         DRM_DEBUG("TV1 connected\n");
2327                         /* fix me */
2328                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2329                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2330                         bios_5_scratch |= RADEON_TV1_ON;
2331                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
2332                 } else {
2333                         DRM_DEBUG("TV1 disconnected\n");
2334                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2335                         bios_5_scratch &= ~RADEON_TV1_ON;
2336                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2337                 }
2338         }
2339         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2340             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2341                 if (connected) {
2342                         DRM_DEBUG("LCD1 connected\n");
2343                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
2344                         bios_5_scratch |= RADEON_LCD1_ON;
2345                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2346                 } else {
2347                         DRM_DEBUG("LCD1 disconnected\n");
2348                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2349                         bios_5_scratch &= ~RADEON_LCD1_ON;
2350                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2351                 }
2352         }
2353         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2354             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2355                 if (connected) {
2356                         DRM_DEBUG("CRT1 connected\n");
2357                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2358                         bios_5_scratch |= RADEON_CRT1_ON;
2359                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2360                 } else {
2361                         DRM_DEBUG("CRT1 disconnected\n");
2362                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2363                         bios_5_scratch &= ~RADEON_CRT1_ON;
2364                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2365                 }
2366         }
2367         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2368             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2369                 if (connected) {
2370                         DRM_DEBUG("CRT2 connected\n");
2371                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2372                         bios_5_scratch |= RADEON_CRT2_ON;
2373                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2374                 } else {
2375                         DRM_DEBUG("CRT2 disconnected\n");
2376                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2377                         bios_5_scratch &= ~RADEON_CRT2_ON;
2378                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2379                 }
2380         }
2381         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2382             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2383                 if (connected) {
2384                         DRM_DEBUG("DFP1 connected\n");
2385                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
2386                         bios_5_scratch |= RADEON_DFP1_ON;
2387                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2388                 } else {
2389                         DRM_DEBUG("DFP1 disconnected\n");
2390                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2391                         bios_5_scratch &= ~RADEON_DFP1_ON;
2392                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2393                 }
2394         }
2395         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2396             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2397                 if (connected) {
2398                         DRM_DEBUG("DFP2 connected\n");
2399                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
2400                         bios_5_scratch |= RADEON_DFP2_ON;
2401                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2402                 } else {
2403                         DRM_DEBUG("DFP2 disconnected\n");
2404                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2405                         bios_5_scratch &= ~RADEON_DFP2_ON;
2406                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2407                 }
2408         }
2409         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2410         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2411 }
2412
2413 void
2414 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2415 {
2416         struct drm_device *dev = encoder->dev;
2417         struct radeon_device *rdev = dev->dev_private;
2418         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2419         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2420
2421         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2422                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2423                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
2424         }
2425         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2426                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
2427                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
2428         }
2429         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2430                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
2431                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
2432         }
2433         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2434                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
2435                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
2436         }
2437         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2438                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
2439                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
2440         }
2441         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2442                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
2443                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
2444         }
2445         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2446 }
2447
2448 void
2449 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2450 {
2451         struct drm_device *dev = encoder->dev;
2452         struct radeon_device *rdev = dev->dev_private;
2453         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2454         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2455
2456         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
2457                 if (on)
2458                         bios_6_scratch |= RADEON_TV_DPMS_ON;
2459                 else
2460                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
2461         }
2462         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2463                 if (on)
2464                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
2465                 else
2466                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
2467         }
2468         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2469                 if (on)
2470                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
2471                 else
2472                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
2473         }
2474         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
2475                 if (on)
2476                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
2477                 else
2478                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
2479         }
2480         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2481 }