git.oblomov.eu Git - linux-2.6/blob - drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.20 2005/11/08 19:51:55 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/config.h>
  50 #include <linux/module.h>
  51 #include <linux/version.h>
  52 #include <linux/errno.h>
  53 #include <linux/signal.h>
  54 #include <linux/sched.h>
  55 #include <linux/timer.h>
  56 #include <linux/interrupt.h>
  57 #include <linux/pci.h>
  58 #include <linux/tty.h>
  59 #include <linux/tty_flip.h>
  60 #include <linux/serial.h>
  61 #include <linux/major.h>
  62 #include <linux/string.h>
  63 #include <linux/fcntl.h>
  64 #include <linux/ptrace.h>
  65 #include <linux/ioport.h>
  66 #include <linux/mm.h>
  67 #include <linux/slab.h>
  68 #include <linux/netdevice.h>
  69 #include <linux/vmalloc.h>
  70 #include <linux/init.h>
  71 #include <linux/delay.h>
  72 #include <linux/ioctl.h>
  73 #include <linux/termios.h>
  74 #include <linux/bitops.h>
  75 #include <linux/workqueue.h>
  76 #include <linux/hdlc.h>
  77
  78 #include <asm/system.h>
  79 #include <asm/io.h>
  80 #include <asm/irq.h>
  81 #include <asm/dma.h>
  82 #include <asm/types.h>
  83 #include <asm/uaccess.h>
  84
  85 #include "linux/synclink.h"
  86
  87 #ifdef CONFIG_HDLC_MODULE
  88 #define CONFIG_HDLC 1
  89 #endif
  90
  91 /*
  92  * module identification
  93  */
  94 static char *driver_name     = "SyncLink GT";
  95 static char *driver_version  = "$Revision: 4.20 $";
  96 static char *tty_driver_name = "synclink_gt";
  97 static char *tty_dev_prefix  = "ttySLG";
  98 MODULE_LICENSE("GPL");
  99 #define MGSL_MAGIC 0x5401
 100 #define MAX_DEVICES 12
 101
 102 static struct pci_device_id pci_table[] = {
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {0,}, /* terminate list */
 107 };
 108 MODULE_DEVICE_TABLE(pci, pci_table);
 109
 110 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 111 static void remove_one(struct pci_dev *dev);
 112 static struct pci_driver pci_driver = {
 113         .name           = "synclink_gt",
 114         .id_table       = pci_table,
 115         .probe          = init_one,
 116         .remove         = __devexit_p(remove_one),
 117 };
 118
 119 static int pci_registered;
 120
 121 /*
 122  * module configuration and status
 123  */
 124 static struct slgt_info *slgt_device_list;
 125 static int slgt_device_count;
 126
 127 static int ttymajor;
 128 static int debug_level;
 129 static int maxframe[MAX_DEVICES];
 130 static int dosyncppp[MAX_DEVICES];
 131
 132 module_param(ttymajor, int, 0);
 133 module_param(debug_level, int, 0);
 134 module_param_array(maxframe, int, NULL, 0);
 135 module_param_array(dosyncppp, int, NULL, 0);
 136
 137 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 138 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 139 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 140 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 141
 142 /*
 143  * tty support and callbacks
 144  */
 145 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 146
 147 static struct tty_driver *serial_driver;
 148
 149 static int  open(struct tty_struct *tty, struct file * filp);
 150 static void close(struct tty_struct *tty, struct file * filp);
 151 static void hangup(struct tty_struct *tty);
 152 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
 153
 154 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 155 static void put_char(struct tty_struct *tty, unsigned char ch);
 156 static void send_xchar(struct tty_struct *tty, char ch);
 157 static void wait_until_sent(struct tty_struct *tty, int timeout);
 158 static int  write_room(struct tty_struct *tty);
 159 static void flush_chars(struct tty_struct *tty);
 160 static void flush_buffer(struct tty_struct *tty);
 161 static void tx_hold(struct tty_struct *tty);
 162 static void tx_release(struct tty_struct *tty);
 163
 164 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 165 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 166 static int  chars_in_buffer(struct tty_struct *tty);
 167 static void throttle(struct tty_struct * tty);
 168 static void unthrottle(struct tty_struct * tty);
 169 static void set_break(struct tty_struct *tty, int break_state);
 170
 171 /*
 172  * generic HDLC support and callbacks
 173  */
 174 #ifdef CONFIG_HDLC
 175 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 176 static void hdlcdev_tx_done(struct slgt_info *info);
 177 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 178 static int  hdlcdev_init(struct slgt_info *info);
 179 static void hdlcdev_exit(struct slgt_info *info);
 180 #endif
 181
 182
 183 /*
 184  * device specific structures, macros and functions
 185  */
 186
 187 #define SLGT_MAX_PORTS 4
 188 #define SLGT_REG_SIZE  256
 189
 190 /*
 191  * DMA buffer descriptor and access macros
 192  */
 193 struct slgt_desc
 194 {
 195         unsigned short count;
 196         unsigned short status;
 197         unsigned int pbuf;  /* physical address of data buffer */
 198         unsigned int next;  /* physical address of next descriptor */
 199
 200         /* driver book keeping */
 201         char *buf;          /* virtual  address of data buffer */
 202         unsigned int pdesc; /* physical address of this descriptor */
 203         dma_addr_t buf_dma_addr;
 204 };
 205
 206 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 207 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 208 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 209 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 210 #define desc_count(a)      (le16_to_cpu((a).count))
 211 #define desc_status(a)     (le16_to_cpu((a).status))
 212 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 213 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 214 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 215 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 216 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 217
 218 struct _input_signal_events {
 219         int ri_up;
 220         int ri_down;
 221         int dsr_up;
 222         int dsr_down;
 223         int dcd_up;
 224         int dcd_down;
 225         int cts_up;
 226         int cts_down;
 227 };
 228
 229 /*
 230  * device instance data structure
 231  */
 232 struct slgt_info {
 233         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 234
 235         struct slgt_info *next_device;  /* device list link */
 236
 237         int magic;
 238         int flags;
 239
 240         char device_name[25];
 241         struct pci_dev *pdev;
 242
 243         int port_count;  /* count of ports on adapter */
 244         int adapter_num; /* adapter instance number */
 245         int port_num;    /* port instance number */
 246
 247         /* array of pointers to port contexts on this adapter */
 248         struct slgt_info *port_array[SLGT_MAX_PORTS];
 249
 250         int                     count;          /* count of opens */
 251         int                     line;           /* tty line instance number */
 252         unsigned short          close_delay;
 253         unsigned short          closing_wait;   /* time to wait before closing */
 254
 255         struct mgsl_icount      icount;
 256
 257         struct tty_struct       *tty;
 258         int                     timeout;
 259         int                     x_char;         /* xon/xoff character */
 260         int                     blocked_open;   /* # of blocked opens */
 261         unsigned int            read_status_mask;
 262         unsigned int            ignore_status_mask;
 263
 264         wait_queue_head_t       open_wait;
 265         wait_queue_head_t       close_wait;
 266
 267         wait_queue_head_t       status_event_wait_q;
 268         wait_queue_head_t       event_wait_q;
 269         struct timer_list       tx_timer;
 270         struct timer_list       rx_timer;
 271
 272         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 273
 274         struct work_struct task;
 275         u32 pending_bh;
 276         int bh_requested;
 277         int bh_running;
 278
 279         int isr_overflow;
 280         int irq_requested;      /* nonzero if IRQ requested */
 281         int irq_occurred;       /* for diagnostics use */
 282
 283         /* device configuration */
 284
 285         unsigned int bus_type;
 286         unsigned int irq_level;
 287         unsigned long irq_flags;
 288
 289         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 290         u32 phys_reg_addr;
 291         u32 reg_offset;
 292         int reg_addr_requested;
 293
 294         MGSL_PARAMS params;       /* communications parameters */
 295         u32 idle_mode;
 296         u32 max_frame_size;       /* as set by device config */
 297
 298         unsigned int raw_rx_size;
 299         unsigned int if_mode;
 300
 301         /* device status */
 302
 303         int rx_enabled;
 304         int rx_restart;
 305
 306         int tx_enabled;
 307         int tx_active;
 308
 309         unsigned char signals;    /* serial signal states */
 310         unsigned int init_error;  /* initialization error */
 311
 312         unsigned char *tx_buf;
 313         int tx_count;
 314
 315         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 316         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 317         BOOLEAN drop_rts_on_tx_done;
 318         struct  _input_signal_events    input_signal_events;
 319
 320         int dcd_chkcount;       /* check counts to prevent */
 321         int cts_chkcount;       /* too many IRQs if a signal */
 322         int dsr_chkcount;       /* is floating */
 323         int ri_chkcount;
 324
 325         char *bufs;             /* virtual address of DMA buffer lists */
 326         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 327
 328         unsigned int rbuf_count;
 329         struct slgt_desc *rbufs;
 330         unsigned int rbuf_current;
 331         unsigned int rbuf_index;
 332
 333         unsigned int tbuf_count;
 334         struct slgt_desc *tbufs;
 335         unsigned int tbuf_current;
 336         unsigned int tbuf_start;
 337
 338         unsigned char *tmp_rbuf;
 339         unsigned int tmp_rbuf_count;
 340
 341         /* SPPP/Cisco HDLC device parts */
 342
 343         int netcount;
 344         int dosyncppp;
 345         spinlock_t netlock;
 346 #ifdef CONFIG_HDLC
 347         struct net_device *netdev;
 348 #endif
 349
 350 };
 351
 352 static MGSL_PARAMS default_params = {
 353         .mode            = MGSL_MODE_HDLC,
 354         .loopback        = 0,
 355         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 356         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 357         .clock_speed     = 0,
 358         .addr_filter     = 0xff,
 359         .crc_type        = HDLC_CRC_16_CCITT,
 360         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 361         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 362         .data_rate       = 9600,
 363         .data_bits       = 8,
 364         .stop_bits       = 1,
 365         .parity          = ASYNC_PARITY_NONE
 366 };
 367
 368
 369 #define BH_RECEIVE  1
 370 #define BH_TRANSMIT 2
 371 #define BH_STATUS   4
 372 #define IO_PIN_SHUTDOWN_LIMIT 100
 373
 374 #define DMABUFSIZE 256
 375 #define DESC_LIST_SIZE 4096
 376
 377 #define MASK_PARITY  BIT1
 378 #define MASK_FRAMING BIT2
 379 #define MASK_BREAK   BIT3
 380 #define MASK_OVERRUN BIT4
 381
 382 #define GSR   0x00 /* global status */
 383 #define TDR   0x80 /* tx data */
 384 #define RDR   0x80 /* rx data */
 385 #define TCR   0x82 /* tx control */
 386 #define TIR   0x84 /* tx idle */
 387 #define TPR   0x85 /* tx preamble */
 388 #define RCR   0x86 /* rx control */
 389 #define VCR   0x88 /* V.24 control */
 390 #define CCR   0x89 /* clock control */
 391 #define BDR   0x8a /* baud divisor */
 392 #define SCR   0x8c /* serial control */
 393 #define SSR   0x8e /* serial status */
 394 #define RDCSR 0x90 /* rx DMA control/status */
 395 #define TDCSR 0x94 /* tx DMA control/status */
 396 #define RDDAR 0x98 /* rx DMA descriptor address */
 397 #define TDDAR 0x9c /* tx DMA descriptor address */
 398
 399 #define RXIDLE      BIT14
 400 #define RXBREAK     BIT14
 401 #define IRQ_TXDATA  BIT13
 402 #define IRQ_TXIDLE  BIT12
 403 #define IRQ_TXUNDER BIT11 /* HDLC */
 404 #define IRQ_RXDATA  BIT10
 405 #define IRQ_RXIDLE  BIT9  /* HDLC */
 406 #define IRQ_RXBREAK BIT9  /* async */
 407 #define IRQ_RXOVER  BIT8
 408 #define IRQ_DSR     BIT7
 409 #define IRQ_CTS     BIT6
 410 #define IRQ_DCD     BIT5
 411 #define IRQ_RI      BIT4
 412 #define IRQ_ALL     0x3ff0
 413 #define IRQ_MASTER  BIT0
 414
 415 #define slgt_irq_on(info, mask) \
 416         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 417 #define slgt_irq_off(info, mask) \
 418         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 419
 420 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 421 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 422 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 423 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 424 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 425 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 426
 427 static void  msc_set_vcr(struct slgt_info *info);
 428
 429 static int  startup(struct slgt_info *info);
 430 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 431 static void shutdown(struct slgt_info *info);
 432 static void program_hw(struct slgt_info *info);
 433 static void change_params(struct slgt_info *info);
 434
 435 static int  register_test(struct slgt_info *info);
 436 static int  irq_test(struct slgt_info *info);
 437 static int  loopback_test(struct slgt_info *info);
 438 static int  adapter_test(struct slgt_info *info);
 439
 440 static void reset_adapter(struct slgt_info *info);
 441 static void reset_port(struct slgt_info *info);
 442 static void async_mode(struct slgt_info *info);
 443 static void hdlc_mode(struct slgt_info *info);
 444
 445 static void rx_stop(struct slgt_info *info);
 446 static void rx_start(struct slgt_info *info);
 447 static void reset_rbufs(struct slgt_info *info);
 448 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 449 static void rdma_reset(struct slgt_info *info);
 450 static int  rx_get_frame(struct slgt_info *info);
 451 static int  rx_get_buf(struct slgt_info *info);
 452
 453 static void tx_start(struct slgt_info *info);
 454 static void tx_stop(struct slgt_info *info);
 455 static void tx_set_idle(struct slgt_info *info);
 456 static unsigned int free_tbuf_count(struct slgt_info *info);
 457 static void reset_tbufs(struct slgt_info *info);
 458 static void tdma_reset(struct slgt_info *info);
 459 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 460
 461 static void get_signals(struct slgt_info *info);
 462 static void set_signals(struct slgt_info *info);
 463 static void enable_loopback(struct slgt_info *info);
 464 static void set_rate(struct slgt_info *info, u32 data_rate);
 465
 466 static int  bh_action(struct slgt_info *info);
 467 static void bh_handler(void* context);
 468 static void bh_transmit(struct slgt_info *info);
 469 static void isr_serial(struct slgt_info *info);
 470 static void isr_rdma(struct slgt_info *info);
 471 static void isr_txeom(struct slgt_info *info, unsigned short status);
 472 static void isr_tdma(struct slgt_info *info);
 473 static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs);
 474
 475 static int  alloc_dma_bufs(struct slgt_info *info);
 476 static void free_dma_bufs(struct slgt_info *info);
 477 static int  alloc_desc(struct slgt_info *info);
 478 static void free_desc(struct slgt_info *info);
 479 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 480 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 481
 482 static int  alloc_tmp_rbuf(struct slgt_info *info);
 483 static void free_tmp_rbuf(struct slgt_info *info);
 484
 485 static void tx_timeout(unsigned long context);
 486 static void rx_timeout(unsigned long context);
 487
 488 /*
 489  * ioctl handlers
 490  */
 491 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 492 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 493 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 494 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 495 static int  set_txidle(struct slgt_info *info, int idle_mode);
 496 static int  tx_enable(struct slgt_info *info, int enable);
 497 static int  tx_abort(struct slgt_info *info);
 498 static int  rx_enable(struct slgt_info *info, int enable);
 499 static int  modem_input_wait(struct slgt_info *info,int arg);
 500 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 501 static int  tiocmget(struct tty_struct *tty, struct file *file);
 502 static int  tiocmset(struct tty_struct *tty, struct file *file,
 503                      unsigned int set, unsigned int clear);
 504 static void set_break(struct tty_struct *tty, int break_state);
 505 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 506 static int  set_interface(struct slgt_info *info, int if_mode);
 507
 508 /*
 509  * driver functions
 510  */
 511 static void add_device(struct slgt_info *info);
 512 static void device_init(int adapter_num, struct pci_dev *pdev);
 513 static int  claim_resources(struct slgt_info *info);
 514 static void release_resources(struct slgt_info *info);
 515
 516 /*
 517  * DEBUG OUTPUT CODE
 518  */
 519 #ifndef DBGINFO
 520 #define DBGINFO(fmt)
 521 #endif
 522 #ifndef DBGERR
 523 #define DBGERR(fmt)
 524 #endif
 525 #ifndef DBGBH
 526 #define DBGBH(fmt)
 527 #endif
 528 #ifndef DBGISR
 529 #define DBGISR(fmt)
 530 #endif
 531
 532 #ifdef DBGDATA
 533 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 534 {
 535         int i;
 536         int linecount;
 537         printk("%s %s data:\n",info->device_name, label);
 538         while(count) {
 539                 linecount = (count > 16) ? 16 : count;
 540                 for(i=0; i < linecount; i++)
 541                         printk("%02X ",(unsigned char)data[i]);
 542                 for(;i<17;i++)
 543                         printk("   ");
 544                 for(i=0;i<linecount;i++) {
 545                         if (data[i]>=040 && data[i]<=0176)
 546                                 printk("%c",data[i]);
 547                         else
 548                                 printk(".");
 549                 }
 550                 printk("\n");
 551                 data  += linecount;
 552                 count -= linecount;
 553         }
 554 }
 555 #else
 556 #define DBGDATA(info, buf, size, label)
 557 #endif
 558
 559 #ifdef DBGTBUF
 560 static void dump_tbufs(struct slgt_info *info)
 561 {
 562         int i;
 563         printk("tbuf_current=%d\n", info->tbuf_current);
 564         for (i=0 ; i < info->tbuf_count ; i++) {
 565                 printk("%d: count=%04X status=%04X\n",
 566                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 567         }
 568 }
 569 #else
 570 #define DBGTBUF(info)
 571 #endif
 572
 573 #ifdef DBGRBUF
 574 static void dump_rbufs(struct slgt_info *info)
 575 {
 576         int i;
 577         printk("rbuf_current=%d\n", info->rbuf_current);
 578         for (i=0 ; i < info->rbuf_count ; i++) {
 579                 printk("%d: count=%04X status=%04X\n",
 580                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 581         }
 582 }
 583 #else
 584 #define DBGRBUF(info)
 585 #endif
 586
 587 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 588 {
 589 #ifdef SANITY_CHECK
 590         if (!info) {
 591                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 592                 return 1;
 593         }
 594         if (info->magic != MGSL_MAGIC) {
 595                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 596                 return 1;
 597         }
 598 #else
 599         if (!info)
 600                 return 1;
 601 #endif
 602         return 0;
 603 }
 604
 605 /**
 606  * line discipline callback wrappers
 607  *
 608  * The wrappers maintain line discipline references
 609  * while calling into the line discipline.
 610  *
 611  * ldisc_receive_buf  - pass receive data to line discipline
 612  */
 613 static void ldisc_receive_buf(struct tty_struct *tty,
 614                               const __u8 *data, char *flags, int count)
 615 {
 616         struct tty_ldisc *ld;
 617         if (!tty)
 618                 return;
 619         ld = tty_ldisc_ref(tty);
 620         if (ld) {
 621                 if (ld->receive_buf)
 622                         ld->receive_buf(tty, data, flags, count);
 623                 tty_ldisc_deref(ld);
 624         }
 625 }
 626
 627 /* tty callbacks */
 628
 629 static int open(struct tty_struct *tty, struct file *filp)
 630 {
 631         struct slgt_info *info;
 632         int retval, line;
 633         unsigned long flags;
 634
 635         line = tty->index;
 636         if ((line < 0) || (line >= slgt_device_count)) {
 637                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 638                 return -ENODEV;
 639         }
 640
 641         info = slgt_device_list;
 642         while(info && info->line != line)
 643                 info = info->next_device;
 644         if (sanity_check(info, tty->name, "open"))
 645                 return -ENODEV;
 646         if (info->init_error) {
 647                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 648                 return -ENODEV;
 649         }
 650
 651         tty->driver_data = info;
 652         info->tty = tty;
 653
 654         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
 655
 656         /* If port is closing, signal caller to try again */
 657         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 658                 if (info->flags & ASYNC_CLOSING)
 659                         interruptible_sleep_on(&info->close_wait);
 660                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 661                         -EAGAIN : -ERESTARTSYS);
 662                 goto cleanup;
 663         }
 664
 665         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 666
 667         spin_lock_irqsave(&info->netlock, flags);
 668         if (info->netcount) {
 669                 retval = -EBUSY;
 670                 spin_unlock_irqrestore(&info->netlock, flags);
 671                 goto cleanup;
 672         }
 673         info->count++;
 674         spin_unlock_irqrestore(&info->netlock, flags);
 675
 676         if (info->count == 1) {
 677                 /* 1st open on this device, init hardware */
 678                 retval = startup(info);
 679                 if (retval < 0)
 680                         goto cleanup;
 681         }
 682
 683         retval = block_til_ready(tty, filp, info);
 684         if (retval) {
 685                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 686                 goto cleanup;
 687         }
 688
 689         retval = 0;
 690
 691 cleanup:
 692         if (retval) {
 693                 if (tty->count == 1)
 694                         info->tty = NULL; /* tty layer will release tty struct */
 695                 if(info->count)
 696                         info->count--;
 697         }
 698
 699         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 700         return retval;
 701 }
 702
 703 static void close(struct tty_struct *tty, struct file *filp)
 704 {
 705         struct slgt_info *info = tty->driver_data;
 706
 707         if (sanity_check(info, tty->name, "close"))
 708                 return;
 709         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
 710
 711         if (!info->count)
 712                 return;
 713
 714         if (tty_hung_up_p(filp))
 715                 goto cleanup;
 716
 717         if ((tty->count == 1) && (info->count != 1)) {
 718                 /*
 719                  * tty->count is 1 and the tty structure will be freed.
 720                  * info->count should be one in this case.
 721                  * if it's not, correct it so that the port is shutdown.
 722                  */
 723                 DBGERR(("%s close: bad refcount; tty->count=1, "
 724                        "info->count=%d\n", info->device_name, info->count));
 725                 info->count = 1;
 726         }
 727
 728         info->count--;
 729
 730         /* if at least one open remaining, leave hardware active */
 731         if (info->count)
 732                 goto cleanup;
 733
 734         info->flags |= ASYNC_CLOSING;
 735
 736         /* set tty->closing to notify line discipline to
 737          * only process XON/XOFF characters. Only the N_TTY
 738          * discipline appears to use this (ppp does not).
 739          */
 740         tty->closing = 1;
 741
 742         /* wait for transmit data to clear all layers */
 743
 744         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 745                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 746                 tty_wait_until_sent(tty, info->closing_wait);
 747         }
 748
 749         if (info->flags & ASYNC_INITIALIZED)
 750                 wait_until_sent(tty, info->timeout);
 751         if (tty->driver->flush_buffer)
 752                 tty->driver->flush_buffer(tty);
 753         tty_ldisc_flush(tty);
 754
 755         shutdown(info);
 756
 757         tty->closing = 0;
 758         info->tty = NULL;
 759
 760         if (info->blocked_open) {
 761                 if (info->close_delay) {
 762                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 763                 }
 764                 wake_up_interruptible(&info->open_wait);
 765         }
 766
 767         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 768
 769         wake_up_interruptible(&info->close_wait);
 770
 771 cleanup:
 772         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
 773 }
 774
 775 static void hangup(struct tty_struct *tty)
 776 {
 777         struct slgt_info *info = tty->driver_data;
 778
 779         if (sanity_check(info, tty->name, "hangup"))
 780                 return;
 781         DBGINFO(("%s hangup\n", info->device_name));
 782
 783         flush_buffer(tty);
 784         shutdown(info);
 785
 786         info->count = 0;
 787         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 788         info->tty = NULL;
 789
 790         wake_up_interruptible(&info->open_wait);
 791 }
 792
 793 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
 794 {
 795         struct slgt_info *info = tty->driver_data;
 796         unsigned long flags;
 797
 798         DBGINFO(("%s set_termios\n", tty->driver->name));
 799
 800         /* just return if nothing has changed */
 801         if ((tty->termios->c_cflag == old_termios->c_cflag)
 802             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 803                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 804                 return;
 805
 806         change_params(info);
 807
 808         /* Handle transition to B0 status */
 809         if (old_termios->c_cflag & CBAUD &&
 810             !(tty->termios->c_cflag & CBAUD)) {
 811                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 812                 spin_lock_irqsave(&info->lock,flags);
 813                 set_signals(info);
 814                 spin_unlock_irqrestore(&info->lock,flags);
 815         }
 816
 817         /* Handle transition away from B0 status */
 818         if (!(old_termios->c_cflag & CBAUD) &&
 819             tty->termios->c_cflag & CBAUD) {
 820                 info->signals |= SerialSignal_DTR;
 821                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 822                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 823                         info->signals |= SerialSignal_RTS;
 824                 }
 825                 spin_lock_irqsave(&info->lock,flags);
 826                 set_signals(info);
 827                 spin_unlock_irqrestore(&info->lock,flags);
 828         }
 829
 830         /* Handle turning off CRTSCTS */
 831         if (old_termios->c_cflag & CRTSCTS &&
 832             !(tty->termios->c_cflag & CRTSCTS)) {
 833                 tty->hw_stopped = 0;
 834                 tx_release(tty);
 835         }
 836 }
 837
 838 static int write(struct tty_struct *tty,
 839                  const unsigned char *buf, int count)
 840 {
 841         int ret = 0;
 842         struct slgt_info *info = tty->driver_data;
 843         unsigned long flags;
 844
 845         if (sanity_check(info, tty->name, "write"))
 846                 goto cleanup;
 847         DBGINFO(("%s write count=%d\n", info->device_name, count));
 848
 849         if (!tty || !info->tx_buf)
 850                 goto cleanup;
 851
 852         if (count > info->max_frame_size) {
 853                 ret = -EIO;
 854                 goto cleanup;
 855         }
 856
 857         if (!count)
 858                 goto cleanup;
 859
 860         if (info->params.mode == MGSL_MODE_RAW) {
 861                 unsigned int bufs_needed = (count/DMABUFSIZE);
 862                 unsigned int bufs_free = free_tbuf_count(info);
 863                 if (count % DMABUFSIZE)
 864                         ++bufs_needed;
 865                 if (bufs_needed > bufs_free)
 866                         goto cleanup;
 867         } else {
 868                 if (info->tx_active)
 869                         goto cleanup;
 870                 if (info->tx_count) {
 871                         /* send accumulated data from send_char() calls */
 872                         /* as frame and wait before accepting more data. */
 873                         tx_load(info, info->tx_buf, info->tx_count);
 874                         goto start;
 875                 }
 876         }
 877
 878         ret = info->tx_count = count;
 879         tx_load(info, buf, count);
 880         goto start;
 881
 882 start:
 883         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 884                 spin_lock_irqsave(&info->lock,flags);
 885                 if (!info->tx_active)
 886                         tx_start(info);
 887                 spin_unlock_irqrestore(&info->lock,flags);
 888         }
 889
 890 cleanup:
 891         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 892         return ret;
 893 }
 894
 895 static void put_char(struct tty_struct *tty, unsigned char ch)
 896 {
 897         struct slgt_info *info = tty->driver_data;
 898         unsigned long flags;
 899
 900         if (sanity_check(info, tty->name, "put_char"))
 901                 return;
 902         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 903         if (!tty || !info->tx_buf)
 904                 return;
 905         spin_lock_irqsave(&info->lock,flags);
 906         if (!info->tx_active && (info->tx_count < info->max_frame_size))
 907                 info->tx_buf[info->tx_count++] = ch;
 908         spin_unlock_irqrestore(&info->lock,flags);
 909 }
 910
 911 static void send_xchar(struct tty_struct *tty, char ch)
 912 {
 913         struct slgt_info *info = tty->driver_data;
 914         unsigned long flags;
 915
 916         if (sanity_check(info, tty->name, "send_xchar"))
 917                 return;
 918         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 919         info->x_char = ch;
 920         if (ch) {
 921                 spin_lock_irqsave(&info->lock,flags);
 922                 if (!info->tx_enabled)
 923                         tx_start(info);
 924                 spin_unlock_irqrestore(&info->lock,flags);
 925         }
 926 }
 927
 928 static void wait_until_sent(struct tty_struct *tty, int timeout)
 929 {
 930         struct slgt_info *info = tty->driver_data;
 931         unsigned long orig_jiffies, char_time;
 932
 933         if (!info )
 934                 return;
 935         if (sanity_check(info, tty->name, "wait_until_sent"))
 936                 return;
 937         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 938         if (!(info->flags & ASYNC_INITIALIZED))
 939                 goto exit;
 940
 941         orig_jiffies = jiffies;
 942
 943         /* Set check interval to 1/5 of estimated time to
 944          * send a character, and make it at least 1. The check
 945          * interval should also be less than the timeout.
 946          * Note: use tight timings here to satisfy the NIST-PCTS.
 947          */
 948
 949         if (info->params.data_rate) {
 950                 char_time = info->timeout/(32 * 5);
 951                 if (!char_time)
 952                         char_time++;
 953         } else
 954                 char_time = 1;
 955
 956         if (timeout)
 957                 char_time = min_t(unsigned long, char_time, timeout);
 958
 959         while (info->tx_active) {
 960                 msleep_interruptible(jiffies_to_msecs(char_time));
 961                 if (signal_pending(current))
 962                         break;
 963                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 964                         break;
 965         }
 966
 967 exit:
 968         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 969 }
 970
 971 static int write_room(struct tty_struct *tty)
 972 {
 973         struct slgt_info *info = tty->driver_data;
 974         int ret;
 975
 976         if (sanity_check(info, tty->name, "write_room"))
 977                 return 0;
 978         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 979         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 980         return ret;
 981 }
 982
 983 static void flush_chars(struct tty_struct *tty)
 984 {
 985         struct slgt_info *info = tty->driver_data;
 986         unsigned long flags;
 987
 988         if (sanity_check(info, tty->name, "flush_chars"))
 989                 return;
 990         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 991
 992         if (info->tx_count <= 0 || tty->stopped ||
 993             tty->hw_stopped || !info->tx_buf)
 994                 return;
 995
 996         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 997
 998         spin_lock_irqsave(&info->lock,flags);
 999         if (!info->tx_active && info->tx_count) {
1000                 tx_load(info, info->tx_buf,info->tx_count);
1001                 tx_start(info);
1002         }
1003         spin_unlock_irqrestore(&info->lock,flags);
1004 }
1005
1006 static void flush_buffer(struct tty_struct *tty)
1007 {
1008         struct slgt_info *info = tty->driver_data;
1009         unsigned long flags;
1010
1011         if (sanity_check(info, tty->name, "flush_buffer"))
1012                 return;
1013         DBGINFO(("%s flush_buffer\n", info->device_name));
1014
1015         spin_lock_irqsave(&info->lock,flags);
1016         if (!info->tx_active)
1017                 info->tx_count = 0;
1018         spin_unlock_irqrestore(&info->lock,flags);
1019
1020         wake_up_interruptible(&tty->write_wait);
1021         tty_wakeup(tty);
1022 }
1023
1024 /*
1025  * throttle (stop) transmitter
1026  */
1027 static void tx_hold(struct tty_struct *tty)
1028 {
1029         struct slgt_info *info = tty->driver_data;
1030         unsigned long flags;
1031
1032         if (sanity_check(info, tty->name, "tx_hold"))
1033                 return;
1034         DBGINFO(("%s tx_hold\n", info->device_name));
1035         spin_lock_irqsave(&info->lock,flags);
1036         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1037                 tx_stop(info);
1038         spin_unlock_irqrestore(&info->lock,flags);
1039 }
1040
1041 /*
1042  * release (start) transmitter
1043  */
1044 static void tx_release(struct tty_struct *tty)
1045 {
1046         struct slgt_info *info = tty->driver_data;
1047         unsigned long flags;
1048
1049         if (sanity_check(info, tty->name, "tx_release"))
1050                 return;
1051         DBGINFO(("%s tx_release\n", info->device_name));
1052         spin_lock_irqsave(&info->lock,flags);
1053         if (!info->tx_active && info->tx_count) {
1054                 tx_load(info, info->tx_buf, info->tx_count);
1055                 tx_start(info);
1056         }
1057         spin_unlock_irqrestore(&info->lock,flags);
1058 }
1059
1060 /*
1061  * Service an IOCTL request
1062  *
1063  * Arguments
1064  *
1065  *      tty     pointer to tty instance data
1066  *      file    pointer to associated file object for device
1067  *      cmd     IOCTL command code
1068  *      arg     command argument/context
1069  *
1070  * Return 0 if success, otherwise error code
1071  */
1072 static int ioctl(struct tty_struct *tty, struct file *file,
1073                  unsigned int cmd, unsigned long arg)
1074 {
1075         struct slgt_info *info = tty->driver_data;
1076         struct mgsl_icount cnow;        /* kernel counter temps */
1077         struct serial_icounter_struct __user *p_cuser;  /* user space */
1078         unsigned long flags;
1079         void __user *argp = (void __user *)arg;
1080
1081         if (sanity_check(info, tty->name, "ioctl"))
1082                 return -ENODEV;
1083         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1084
1085         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1086             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1087                 if (tty->flags & (1 << TTY_IO_ERROR))
1088                     return -EIO;
1089         }
1090
1091         switch (cmd) {
1092         case MGSL_IOCGPARAMS:
1093                 return get_params(info, argp);
1094         case MGSL_IOCSPARAMS:
1095                 return set_params(info, argp);
1096         case MGSL_IOCGTXIDLE:
1097                 return get_txidle(info, argp);
1098         case MGSL_IOCSTXIDLE:
1099                 return set_txidle(info, (int)arg);
1100         case MGSL_IOCTXENABLE:
1101                 return tx_enable(info, (int)arg);
1102         case MGSL_IOCRXENABLE:
1103                 return rx_enable(info, (int)arg);
1104         case MGSL_IOCTXABORT:
1105                 return tx_abort(info);
1106         case MGSL_IOCGSTATS:
1107                 return get_stats(info, argp);
1108         case MGSL_IOCWAITEVENT:
1109                 return wait_mgsl_event(info, argp);
1110         case TIOCMIWAIT:
1111                 return modem_input_wait(info,(int)arg);
1112         case MGSL_IOCGIF:
1113                 return get_interface(info, argp);
1114         case MGSL_IOCSIF:
1115                 return set_interface(info,(int)arg);
1116         case TIOCGICOUNT:
1117                 spin_lock_irqsave(&info->lock,flags);
1118                 cnow = info->icount;
1119                 spin_unlock_irqrestore(&info->lock,flags);
1120                 p_cuser = argp;
1121                 if (put_user(cnow.cts, &p_cuser->cts) ||
1122                     put_user(cnow.dsr, &p_cuser->dsr) ||
1123                     put_user(cnow.rng, &p_cuser->rng) ||
1124                     put_user(cnow.dcd, &p_cuser->dcd) ||
1125                     put_user(cnow.rx, &p_cuser->rx) ||
1126                     put_user(cnow.tx, &p_cuser->tx) ||
1127                     put_user(cnow.frame, &p_cuser->frame) ||
1128                     put_user(cnow.overrun, &p_cuser->overrun) ||
1129                     put_user(cnow.parity, &p_cuser->parity) ||
1130                     put_user(cnow.brk, &p_cuser->brk) ||
1131                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1132                         return -EFAULT;
1133                 return 0;
1134         default:
1135                 return -ENOIOCTLCMD;
1136         }
1137         return 0;
1138 }
1139
1140 /*
1141  * proc fs support
1142  */
1143 static inline int line_info(char *buf, struct slgt_info *info)
1144 {
1145         char stat_buf[30];
1146         int ret;
1147         unsigned long flags;
1148
1149         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1150                       info->device_name, info->phys_reg_addr,
1151                       info->irq_level, info->max_frame_size);
1152
1153         /* output current serial signal states */
1154         spin_lock_irqsave(&info->lock,flags);
1155         get_signals(info);
1156         spin_unlock_irqrestore(&info->lock,flags);
1157
1158         stat_buf[0] = 0;
1159         stat_buf[1] = 0;
1160         if (info->signals & SerialSignal_RTS)
1161                 strcat(stat_buf, "|RTS");
1162         if (info->signals & SerialSignal_CTS)
1163                 strcat(stat_buf, "|CTS");
1164         if (info->signals & SerialSignal_DTR)
1165                 strcat(stat_buf, "|DTR");
1166         if (info->signals & SerialSignal_DSR)
1167                 strcat(stat_buf, "|DSR");
1168         if (info->signals & SerialSignal_DCD)
1169                 strcat(stat_buf, "|CD");
1170         if (info->signals & SerialSignal_RI)
1171                 strcat(stat_buf, "|RI");
1172
1173         if (info->params.mode != MGSL_MODE_ASYNC) {
1174                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1175                                info->icount.txok, info->icount.rxok);
1176                 if (info->icount.txunder)
1177                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1178                 if (info->icount.txabort)
1179                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1180                 if (info->icount.rxshort)
1181                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1182                 if (info->icount.rxlong)
1183                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1184                 if (info->icount.rxover)
1185                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1186                 if (info->icount.rxcrc)
1187                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1188         } else {
1189                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1190                                info->icount.tx, info->icount.rx);
1191                 if (info->icount.frame)
1192                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1193                 if (info->icount.parity)
1194                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1195                 if (info->icount.brk)
1196                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1197                 if (info->icount.overrun)
1198                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1199         }
1200
1201         /* Append serial signal status to end */
1202         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1203
1204         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1205                        info->tx_active,info->bh_requested,info->bh_running,
1206                        info->pending_bh);
1207
1208         return ret;
1209 }
1210
1211 /* Called to print information about devices
1212  */
1213 static int read_proc(char *page, char **start, off_t off, int count,
1214                      int *eof, void *data)
1215 {
1216         int len = 0, l;
1217         off_t   begin = 0;
1218         struct slgt_info *info;
1219
1220         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1221
1222         info = slgt_device_list;
1223         while( info ) {
1224                 l = line_info(page + len, info);
1225                 len += l;
1226                 if (len+begin > off+count)
1227                         goto done;
1228                 if (len+begin < off) {
1229                         begin += len;
1230                         len = 0;
1231                 }
1232                 info = info->next_device;
1233         }
1234
1235         *eof = 1;
1236 done:
1237         if (off >= len+begin)
1238                 return 0;
1239         *start = page + (off-begin);
1240         return ((count < begin+len-off) ? count : begin+len-off);
1241 }
1242
1243 /*
1244  * return count of bytes in transmit buffer
1245  */
1246 static int chars_in_buffer(struct tty_struct *tty)
1247 {
1248         struct slgt_info *info = tty->driver_data;
1249         if (sanity_check(info, tty->name, "chars_in_buffer"))
1250                 return 0;
1251         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1252         return info->tx_count;
1253 }
1254
1255 /*
1256  * signal remote device to throttle send data (our receive data)
1257  */
1258 static void throttle(struct tty_struct * tty)
1259 {
1260         struct slgt_info *info = tty->driver_data;
1261         unsigned long flags;
1262
1263         if (sanity_check(info, tty->name, "throttle"))
1264                 return;
1265         DBGINFO(("%s throttle\n", info->device_name));
1266         if (I_IXOFF(tty))
1267                 send_xchar(tty, STOP_CHAR(tty));
1268         if (tty->termios->c_cflag & CRTSCTS) {
1269                 spin_lock_irqsave(&info->lock,flags);
1270                 info->signals &= ~SerialSignal_RTS;
1271                 set_signals(info);
1272                 spin_unlock_irqrestore(&info->lock,flags);
1273         }
1274 }
1275
1276 /*
1277  * signal remote device to stop throttling send data (our receive data)
1278  */
1279 static void unthrottle(struct tty_struct * tty)
1280 {
1281         struct slgt_info *info = tty->driver_data;
1282         unsigned long flags;
1283
1284         if (sanity_check(info, tty->name, "unthrottle"))
1285                 return;
1286         DBGINFO(("%s unthrottle\n", info->device_name));
1287         if (I_IXOFF(tty)) {
1288                 if (info->x_char)
1289                         info->x_char = 0;
1290                 else
1291                         send_xchar(tty, START_CHAR(tty));
1292         }
1293         if (tty->termios->c_cflag & CRTSCTS) {
1294                 spin_lock_irqsave(&info->lock,flags);
1295                 info->signals |= SerialSignal_RTS;
1296                 set_signals(info);
1297                 spin_unlock_irqrestore(&info->lock,flags);
1298         }
1299 }
1300
1301 /*
1302  * set or clear transmit break condition
1303  * break_state  -1=set break condition, 0=clear
1304  */
1305 static void set_break(struct tty_struct *tty, int break_state)
1306 {
1307         struct slgt_info *info = tty->driver_data;
1308         unsigned short value;
1309         unsigned long flags;
1310
1311         if (sanity_check(info, tty->name, "set_break"))
1312                 return;
1313         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1314
1315         spin_lock_irqsave(&info->lock,flags);
1316         value = rd_reg16(info, TCR);
1317         if (break_state == -1)
1318                 value |= BIT6;
1319         else
1320                 value &= ~BIT6;
1321         wr_reg16(info, TCR, value);
1322         spin_unlock_irqrestore(&info->lock,flags);
1323 }
1324
1325 #ifdef CONFIG_HDLC
1326
1327 /**
1328  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1329  * set encoding and frame check sequence (FCS) options
1330  *
1331  * dev       pointer to network device structure
1332  * encoding  serial encoding setting
1333  * parity    FCS setting
1334  *
1335  * returns 0 if success, otherwise error code
1336  */
1337 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1338                           unsigned short parity)
1339 {
1340         struct slgt_info *info = dev_to_port(dev);
1341         unsigned char  new_encoding;
1342         unsigned short new_crctype;
1343
1344         /* return error if TTY interface open */
1345         if (info->count)
1346                 return -EBUSY;
1347
1348         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1349
1350         switch (encoding)
1351         {
1352         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1353         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1354         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1355         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1356         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1357         default: return -EINVAL;
1358         }
1359
1360         switch (parity)
1361         {
1362         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1363         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1364         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1365         default: return -EINVAL;
1366         }
1367
1368         info->params.encoding = new_encoding;
1369         info->params.crc_type = new_crctype;;
1370
1371         /* if network interface up, reprogram hardware */
1372         if (info->netcount)
1373                 program_hw(info);
1374
1375         return 0;
1376 }
1377
1378 /**
1379  * called by generic HDLC layer to send frame
1380  *
1381  * skb  socket buffer containing HDLC frame
1382  * dev  pointer to network device structure
1383  *
1384  * returns 0 if success, otherwise error code
1385  */
1386 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1387 {
1388         struct slgt_info *info = dev_to_port(dev);
1389         struct net_device_stats *stats = hdlc_stats(dev);
1390         unsigned long flags;
1391
1392         DBGINFO(("%s hdlc_xmit\n", dev->name));
1393
1394         /* stop sending until this frame completes */
1395         netif_stop_queue(dev);
1396
1397         /* copy data to device buffers */
1398         info->tx_count = skb->len;
1399         tx_load(info, skb->data, skb->len);
1400
1401         /* update network statistics */
1402         stats->tx_packets++;
1403         stats->tx_bytes += skb->len;
1404
1405         /* done with socket buffer, so free it */
1406         dev_kfree_skb(skb);
1407
1408         /* save start time for transmit timeout detection */
1409         dev->trans_start = jiffies;
1410
1411         /* start hardware transmitter if necessary */
1412         spin_lock_irqsave(&info->lock,flags);
1413         if (!info->tx_active)
1414                 tx_start(info);
1415         spin_unlock_irqrestore(&info->lock,flags);
1416
1417         return 0;
1418 }
1419
1420 /**
1421  * called by network layer when interface enabled
1422  * claim resources and initialize hardware
1423  *
1424  * dev  pointer to network device structure
1425  *
1426  * returns 0 if success, otherwise error code
1427  */
1428 static int hdlcdev_open(struct net_device *dev)
1429 {
1430         struct slgt_info *info = dev_to_port(dev);
1431         int rc;
1432         unsigned long flags;
1433
1434         DBGINFO(("%s hdlcdev_open\n", dev->name));
1435
1436         /* generic HDLC layer open processing */
1437         if ((rc = hdlc_open(dev)))
1438                 return rc;
1439
1440         /* arbitrate between network and tty opens */
1441         spin_lock_irqsave(&info->netlock, flags);
1442         if (info->count != 0 || info->netcount != 0) {
1443                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1444                 spin_unlock_irqrestore(&info->netlock, flags);
1445                 return -EBUSY;
1446         }
1447         info->netcount=1;
1448         spin_unlock_irqrestore(&info->netlock, flags);
1449
1450         /* claim resources and init adapter */
1451         if ((rc = startup(info)) != 0) {
1452                 spin_lock_irqsave(&info->netlock, flags);
1453                 info->netcount=0;
1454                 spin_unlock_irqrestore(&info->netlock, flags);
1455                 return rc;
1456         }
1457
1458         /* assert DTR and RTS, apply hardware settings */
1459         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1460         program_hw(info);
1461
1462         /* enable network layer transmit */
1463         dev->trans_start = jiffies;
1464         netif_start_queue(dev);
1465
1466         /* inform generic HDLC layer of current DCD status */
1467         spin_lock_irqsave(&info->lock, flags);
1468         get_signals(info);
1469         spin_unlock_irqrestore(&info->lock, flags);
1470         hdlc_set_carrier(info->signals & SerialSignal_DCD, dev);
1471
1472         return 0;
1473 }
1474
1475 /**
1476  * called by network layer when interface is disabled
1477  * shutdown hardware and release resources
1478  *
1479  * dev  pointer to network device structure
1480  *
1481  * returns 0 if success, otherwise error code
1482  */
1483 static int hdlcdev_close(struct net_device *dev)
1484 {
1485         struct slgt_info *info = dev_to_port(dev);
1486         unsigned long flags;
1487
1488         DBGINFO(("%s hdlcdev_close\n", dev->name));
1489
1490         netif_stop_queue(dev);
1491
1492         /* shutdown adapter and release resources */
1493         shutdown(info);
1494
1495         hdlc_close(dev);
1496
1497         spin_lock_irqsave(&info->netlock, flags);
1498         info->netcount=0;
1499         spin_unlock_irqrestore(&info->netlock, flags);
1500
1501         return 0;
1502 }
1503
1504 /**
1505  * called by network layer to process IOCTL call to network device
1506  *
1507  * dev  pointer to network device structure
1508  * ifr  pointer to network interface request structure
1509  * cmd  IOCTL command code
1510  *
1511  * returns 0 if success, otherwise error code
1512  */
1513 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1514 {
1515         const size_t size = sizeof(sync_serial_settings);
1516         sync_serial_settings new_line;
1517         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1518         struct slgt_info *info = dev_to_port(dev);
1519         unsigned int flags;
1520
1521         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1522
1523         /* return error if TTY interface open */
1524         if (info->count)
1525                 return -EBUSY;
1526
1527         if (cmd != SIOCWANDEV)
1528                 return hdlc_ioctl(dev, ifr, cmd);
1529
1530         switch(ifr->ifr_settings.type) {
1531         case IF_GET_IFACE: /* return current sync_serial_settings */
1532
1533                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1534                 if (ifr->ifr_settings.size < size) {
1535                         ifr->ifr_settings.size = size; /* data size wanted */
1536                         return -ENOBUFS;
1537                 }
1538
1539                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1540                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1541                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1542                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1543
1544                 switch (flags){
1545                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1546                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1547                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1548                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1549                 default: new_line.clock_type = CLOCK_DEFAULT;
1550                 }
1551
1552                 new_line.clock_rate = info->params.clock_speed;
1553                 new_line.loopback   = info->params.loopback ? 1:0;
1554
1555                 if (copy_to_user(line, &new_line, size))
1556                         return -EFAULT;
1557                 return 0;
1558
1559         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1560
1561                 if(!capable(CAP_NET_ADMIN))
1562                         return -EPERM;
1563                 if (copy_from_user(&new_line, line, size))
1564                         return -EFAULT;
1565
1566                 switch (new_line.clock_type)
1567                 {
1568                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1569                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1570                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1571                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1572                 case CLOCK_DEFAULT:  flags = info->params.flags &
1573                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1574                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1575                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1576                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1577                 default: return -EINVAL;
1578                 }
1579
1580                 if (new_line.loopback != 0 && new_line.loopback != 1)
1581                         return -EINVAL;
1582
1583                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1584                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1585                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1586                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1587                 info->params.flags |= flags;
1588
1589                 info->params.loopback = new_line.loopback;
1590
1591                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1592                         info->params.clock_speed = new_line.clock_rate;
1593                 else
1594                         info->params.clock_speed = 0;
1595
1596                 /* if network interface up, reprogram hardware */
1597                 if (info->netcount)
1598                         program_hw(info);
1599                 return 0;
1600
1601         default:
1602                 return hdlc_ioctl(dev, ifr, cmd);
1603         }
1604 }
1605
1606 /**
1607  * called by network layer when transmit timeout is detected
1608  *
1609  * dev  pointer to network device structure
1610  */
1611 static void hdlcdev_tx_timeout(struct net_device *dev)
1612 {
1613         struct slgt_info *info = dev_to_port(dev);
1614         struct net_device_stats *stats = hdlc_stats(dev);
1615         unsigned long flags;
1616
1617         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1618
1619         stats->tx_errors++;
1620         stats->tx_aborted_errors++;
1621
1622         spin_lock_irqsave(&info->lock,flags);
1623         tx_stop(info);
1624         spin_unlock_irqrestore(&info->lock,flags);
1625
1626         netif_wake_queue(dev);
1627 }
1628
1629 /**
1630  * called by device driver when transmit completes
1631  * reenable network layer transmit if stopped
1632  *
1633  * info  pointer to device instance information
1634  */
1635 static void hdlcdev_tx_done(struct slgt_info *info)
1636 {
1637         if (netif_queue_stopped(info->netdev))
1638                 netif_wake_queue(info->netdev);
1639 }
1640
1641 /**
1642  * called by device driver when frame received
1643  * pass frame to network layer
1644  *
1645  * info  pointer to device instance information
1646  * buf   pointer to buffer contianing frame data
1647  * size  count of data bytes in buf
1648  */
1649 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1650 {
1651         struct sk_buff *skb = dev_alloc_skb(size);
1652         struct net_device *dev = info->netdev;
1653         struct net_device_stats *stats = hdlc_stats(dev);
1654
1655         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1656
1657         if (skb == NULL) {
1658                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1659                 stats->rx_dropped++;
1660                 return;
1661         }
1662
1663         memcpy(skb_put(skb, size),buf,size);
1664
1665         skb->protocol = hdlc_type_trans(skb, info->netdev);
1666
1667         stats->rx_packets++;
1668         stats->rx_bytes += size;
1669
1670         netif_rx(skb);
1671
1672         info->netdev->last_rx = jiffies;
1673 }
1674
1675 /**
1676  * called by device driver when adding device instance
1677  * do generic HDLC initialization
1678  *
1679  * info  pointer to device instance information
1680  *
1681  * returns 0 if success, otherwise error code
1682  */
1683 static int hdlcdev_init(struct slgt_info *info)
1684 {
1685         int rc;
1686         struct net_device *dev;
1687         hdlc_device *hdlc;
1688
1689         /* allocate and initialize network and HDLC layer objects */
1690
1691         if (!(dev = alloc_hdlcdev(info))) {
1692                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1693                 return -ENOMEM;
1694         }
1695
1696         /* for network layer reporting purposes only */
1697         dev->mem_start = info->phys_reg_addr;
1698         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1699         dev->irq       = info->irq_level;
1700
1701         /* network layer callbacks and settings */
1702         dev->do_ioctl       = hdlcdev_ioctl;
1703         dev->open           = hdlcdev_open;
1704         dev->stop           = hdlcdev_close;
1705         dev->tx_timeout     = hdlcdev_tx_timeout;
1706         dev->watchdog_timeo = 10*HZ;
1707         dev->tx_queue_len   = 50;
1708
1709         /* generic HDLC layer callbacks and settings */
1710         hdlc         = dev_to_hdlc(dev);
1711         hdlc->attach = hdlcdev_attach;
1712         hdlc->xmit   = hdlcdev_xmit;
1713
1714         /* register objects with HDLC layer */
1715         if ((rc = register_hdlc_device(dev))) {
1716                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1717                 free_netdev(dev);
1718                 return rc;
1719         }
1720
1721         info->netdev = dev;
1722         return 0;
1723 }
1724
1725 /**
1726  * called by device driver when removing device instance
1727  * do generic HDLC cleanup
1728  *
1729  * info  pointer to device instance information
1730  */
1731 static void hdlcdev_exit(struct slgt_info *info)
1732 {
1733         unregister_hdlc_device(info->netdev);
1734         free_netdev(info->netdev);
1735         info->netdev = NULL;
1736 }
1737
1738 #endif /* ifdef CONFIG_HDLC */
1739
1740 /*
1741  * get async data from rx DMA buffers
1742  */
1743 static void rx_async(struct slgt_info *info)
1744 {
1745         struct tty_struct *tty = info->tty;
1746         struct mgsl_icount *icount = &info->icount;
1747         unsigned int start, end;
1748         unsigned char *p;
1749         unsigned char status;
1750         struct slgt_desc *bufs = info->rbufs;
1751         int i, count;
1752         int chars = 0;
1753         int stat;
1754         unsigned char ch;
1755
1756         start = end = info->rbuf_current;
1757
1758         while(desc_complete(bufs[end])) {
1759                 count = desc_count(bufs[end]) - info->rbuf_index;
1760                 p     = bufs[end].buf + info->rbuf_index;
1761
1762                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1763                 DBGDATA(info, p, count, "rx");
1764
1765                 for(i=0 ; i < count; i+=2, p+=2) {
1766                         if (tty && chars) {
1767                                 tty_flip_buffer_push(tty);
1768                                 chars = 0;
1769                         }
1770                         ch = *p;
1771                         icount->rx++;
1772
1773                         stat = 0;
1774
1775                         if ((status = *(p+1) & (BIT9 + BIT8))) {
1776                                 if (status & BIT9)
1777                                         icount->parity++;
1778                                 else if (status & BIT8)
1779                                         icount->frame++;
1780                                 /* discard char if tty control flags say so */
1781                                 if (status & info->ignore_status_mask)
1782                                         continue;
1783                                 if (status & BIT9)
1784                                         stat = TTY_PARITY;
1785                                 else if (status & BIT8)
1786                                         stat = TTY_FRAME;
1787                         }
1788                         if (tty) {
1789                                 tty_insert_flip_char(tty, ch, stat);
1790                                 chars++;
1791                         }
1792                 }
1793
1794                 if (i < count) {
1795                         /* receive buffer not completed */
1796                         info->rbuf_index += i;
1797                         info->rx_timer.expires = jiffies + 1;
1798                         add_timer(&info->rx_timer);
1799                         break;
1800                 }
1801
1802                 info->rbuf_index = 0;
1803                 free_rbufs(info, end, end);
1804
1805                 if (++end == info->rbuf_count)
1806                         end = 0;
1807
1808                 /* if entire list searched then no frame available */
1809                 if (end == start)
1810                         break;
1811         }
1812
1813         if (tty && chars)
1814                 tty_flip_buffer_push(tty);
1815 }
1816
1817 /*
1818  * return next bottom half action to perform
1819  */
1820 static int bh_action(struct slgt_info *info)
1821 {
1822         unsigned long flags;
1823         int rc;
1824
1825         spin_lock_irqsave(&info->lock,flags);
1826
1827         if (info->pending_bh & BH_RECEIVE) {
1828                 info->pending_bh &= ~BH_RECEIVE;
1829                 rc = BH_RECEIVE;
1830         } else if (info->pending_bh & BH_TRANSMIT) {
1831                 info->pending_bh &= ~BH_TRANSMIT;
1832                 rc = BH_TRANSMIT;
1833         } else if (info->pending_bh & BH_STATUS) {
1834                 info->pending_bh &= ~BH_STATUS;
1835                 rc = BH_STATUS;
1836         } else {
1837                 /* Mark BH routine as complete */
1838                 info->bh_running   = 0;
1839                 info->bh_requested = 0;
1840                 rc = 0;
1841         }
1842
1843         spin_unlock_irqrestore(&info->lock,flags);
1844
1845         return rc;
1846 }
1847
1848 /*
1849  * perform bottom half processing
1850  */
1851 static void bh_handler(void* context)
1852 {
1853         struct slgt_info *info = context;
1854         int action;
1855
1856         if (!info)
1857                 return;
1858         info->bh_running = 1;
1859
1860         while((action = bh_action(info))) {
1861                 switch (action) {
1862                 case BH_RECEIVE:
1863                         DBGBH(("%s bh receive\n", info->device_name));
1864                         switch(info->params.mode) {
1865                         case MGSL_MODE_ASYNC:
1866                                 rx_async(info);
1867                                 break;
1868                         case MGSL_MODE_HDLC:
1869                                 while(rx_get_frame(info));
1870                                 break;
1871                         case MGSL_MODE_RAW:
1872                                 while(rx_get_buf(info));
1873                                 break;
1874                         }
1875                         /* restart receiver if rx DMA buffers exhausted */
1876                         if (info->rx_restart)
1877                                 rx_start(info);
1878                         break;
1879                 case BH_TRANSMIT:
1880                         bh_transmit(info);
1881                         break;
1882                 case BH_STATUS:
1883                         DBGBH(("%s bh status\n", info->device_name));
1884                         info->ri_chkcount = 0;
1885                         info->dsr_chkcount = 0;
1886                         info->dcd_chkcount = 0;
1887                         info->cts_chkcount = 0;
1888                         break;
1889                 default:
1890                         DBGBH(("%s unknown action\n", info->device_name));
1891                         break;
1892                 }
1893         }
1894         DBGBH(("%s bh_handler exit\n", info->device_name));
1895 }
1896
1897 static void bh_transmit(struct slgt_info *info)
1898 {
1899         struct tty_struct *tty = info->tty;
1900
1901         DBGBH(("%s bh_transmit\n", info->device_name));
1902         if (tty) {
1903                 tty_wakeup(tty);
1904                 wake_up_interruptible(&tty->write_wait);
1905         }
1906 }
1907
1908 static void dsr_change(struct slgt_info *info)
1909 {
1910         get_signals(info);
1911         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1912         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1913                 slgt_irq_off(info, IRQ_DSR);
1914                 return;
1915         }
1916         info->icount.dsr++;
1917         if (info->signals & SerialSignal_DSR)
1918                 info->input_signal_events.dsr_up++;
1919         else
1920                 info->input_signal_events.dsr_down++;
1921         wake_up_interruptible(&info->status_event_wait_q);
1922         wake_up_interruptible(&info->event_wait_q);
1923         info->pending_bh |= BH_STATUS;
1924 }
1925
1926 static void cts_change(struct slgt_info *info)
1927 {
1928         get_signals(info);
1929         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1930         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1931                 slgt_irq_off(info, IRQ_CTS);
1932                 return;
1933         }
1934         info->icount.cts++;
1935         if (info->signals & SerialSignal_CTS)
1936                 info->input_signal_events.cts_up++;
1937         else
1938                 info->input_signal_events.cts_down++;
1939         wake_up_interruptible(&info->status_event_wait_q);
1940         wake_up_interruptible(&info->event_wait_q);
1941         info->pending_bh |= BH_STATUS;
1942
1943         if (info->flags & ASYNC_CTS_FLOW) {
1944                 if (info->tty) {
1945                         if (info->tty->hw_stopped) {
1946                                 if (info->signals & SerialSignal_CTS) {
1947                                         info->tty->hw_stopped = 0;
1948                                         info->pending_bh |= BH_TRANSMIT;
1949                                         return;
1950                                 }
1951                         } else {
1952                                 if (!(info->signals & SerialSignal_CTS))
1953                                         info->tty->hw_stopped = 1;
1954                         }
1955                 }
1956         }
1957 }
1958
1959 static void dcd_change(struct slgt_info *info)
1960 {
1961         get_signals(info);
1962         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1963         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1964                 slgt_irq_off(info, IRQ_DCD);
1965                 return;
1966         }
1967         info->icount.dcd++;
1968         if (info->signals & SerialSignal_DCD) {
1969                 info->input_signal_events.dcd_up++;
1970         } else {
1971                 info->input_signal_events.dcd_down++;
1972         }
1973 #ifdef CONFIG_HDLC
1974         if (info->netcount)
1975                 hdlc_set_carrier(info->signals & SerialSignal_DCD, info->netdev);
1976 #endif
1977         wake_up_interruptible(&info->status_event_wait_q);
1978         wake_up_interruptible(&info->event_wait_q);
1979         info->pending_bh |= BH_STATUS;
1980
1981         if (info->flags & ASYNC_CHECK_CD) {
1982                 if (info->signals & SerialSignal_DCD)
1983                         wake_up_interruptible(&info->open_wait);
1984                 else {
1985                         if (info->tty)
1986                                 tty_hangup(info->tty);
1987                 }
1988         }
1989 }
1990
1991 static void ri_change(struct slgt_info *info)
1992 {
1993         get_signals(info);
1994         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
1995         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1996                 slgt_irq_off(info, IRQ_RI);
1997                 return;
1998         }
1999         info->icount.dcd++;
2000         if (info->signals & SerialSignal_RI) {
2001                 info->input_signal_events.ri_up++;
2002         } else {
2003                 info->input_signal_events.ri_down++;
2004         }
2005         wake_up_interruptible(&info->status_event_wait_q);
2006         wake_up_interruptible(&info->event_wait_q);
2007         info->pending_bh |= BH_STATUS;
2008 }
2009
2010 static void isr_serial(struct slgt_info *info)
2011 {
2012         unsigned short status = rd_reg16(info, SSR);
2013
2014         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2015
2016         wr_reg16(info, SSR, status); /* clear pending */
2017
2018         info->irq_occurred = 1;
2019
2020         if (info->params.mode == MGSL_MODE_ASYNC) {
2021                 if (status & IRQ_TXIDLE) {
2022                         if (info->tx_count)
2023                                 isr_txeom(info, status);
2024                 }
2025                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2026                         info->icount.brk++;
2027                         /* process break detection if tty control allows */
2028                         if (info->tty) {
2029                                 if (!(status & info->ignore_status_mask)) {
2030                                         if (info->read_status_mask & MASK_BREAK) {
2031                                                 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2032                                                 if (info->flags & ASYNC_SAK)
2033                                                         do_SAK(info->tty);
2034                                         }
2035                                 }
2036                         }
2037                 }
2038         } else {
2039                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2040                         isr_txeom(info, status);
2041
2042                 if (status & IRQ_RXIDLE) {
2043                         if (status & RXIDLE)
2044                                 info->icount.rxidle++;
2045                         else
2046                                 info->icount.exithunt++;
2047                         wake_up_interruptible(&info->event_wait_q);
2048                 }
2049
2050                 if (status & IRQ_RXOVER)
2051                         rx_start(info);
2052         }
2053
2054         if (status & IRQ_DSR)
2055                 dsr_change(info);
2056         if (status & IRQ_CTS)
2057                 cts_change(info);
2058         if (status & IRQ_DCD)
2059                 dcd_change(info);
2060         if (status & IRQ_RI)
2061                 ri_change(info);
2062 }
2063
2064 static void isr_rdma(struct slgt_info *info)
2065 {
2066         unsigned int status = rd_reg32(info, RDCSR);
2067
2068         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2069
2070         /* RDCSR (rx DMA control/status)
2071          *
2072          * 31..07  reserved
2073          * 06      save status byte to DMA buffer
2074          * 05      error
2075          * 04      eol (end of list)
2076          * 03      eob (end of buffer)
2077          * 02      IRQ enable
2078          * 01      reset
2079          * 00      enable
2080          */
2081         wr_reg32(info, RDCSR, status);  /* clear pending */
2082
2083         if (status & (BIT5 + BIT4)) {
2084                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2085                 info->rx_restart = 1;
2086         }
2087         info->pending_bh |= BH_RECEIVE;
2088 }
2089
2090 static void isr_tdma(struct slgt_info *info)
2091 {
2092         unsigned int status = rd_reg32(info, TDCSR);
2093
2094         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2095
2096         /* TDCSR (tx DMA control/status)
2097          *
2098          * 31..06  reserved
2099          * 05      error
2100          * 04      eol (end of list)
2101          * 03      eob (end of buffer)
2102          * 02      IRQ enable
2103          * 01      reset
2104          * 00      enable
2105          */
2106         wr_reg32(info, TDCSR, status);  /* clear pending */
2107
2108         if (status & (BIT5 + BIT4 + BIT3)) {
2109                 // another transmit buffer has completed
2110                 // run bottom half to get more send data from user
2111                 info->pending_bh |= BH_TRANSMIT;
2112         }
2113 }
2114
2115 static void isr_txeom(struct slgt_info *info, unsigned short status)
2116 {
2117         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2118
2119         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2120         tdma_reset(info);
2121         reset_tbufs(info);
2122         if (status & IRQ_TXUNDER) {
2123                 unsigned short val = rd_reg16(info, TCR);
2124                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2125                 wr_reg16(info, TCR, val); /* clear reset bit */
2126         }
2127
2128         if (info->tx_active) {
2129                 if (info->params.mode != MGSL_MODE_ASYNC) {
2130                         if (status & IRQ_TXUNDER)
2131                                 info->icount.txunder++;
2132                         else if (status & IRQ_TXIDLE)
2133                                 info->icount.txok++;
2134                 }
2135
2136                 info->tx_active = 0;
2137                 info->tx_count = 0;
2138
2139                 del_timer(&info->tx_timer);
2140
2141                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2142                         info->signals &= ~SerialSignal_RTS;
2143                         info->drop_rts_on_tx_done = 0;
2144                         set_signals(info);
2145                 }
2146
2147 #ifdef CONFIG_HDLC
2148                 if (info->netcount)
2149                         hdlcdev_tx_done(info);
2150                 else
2151 #endif
2152                 {
2153                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2154                                 tx_stop(info);
2155                                 return;
2156                         }
2157                         info->pending_bh |= BH_TRANSMIT;
2158                 }
2159         }
2160 }
2161
2162 /* interrupt service routine
2163  *
2164  *      irq     interrupt number
2165  *      dev_id  device ID supplied during interrupt registration
2166  *      regs    interrupted processor context
2167  */
2168 static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2169 {
2170         struct slgt_info *info;
2171         unsigned int gsr;
2172         unsigned int i;
2173
2174         DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2175
2176         info = dev_id;
2177         if (!info)
2178                 return IRQ_NONE;
2179
2180         spin_lock(&info->lock);
2181
2182         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2183                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2184                 info->irq_occurred = 1;
2185                 for(i=0; i < info->port_count ; i++) {
2186                         if (info->port_array[i] == NULL)
2187                                 continue;
2188                         if (gsr & (BIT8 << i))
2189                                 isr_serial(info->port_array[i]);
2190                         if (gsr & (BIT16 << (i*2)))
2191                                 isr_rdma(info->port_array[i]);
2192                         if (gsr & (BIT17 << (i*2)))
2193                                 isr_tdma(info->port_array[i]);
2194                 }
2195         }
2196
2197         for(i=0; i < info->port_count ; i++) {
2198                 struct slgt_info *port = info->port_array[i];
2199
2200                 if (port && (port->count || port->netcount) &&
2201                     port->pending_bh && !port->bh_running &&
2202                     !port->bh_requested) {
2203                         DBGISR(("%s bh queued\n", port->device_name));
2204                         schedule_work(&port->task);
2205                         port->bh_requested = 1;
2206                 }
2207         }
2208
2209         spin_unlock(&info->lock);
2210
2211         DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2212         return IRQ_HANDLED;
2213 }
2214
2215 static int startup(struct slgt_info *info)
2216 {
2217         DBGINFO(("%s startup\n", info->device_name));
2218
2219         if (info->flags & ASYNC_INITIALIZED)
2220                 return 0;
2221
2222         if (!info->tx_buf) {
2223                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2224                 if (!info->tx_buf) {
2225                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2226                         return -ENOMEM;
2227                 }
2228         }
2229
2230         info->pending_bh = 0;
2231
2232         memset(&info->icount, 0, sizeof(info->icount));
2233
2234         /* program hardware for current parameters */
2235         change_params(info);
2236
2237         if (info->tty)
2238                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2239
2240         info->flags |= ASYNC_INITIALIZED;
2241
2242         return 0;
2243 }
2244
2245 /*
2246  *  called by close() and hangup() to shutdown hardware
2247  */
2248 static void shutdown(struct slgt_info *info)
2249 {
2250         unsigned long flags;
2251
2252         if (!(info->flags & ASYNC_INITIALIZED))
2253                 return;
2254
2255         DBGINFO(("%s shutdown\n", info->device_name));
2256
2257         /* clear status wait queue because status changes */
2258         /* can't happen after shutting down the hardware */
2259         wake_up_interruptible(&info->status_event_wait_q);
2260         wake_up_interruptible(&info->event_wait_q);
2261
2262         del_timer_sync(&info->tx_timer);
2263         del_timer_sync(&info->rx_timer);
2264
2265         kfree(info->tx_buf);
2266         info->tx_buf = NULL;
2267
2268         spin_lock_irqsave(&info->lock,flags);
2269
2270         tx_stop(info);
2271         rx_stop(info);
2272
2273         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2274
2275         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2276                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2277                 set_signals(info);
2278         }
2279
2280         spin_unlock_irqrestore(&info->lock,flags);
2281
2282         if (info->tty)
2283                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2284
2285         info->flags &= ~ASYNC_INITIALIZED;
2286 }
2287
2288 static void program_hw(struct slgt_info *info)
2289 {
2290         unsigned long flags;
2291
2292         spin_lock_irqsave(&info->lock,flags);
2293
2294         rx_stop(info);
2295         tx_stop(info);
2296
2297         if (info->params.mode == MGSL_MODE_HDLC ||
2298             info->params.mode == MGSL_MODE_RAW ||
2299             info->netcount)
2300                 hdlc_mode(info);
2301         else
2302                 async_mode(info);
2303
2304         set_signals(info);
2305
2306         info->dcd_chkcount = 0;
2307         info->cts_chkcount = 0;
2308         info->ri_chkcount = 0;
2309         info->dsr_chkcount = 0;
2310
2311         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2312         get_signals(info);
2313
2314         if (info->netcount ||
2315             (info->tty && info->tty->termios->c_cflag & CREAD))
2316                 rx_start(info);
2317
2318         spin_unlock_irqrestore(&info->lock,flags);
2319 }
2320
2321 /*
2322  * reconfigure adapter based on new parameters
2323  */
2324 static void change_params(struct slgt_info *info)
2325 {
2326         unsigned cflag;
2327         int bits_per_char;
2328
2329         if (!info->tty || !info->tty->termios)
2330                 return;
2331         DBGINFO(("%s change_params\n", info->device_name));
2332
2333         cflag = info->tty->termios->c_cflag;
2334
2335         /* if B0 rate (hangup) specified then negate DTR and RTS */
2336         /* otherwise assert DTR and RTS */
2337         if (cflag & CBAUD)
2338                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2339         else
2340                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2341
2342         /* byte size and parity */
2343
2344         switch (cflag & CSIZE) {
2345         case CS5: info->params.data_bits = 5; break;
2346         case CS6: info->params.data_bits = 6; break;
2347         case CS7: info->params.data_bits = 7; break;
2348         case CS8: info->params.data_bits = 8; break;
2349         default:  info->params.data_bits = 7; break;
2350         }
2351
2352         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2353
2354         if (cflag & PARENB)
2355                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2356         else
2357                 info->params.parity = ASYNC_PARITY_NONE;
2358
2359         /* calculate number of jiffies to transmit a full
2360          * FIFO (32 bytes) at specified data rate
2361          */
2362         bits_per_char = info->params.data_bits +
2363                         info->params.stop_bits + 1;
2364
2365         info->params.data_rate = tty_get_baud_rate(info->tty);
2366
2367         if (info->params.data_rate) {
2368                 info->timeout = (32*HZ*bits_per_char) /
2369                                 info->params.data_rate;
2370         }
2371         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2372
2373         if (cflag & CRTSCTS)
2374                 info->flags |= ASYNC_CTS_FLOW;
2375         else
2376                 info->flags &= ~ASYNC_CTS_FLOW;
2377
2378         if (cflag & CLOCAL)
2379                 info->flags &= ~ASYNC_CHECK_CD;
2380         else
2381                 info->flags |= ASYNC_CHECK_CD;
2382
2383         /* process tty input control flags */
2384
2385         info->read_status_mask = IRQ_RXOVER;
2386         if (I_INPCK(info->tty))
2387                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2388         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2389                 info->read_status_mask |= MASK_BREAK;
2390         if (I_IGNPAR(info->tty))
2391                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2392         if (I_IGNBRK(info->tty)) {
2393                 info->ignore_status_mask |= MASK_BREAK;
2394                 /* If ignoring parity and break indicators, ignore
2395                  * overruns too.  (For real raw support).
2396                  */
2397                 if (I_IGNPAR(info->tty))
2398                         info->ignore_status_mask |= MASK_OVERRUN;
2399         }
2400
2401         program_hw(info);
2402 }
2403
2404 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2405 {
2406         DBGINFO(("%s get_stats\n",  info->device_name));
2407         if (!user_icount) {
2408                 memset(&info->icount, 0, sizeof(info->icount));
2409         } else {
2410                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2411                         return -EFAULT;
2412         }
2413         return 0;
2414 }
2415
2416 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2417 {
2418         DBGINFO(("%s get_params\n", info->device_name));
2419         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2420                 return -EFAULT;
2421         return 0;
2422 }
2423
2424 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2425 {
2426         unsigned long flags;
2427         MGSL_PARAMS tmp_params;
2428
2429         DBGINFO(("%s set_params\n", info->device_name));
2430         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2431                 return -EFAULT;
2432
2433         spin_lock_irqsave(&info->lock, flags);
2434         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2435         spin_unlock_irqrestore(&info->lock, flags);
2436
2437         change_params(info);
2438
2439         return 0;
2440 }
2441
2442 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2443 {
2444         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2445         if (put_user(info->idle_mode, idle_mode))
2446                 return -EFAULT;
2447         return 0;
2448 }
2449
2450 static int set_txidle(struct slgt_info *info, int idle_mode)
2451 {
2452         unsigned long flags;
2453         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2454         spin_lock_irqsave(&info->lock,flags);
2455         info->idle_mode = idle_mode;
2456         tx_set_idle(info);
2457         spin_unlock_irqrestore(&info->lock,flags);
2458         return 0;
2459 }
2460
2461 static int tx_enable(struct slgt_info *info, int enable)
2462 {
2463         unsigned long flags;
2464         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2465         spin_lock_irqsave(&info->lock,flags);
2466         if (enable) {
2467                 if (!info->tx_enabled)
2468                         tx_start(info);
2469         } else {
2470                 if (info->tx_enabled)
2471                         tx_stop(info);
2472         }
2473         spin_unlock_irqrestore(&info->lock,flags);
2474         return 0;
2475 }
2476
2477 /*
2478  * abort transmit HDLC frame
2479  */
2480 static int tx_abort(struct slgt_info *info)
2481 {
2482         unsigned long flags;
2483         DBGINFO(("%s tx_abort\n", info->device_name));
2484         spin_lock_irqsave(&info->lock,flags);
2485         tdma_reset(info);
2486         spin_unlock_irqrestore(&info->lock,flags);
2487         return 0;
2488 }
2489
2490 static int rx_enable(struct slgt_info *info, int enable)
2491 {
2492         unsigned long flags;
2493         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2494         spin_lock_irqsave(&info->lock,flags);
2495         if (enable) {
2496                 if (!info->rx_enabled)
2497                         rx_start(info);
2498         } else {
2499                 if (info->rx_enabled)
2500                         rx_stop(info);
2501         }
2502         spin_unlock_irqrestore(&info->lock,flags);
2503         return 0;
2504 }
2505
2506 /*
2507  *  wait for specified event to occur
2508  */
2509 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2510 {
2511         unsigned long flags;
2512         int s;
2513         int rc=0;
2514         struct mgsl_icount cprev, cnow;
2515         int events;
2516         int mask;
2517         struct  _input_signal_events oldsigs, newsigs;
2518         DECLARE_WAITQUEUE(wait, current);
2519
2520         if (get_user(mask, mask_ptr))
2521                 return -EFAULT;
2522
2523         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2524
2525         spin_lock_irqsave(&info->lock,flags);
2526
2527         /* return immediately if state matches requested events */
2528         get_signals(info);
2529         s = info->signals;
2530
2531         events = mask &
2532                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2533                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2534                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2535                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2536         if (events) {
2537                 spin_unlock_irqrestore(&info->lock,flags);
2538                 goto exit;
2539         }
2540
2541         /* save current irq counts */
2542         cprev = info->icount;
2543         oldsigs = info->input_signal_events;
2544
2545         /* enable hunt and idle irqs if needed */
2546         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2547                 unsigned short val = rd_reg16(info, SCR);
2548                 if (!(val & IRQ_RXIDLE))
2549                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2550         }
2551
2552         set_current_state(TASK_INTERRUPTIBLE);
2553         add_wait_queue(&info->event_wait_q, &wait);
2554
2555         spin_unlock_irqrestore(&info->lock,flags);
2556
2557         for(;;) {
2558                 schedule();
2559                 if (signal_pending(current)) {
2560                         rc = -ERESTARTSYS;
2561                         break;
2562                 }
2563
2564                 /* get current irq counts */
2565                 spin_lock_irqsave(&info->lock,flags);
2566                 cnow = info->icount;
2567                 newsigs = info->input_signal_events;
2568                 set_current_state(TASK_INTERRUPTIBLE);
2569                 spin_unlock_irqrestore(&info->lock,flags);
2570
2571                 /* if no change, wait aborted for some reason */
2572                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2573                     newsigs.dsr_down == oldsigs.dsr_down &&
2574                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2575                     newsigs.dcd_down == oldsigs.dcd_down &&
2576                     newsigs.cts_up   == oldsigs.cts_up   &&
2577                     newsigs.cts_down == oldsigs.cts_down &&
2578                     newsigs.ri_up    == oldsigs.ri_up    &&
2579                     newsigs.ri_down  == oldsigs.ri_down  &&
2580                     cnow.exithunt    == cprev.exithunt   &&
2581                     cnow.rxidle      == cprev.rxidle) {
2582                         rc = -EIO;
2583                         break;
2584                 }
2585
2586                 events = mask &
2587                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2588                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2589                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2590                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2591                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2592                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2593                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2594                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2595                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2596                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2597                 if (events)
2598                         break;
2599
2600                 cprev = cnow;
2601                 oldsigs = newsigs;
2602         }
2603
2604         remove_wait_queue(&info->event_wait_q, &wait);
2605         set_current_state(TASK_RUNNING);
2606
2607
2608         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2609                 spin_lock_irqsave(&info->lock,flags);
2610                 if (!waitqueue_active(&info->event_wait_q)) {
2611                         /* disable enable exit hunt mode/idle rcvd IRQs */
2612                         wr_reg16(info, SCR,
2613                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2614                 }
2615                 spin_unlock_irqrestore(&info->lock,flags);
2616         }
2617 exit:
2618         if (rc == 0)
2619                 rc = put_user(events, mask_ptr);
2620         return rc;
2621 }
2622
2623 static int get_interface(struct slgt_info *info, int __user *if_mode)
2624 {
2625         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2626         if (put_user(info->if_mode, if_mode))
2627                 return -EFAULT;
2628         return 0;
2629 }
2630
2631 static int set_interface(struct slgt_info *info, int if_mode)
2632 {
2633         unsigned long flags;
2634         unsigned char val;
2635
2636         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2637         spin_lock_irqsave(&info->lock,flags);
2638         info->if_mode = if_mode;
2639
2640         msc_set_vcr(info);
2641
2642         /* TCR (tx control) 07  1=RTS driver control */
2643         val = rd_reg16(info, TCR);
2644         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2645                 val |= BIT7;
2646         else
2647                 val &= ~BIT7;
2648         wr_reg16(info, TCR, val);
2649
2650         spin_unlock_irqrestore(&info->lock,flags);
2651         return 0;
2652 }
2653
2654 static int modem_input_wait(struct slgt_info *info,int arg)
2655 {
2656         unsigned long flags;
2657         int rc;
2658         struct mgsl_icount cprev, cnow;
2659         DECLARE_WAITQUEUE(wait, current);
2660
2661         /* save current irq counts */
2662         spin_lock_irqsave(&info->lock,flags);
2663         cprev = info->icount;
2664         add_wait_queue(&info->status_event_wait_q, &wait);
2665         set_current_state(TASK_INTERRUPTIBLE);
2666         spin_unlock_irqrestore(&info->lock,flags);
2667
2668         for(;;) {
2669                 schedule();
2670                 if (signal_pending(current)) {
2671                         rc = -ERESTARTSYS;
2672                         break;
2673                 }
2674
2675                 /* get new irq counts */
2676                 spin_lock_irqsave(&info->lock,flags);
2677                 cnow = info->icount;
2678                 set_current_state(TASK_INTERRUPTIBLE);
2679                 spin_unlock_irqrestore(&info->lock,flags);
2680
2681                 /* if no change, wait aborted for some reason */
2682                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2683                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2684                         rc = -EIO;
2685                         break;
2686                 }
2687
2688                 /* check for change in caller specified modem input */
2689                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2690                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2691                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
2692                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2693                         rc = 0;
2694                         break;
2695                 }
2696
2697                 cprev = cnow;
2698         }
2699         remove_wait_queue(&info->status_event_wait_q, &wait);
2700         set_current_state(TASK_RUNNING);
2701         return rc;
2702 }
2703
2704 /*
2705  *  return state of serial control and status signals
2706  */
2707 static int tiocmget(struct tty_struct *tty, struct file *file)
2708 {
2709         struct slgt_info *info = tty->driver_data;
2710         unsigned int result;
2711         unsigned long flags;
2712
2713         spin_lock_irqsave(&info->lock,flags);
2714         get_signals(info);
2715         spin_unlock_irqrestore(&info->lock,flags);
2716
2717         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2718                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2719                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2720                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
2721                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2722                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2723
2724         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
2725         return result;
2726 }
2727
2728 /*
2729  * set modem control signals (DTR/RTS)
2730  *
2731  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2732  *              TIOCMSET = set/clear signal values
2733  *      value   bit mask for command
2734  */
2735 static int tiocmset(struct tty_struct *tty, struct file *file,
2736                     unsigned int set, unsigned int clear)
2737 {
2738         struct slgt_info *info = tty->driver_data;
2739         unsigned long flags;
2740
2741         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
2742
2743         if (set & TIOCM_RTS)
2744                 info->signals |= SerialSignal_RTS;
2745         if (set & TIOCM_DTR)
2746                 info->signals |= SerialSignal_DTR;
2747         if (clear & TIOCM_RTS)
2748                 info->signals &= ~SerialSignal_RTS;
2749         if (clear & TIOCM_DTR)
2750                 info->signals &= ~SerialSignal_DTR;
2751
2752         spin_lock_irqsave(&info->lock,flags);
2753         set_signals(info);
2754         spin_unlock_irqrestore(&info->lock,flags);
2755         return 0;
2756 }
2757
2758 /*
2759  *  block current process until the device is ready to open
2760  */
2761 static int block_til_ready(struct tty_struct *tty, struct file *filp,
2762                            struct slgt_info *info)
2763 {
2764         DECLARE_WAITQUEUE(wait, current);
2765         int             retval;
2766         int             do_clocal = 0, extra_count = 0;
2767         unsigned long   flags;
2768
2769         DBGINFO(("%s block_til_ready\n", tty->driver->name));
2770
2771         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
2772                 /* nonblock mode is set or port is not enabled */
2773                 info->flags |= ASYNC_NORMAL_ACTIVE;
2774                 return 0;
2775         }
2776
2777         if (tty->termios->c_cflag & CLOCAL)
2778                 do_clocal = 1;
2779
2780         /* Wait for carrier detect and the line to become
2781          * free (i.e., not in use by the callout).  While we are in
2782          * this loop, info->count is dropped by one, so that
2783          * close() knows when to free things.  We restore it upon
2784          * exit, either normal or abnormal.
2785          */
2786
2787         retval = 0;
2788         add_wait_queue(&info->open_wait, &wait);
2789
2790         spin_lock_irqsave(&info->lock, flags);
2791         if (!tty_hung_up_p(filp)) {
2792                 extra_count = 1;
2793                 info->count--;
2794         }
2795         spin_unlock_irqrestore(&info->lock, flags);
2796         info->blocked_open++;
2797
2798         while (1) {
2799                 if ((tty->termios->c_cflag & CBAUD)) {
2800                         spin_lock_irqsave(&info->lock,flags);
2801                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2802                         set_signals(info);
2803                         spin_unlock_irqrestore(&info->lock,flags);
2804                 }
2805
2806                 set_current_state(TASK_INTERRUPTIBLE);
2807
2808                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
2809                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
2810                                         -EAGAIN : -ERESTARTSYS;
2811                         break;
2812                 }
2813
2814                 spin_lock_irqsave(&info->lock,flags);
2815                 get_signals(info);
2816                 spin_unlock_irqrestore(&info->lock,flags);
2817
2818                 if (!(info->flags & ASYNC_CLOSING) &&
2819                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
2820                         break;
2821                 }
2822
2823                 if (signal_pending(current)) {
2824                         retval = -ERESTARTSYS;
2825                         break;
2826                 }
2827
2828                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
2829                 schedule();
2830         }
2831
2832         set_current_state(TASK_RUNNING);
2833         remove_wait_queue(&info->open_wait, &wait);
2834
2835         if (extra_count)
2836                 info->count++;
2837         info->blocked_open--;
2838
2839         if (!retval)
2840                 info->flags |= ASYNC_NORMAL_ACTIVE;
2841
2842         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
2843         return retval;
2844 }
2845
2846 static int alloc_tmp_rbuf(struct slgt_info *info)
2847 {
2848         info->tmp_rbuf = kmalloc(info->max_frame_size, GFP_KERNEL);
2849         if (info->tmp_rbuf == NULL)
2850                 return -ENOMEM;
2851         return 0;
2852 }
2853
2854 static void free_tmp_rbuf(struct slgt_info *info)
2855 {
2856         kfree(info->tmp_rbuf);
2857         info->tmp_rbuf = NULL;
2858 }
2859
2860 /*
2861  * allocate DMA descriptor lists.
2862  */
2863 static int alloc_desc(struct slgt_info *info)
2864 {
2865         unsigned int i;
2866         unsigned int pbufs;
2867
2868         /* allocate memory to hold descriptor lists */
2869         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
2870         if (info->bufs == NULL)
2871                 return -ENOMEM;
2872
2873         memset(info->bufs, 0, DESC_LIST_SIZE);
2874
2875         info->rbufs = (struct slgt_desc*)info->bufs;
2876         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
2877
2878         pbufs = (unsigned int)info->bufs_dma_addr;
2879
2880         /*
2881          * Build circular lists of descriptors
2882          */
2883
2884         for (i=0; i < info->rbuf_count; i++) {
2885                 /* physical address of this descriptor */
2886                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
2887
2888                 /* physical address of next descriptor */
2889                 if (i == info->rbuf_count - 1)
2890                         info->rbufs[i].next = cpu_to_le32(pbufs);
2891                 else
2892                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
2893                 set_desc_count(info->rbufs[i], DMABUFSIZE);
2894         }
2895
2896         for (i=0; i < info->tbuf_count; i++) {
2897                 /* physical address of this descriptor */
2898                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
2899
2900                 /* physical address of next descriptor */
2901                 if (i == info->tbuf_count - 1)
2902                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
2903                 else
2904                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
2905         }
2906
2907         return 0;
2908 }
2909
2910 static void free_desc(struct slgt_info *info)
2911 {
2912         if (info->bufs != NULL) {
2913                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
2914                 info->bufs  = NULL;
2915                 info->rbufs = NULL;
2916                 info->tbufs = NULL;
2917         }
2918 }
2919
2920 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
2921 {
2922         int i;
2923         for (i=0; i < count; i++) {
2924                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
2925                         return -ENOMEM;
2926                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
2927         }
2928         return 0;
2929 }
2930
2931 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
2932 {
2933         int i;
2934         for (i=0; i < count; i++) {
2935                 if (bufs[i].buf == NULL)
2936                         continue;
2937                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
2938                 bufs[i].buf = NULL;
2939         }
2940 }
2941
2942 static int alloc_dma_bufs(struct slgt_info *info)
2943 {
2944         info->rbuf_count = 32;
2945         info->tbuf_count = 32;
2946
2947         if (alloc_desc(info) < 0 ||
2948             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
2949             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
2950             alloc_tmp_rbuf(info) < 0) {
2951                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
2952                 return -ENOMEM;
2953         }
2954         reset_rbufs(info);
2955         return 0;
2956 }
2957
2958 static void free_dma_bufs(struct slgt_info *info)
2959 {
2960         if (info->bufs) {
2961                 free_bufs(info, info->rbufs, info->rbuf_count);
2962                 free_bufs(info, info->tbufs, info->tbuf_count);
2963                 free_desc(info);
2964         }
2965         free_tmp_rbuf(info);
2966 }
2967
2968 static int claim_resources(struct slgt_info *info)
2969 {
2970         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
2971                 DBGERR(("%s reg addr conflict, addr=%08X\n",
2972                         info->device_name, info->phys_reg_addr));
2973                 info->init_error = DiagStatus_AddressConflict;
2974                 goto errout;
2975         }
2976         else
2977                 info->reg_addr_requested = 1;
2978
2979         info->reg_addr = ioremap(info->phys_reg_addr, PAGE_SIZE);
2980         if (!info->reg_addr) {
2981                 DBGERR(("%s cant map device registers, addr=%08X\n",
2982                         info->device_name, info->phys_reg_addr));
2983                 info->init_error = DiagStatus_CantAssignPciResources;
2984                 goto errout;
2985         }
2986         info->reg_addr += info->reg_offset;
2987         return 0;
2988
2989 errout:
2990         release_resources(info);
2991         return -ENODEV;
2992 }
2993
2994 static void release_resources(struct slgt_info *info)
2995 {
2996         if (info->irq_requested) {
2997                 free_irq(info->irq_level, info);
2998                 info->irq_requested = 0;
2999         }
3000
3001         if (info->reg_addr_requested) {
3002                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3003                 info->reg_addr_requested = 0;
3004         }
3005
3006         if (info->reg_addr) {
3007                 iounmap(info->reg_addr - info->reg_offset);
3008                 info->reg_addr = NULL;
3009         }
3010 }
3011
3012 /* Add the specified device instance data structure to the
3013  * global linked list of devices and increment the device count.
3014  */
3015 static void add_device(struct slgt_info *info)
3016 {
3017         char *devstr;
3018
3019         info->next_device = NULL;
3020         info->line = slgt_device_count;
3021         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3022
3023         if (info->line < MAX_DEVICES) {
3024                 if (maxframe[info->line])
3025                         info->max_frame_size = maxframe[info->line];
3026                 info->dosyncppp = dosyncppp[info->line];
3027         }
3028
3029         slgt_device_count++;
3030
3031         if (!slgt_device_list)
3032                 slgt_device_list = info;
3033         else {
3034                 struct slgt_info *current_dev = slgt_device_list;
3035                 while(current_dev->next_device)
3036                         current_dev = current_dev->next_device;
3037                 current_dev->next_device = info;
3038         }
3039
3040         if (info->max_frame_size < 4096)
3041                 info->max_frame_size = 4096;
3042         else if (info->max_frame_size > 65535)
3043                 info->max_frame_size = 65535;
3044
3045         switch(info->pdev->device) {
3046         case SYNCLINK_GT_DEVICE_ID:
3047                 devstr = "GT";
3048                 break;
3049         case SYNCLINK_GT4_DEVICE_ID:
3050                 devstr = "GT4";
3051                 break;
3052         case SYNCLINK_AC_DEVICE_ID:
3053                 devstr = "AC";
3054                 info->params.mode = MGSL_MODE_ASYNC;
3055                 break;
3056         default:
3057                 devstr = "(unknown model)";
3058         }
3059         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3060                 devstr, info->device_name, info->phys_reg_addr,
3061                 info->irq_level, info->max_frame_size);
3062
3063 #ifdef CONFIG_HDLC
3064         hdlcdev_init(info);
3065 #endif
3066 }
3067
3068 /*
3069  *  allocate device instance structure, return NULL on failure
3070  */
3071 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3072 {
3073         struct slgt_info *info;
3074
3075         info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL);
3076
3077         if (!info) {
3078                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3079                         driver_name, adapter_num, port_num));
3080         } else {
3081                 memset(info, 0, sizeof(struct slgt_info));
3082                 info->magic = MGSL_MAGIC;
3083                 INIT_WORK(&info->task, bh_handler, info);
3084                 info->max_frame_size = 4096;
3085                 info->raw_rx_size = DMABUFSIZE;
3086                 info->close_delay = 5*HZ/10;
3087                 info->closing_wait = 30*HZ;
3088                 init_waitqueue_head(&info->open_wait);
3089                 init_waitqueue_head(&info->close_wait);
3090                 init_waitqueue_head(&info->status_event_wait_q);
3091                 init_waitqueue_head(&info->event_wait_q);
3092                 spin_lock_init(&info->netlock);
3093                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3094                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3095                 info->adapter_num = adapter_num;
3096                 info->port_num = port_num;
3097
3098                 init_timer(&info->tx_timer);
3099                 info->tx_timer.data = (unsigned long)info;
3100                 info->tx_timer.function = tx_timeout;
3101
3102                 init_timer(&info->rx_timer);
3103                 info->rx_timer.data = (unsigned long)info;
3104                 info->rx_timer.function = rx_timeout;
3105
3106                 /* Copy configuration info to device instance data */
3107                 info->pdev = pdev;
3108                 info->irq_level = pdev->irq;
3109                 info->phys_reg_addr = pci_resource_start(pdev,0);
3110
3111                 /* veremap works on page boundaries
3112                  * map full page starting at the page boundary
3113                  */
3114                 info->reg_offset    = info->phys_reg_addr & (PAGE_SIZE-1);
3115                 info->phys_reg_addr &= ~(PAGE_SIZE-1);
3116
3117                 info->bus_type = MGSL_BUS_TYPE_PCI;
3118                 info->irq_flags = SA_SHIRQ;
3119
3120                 info->init_error = -1; /* assume error, set to 0 on successful init */
3121         }
3122
3123         return info;
3124 }
3125
3126 static void device_init(int adapter_num, struct pci_dev *pdev)
3127 {
3128         struct slgt_info *port_array[SLGT_MAX_PORTS];
3129         int i;
3130         int port_count = 1;
3131
3132         if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3133                 port_count = 4;
3134
3135         /* allocate device instances for all ports */
3136         for (i=0; i < port_count; ++i) {
3137                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3138                 if (port_array[i] == NULL) {
3139                         for (--i; i >= 0; --i)
3140                                 kfree(port_array[i]);
3141                         return;
3142                 }
3143         }
3144
3145         /* give copy of port_array to all ports and add to device list  */
3146         for (i=0; i < port_count; ++i) {
3147                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3148                 add_device(port_array[i]);
3149                 port_array[i]->port_count = port_count;
3150                 spin_lock_init(&port_array[i]->lock);
3151         }
3152
3153         /* Allocate and claim adapter resources */
3154         if (!claim_resources(port_array[0])) {
3155
3156                 alloc_dma_bufs(port_array[0]);
3157
3158                 /* copy resource information from first port to others */
3159                 for (i = 1; i < port_count; ++i) {
3160                         port_array[i]->lock      = port_array[0]->lock;
3161                         port_array[i]->irq_level = port_array[0]->irq_level;
3162                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3163                         alloc_dma_bufs(port_array[i]);
3164                 }
3165
3166                 if (request_irq(port_array[0]->irq_level,
3167                                         slgt_interrupt,
3168                                         port_array[0]->irq_flags,
3169                                         port_array[0]->device_name,
3170                                         port_array[0]) < 0) {
3171                         DBGERR(("%s request_irq failed IRQ=%d\n",
3172                                 port_array[0]->device_name,
3173                                 port_array[0]->irq_level));
3174                 } else {
3175                         port_array[0]->irq_requested = 1;
3176                         adapter_test(port_array[0]);
3177                         for (i=1 ; i < port_count ; i++)
3178                                 port_array[i]->init_error = port_array[0]->init_error;
3179                 }
3180         }
3181 }
3182
3183 static int __devinit init_one(struct pci_dev *dev,
3184                               const struct pci_device_id *ent)
3185 {
3186         if (pci_enable_device(dev)) {
3187                 printk("error enabling pci device %p\n", dev);
3188                 return -EIO;
3189         }
3190         pci_set_master(dev);
3191         device_init(slgt_device_count, dev);
3192         return 0;
3193 }
3194
3195 static void __devexit remove_one(struct pci_dev *dev)
3196 {
3197 }
3198
3199 static struct tty_operations ops = {
3200         .open = open,
3201         .close = close,
3202         .write = write,
3203         .put_char = put_char,
3204         .flush_chars = flush_chars,
3205         .write_room = write_room,
3206         .chars_in_buffer = chars_in_buffer,
3207         .flush_buffer = flush_buffer,
3208         .ioctl = ioctl,
3209         .throttle = throttle,
3210         .unthrottle = unthrottle,
3211         .send_xchar = send_xchar,
3212         .break_ctl = set_break,
3213         .wait_until_sent = wait_until_sent,
3214         .read_proc = read_proc,
3215         .set_termios = set_termios,
3216         .stop = tx_hold,
3217         .start = tx_release,
3218         .hangup = hangup,
3219         .tiocmget = tiocmget,
3220         .tiocmset = tiocmset,
3221 };
3222
3223 static void slgt_cleanup(void)
3224 {
3225         int rc;
3226         struct slgt_info *info;
3227         struct slgt_info *tmp;
3228
3229         printk("unload %s %s\n", driver_name, driver_version);
3230
3231         if (serial_driver) {
3232                 if ((rc = tty_unregister_driver(serial_driver)))
3233                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3234                 put_tty_driver(serial_driver);
3235         }
3236
3237         /* reset devices */
3238         info = slgt_device_list;
3239         while(info) {
3240                 reset_port(info);
3241                 info = info->next_device;
3242         }
3243
3244         /* release devices */
3245         info = slgt_device_list;
3246         while(info) {
3247 #ifdef CONFIG_HDLC
3248                 hdlcdev_exit(info);
3249 #endif
3250                 free_dma_bufs(info);
3251                 free_tmp_rbuf(info);
3252                 if (info->port_num == 0)
3253                         release_resources(info);
3254                 tmp = info;
3255                 info = info->next_device;
3256                 kfree(tmp);
3257         }
3258
3259         if (pci_registered)
3260                 pci_unregister_driver(&pci_driver);
3261 }
3262
3263 /*
3264  *  Driver initialization entry point.
3265  */
3266 static int __init slgt_init(void)
3267 {
3268         int rc;
3269
3270         printk("%s %s\n", driver_name, driver_version);
3271
3272         slgt_device_count = 0;
3273         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3274                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3275                 return rc;
3276         }
3277         pci_registered = 1;
3278
3279         if (!slgt_device_list) {
3280                 printk("%s no devices found\n",driver_name);
3281                 return -ENODEV;
3282         }
3283
3284         serial_driver = alloc_tty_driver(MAX_DEVICES);
3285         if (!serial_driver) {
3286                 rc = -ENOMEM;
3287                 goto error;
3288         }
3289
3290         /* Initialize the tty_driver structure */
3291
3292         serial_driver->owner = THIS_MODULE;
3293         serial_driver->driver_name = tty_driver_name;
3294         serial_driver->name = tty_dev_prefix;
3295         serial_driver->major = ttymajor;
3296         serial_driver->minor_start = 64;
3297         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3298         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3299         serial_driver->init_termios = tty_std_termios;
3300         serial_driver->init_termios.c_cflag =
3301                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3302         serial_driver->flags = TTY_DRIVER_REAL_RAW;
3303         tty_set_operations(serial_driver, &ops);
3304         if ((rc = tty_register_driver(serial_driver)) < 0) {
3305                 DBGERR(("%s can't register serial driver\n", driver_name));
3306                 put_tty_driver(serial_driver);
3307                 serial_driver = NULL;
3308                 goto error;
3309         }
3310
3311         printk("%s %s, tty major#%d\n",
3312                 driver_name, driver_version,
3313                 serial_driver->major);
3314
3315         return 0;
3316
3317 error:
3318         slgt_cleanup();
3319         return rc;
3320 }
3321
3322 static void __exit slgt_exit(void)
3323 {
3324         slgt_cleanup();
3325 }
3326
3327 module_init(slgt_init);
3328 module_exit(slgt_exit);
3329
3330 /*
3331  * register access routines
3332  */
3333
3334 #define CALC_REGADDR() \
3335         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3336         if (addr >= 0x80) \
3337                 reg_addr += (info->port_num) * 32;
3338
3339 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3340 {
3341         CALC_REGADDR();
3342         return readb((void __iomem *)reg_addr);
3343 }
3344
3345 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3346 {
3347         CALC_REGADDR();
3348         writeb(value, (void __iomem *)reg_addr);
3349 }
3350
3351 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3352 {
3353         CALC_REGADDR();
3354         return readw((void __iomem *)reg_addr);
3355 }
3356
3357 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3358 {
3359         CALC_REGADDR();
3360         writew(value, (void __iomem *)reg_addr);
3361 }
3362
3363 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3364 {
3365         CALC_REGADDR();
3366         return readl((void __iomem *)reg_addr);
3367 }
3368
3369 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3370 {
3371         CALC_REGADDR();
3372         writel(value, (void __iomem *)reg_addr);
3373 }
3374
3375 static void rdma_reset(struct slgt_info *info)
3376 {
3377         unsigned int i;
3378
3379         /* set reset bit */
3380         wr_reg32(info, RDCSR, BIT1);
3381
3382         /* wait for enable bit cleared */
3383         for(i=0 ; i < 1000 ; i++)
3384                 if (!(rd_reg32(info, RDCSR) & BIT0))
3385                         break;
3386 }
3387
3388 static void tdma_reset(struct slgt_info *info)
3389 {
3390         unsigned int i;
3391
3392         /* set reset bit */
3393         wr_reg32(info, TDCSR, BIT1);
3394
3395         /* wait for enable bit cleared */
3396         for(i=0 ; i < 1000 ; i++)
3397                 if (!(rd_reg32(info, TDCSR) & BIT0))
3398                         break;
3399 }
3400
3401 /*
3402  * enable internal loopback
3403  * TxCLK and RxCLK are generated from BRG
3404  * and TxD is looped back to RxD internally.
3405  */
3406 static void enable_loopback(struct slgt_info *info)
3407 {
3408         /* SCR (serial control) BIT2=looopback enable */
3409         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3410
3411         if (info->params.mode != MGSL_MODE_ASYNC) {
3412                 /* CCR (clock control)
3413                  * 07..05  tx clock source (010 = BRG)
3414                  * 04..02  rx clock source (010 = BRG)
3415                  * 01      auxclk enable   (0 = disable)
3416                  * 00      BRG enable      (1 = enable)
3417                  *
3418                  * 0100 1001
3419                  */
3420                 wr_reg8(info, CCR, 0x49);
3421
3422                 /* set speed if available, otherwise use default */
3423                 if (info->params.clock_speed)
3424                         set_rate(info, info->params.clock_speed);
3425                 else
3426                         set_rate(info, 3686400);
3427         }
3428 }
3429
3430 /*
3431  *  set baud rate generator to specified rate
3432  */
3433 static void set_rate(struct slgt_info *info, u32 rate)
3434 {
3435         unsigned int div;
3436         static unsigned int osc = 14745600;
3437
3438         /* div = osc/rate - 1
3439          *
3440          * Round div up if osc/rate is not integer to
3441          * force to next slowest rate.
3442          */
3443
3444         if (rate) {
3445                 div = osc/rate;
3446                 if (!(osc % rate) && div)
3447                         div--;
3448                 wr_reg16(info, BDR, (unsigned short)div);
3449         }
3450 }
3451
3452 static void rx_stop(struct slgt_info *info)
3453 {
3454         unsigned short val;
3455
3456         /* disable and reset receiver */
3457         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3458         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3459         wr_reg16(info, RCR, val);                  /* clear reset bit */
3460
3461         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3462
3463         /* clear pending rx interrupts */
3464         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3465
3466         rdma_reset(info);
3467
3468         info->rx_enabled = 0;
3469         info->rx_restart = 0;
3470 }
3471
3472 static void rx_start(struct slgt_info *info)
3473 {
3474         unsigned short val;
3475
3476         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3477
3478         /* clear pending rx overrun IRQ */
3479         wr_reg16(info, SSR, IRQ_RXOVER);
3480
3481         /* reset and disable receiver */
3482         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3483         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3484         wr_reg16(info, RCR, val);                  /* clear reset bit */
3485
3486         rdma_reset(info);
3487         reset_rbufs(info);
3488
3489         /* set 1st descriptor address */
3490         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3491
3492         if (info->params.mode != MGSL_MODE_ASYNC) {
3493                 /* enable rx DMA and DMA interrupt */
3494                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3495         } else {
3496                 /* enable saving of rx status, rx DMA and DMA interrupt */
3497                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3498         }
3499
3500         slgt_irq_on(info, IRQ_RXOVER);
3501
3502         /* enable receiver */
3503         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3504
3505         info->rx_restart = 0;
3506         info->rx_enabled = 1;
3507 }
3508
3509 static void tx_start(struct slgt_info *info)
3510 {
3511         if (!info->tx_enabled) {
3512                 wr_reg16(info, TCR,
3513                         (unsigned short)(rd_reg16(info, TCR) | BIT1));
3514                 info->tx_enabled = TRUE;
3515         }
3516
3517         if (info->tx_count) {
3518                 info->drop_rts_on_tx_done = 0;
3519
3520                 if (info->params.mode != MGSL_MODE_ASYNC) {
3521                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3522                                 get_signals(info);
3523                                 if (!(info->signals & SerialSignal_RTS)) {
3524                                         info->signals |= SerialSignal_RTS;
3525                                         set_signals(info);
3526                                         info->drop_rts_on_tx_done = 1;
3527                                 }
3528                         }
3529
3530                         slgt_irq_off(info, IRQ_TXDATA);
3531                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3532                         /* clear tx idle and underrun status bits */
3533                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3534
3535                         if (!(rd_reg32(info, TDCSR) & BIT0)) {
3536                                 /* tx DMA stopped, restart tx DMA */
3537                                 tdma_reset(info);
3538                                 /* set 1st descriptor address */
3539                                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3540                                 if (info->params.mode == MGSL_MODE_RAW)
3541                                         wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3542                                 else
3543                                         wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3544                         }
3545
3546                         if (info->params.mode != MGSL_MODE_RAW) {
3547                                 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
3548                                 add_timer(&info->tx_timer);
3549                         }
3550                 } else {
3551                         tdma_reset(info);
3552                         /* set 1st descriptor address */
3553                         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3554
3555                         slgt_irq_off(info, IRQ_TXDATA);
3556                         slgt_irq_on(info, IRQ_TXIDLE);
3557                         /* clear tx idle status bit */
3558                         wr_reg16(info, SSR, IRQ_TXIDLE);
3559
3560                         /* enable tx DMA */
3561                         wr_reg32(info, TDCSR, BIT0);
3562                 }
3563
3564                 info->tx_active = 1;
3565         }
3566 }
3567
3568 static void tx_stop(struct slgt_info *info)
3569 {
3570         unsigned short val;
3571
3572         del_timer(&info->tx_timer);
3573
3574         tdma_reset(info);
3575
3576         /* reset and disable transmitter */
3577         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3578         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3579         wr_reg16(info, TCR, val);                  /* clear reset */
3580
3581         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3582
3583         /* clear tx idle and underrun status bit */
3584         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3585
3586         reset_tbufs(info);
3587
3588         info->tx_enabled = 0;
3589         info->tx_active  = 0;
3590 }
3591
3592 static void reset_port(struct slgt_info *info)
3593 {
3594         if (!info->reg_addr)
3595                 return;
3596
3597         tx_stop(info);
3598         rx_stop(info);
3599
3600         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3601         set_signals(info);
3602
3603         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3604 }
3605
3606 static void reset_adapter(struct slgt_info *info)
3607 {
3608         int i;
3609         for (i=0; i < info->port_count; ++i) {
3610                 if (info->port_array[i])
3611                         reset_port(info->port_array[i]);
3612         }
3613 }
3614
3615 static void async_mode(struct slgt_info *info)
3616 {
3617         unsigned short val;
3618
3619         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3620         tx_stop(info);
3621         rx_stop(info);
3622
3623         /* TCR (tx control)
3624          *
3625          * 15..13  mode, 010=async
3626          * 12..10  encoding, 000=NRZ
3627          * 09      parity enable
3628          * 08      1=odd parity, 0=even parity
3629          * 07      1=RTS driver control
3630          * 06      1=break enable
3631          * 05..04  character length
3632          *         00=5 bits
3633          *         01=6 bits
3634          *         10=7 bits
3635          *         11=8 bits
3636          * 03      0=1 stop bit, 1=2 stop bits
3637          * 02      reset
3638          * 01      enable
3639          * 00      auto-CTS enable
3640          */
3641         val = 0x4000;
3642
3643         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3644                 val |= BIT7;
3645
3646         if (info->params.parity != ASYNC_PARITY_NONE) {
3647                 val |= BIT9;
3648                 if (info->params.parity == ASYNC_PARITY_ODD)
3649                         val |= BIT8;
3650         }
3651
3652         switch (info->params.data_bits)
3653         {
3654         case 6: val |= BIT4; break;
3655         case 7: val |= BIT5; break;
3656         case 8: val |= BIT5 + BIT4; break;
3657         }
3658
3659         if (info->params.stop_bits != 1)
3660                 val |= BIT3;
3661
3662         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3663                 val |= BIT0;
3664
3665         wr_reg16(info, TCR, val);
3666
3667         /* RCR (rx control)
3668          *
3669          * 15..13  mode, 010=async
3670          * 12..10  encoding, 000=NRZ
3671          * 09      parity enable
3672          * 08      1=odd parity, 0=even parity
3673          * 07..06  reserved, must be 0
3674          * 05..04  character length
3675          *         00=5 bits
3676          *         01=6 bits
3677          *         10=7 bits
3678          *         11=8 bits
3679          * 03      reserved, must be zero
3680          * 02      reset
3681          * 01      enable
3682          * 00      auto-DCD enable
3683          */
3684         val = 0x4000;
3685
3686         if (info->params.parity != ASYNC_PARITY_NONE) {
3687                 val |= BIT9;
3688                 if (info->params.parity == ASYNC_PARITY_ODD)
3689                         val |= BIT8;
3690         }
3691
3692         switch (info->params.data_bits)
3693         {
3694         case 6: val |= BIT4; break;
3695         case 7: val |= BIT5; break;
3696         case 8: val |= BIT5 + BIT4; break;
3697         }
3698
3699         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3700                 val |= BIT0;
3701
3702         wr_reg16(info, RCR, val);
3703
3704         /* CCR (clock control)
3705          *
3706          * 07..05  011 = tx clock source is BRG/16
3707          * 04..02  010 = rx clock source is BRG
3708          * 01      0 = auxclk disabled
3709          * 00      1 = BRG enabled
3710          *
3711          * 0110 1001
3712          */
3713         wr_reg8(info, CCR, 0x69);
3714
3715         msc_set_vcr(info);
3716
3717         tx_set_idle(info);
3718
3719         /* SCR (serial control)
3720          *
3721          * 15  1=tx req on FIFO half empty
3722          * 14  1=rx req on FIFO half full
3723          * 13  tx data  IRQ enable
3724          * 12  tx idle  IRQ enable
3725          * 11  rx break on IRQ enable
3726          * 10  rx data  IRQ enable
3727          * 09  rx break off IRQ enable
3728          * 08  overrun  IRQ enable
3729          * 07  DSR      IRQ enable
3730          * 06  CTS      IRQ enable
3731          * 05  DCD      IRQ enable
3732          * 04  RI       IRQ enable
3733          * 03  reserved, must be zero
3734          * 02  1=txd->rxd internal loopback enable
3735          * 01  reserved, must be zero
3736          * 00  1=master IRQ enable
3737          */
3738         val = BIT15 + BIT14 + BIT0;
3739         wr_reg16(info, SCR, val);
3740
3741         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
3742
3743         set_rate(info, info->params.data_rate * 16);
3744
3745         if (info->params.loopback)
3746                 enable_loopback(info);
3747 }
3748
3749 static void hdlc_mode(struct slgt_info *info)
3750 {
3751         unsigned short val;
3752
3753         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3754         tx_stop(info);
3755         rx_stop(info);
3756
3757         /* TCR (tx control)
3758          *
3759          * 15..13  mode, 000=HDLC 001=raw sync
3760          * 12..10  encoding
3761          * 09      CRC enable
3762          * 08      CRC32
3763          * 07      1=RTS driver control
3764          * 06      preamble enable
3765          * 05..04  preamble length
3766          * 03      share open/close flag
3767          * 02      reset
3768          * 01      enable
3769          * 00      auto-CTS enable
3770          */
3771         val = 0;
3772
3773         if (info->params.mode == MGSL_MODE_RAW)
3774                 val |= BIT13;
3775         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3776                 val |= BIT7;
3777
3778         switch(info->params.encoding)
3779         {
3780         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
3781         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
3782         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
3783         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
3784         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
3785         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
3786         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
3787         }
3788
3789         switch (info->params.crc_type)
3790         {
3791         case HDLC_CRC_16_CCITT: val |= BIT9; break;
3792         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
3793         }
3794
3795         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
3796                 val |= BIT6;
3797
3798         switch (info->params.preamble_length)
3799         {
3800         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
3801         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
3802         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
3803         }
3804
3805         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3806                 val |= BIT0;
3807
3808         wr_reg16(info, TCR, val);
3809
3810         /* TPR (transmit preamble) */
3811
3812         switch (info->params.preamble)
3813         {
3814         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
3815         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
3816         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
3817         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
3818         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
3819         default:                          val = 0x7e; break;
3820         }
3821         wr_reg8(info, TPR, (unsigned char)val);
3822
3823         /* RCR (rx control)
3824          *
3825          * 15..13  mode, 000=HDLC 001=raw sync
3826          * 12..10  encoding
3827          * 09      CRC enable
3828          * 08      CRC32
3829          * 07..03  reserved, must be 0
3830          * 02      reset
3831          * 01      enable
3832          * 00      auto-DCD enable
3833          */
3834         val = 0;
3835
3836         if (info->params.mode == MGSL_MODE_RAW)
3837                 val |= BIT13;
3838
3839         switch(info->params.encoding)
3840         {
3841         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
3842         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
3843         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
3844         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
3845         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
3846         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
3847         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
3848         }
3849
3850         switch (info->params.crc_type)
3851         {
3852         case HDLC_CRC_16_CCITT: val |= BIT9; break;
3853         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
3854         }
3855
3856         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3857                 val |= BIT0;
3858
3859         wr_reg16(info, RCR, val);
3860
3861         /* CCR (clock control)
3862          *
3863          * 07..05  tx clock source
3864          * 04..02  rx clock source
3865          * 01      auxclk enable
3866          * 00      BRG enable
3867          */
3868         val = 0;
3869
3870         if (info->params.flags & HDLC_FLAG_TXC_BRG)
3871         {
3872                 // when RxC source is DPLL, BRG generates 16X DPLL
3873                 // reference clock, so take TxC from BRG/16 to get
3874                 // transmit clock at actual data rate
3875                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3876                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
3877                 else
3878                         val |= BIT6;    /* 010, txclk = BRG */
3879         }
3880         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
3881                 val |= BIT7;    /* 100, txclk = DPLL Input */
3882         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
3883                 val |= BIT5;    /* 001, txclk = RXC Input */
3884
3885         if (info->params.flags & HDLC_FLAG_RXC_BRG)
3886                 val |= BIT3;    /* 010, rxclk = BRG */
3887         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3888                 val |= BIT4;    /* 100, rxclk = DPLL */
3889         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
3890                 val |= BIT2;    /* 001, rxclk = TXC Input */
3891
3892         if (info->params.clock_speed)
3893                 val |= BIT1 + BIT0;
3894
3895         wr_reg8(info, CCR, (unsigned char)val);
3896
3897         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
3898         {
3899                 // program DPLL mode
3900                 switch(info->params.encoding)
3901                 {
3902                 case HDLC_ENCODING_BIPHASE_MARK:
3903                 case HDLC_ENCODING_BIPHASE_SPACE:
3904                         val = BIT7; break;
3905                 case HDLC_ENCODING_BIPHASE_LEVEL:
3906                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
3907                         val = BIT7 + BIT6; break;
3908                 default: val = BIT6;    // NRZ encodings
3909                 }
3910                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
3911
3912                 // DPLL requires a 16X reference clock from BRG
3913                 set_rate(info, info->params.clock_speed * 16);
3914         }
3915         else
3916                 set_rate(info, info->params.clock_speed);
3917
3918         tx_set_idle(info);
3919
3920         msc_set_vcr(info);
3921
3922         /* SCR (serial control)
3923          *
3924          * 15  1=tx req on FIFO half empty
3925          * 14  1=rx req on FIFO half full
3926          * 13  tx data  IRQ enable
3927          * 12  tx idle  IRQ enable
3928          * 11  underrun IRQ enable
3929          * 10  rx data  IRQ enable
3930          * 09  rx idle  IRQ enable
3931          * 08  overrun  IRQ enable
3932          * 07  DSR      IRQ enable
3933          * 06  CTS      IRQ enable
3934          * 05  DCD      IRQ enable
3935          * 04  RI       IRQ enable
3936          * 03  reserved, must be zero
3937          * 02  1=txd->rxd internal loopback enable
3938          * 01  reserved, must be zero
3939          * 00  1=master IRQ enable
3940          */
3941         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
3942
3943         if (info->params.loopback)
3944                 enable_loopback(info);
3945 }
3946
3947 /*
3948  *  set transmit idle mode
3949  */
3950 static void tx_set_idle(struct slgt_info *info)
3951 {
3952         unsigned char val = 0xff;
3953
3954         switch(info->idle_mode)
3955         {
3956         case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
3957         case HDLC_TXIDLE_ALT_ZEROS_ONES: val = 0xaa; break;
3958         case HDLC_TXIDLE_ZEROS:          val = 0x00; break;
3959         case HDLC_TXIDLE_ONES:           val = 0xff; break;
3960         case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
3961         case HDLC_TXIDLE_SPACE:          val = 0x00; break;
3962         case HDLC_TXIDLE_MARK:           val = 0xff; break;
3963         }
3964
3965         wr_reg8(info, TIR, val);
3966 }
3967
3968 /*
3969  * get state of V24 status (input) signals
3970  */
3971 static void get_signals(struct slgt_info *info)
3972 {
3973         unsigned short status = rd_reg16(info, SSR);
3974
3975         /* clear all serial signals except DTR and RTS */
3976         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
3977
3978         if (status & BIT3)
3979                 info->signals |= SerialSignal_DSR;
3980         if (status & BIT2)
3981                 info->signals |= SerialSignal_CTS;
3982         if (status & BIT1)
3983                 info->signals |= SerialSignal_DCD;
3984         if (status & BIT0)
3985                 info->signals |= SerialSignal_RI;
3986 }
3987
3988 /*
3989  * set V.24 Control Register based on current configuration
3990  */
3991 static void msc_set_vcr(struct slgt_info *info)
3992 {
3993         unsigned char val = 0;
3994
3995         /* VCR (V.24 control)
3996          *
3997          * 07..04  serial IF select
3998          * 03      DTR
3999          * 02      RTS
4000          * 01      LL
4001          * 00      RL
4002          */
4003
4004         switch(info->if_mode & MGSL_INTERFACE_MASK)
4005         {
4006         case MGSL_INTERFACE_RS232:
4007                 val |= BIT5; /* 0010 */
4008                 break;
4009         case MGSL_INTERFACE_V35:
4010                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4011                 break;
4012         case MGSL_INTERFACE_RS422:
4013                 val |= BIT6; /* 0100 */
4014                 break;
4015         }
4016
4017         if (info->signals & SerialSignal_DTR)
4018                 val |= BIT3;
4019         if (info->signals & SerialSignal_RTS)
4020                 val |= BIT2;
4021         if (info->if_mode & MGSL_INTERFACE_LL)
4022                 val |= BIT1;
4023         if (info->if_mode & MGSL_INTERFACE_RL)
4024                 val |= BIT0;
4025         wr_reg8(info, VCR, val);
4026 }
4027
4028 /*
4029  * set state of V24 control (output) signals
4030  */
4031 static void set_signals(struct slgt_info *info)
4032 {
4033         unsigned char val = rd_reg8(info, VCR);
4034         if (info->signals & SerialSignal_DTR)
4035                 val |= BIT3;
4036         else
4037                 val &= ~BIT3;
4038         if (info->signals & SerialSignal_RTS)
4039                 val |= BIT2;
4040         else
4041                 val &= ~BIT2;
4042         wr_reg8(info, VCR, val);
4043 }
4044
4045 /*
4046  * free range of receive DMA buffers (i to last)
4047  */
4048 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4049 {
4050         int done = 0;
4051
4052         while(!done) {
4053                 /* reset current buffer for reuse */
4054                 info->rbufs[i].status = 0;
4055                 if (info->params.mode == MGSL_MODE_RAW)
4056                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4057                 else
4058                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4059
4060                 if (i == last)
4061                         done = 1;
4062                 if (++i == info->rbuf_count)
4063                         i = 0;
4064         }
4065         info->rbuf_current = i;
4066 }
4067
4068 /*
4069  * mark all receive DMA buffers as free
4070  */
4071 static void reset_rbufs(struct slgt_info *info)
4072 {
4073         free_rbufs(info, 0, info->rbuf_count - 1);
4074 }
4075
4076 /*
4077  * pass receive HDLC frame to upper layer
4078  *
4079  * return 1 if frame available, otherwise 0
4080  */
4081 static int rx_get_frame(struct slgt_info *info)
4082 {
4083         unsigned int start, end;
4084         unsigned short status;
4085         unsigned int framesize = 0;
4086         int rc = 0;
4087         unsigned long flags;
4088         struct tty_struct *tty = info->tty;
4089         unsigned char addr_field = 0xff;
4090
4091 check_again:
4092
4093         framesize = 0;
4094         addr_field = 0xff;
4095         start = end = info->rbuf_current;
4096
4097         for (;;) {
4098                 if (!desc_complete(info->rbufs[end]))
4099                         goto cleanup;
4100
4101                 if (framesize == 0 && info->params.addr_filter != 0xff)
4102                         addr_field = info->rbufs[end].buf[0];
4103
4104                 framesize += desc_count(info->rbufs[end]);
4105
4106                 if (desc_eof(info->rbufs[end]))
4107                         break;
4108
4109                 if (++end == info->rbuf_count)
4110                         end = 0;
4111
4112                 if (end == info->rbuf_current) {
4113                         if (info->rx_enabled){
4114                                 spin_lock_irqsave(&info->lock,flags);
4115                                 rx_start(info);
4116                                 spin_unlock_irqrestore(&info->lock,flags);
4117                         }
4118                         goto cleanup;
4119                 }
4120         }
4121
4122         /* status
4123          *
4124          * 15      buffer complete
4125          * 14..06  reserved
4126          * 05..04  residue
4127          * 02      eof (end of frame)
4128          * 01      CRC error
4129          * 00      abort
4130          */
4131         status = desc_status(info->rbufs[end]);
4132
4133         /* ignore CRC bit if not using CRC (bit is undefined) */
4134         if (info->params.crc_type == HDLC_CRC_NONE)
4135                 status &= ~BIT1;
4136
4137         if (framesize == 0 ||
4138                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4139                 free_rbufs(info, start, end);
4140                 goto check_again;
4141         }
4142
4143         if (framesize < 2 || status & (BIT1+BIT0)) {
4144                 if (framesize < 2 || (status & BIT0))
4145                         info->icount.rxshort++;
4146                 else
4147                         info->icount.rxcrc++;
4148                 framesize = 0;
4149
4150 #ifdef CONFIG_HDLC
4151                 {
4152                         struct net_device_stats *stats = hdlc_stats(info->netdev);
4153                         stats->rx_errors++;
4154                         stats->rx_frame_errors++;
4155                 }
4156 #endif
4157         } else {
4158                 /* adjust frame size for CRC, if any */
4159                 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4160                         framesize -= 2;
4161                 else if (info->params.crc_type == HDLC_CRC_32_CCITT)
4162                         framesize -= 4;
4163         }
4164
4165         DBGBH(("%s rx frame status=%04X size=%d\n",
4166                 info->device_name, status, framesize));
4167         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4168
4169         if (framesize) {
4170                 if (framesize > info->max_frame_size)
4171                         info->icount.rxlong++;
4172                 else {
4173                         /* copy dma buffer(s) to contiguous temp buffer */
4174                         int copy_count = framesize;
4175                         int i = start;
4176                         unsigned char *p = info->tmp_rbuf;
4177                         info->tmp_rbuf_count = framesize;
4178
4179                         info->icount.rxok++;
4180
4181                         while(copy_count) {
4182                                 int partial_count = min(copy_count, DMABUFSIZE);
4183                                 memcpy(p, info->rbufs[i].buf, partial_count);
4184                                 p += partial_count;
4185                                 copy_count -= partial_count;
4186                                 if (++i == info->rbuf_count)
4187                                         i = 0;
4188                         }
4189
4190 #ifdef CONFIG_HDLC
4191                         if (info->netcount)
4192                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4193                         else
4194 #endif
4195                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4196                 }
4197         }
4198         free_rbufs(info, start, end);
4199         rc = 1;
4200
4201 cleanup:
4202         return rc;
4203 }
4204
4205 /*
4206  * pass receive buffer (RAW synchronous mode) to tty layer
4207  * return 1 if buffer available, otherwise 0
4208  */
4209 static int rx_get_buf(struct slgt_info *info)
4210 {
4211         unsigned int i = info->rbuf_current;
4212
4213         if (!desc_complete(info->rbufs[i]))
4214                 return 0;
4215         DBGDATA(info, info->rbufs[i].buf, desc_count(info->rbufs[i]), "rx");
4216         DBGINFO(("rx_get_buf size=%d\n", desc_count(info->rbufs[i])));
4217         ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4218                           info->flag_buf, desc_count(info->rbufs[i]));
4219         free_rbufs(info, i, i);
4220         return 1;
4221 }
4222
4223 static void reset_tbufs(struct slgt_info *info)
4224 {
4225         unsigned int i;
4226         info->tbuf_current = 0;
4227         for (i=0 ; i < info->tbuf_count ; i++) {
4228                 info->tbufs[i].status = 0;
4229                 info->tbufs[i].count  = 0;
4230         }
4231 }
4232
4233 /*
4234  * return number of free transmit DMA buffers
4235  */
4236 static unsigned int free_tbuf_count(struct slgt_info *info)
4237 {
4238         unsigned int count = 0;
4239         unsigned int i = info->tbuf_current;
4240
4241         do
4242         {
4243                 if (desc_count(info->tbufs[i]))
4244                         break; /* buffer in use */
4245                 ++count;
4246                 if (++i == info->tbuf_count)
4247                         i=0;
4248         } while (i != info->tbuf_current);
4249
4250         /* last buffer with zero count may be in use, assume it is */
4251         if (count)
4252                 --count;
4253
4254         return count;
4255 }
4256
4257 /*
4258  * load transmit DMA buffer(s) with data
4259  */
4260 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4261 {
4262         unsigned short count;
4263         unsigned int i;
4264         struct slgt_desc *d;
4265
4266         if (size == 0)
4267                 return;
4268
4269         DBGDATA(info, buf, size, "tx");
4270
4271         info->tbuf_start = i = info->tbuf_current;
4272
4273         while (size) {
4274                 d = &info->tbufs[i];
4275                 if (++i == info->tbuf_count)
4276                         i = 0;
4277
4278                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4279                 memcpy(d->buf, buf, count);
4280
4281                 size -= count;
4282                 buf  += count;
4283
4284                 if (!size && info->params.mode != MGSL_MODE_RAW)
4285                         set_desc_eof(*d, 1); /* HDLC: set EOF of last desc */
4286                 else
4287                         set_desc_eof(*d, 0);
4288
4289                 set_desc_count(*d, count);
4290         }
4291
4292         info->tbuf_current = i;
4293 }
4294
4295 static int register_test(struct slgt_info *info)
4296 {
4297         static unsigned short patterns[] =
4298                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4299         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4300         unsigned int i;
4301         int rc = 0;
4302
4303         for (i=0 ; i < count ; i++) {
4304                 wr_reg16(info, TIR, patterns[i]);
4305                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4306                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4307                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4308                         rc = -ENODEV;
4309                         break;
4310                 }
4311         }
4312
4313         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4314         return rc;
4315 }
4316
4317 static int irq_test(struct slgt_info *info)
4318 {
4319         unsigned long timeout;
4320         unsigned long flags;
4321         struct tty_struct *oldtty = info->tty;
4322         u32 speed = info->params.data_rate;
4323
4324         info->params.data_rate = 921600;
4325         info->tty = NULL;
4326
4327         spin_lock_irqsave(&info->lock, flags);
4328         async_mode(info);
4329         slgt_irq_on(info, IRQ_TXIDLE);
4330
4331         /* enable transmitter */
4332         wr_reg16(info, TCR,
4333                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4334
4335         /* write one byte and wait for tx idle */
4336         wr_reg16(info, TDR, 0);
4337
4338         /* assume failure */
4339         info->init_error = DiagStatus_IrqFailure;
4340         info->irq_occurred = FALSE;
4341
4342         spin_unlock_irqrestore(&info->lock, flags);
4343
4344         timeout=100;
4345         while(timeout-- && !info->irq_occurred)
4346                 msleep_interruptible(10);
4347
4348         spin_lock_irqsave(&info->lock,flags);
4349         reset_port(info);
4350         spin_unlock_irqrestore(&info->lock,flags);
4351
4352         info->params.data_rate = speed;
4353         info->tty = oldtty;
4354
4355         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4356         return info->irq_occurred ? 0 : -ENODEV;
4357 }
4358
4359 static int loopback_test_rx(struct slgt_info *info)
4360 {
4361         unsigned char *src, *dest;
4362         int count;
4363
4364         if (desc_complete(info->rbufs[0])) {
4365                 count = desc_count(info->rbufs[0]);
4366                 src   = info->rbufs[0].buf;
4367                 dest  = info->tmp_rbuf;
4368
4369                 for( ; count ; count-=2, src+=2) {
4370                         /* src=data byte (src+1)=status byte */
4371                         if (!(*(src+1) & (BIT9 + BIT8))) {
4372                                 *dest = *src;
4373                                 dest++;
4374                                 info->tmp_rbuf_count++;
4375                         }
4376                 }
4377                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4378                 return 1;
4379         }
4380         return 0;
4381 }
4382
4383 static int loopback_test(struct slgt_info *info)
4384 {
4385 #define TESTFRAMESIZE 20
4386
4387         unsigned long timeout;
4388         u16 count = TESTFRAMESIZE;
4389         unsigned char buf[TESTFRAMESIZE];
4390         int rc = -ENODEV;
4391         unsigned long flags;
4392
4393         struct tty_struct *oldtty = info->tty;
4394         MGSL_PARAMS params;
4395
4396         memcpy(&params, &info->params, sizeof(params));
4397
4398         info->params.mode = MGSL_MODE_ASYNC;
4399         info->params.data_rate = 921600;
4400         info->params.loopback = 1;
4401         info->tty = NULL;
4402
4403         /* build and send transmit frame */
4404         for (count = 0; count < TESTFRAMESIZE; ++count)
4405                 buf[count] = (unsigned char)count;
4406
4407         info->tmp_rbuf_count = 0;
4408         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4409
4410         /* program hardware for HDLC and enabled receiver */
4411         spin_lock_irqsave(&info->lock,flags);
4412         async_mode(info);
4413         rx_start(info);
4414         info->tx_count = count;
4415         tx_load(info, buf, count);
4416         tx_start(info);
4417         spin_unlock_irqrestore(&info->lock, flags);
4418
4419         /* wait for receive complete */
4420         for (timeout = 100; timeout; --timeout) {
4421                 msleep_interruptible(10);
4422                 if (loopback_test_rx(info)) {
4423                         rc = 0;
4424                         break;
4425                 }
4426         }
4427
4428         /* verify received frame length and contents */
4429         if (!rc && (info->tmp_rbuf_count != count ||
4430                   memcmp(buf, info->tmp_rbuf, count))) {
4431                 rc = -ENODEV;
4432         }
4433
4434         spin_lock_irqsave(&info->lock,flags);
4435         reset_adapter(info);
4436         spin_unlock_irqrestore(&info->lock,flags);
4437
4438         memcpy(&info->params, &params, sizeof(info->params));
4439         info->tty = oldtty;
4440
4441         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4442         return rc;
4443 }
4444
4445 static int adapter_test(struct slgt_info *info)
4446 {
4447         DBGINFO(("testing %s\n", info->device_name));
4448         if ((info->init_error = register_test(info)) < 0) {
4449                 printk("register test failure %s addr=%08X\n",
4450                         info->device_name, info->phys_reg_addr);
4451         } else if ((info->init_error = irq_test(info)) < 0) {
4452                 printk("IRQ test failure %s IRQ=%d\n",
4453                         info->device_name, info->irq_level);
4454         } else if ((info->init_error = loopback_test(info)) < 0) {
4455                 printk("loopback test failure %s\n", info->device_name);
4456         }
4457         return info->init_error;
4458 }
4459
4460 /*
4461  * transmit timeout handler
4462  */
4463 static void tx_timeout(unsigned long context)
4464 {
4465         struct slgt_info *info = (struct slgt_info*)context;
4466         unsigned long flags;
4467
4468         DBGINFO(("%s tx_timeout\n", info->device_name));
4469         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4470                 info->icount.txtimeout++;
4471         }
4472         spin_lock_irqsave(&info->lock,flags);
4473         info->tx_active = 0;
4474         info->tx_count = 0;
4475         spin_unlock_irqrestore(&info->lock,flags);
4476
4477 #ifdef CONFIG_HDLC
4478         if (info->netcount)
4479                 hdlcdev_tx_done(info);
4480         else
4481 #endif
4482                 bh_transmit(info);
4483 }
4484
4485 /*
4486  * receive buffer polling timer
4487  */
4488 static void rx_timeout(unsigned long context)
4489 {
4490         struct slgt_info *info = (struct slgt_info*)context;
4491         unsigned long flags;
4492
4493         DBGINFO(("%s rx_timeout\n", info->device_name));
4494         spin_lock_irqsave(&info->lock, flags);
4495         info->pending_bh |= BH_RECEIVE;
4496         spin_unlock_irqrestore(&info->lock, flags);
4497         bh_handler(info);
4498 }
4499