git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/sysdev/mpic.c

   1 /*
   2  *  arch/powerpc/kernel/mpic.c
   3  *
   4  *  Driver for interrupt controllers following the OpenPIC standard, the
   5  *  common implementation beeing IBM's MPIC. This driver also can deal
   6  *  with various broken implementations of this HW.
   7  *
   8  *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
   9  *
  10  *  This file is subject to the terms and conditions of the GNU General Public
  11  *  License.  See the file COPYING in the main directory of this archive
  12  *  for more details.
  13  */
  14
  15 #undef DEBUG
  16 #undef DEBUG_IPI
  17 #undef DEBUG_IRQ
  18 #undef DEBUG_LOW
  19
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/irq.h>
  24 #include <linux/smp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/bootmem.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/pci.h>
  29
  30 #include <asm/ptrace.h>
  31 #include <asm/signal.h>
  32 #include <asm/io.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/irq.h>
  35 #include <asm/machdep.h>
  36 #include <asm/mpic.h>
  37 #include <asm/smp.h>
  38
  39 #include "mpic.h"
  40
  41 #ifdef DEBUG
  42 #define DBG(fmt...) printk(fmt)
  43 #else
  44 #define DBG(fmt...)
  45 #endif
  46
  47 static struct mpic *mpics;
  48 static struct mpic *mpic_primary;
  49 static DEFINE_SPINLOCK(mpic_lock);
  50
  51 #ifdef CONFIG_PPC32     /* XXX for now */
  52 #ifdef CONFIG_IRQ_ALL_CPUS
  53 #define distribute_irqs (1)
  54 #else
  55 #define distribute_irqs (0)
  56 #endif
  57 #endif
  58
  59 #ifdef CONFIG_MPIC_WEIRD
  60 static u32 mpic_infos[][MPIC_IDX_END] = {
  61         [0] = { /* Original OpenPIC compatible MPIC */
  62                 MPIC_GREG_BASE,
  63                 MPIC_GREG_FEATURE_0,
  64                 MPIC_GREG_GLOBAL_CONF_0,
  65                 MPIC_GREG_VENDOR_ID,
  66                 MPIC_GREG_IPI_VECTOR_PRI_0,
  67                 MPIC_GREG_IPI_STRIDE,
  68                 MPIC_GREG_SPURIOUS,
  69                 MPIC_GREG_TIMER_FREQ,
  70
  71                 MPIC_TIMER_BASE,
  72                 MPIC_TIMER_STRIDE,
  73                 MPIC_TIMER_CURRENT_CNT,
  74                 MPIC_TIMER_BASE_CNT,
  75                 MPIC_TIMER_VECTOR_PRI,
  76                 MPIC_TIMER_DESTINATION,
  77
  78                 MPIC_CPU_BASE,
  79                 MPIC_CPU_STRIDE,
  80                 MPIC_CPU_IPI_DISPATCH_0,
  81                 MPIC_CPU_IPI_DISPATCH_STRIDE,
  82                 MPIC_CPU_CURRENT_TASK_PRI,
  83                 MPIC_CPU_WHOAMI,
  84                 MPIC_CPU_INTACK,
  85                 MPIC_CPU_EOI,
  86                 MPIC_CPU_MCACK,
  87
  88                 MPIC_IRQ_BASE,
  89                 MPIC_IRQ_STRIDE,
  90                 MPIC_IRQ_VECTOR_PRI,
  91                 MPIC_VECPRI_VECTOR_MASK,
  92                 MPIC_VECPRI_POLARITY_POSITIVE,
  93                 MPIC_VECPRI_POLARITY_NEGATIVE,
  94                 MPIC_VECPRI_SENSE_LEVEL,
  95                 MPIC_VECPRI_SENSE_EDGE,
  96                 MPIC_VECPRI_POLARITY_MASK,
  97                 MPIC_VECPRI_SENSE_MASK,
  98                 MPIC_IRQ_DESTINATION
  99         },
 100         [1] = { /* Tsi108/109 PIC */
 101                 TSI108_GREG_BASE,
 102                 TSI108_GREG_FEATURE_0,
 103                 TSI108_GREG_GLOBAL_CONF_0,
 104                 TSI108_GREG_VENDOR_ID,
 105                 TSI108_GREG_IPI_VECTOR_PRI_0,
 106                 TSI108_GREG_IPI_STRIDE,
 107                 TSI108_GREG_SPURIOUS,
 108                 TSI108_GREG_TIMER_FREQ,
 109
 110                 TSI108_TIMER_BASE,
 111                 TSI108_TIMER_STRIDE,
 112                 TSI108_TIMER_CURRENT_CNT,
 113                 TSI108_TIMER_BASE_CNT,
 114                 TSI108_TIMER_VECTOR_PRI,
 115                 TSI108_TIMER_DESTINATION,
 116
 117                 TSI108_CPU_BASE,
 118                 TSI108_CPU_STRIDE,
 119                 TSI108_CPU_IPI_DISPATCH_0,
 120                 TSI108_CPU_IPI_DISPATCH_STRIDE,
 121                 TSI108_CPU_CURRENT_TASK_PRI,
 122                 TSI108_CPU_WHOAMI,
 123                 TSI108_CPU_INTACK,
 124                 TSI108_CPU_EOI,
 125                 TSI108_CPU_MCACK,
 126
 127                 TSI108_IRQ_BASE,
 128                 TSI108_IRQ_STRIDE,
 129                 TSI108_IRQ_VECTOR_PRI,
 130                 TSI108_VECPRI_VECTOR_MASK,
 131                 TSI108_VECPRI_POLARITY_POSITIVE,
 132                 TSI108_VECPRI_POLARITY_NEGATIVE,
 133                 TSI108_VECPRI_SENSE_LEVEL,
 134                 TSI108_VECPRI_SENSE_EDGE,
 135                 TSI108_VECPRI_POLARITY_MASK,
 136                 TSI108_VECPRI_SENSE_MASK,
 137                 TSI108_IRQ_DESTINATION
 138         },
 139 };
 140
 141 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
 142
 143 #else /* CONFIG_MPIC_WEIRD */
 144
 145 #define MPIC_INFO(name) MPIC_##name
 146
 147 #endif /* CONFIG_MPIC_WEIRD */
 148
 149 /*
 150  * Register accessor functions
 151  */
 152
 153
 154 static inline u32 _mpic_read(enum mpic_reg_type type,
 155                              struct mpic_reg_bank *rb,
 156                              unsigned int reg)
 157 {
 158         switch(type) {
 159 #ifdef CONFIG_PPC_DCR
 160         case mpic_access_dcr:
 161                 return dcr_read(rb->dhost, reg);
 162 #endif
 163         case mpic_access_mmio_be:
 164                 return in_be32(rb->base + (reg >> 2));
 165         case mpic_access_mmio_le:
 166         default:
 167                 return in_le32(rb->base + (reg >> 2));
 168         }
 169 }
 170
 171 static inline void _mpic_write(enum mpic_reg_type type,
 172                                struct mpic_reg_bank *rb,
 173                                unsigned int reg, u32 value)
 174 {
 175         switch(type) {
 176 #ifdef CONFIG_PPC_DCR
 177         case mpic_access_dcr:
 178                 dcr_write(rb->dhost, reg, value);
 179                 break;
 180 #endif
 181         case mpic_access_mmio_be:
 182                 out_be32(rb->base + (reg >> 2), value);
 183                 break;
 184         case mpic_access_mmio_le:
 185         default:
 186                 out_le32(rb->base + (reg >> 2), value);
 187                 break;
 188         }
 189 }
 190
 191 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
 192 {
 193         enum mpic_reg_type type = mpic->reg_type;
 194         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 195                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 196
 197         if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
 198                 type = mpic_access_mmio_be;
 199         return _mpic_read(type, &mpic->gregs, offset);
 200 }
 201
 202 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
 203 {
 204         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 205                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 206
 207         _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
 208 }
 209
 210 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
 211 {
 212         unsigned int cpu = 0;
 213
 214         if (mpic->flags & MPIC_PRIMARY)
 215                 cpu = hard_smp_processor_id();
 216         return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
 217 }
 218
 219 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
 220 {
 221         unsigned int cpu = 0;
 222
 223         if (mpic->flags & MPIC_PRIMARY)
 224                 cpu = hard_smp_processor_id();
 225
 226         _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
 227 }
 228
 229 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
 230 {
 231         unsigned int    isu = src_no >> mpic->isu_shift;
 232         unsigned int    idx = src_no & mpic->isu_mask;
 233
 234 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 235         if (reg == 0)
 236                 return mpic->isu_reg0_shadow[idx];
 237         else
 238 #endif
 239                 return _mpic_read(mpic->reg_type, &mpic->isus[isu],
 240                                   reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 241 }
 242
 243 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
 244                                    unsigned int reg, u32 value)
 245 {
 246         unsigned int    isu = src_no >> mpic->isu_shift;
 247         unsigned int    idx = src_no & mpic->isu_mask;
 248
 249         _mpic_write(mpic->reg_type, &mpic->isus[isu],
 250                     reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
 251
 252 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 253         if (reg == 0)
 254                 mpic->isu_reg0_shadow[idx] = value;
 255 #endif
 256 }
 257
 258 #define mpic_read(b,r)          _mpic_read(mpic->reg_type,&(b),(r))
 259 #define mpic_write(b,r,v)       _mpic_write(mpic->reg_type,&(b),(r),(v))
 260 #define mpic_ipi_read(i)        _mpic_ipi_read(mpic,(i))
 261 #define mpic_ipi_write(i,v)     _mpic_ipi_write(mpic,(i),(v))
 262 #define mpic_cpu_read(i)        _mpic_cpu_read(mpic,(i))
 263 #define mpic_cpu_write(i,v)     _mpic_cpu_write(mpic,(i),(v))
 264 #define mpic_irq_read(s,r)      _mpic_irq_read(mpic,(s),(r))
 265 #define mpic_irq_write(s,r,v)   _mpic_irq_write(mpic,(s),(r),(v))
 266
 267
 268 /*
 269  * Low level utility functions
 270  */
 271
 272
 273 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
 274                            struct mpic_reg_bank *rb, unsigned int offset,
 275                            unsigned int size)
 276 {
 277         rb->base = ioremap(phys_addr + offset, size);
 278         BUG_ON(rb->base == NULL);
 279 }
 280
 281 #ifdef CONFIG_PPC_DCR
 282 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
 283                           struct mpic_reg_bank *rb,
 284                           unsigned int offset, unsigned int size)
 285 {
 286         const u32 *dbasep;
 287
 288         dbasep = of_get_property(node, "dcr-reg", NULL);
 289
 290         rb->dhost = dcr_map(node, *dbasep + offset, size);
 291         BUG_ON(!DCR_MAP_OK(rb->dhost));
 292 }
 293
 294 static inline void mpic_map(struct mpic *mpic, struct device_node *node,
 295                             phys_addr_t phys_addr, struct mpic_reg_bank *rb,
 296                             unsigned int offset, unsigned int size)
 297 {
 298         if (mpic->flags & MPIC_USES_DCR)
 299                 _mpic_map_dcr(mpic, node, rb, offset, size);
 300         else
 301                 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
 302 }
 303 #else /* CONFIG_PPC_DCR */
 304 #define mpic_map(m,n,p,b,o,s)   _mpic_map_mmio(m,p,b,o,s)
 305 #endif /* !CONFIG_PPC_DCR */
 306
 307
 308
 309 /* Check if we have one of those nice broken MPICs with a flipped endian on
 310  * reads from IPI registers
 311  */
 312 static void __init mpic_test_broken_ipi(struct mpic *mpic)
 313 {
 314         u32 r;
 315
 316         mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
 317         r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
 318
 319         if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
 320                 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
 321                 mpic->flags |= MPIC_BROKEN_IPI;
 322         }
 323 }
 324
 325 #ifdef CONFIG_MPIC_U3_HT_IRQS
 326
 327 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 328  * to force the edge setting on the MPIC and do the ack workaround.
 329  */
 330 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 331 {
 332         if (source >= 128 || !mpic->fixups)
 333                 return 0;
 334         return mpic->fixups[source].base != NULL;
 335 }
 336
 337
 338 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
 339 {
 340         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 341
 342         if (fixup->applebase) {
 343                 unsigned int soff = (fixup->index >> 3) & ~3;
 344                 unsigned int mask = 1U << (fixup->index & 0x1f);
 345                 writel(mask, fixup->applebase + soff);
 346         } else {
 347                 spin_lock(&mpic->fixup_lock);
 348                 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
 349                 writel(fixup->data, fixup->base + 4);
 350                 spin_unlock(&mpic->fixup_lock);
 351         }
 352 }
 353
 354 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
 355                                       unsigned int irqflags)
 356 {
 357         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 358         unsigned long flags;
 359         u32 tmp;
 360
 361         if (fixup->base == NULL)
 362                 return;
 363
 364         DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
 365             source, irqflags, fixup->index);
 366         spin_lock_irqsave(&mpic->fixup_lock, flags);
 367         /* Enable and configure */
 368         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 369         tmp = readl(fixup->base + 4);
 370         tmp &= ~(0x23U);
 371         if (irqflags & IRQ_LEVEL)
 372                 tmp |= 0x22;
 373         writel(tmp, fixup->base + 4);
 374         spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 375
 376 #ifdef CONFIG_PM
 377         /* use the lowest bit inverted to the actual HW,
 378          * set if this fixup was enabled, clear otherwise */
 379         mpic->save_data[source].fixup_data = tmp | 1;
 380 #endif
 381 }
 382
 383 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
 384                                        unsigned int irqflags)
 385 {
 386         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 387         unsigned long flags;
 388         u32 tmp;
 389
 390         if (fixup->base == NULL)
 391                 return;
 392
 393         DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
 394
 395         /* Disable */
 396         spin_lock_irqsave(&mpic->fixup_lock, flags);
 397         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 398         tmp = readl(fixup->base + 4);
 399         tmp |= 1;
 400         writel(tmp, fixup->base + 4);
 401         spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 402
 403 #ifdef CONFIG_PM
 404         /* use the lowest bit inverted to the actual HW,
 405          * set if this fixup was enabled, clear otherwise */
 406         mpic->save_data[source].fixup_data = tmp & ~1;
 407 #endif
 408 }
 409
 410 #ifdef CONFIG_PCI_MSI
 411 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 412                                     unsigned int devfn)
 413 {
 414         u8 __iomem *base;
 415         u8 pos, flags;
 416         u64 addr = 0;
 417
 418         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 419              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 420                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 421                 if (id == PCI_CAP_ID_HT) {
 422                         id = readb(devbase + pos + 3);
 423                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
 424                                 break;
 425                 }
 426         }
 427
 428         if (pos == 0)
 429                 return;
 430
 431         base = devbase + pos;
 432
 433         flags = readb(base + HT_MSI_FLAGS);
 434         if (!(flags & HT_MSI_FLAGS_FIXED)) {
 435                 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
 436                 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
 437         }
 438
 439         printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
 440                 PCI_SLOT(devfn), PCI_FUNC(devfn),
 441                 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
 442
 443         if (!(flags & HT_MSI_FLAGS_ENABLE))
 444                 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
 445 }
 446 #else
 447 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 448                                     unsigned int devfn)
 449 {
 450         return;
 451 }
 452 #endif
 453
 454 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
 455                                     unsigned int devfn, u32 vdid)
 456 {
 457         int i, irq, n;
 458         u8 __iomem *base;
 459         u32 tmp;
 460         u8 pos;
 461
 462         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 463              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 464                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 465                 if (id == PCI_CAP_ID_HT) {
 466                         id = readb(devbase + pos + 3);
 467                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
 468                                 break;
 469                 }
 470         }
 471         if (pos == 0)
 472                 return;
 473
 474         base = devbase + pos;
 475         writeb(0x01, base + 2);
 476         n = (readl(base + 4) >> 16) & 0xff;
 477
 478         printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
 479                " has %d irqs\n",
 480                devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
 481
 482         for (i = 0; i <= n; i++) {
 483                 writeb(0x10 + 2 * i, base + 2);
 484                 tmp = readl(base + 4);
 485                 irq = (tmp >> 16) & 0xff;
 486                 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
 487                 /* mask it , will be unmasked later */
 488                 tmp |= 0x1;
 489                 writel(tmp, base + 4);
 490                 mpic->fixups[irq].index = i;
 491                 mpic->fixups[irq].base = base;
 492                 /* Apple HT PIC has a non-standard way of doing EOIs */
 493                 if ((vdid & 0xffff) == 0x106b)
 494                         mpic->fixups[irq].applebase = devbase + 0x60;
 495                 else
 496                         mpic->fixups[irq].applebase = NULL;
 497                 writeb(0x11 + 2 * i, base + 2);
 498                 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
 499         }
 500 }
 501
 502
 503 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 504 {
 505         unsigned int devfn;
 506         u8 __iomem *cfgspace;
 507
 508         printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
 509
 510         /* Allocate fixups array */
 511         mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
 512         BUG_ON(mpic->fixups == NULL);
 513         memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
 514
 515         /* Init spinlock */
 516         spin_lock_init(&mpic->fixup_lock);
 517
 518         /* Map U3 config space. We assume all IO-APICs are on the primary bus
 519          * so we only need to map 64kB.
 520          */
 521         cfgspace = ioremap(0xf2000000, 0x10000);
 522         BUG_ON(cfgspace == NULL);
 523
 524         /* Now we scan all slots. We do a very quick scan, we read the header
 525          * type, vendor ID and device ID only, that's plenty enough
 526          */
 527         for (devfn = 0; devfn < 0x100; devfn++) {
 528                 u8 __iomem *devbase = cfgspace + (devfn << 8);
 529                 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
 530                 u32 l = readl(devbase + PCI_VENDOR_ID);
 531                 u16 s;
 532
 533                 DBG("devfn %x, l: %x\n", devfn, l);
 534
 535                 /* If no device, skip */
 536                 if (l == 0xffffffff || l == 0x00000000 ||
 537                     l == 0x0000ffff || l == 0xffff0000)
 538                         goto next;
 539                 /* Check if is supports capability lists */
 540                 s = readw(devbase + PCI_STATUS);
 541                 if (!(s & PCI_STATUS_CAP_LIST))
 542                         goto next;
 543
 544                 mpic_scan_ht_pic(mpic, devbase, devfn, l);
 545                 mpic_scan_ht_msi(mpic, devbase, devfn);
 546
 547         next:
 548                 /* next device, if function 0 */
 549                 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
 550                         devfn += 7;
 551         }
 552 }
 553
 554 #else /* CONFIG_MPIC_U3_HT_IRQS */
 555
 556 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 557 {
 558         return 0;
 559 }
 560
 561 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 562 {
 563 }
 564
 565 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 566
 567 #ifdef CONFIG_SMP
 568 static int irq_choose_cpu(unsigned int virt_irq)
 569 {
 570         cpumask_t mask;
 571         int cpuid;
 572
 573         cpumask_copy(&mask, irq_desc[virt_irq].affinity);
 574         if (cpus_equal(mask, CPU_MASK_ALL)) {
 575                 static int irq_rover;
 576                 static DEFINE_SPINLOCK(irq_rover_lock);
 577                 unsigned long flags;
 578
 579                 /* Round-robin distribution... */
 580         do_round_robin:
 581                 spin_lock_irqsave(&irq_rover_lock, flags);
 582
 583                 while (!cpu_online(irq_rover)) {
 584                         if (++irq_rover >= NR_CPUS)
 585                                 irq_rover = 0;
 586                 }
 587                 cpuid = irq_rover;
 588                 do {
 589                         if (++irq_rover >= NR_CPUS)
 590                                 irq_rover = 0;
 591                 } while (!cpu_online(irq_rover));
 592
 593                 spin_unlock_irqrestore(&irq_rover_lock, flags);
 594         } else {
 595                 cpumask_t tmp;
 596
 597                 cpus_and(tmp, cpu_online_map, mask);
 598
 599                 if (cpus_empty(tmp))
 600                         goto do_round_robin;
 601
 602                 cpuid = first_cpu(tmp);
 603         }
 604
 605         return get_hard_smp_processor_id(cpuid);
 606 }
 607 #else
 608 static int irq_choose_cpu(unsigned int virt_irq)
 609 {
 610         return hard_smp_processor_id();
 611 }
 612 #endif
 613
 614 #define mpic_irq_to_hw(virq)    ((unsigned int)irq_map[virq].hwirq)
 615
 616 /* Find an mpic associated with a given linux interrupt */
 617 static struct mpic *mpic_find(unsigned int irq)
 618 {
 619         if (irq < NUM_ISA_INTERRUPTS)
 620                 return NULL;
 621
 622         return irq_desc[irq].chip_data;
 623 }
 624
 625 /* Determine if the linux irq is an IPI */
 626 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
 627 {
 628         unsigned int src = mpic_irq_to_hw(irq);
 629
 630         return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 631 }
 632
 633
 634 /* Convert a cpu mask from logical to physical cpu numbers. */
 635 static inline u32 mpic_physmask(u32 cpumask)
 636 {
 637         int i;
 638         u32 mask = 0;
 639
 640         for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
 641                 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
 642         return mask;
 643 }
 644
 645 #ifdef CONFIG_SMP
 646 /* Get the mpic structure from the IPI number */
 647 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
 648 {
 649         return irq_desc[ipi].chip_data;
 650 }
 651 #endif
 652
 653 /* Get the mpic structure from the irq number */
 654 static inline struct mpic * mpic_from_irq(unsigned int irq)
 655 {
 656         return irq_desc[irq].chip_data;
 657 }
 658
 659 /* Send an EOI */
 660 static inline void mpic_eoi(struct mpic *mpic)
 661 {
 662         mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
 663         (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
 664 }
 665
 666 /*
 667  * Linux descriptor level callbacks
 668  */
 669
 670
 671 void mpic_unmask_irq(unsigned int irq)
 672 {
 673         unsigned int loops = 100000;
 674         struct mpic *mpic = mpic_from_irq(irq);
 675         unsigned int src = mpic_irq_to_hw(irq);
 676
 677         DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
 678
 679         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 680                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
 681                        ~MPIC_VECPRI_MASK);
 682         /* make sure mask gets to controller before we return to user */
 683         do {
 684                 if (!loops--) {
 685                         printk(KERN_ERR "mpic_enable_irq timeout\n");
 686                         break;
 687                 }
 688         } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
 689 }
 690
 691 void mpic_mask_irq(unsigned int irq)
 692 {
 693         unsigned int loops = 100000;
 694         struct mpic *mpic = mpic_from_irq(irq);
 695         unsigned int src = mpic_irq_to_hw(irq);
 696
 697         DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
 698
 699         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 700                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
 701                        MPIC_VECPRI_MASK);
 702
 703         /* make sure mask gets to controller before we return to user */
 704         do {
 705                 if (!loops--) {
 706                         printk(KERN_ERR "mpic_enable_irq timeout\n");
 707                         break;
 708                 }
 709         } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
 710 }
 711
 712 void mpic_end_irq(unsigned int irq)
 713 {
 714         struct mpic *mpic = mpic_from_irq(irq);
 715
 716 #ifdef DEBUG_IRQ
 717         DBG("%s: end_irq: %d\n", mpic->name, irq);
 718 #endif
 719         /* We always EOI on end_irq() even for edge interrupts since that
 720          * should only lower the priority, the MPIC should have properly
 721          * latched another edge interrupt coming in anyway
 722          */
 723
 724         mpic_eoi(mpic);
 725 }
 726
 727 #ifdef CONFIG_MPIC_U3_HT_IRQS
 728
 729 static void mpic_unmask_ht_irq(unsigned int irq)
 730 {
 731         struct mpic *mpic = mpic_from_irq(irq);
 732         unsigned int src = mpic_irq_to_hw(irq);
 733
 734         mpic_unmask_irq(irq);
 735
 736         if (irq_desc[irq].status & IRQ_LEVEL)
 737                 mpic_ht_end_irq(mpic, src);
 738 }
 739
 740 static unsigned int mpic_startup_ht_irq(unsigned int irq)
 741 {
 742         struct mpic *mpic = mpic_from_irq(irq);
 743         unsigned int src = mpic_irq_to_hw(irq);
 744
 745         mpic_unmask_irq(irq);
 746         mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
 747
 748         return 0;
 749 }
 750
 751 static void mpic_shutdown_ht_irq(unsigned int irq)
 752 {
 753         struct mpic *mpic = mpic_from_irq(irq);
 754         unsigned int src = mpic_irq_to_hw(irq);
 755
 756         mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
 757         mpic_mask_irq(irq);
 758 }
 759
 760 static void mpic_end_ht_irq(unsigned int irq)
 761 {
 762         struct mpic *mpic = mpic_from_irq(irq);
 763         unsigned int src = mpic_irq_to_hw(irq);
 764
 765 #ifdef DEBUG_IRQ
 766         DBG("%s: end_irq: %d\n", mpic->name, irq);
 767 #endif
 768         /* We always EOI on end_irq() even for edge interrupts since that
 769          * should only lower the priority, the MPIC should have properly
 770          * latched another edge interrupt coming in anyway
 771          */
 772
 773         if (irq_desc[irq].status & IRQ_LEVEL)
 774                 mpic_ht_end_irq(mpic, src);
 775         mpic_eoi(mpic);
 776 }
 777 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
 778
 779 #ifdef CONFIG_SMP
 780
 781 static void mpic_unmask_ipi(unsigned int irq)
 782 {
 783         struct mpic *mpic = mpic_from_ipi(irq);
 784         unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
 785
 786         DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
 787         mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
 788 }
 789
 790 static void mpic_mask_ipi(unsigned int irq)
 791 {
 792         /* NEVER disable an IPI... that's just plain wrong! */
 793 }
 794
 795 static void mpic_end_ipi(unsigned int irq)
 796 {
 797         struct mpic *mpic = mpic_from_ipi(irq);
 798
 799         /*
 800          * IPIs are marked IRQ_PER_CPU. This has the side effect of
 801          * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
 802          * applying to them. We EOI them late to avoid re-entering.
 803          * We mark IPI's with IRQF_DISABLED as they must run with
 804          * irqs disabled.
 805          */
 806         mpic_eoi(mpic);
 807 }
 808
 809 #endif /* CONFIG_SMP */
 810
 811 int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
 812 {
 813         struct mpic *mpic = mpic_from_irq(irq);
 814         unsigned int src = mpic_irq_to_hw(irq);
 815
 816         if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
 817                 int cpuid = irq_choose_cpu(irq);
 818
 819                 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 820         } else {
 821                 cpumask_t tmp;
 822
 823                 cpumask_and(&tmp, cpumask, cpu_online_mask);
 824
 825                 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
 826                                mpic_physmask(cpus_addr(tmp)[0]));
 827         }
 828
 829         return 0;
 830 }
 831
 832 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
 833 {
 834         /* Now convert sense value */
 835         switch(type & IRQ_TYPE_SENSE_MASK) {
 836         case IRQ_TYPE_EDGE_RISING:
 837                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
 838                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 839         case IRQ_TYPE_EDGE_FALLING:
 840         case IRQ_TYPE_EDGE_BOTH:
 841                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
 842                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 843         case IRQ_TYPE_LEVEL_HIGH:
 844                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 845                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 846         case IRQ_TYPE_LEVEL_LOW:
 847         default:
 848                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 849                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 850         }
 851 }
 852
 853 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
 854 {
 855         struct mpic *mpic = mpic_from_irq(virq);
 856         unsigned int src = mpic_irq_to_hw(virq);
 857         struct irq_desc *desc = get_irq_desc(virq);
 858         unsigned int vecpri, vold, vnew;
 859
 860         DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
 861             mpic, virq, src, flow_type);
 862
 863         if (src >= mpic->irq_count)
 864                 return -EINVAL;
 865
 866         if (flow_type == IRQ_TYPE_NONE)
 867                 if (mpic->senses && src < mpic->senses_count)
 868                         flow_type = mpic->senses[src];
 869         if (flow_type == IRQ_TYPE_NONE)
 870                 flow_type = IRQ_TYPE_LEVEL_LOW;
 871
 872         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
 873         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
 874         if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
 875                 desc->status |= IRQ_LEVEL;
 876
 877         if (mpic_is_ht_interrupt(mpic, src))
 878                 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
 879                         MPIC_VECPRI_SENSE_EDGE;
 880         else
 881                 vecpri = mpic_type_to_vecpri(mpic, flow_type);
 882
 883         vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 884         vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
 885                         MPIC_INFO(VECPRI_SENSE_MASK));
 886         vnew |= vecpri;
 887         if (vold != vnew)
 888                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
 889
 890         return 0;
 891 }
 892
 893 void mpic_set_vector(unsigned int virq, unsigned int vector)
 894 {
 895         struct mpic *mpic = mpic_from_irq(virq);
 896         unsigned int src = mpic_irq_to_hw(virq);
 897         unsigned int vecpri;
 898
 899         DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
 900             mpic, virq, src, vector);
 901
 902         if (src >= mpic->irq_count)
 903                 return;
 904
 905         vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 906         vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
 907         vecpri |= vector;
 908         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
 909 }
 910
 911 static struct irq_chip mpic_irq_chip = {
 912         .mask           = mpic_mask_irq,
 913         .unmask         = mpic_unmask_irq,
 914         .eoi            = mpic_end_irq,
 915         .set_type       = mpic_set_irq_type,
 916 };
 917
 918 #ifdef CONFIG_SMP
 919 static struct irq_chip mpic_ipi_chip = {
 920         .mask           = mpic_mask_ipi,
 921         .unmask         = mpic_unmask_ipi,
 922         .eoi            = mpic_end_ipi,
 923 };
 924 #endif /* CONFIG_SMP */
 925
 926 #ifdef CONFIG_MPIC_U3_HT_IRQS
 927 static struct irq_chip mpic_irq_ht_chip = {
 928         .startup        = mpic_startup_ht_irq,
 929         .shutdown       = mpic_shutdown_ht_irq,
 930         .mask           = mpic_mask_irq,
 931         .unmask         = mpic_unmask_ht_irq,
 932         .eoi            = mpic_end_ht_irq,
 933         .set_type       = mpic_set_irq_type,
 934 };
 935 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 936
 937
 938 static int mpic_host_match(struct irq_host *h, struct device_node *node)
 939 {
 940         /* Exact match, unless mpic node is NULL */
 941         return h->of_node == NULL || h->of_node == node;
 942 }
 943
 944 static int mpic_host_map(struct irq_host *h, unsigned int virq,
 945                          irq_hw_number_t hw)
 946 {
 947         struct mpic *mpic = h->host_data;
 948         struct irq_chip *chip;
 949
 950         DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
 951
 952         if (hw == mpic->spurious_vec)
 953                 return -EINVAL;
 954         if (mpic->protected && test_bit(hw, mpic->protected))
 955                 return -EINVAL;
 956
 957 #ifdef CONFIG_SMP
 958         else if (hw >= mpic->ipi_vecs[0]) {
 959                 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
 960
 961                 DBG("mpic: mapping as IPI\n");
 962                 set_irq_chip_data(virq, mpic);
 963                 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
 964                                          handle_percpu_irq);
 965                 return 0;
 966         }
 967 #endif /* CONFIG_SMP */
 968
 969         if (hw >= mpic->irq_count)
 970                 return -EINVAL;
 971
 972         mpic_msi_reserve_hwirq(mpic, hw);
 973
 974         /* Default chip */
 975         chip = &mpic->hc_irq;
 976
 977 #ifdef CONFIG_MPIC_U3_HT_IRQS
 978         /* Check for HT interrupts, override vecpri */
 979         if (mpic_is_ht_interrupt(mpic, hw))
 980                 chip = &mpic->hc_ht_irq;
 981 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 982
 983         DBG("mpic: mapping to irq chip @%p\n", chip);
 984
 985         set_irq_chip_data(virq, mpic);
 986         set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
 987
 988         /* Set default irq type */
 989         set_irq_type(virq, IRQ_TYPE_NONE);
 990
 991         return 0;
 992 }
 993
 994 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
 995                            u32 *intspec, unsigned int intsize,
 996                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 997
 998 {
 999         static unsigned char map_mpic_senses[4] = {
1000                 IRQ_TYPE_EDGE_RISING,
1001                 IRQ_TYPE_LEVEL_LOW,
1002                 IRQ_TYPE_LEVEL_HIGH,
1003                 IRQ_TYPE_EDGE_FALLING,
1004         };
1005
1006         *out_hwirq = intspec[0];
1007         if (intsize > 1) {
1008                 u32 mask = 0x3;
1009
1010                 /* Apple invented a new race of encoding on machines with
1011                  * an HT APIC. They encode, among others, the index within
1012                  * the HT APIC. We don't care about it here since thankfully,
1013                  * it appears that they have the APIC already properly
1014                  * configured, and thus our current fixup code that reads the
1015                  * APIC config works fine. However, we still need to mask out
1016                  * bits in the specifier to make sure we only get bit 0 which
1017                  * is the level/edge bit (the only sense bit exposed by Apple),
1018                  * as their bit 1 means something else.
1019                  */
1020                 if (machine_is(powermac))
1021                         mask = 0x1;
1022                 *out_flags = map_mpic_senses[intspec[1] & mask];
1023         } else
1024                 *out_flags = IRQ_TYPE_NONE;
1025
1026         DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1027             intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1028
1029         return 0;
1030 }
1031
1032 static struct irq_host_ops mpic_host_ops = {
1033         .match = mpic_host_match,
1034         .map = mpic_host_map,
1035         .xlate = mpic_host_xlate,
1036 };
1037
1038 /*
1039  * Exported functions
1040  */
1041
1042 struct mpic * __init mpic_alloc(struct device_node *node,
1043                                 phys_addr_t phys_addr,
1044                                 unsigned int flags,
1045                                 unsigned int isu_size,
1046                                 unsigned int irq_count,
1047                                 const char *name)
1048 {
1049         struct mpic     *mpic;
1050         u32             greg_feature;
1051         const char      *vers;
1052         int             i;
1053         int             intvec_top;
1054         u64             paddr = phys_addr;
1055
1056         mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1057         if (mpic == NULL)
1058                 return NULL;
1059
1060         mpic->name = name;
1061
1062         mpic->hc_irq = mpic_irq_chip;
1063         mpic->hc_irq.typename = name;
1064         if (flags & MPIC_PRIMARY)
1065                 mpic->hc_irq.set_affinity = mpic_set_affinity;
1066 #ifdef CONFIG_MPIC_U3_HT_IRQS
1067         mpic->hc_ht_irq = mpic_irq_ht_chip;
1068         mpic->hc_ht_irq.typename = name;
1069         if (flags & MPIC_PRIMARY)
1070                 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1071 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1072
1073 #ifdef CONFIG_SMP
1074         mpic->hc_ipi = mpic_ipi_chip;
1075         mpic->hc_ipi.typename = name;
1076 #endif /* CONFIG_SMP */
1077
1078         mpic->flags = flags;
1079         mpic->isu_size = isu_size;
1080         mpic->irq_count = irq_count;
1081         mpic->num_sources = 0; /* so far */
1082
1083         if (flags & MPIC_LARGE_VECTORS)
1084                 intvec_top = 2047;
1085         else
1086                 intvec_top = 255;
1087
1088         mpic->timer_vecs[0] = intvec_top - 8;
1089         mpic->timer_vecs[1] = intvec_top - 7;
1090         mpic->timer_vecs[2] = intvec_top - 6;
1091         mpic->timer_vecs[3] = intvec_top - 5;
1092         mpic->ipi_vecs[0]   = intvec_top - 4;
1093         mpic->ipi_vecs[1]   = intvec_top - 3;
1094         mpic->ipi_vecs[2]   = intvec_top - 2;
1095         mpic->ipi_vecs[3]   = intvec_top - 1;
1096         mpic->spurious_vec  = intvec_top;
1097
1098         /* Check for "big-endian" in device-tree */
1099         if (node && of_get_property(node, "big-endian", NULL) != NULL)
1100                 mpic->flags |= MPIC_BIG_ENDIAN;
1101
1102         /* Look for protected sources */
1103         if (node) {
1104                 int psize;
1105                 unsigned int bits, mapsize;
1106                 const u32 *psrc =
1107                         of_get_property(node, "protected-sources", &psize);
1108                 if (psrc) {
1109                         psize /= 4;
1110                         bits = intvec_top + 1;
1111                         mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1112                         mpic->protected = alloc_bootmem(mapsize);
1113                         BUG_ON(mpic->protected == NULL);
1114                         memset(mpic->protected, 0, mapsize);
1115                         for (i = 0; i < psize; i++) {
1116                                 if (psrc[i] > intvec_top)
1117                                         continue;
1118                                 __set_bit(psrc[i], mpic->protected);
1119                         }
1120                 }
1121         }
1122
1123 #ifdef CONFIG_MPIC_WEIRD
1124         mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1125 #endif
1126
1127         /* default register type */
1128         mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1129                 mpic_access_mmio_be : mpic_access_mmio_le;
1130
1131         /* If no physical address is passed in, a device-node is mandatory */
1132         BUG_ON(paddr == 0 && node == NULL);
1133
1134         /* If no physical address passed in, check if it's dcr based */
1135         if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1136 #ifdef CONFIG_PPC_DCR
1137                 mpic->flags |= MPIC_USES_DCR;
1138                 mpic->reg_type = mpic_access_dcr;
1139 #else
1140                 BUG();
1141 #endif /* CONFIG_PPC_DCR */
1142         }
1143
1144         /* If the MPIC is not DCR based, and no physical address was passed
1145          * in, try to obtain one
1146          */
1147         if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1148                 const u32 *reg = of_get_property(node, "reg", NULL);
1149                 BUG_ON(reg == NULL);
1150                 paddr = of_translate_address(node, reg);
1151                 BUG_ON(paddr == OF_BAD_ADDR);
1152         }
1153
1154         /* Map the global registers */
1155         mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1156         mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1157
1158         /* Reset */
1159         if (flags & MPIC_WANTS_RESET) {
1160                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1161                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1162                            | MPIC_GREG_GCONF_RESET);
1163                 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1164                        & MPIC_GREG_GCONF_RESET)
1165                         mb();
1166         }
1167
1168         /* CoreInt */
1169         if (flags & MPIC_ENABLE_COREINT)
1170                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1171                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1172                            | MPIC_GREG_GCONF_COREINT);
1173
1174         if (flags & MPIC_ENABLE_MCK)
1175                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1176                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1177                            | MPIC_GREG_GCONF_MCK);
1178
1179         /* Read feature register, calculate num CPUs and, for non-ISU
1180          * MPICs, num sources as well. On ISU MPICs, sources are counted
1181          * as ISUs are added
1182          */
1183         greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1184         mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1185                           >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1186         if (isu_size == 0) {
1187                 if (flags & MPIC_BROKEN_FRR_NIRQS)
1188                         mpic->num_sources = mpic->irq_count;
1189                 else
1190                         mpic->num_sources =
1191                                 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1192                                  >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1193         }
1194
1195         /* Map the per-CPU registers */
1196         for (i = 0; i < mpic->num_cpus; i++) {
1197                 mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1198                          MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1199                          0x1000);
1200         }
1201
1202         /* Initialize main ISU if none provided */
1203         if (mpic->isu_size == 0) {
1204                 mpic->isu_size = mpic->num_sources;
1205                 mpic_map(mpic, node, paddr, &mpic->isus[0],
1206                          MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1207         }
1208         mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1209         mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1210
1211         mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1212                                        isu_size ? isu_size : mpic->num_sources,
1213                                        &mpic_host_ops,
1214                                        flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1215         if (mpic->irqhost == NULL)
1216                 return NULL;
1217
1218         mpic->irqhost->host_data = mpic;
1219
1220         /* Display version */
1221         switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1222         case 1:
1223                 vers = "1.0";
1224                 break;
1225         case 2:
1226                 vers = "1.2";
1227                 break;
1228         case 3:
1229                 vers = "1.3";
1230                 break;
1231         default:
1232                 vers = "<unknown>";
1233                 break;
1234         }
1235         printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1236                " max %d CPUs\n",
1237                name, vers, (unsigned long long)paddr, mpic->num_cpus);
1238         printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1239                mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1240
1241         mpic->next = mpics;
1242         mpics = mpic;
1243
1244         if (flags & MPIC_PRIMARY) {
1245                 mpic_primary = mpic;
1246                 irq_set_default_host(mpic->irqhost);
1247         }
1248
1249         return mpic;
1250 }
1251
1252 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1253                             phys_addr_t paddr)
1254 {
1255         unsigned int isu_first = isu_num * mpic->isu_size;
1256
1257         BUG_ON(isu_num >= MPIC_MAX_ISU);
1258
1259         mpic_map(mpic, mpic->irqhost->of_node,
1260                  paddr, &mpic->isus[isu_num], 0,
1261                  MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1262
1263         if ((isu_first + mpic->isu_size) > mpic->num_sources)
1264                 mpic->num_sources = isu_first + mpic->isu_size;
1265 }
1266
1267 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1268 {
1269         mpic->senses = senses;
1270         mpic->senses_count = count;
1271 }
1272
1273 void __init mpic_init(struct mpic *mpic)
1274 {
1275         int i;
1276         int cpu;
1277
1278         BUG_ON(mpic->num_sources == 0);
1279
1280         printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1281
1282         /* Set current processor priority to max */
1283         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1284
1285         /* Initialize timers: just disable them all */
1286         for (i = 0; i < 4; i++) {
1287                 mpic_write(mpic->tmregs,
1288                            i * MPIC_INFO(TIMER_STRIDE) +
1289                            MPIC_INFO(TIMER_DESTINATION), 0);
1290                 mpic_write(mpic->tmregs,
1291                            i * MPIC_INFO(TIMER_STRIDE) +
1292                            MPIC_INFO(TIMER_VECTOR_PRI),
1293                            MPIC_VECPRI_MASK |
1294                            (mpic->timer_vecs[0] + i));
1295         }
1296
1297         /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1298         mpic_test_broken_ipi(mpic);
1299         for (i = 0; i < 4; i++) {
1300                 mpic_ipi_write(i,
1301                                MPIC_VECPRI_MASK |
1302                                (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1303                                (mpic->ipi_vecs[0] + i));
1304         }
1305
1306         /* Initialize interrupt sources */
1307         if (mpic->irq_count == 0)
1308                 mpic->irq_count = mpic->num_sources;
1309
1310         /* Do the HT PIC fixups on U3 broken mpic */
1311         DBG("MPIC flags: %x\n", mpic->flags);
1312         if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1313                 mpic_scan_ht_pics(mpic);
1314                 mpic_u3msi_init(mpic);
1315         }
1316
1317         mpic_pasemi_msi_init(mpic);
1318
1319         if (mpic->flags & MPIC_PRIMARY)
1320                 cpu = hard_smp_processor_id();
1321         else
1322                 cpu = 0;
1323
1324         for (i = 0; i < mpic->num_sources; i++) {
1325                 /* start with vector = source number, and masked */
1326                 u32 vecpri = MPIC_VECPRI_MASK | i |
1327                         (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1328
1329                 /* check if protected */
1330                 if (mpic->protected && test_bit(i, mpic->protected))
1331                         continue;
1332                 /* init hw */
1333                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1334                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1335         }
1336
1337         /* Init spurious vector */
1338         mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1339
1340         /* Disable 8259 passthrough, if supported */
1341         if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1342                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1343                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1344                            | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1345
1346         if (mpic->flags & MPIC_NO_BIAS)
1347                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1348                         mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1349                         | MPIC_GREG_GCONF_NO_BIAS);
1350
1351         /* Set current processor priority to 0 */
1352         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1353
1354 #ifdef CONFIG_PM
1355         /* allocate memory to save mpic state */
1356         mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save));
1357         BUG_ON(mpic->save_data == NULL);
1358 #endif
1359 }
1360
1361 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1362 {
1363         u32 v;
1364
1365         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1366         v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1367         v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1368         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1369 }
1370
1371 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1372 {
1373         unsigned long flags;
1374         u32 v;
1375
1376         spin_lock_irqsave(&mpic_lock, flags);
1377         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1378         if (enable)
1379                 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1380         else
1381                 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1382         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1383         spin_unlock_irqrestore(&mpic_lock, flags);
1384 }
1385
1386 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1387 {
1388         struct mpic *mpic = mpic_find(irq);
1389         unsigned int src = mpic_irq_to_hw(irq);
1390         unsigned long flags;
1391         u32 reg;
1392
1393         if (!mpic)
1394                 return;
1395
1396         spin_lock_irqsave(&mpic_lock, flags);
1397         if (mpic_is_ipi(mpic, irq)) {
1398                 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1399                         ~MPIC_VECPRI_PRIORITY_MASK;
1400                 mpic_ipi_write(src - mpic->ipi_vecs[0],
1401                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1402         } else {
1403                 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1404                         & ~MPIC_VECPRI_PRIORITY_MASK;
1405                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1406                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1407         }
1408         spin_unlock_irqrestore(&mpic_lock, flags);
1409 }
1410
1411 void mpic_setup_this_cpu(void)
1412 {
1413 #ifdef CONFIG_SMP
1414         struct mpic *mpic = mpic_primary;
1415         unsigned long flags;
1416         u32 msk = 1 << hard_smp_processor_id();
1417         unsigned int i;
1418
1419         BUG_ON(mpic == NULL);
1420
1421         DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1422
1423         spin_lock_irqsave(&mpic_lock, flags);
1424
1425         /* let the mpic know we want intrs. default affinity is 0xffffffff
1426          * until changed via /proc. That's how it's done on x86. If we want
1427          * it differently, then we should make sure we also change the default
1428          * values of irq_desc[].affinity in irq.c.
1429          */
1430         if (distribute_irqs) {
1431                 for (i = 0; i < mpic->num_sources ; i++)
1432                         mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1433                                 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1434         }
1435
1436         /* Set current processor priority to 0 */
1437         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1438
1439         spin_unlock_irqrestore(&mpic_lock, flags);
1440 #endif /* CONFIG_SMP */
1441 }
1442
1443 int mpic_cpu_get_priority(void)
1444 {
1445         struct mpic *mpic = mpic_primary;
1446
1447         return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1448 }
1449
1450 void mpic_cpu_set_priority(int prio)
1451 {
1452         struct mpic *mpic = mpic_primary;
1453
1454         prio &= MPIC_CPU_TASKPRI_MASK;
1455         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1456 }
1457
1458 void mpic_teardown_this_cpu(int secondary)
1459 {
1460         struct mpic *mpic = mpic_primary;
1461         unsigned long flags;
1462         u32 msk = 1 << hard_smp_processor_id();
1463         unsigned int i;
1464
1465         BUG_ON(mpic == NULL);
1466
1467         DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1468         spin_lock_irqsave(&mpic_lock, flags);
1469
1470         /* let the mpic know we don't want intrs.  */
1471         for (i = 0; i < mpic->num_sources ; i++)
1472                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1473                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1474
1475         /* Set current processor priority to max */
1476         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1477         /* We need to EOI the IPI since not all platforms reset the MPIC
1478          * on boot and new interrupts wouldn't get delivered otherwise.
1479          */
1480         mpic_eoi(mpic);
1481
1482         spin_unlock_irqrestore(&mpic_lock, flags);
1483 }
1484
1485
1486 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1487 {
1488         struct mpic *mpic = mpic_primary;
1489
1490         BUG_ON(mpic == NULL);
1491
1492 #ifdef DEBUG_IPI
1493         DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1494 #endif
1495
1496         mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1497                        ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1498                        mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1499 }
1500
1501 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1502 {
1503         u32 src;
1504
1505         src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1506 #ifdef DEBUG_LOW
1507         DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1508 #endif
1509         if (unlikely(src == mpic->spurious_vec)) {
1510                 if (mpic->flags & MPIC_SPV_EOI)
1511                         mpic_eoi(mpic);
1512                 return NO_IRQ;
1513         }
1514         if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1515                 if (printk_ratelimit())
1516                         printk(KERN_WARNING "%s: Got protected source %d !\n",
1517                                mpic->name, (int)src);
1518                 mpic_eoi(mpic);
1519                 return NO_IRQ;
1520         }
1521
1522         return irq_linear_revmap(mpic->irqhost, src);
1523 }
1524
1525 unsigned int mpic_get_one_irq(struct mpic *mpic)
1526 {
1527         return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1528 }
1529
1530 unsigned int mpic_get_irq(void)
1531 {
1532         struct mpic *mpic = mpic_primary;
1533
1534         BUG_ON(mpic == NULL);
1535
1536         return mpic_get_one_irq(mpic);
1537 }
1538
1539 unsigned int mpic_get_coreint_irq(void)
1540 {
1541 #ifdef CONFIG_BOOKE
1542         struct mpic *mpic = mpic_primary;
1543         u32 src;
1544
1545         BUG_ON(mpic == NULL);
1546
1547         src = mfspr(SPRN_EPR);
1548
1549         if (unlikely(src == mpic->spurious_vec)) {
1550                 if (mpic->flags & MPIC_SPV_EOI)
1551                         mpic_eoi(mpic);
1552                 return NO_IRQ;
1553         }
1554         if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1555                 if (printk_ratelimit())
1556                         printk(KERN_WARNING "%s: Got protected source %d !\n",
1557                                mpic->name, (int)src);
1558                 return NO_IRQ;
1559         }
1560
1561         return irq_linear_revmap(mpic->irqhost, src);
1562 #else
1563         return NO_IRQ;
1564 #endif
1565 }
1566
1567 unsigned int mpic_get_mcirq(void)
1568 {
1569         struct mpic *mpic = mpic_primary;
1570
1571         BUG_ON(mpic == NULL);
1572
1573         return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1574 }
1575
1576 #ifdef CONFIG_SMP
1577 void mpic_request_ipis(void)
1578 {
1579         struct mpic *mpic = mpic_primary;
1580         int i;
1581         BUG_ON(mpic == NULL);
1582
1583         printk(KERN_INFO "mpic: requesting IPIs ... \n");
1584
1585         for (i = 0; i < 4; i++) {
1586                 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1587                                                        mpic->ipi_vecs[0] + i);
1588                 if (vipi == NO_IRQ) {
1589                         printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1590                         continue;
1591                 }
1592                 smp_request_message_ipi(vipi, i);
1593         }
1594 }
1595
1596 void smp_mpic_message_pass(int target, int msg)
1597 {
1598         /* make sure we're sending something that translates to an IPI */
1599         if ((unsigned int)msg > 3) {
1600                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1601                        smp_processor_id(), msg);
1602                 return;
1603         }
1604         switch (target) {
1605         case MSG_ALL:
1606                 mpic_send_ipi(msg, 0xffffffff);
1607                 break;
1608         case MSG_ALL_BUT_SELF:
1609                 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1610                 break;
1611         default:
1612                 mpic_send_ipi(msg, 1 << target);
1613                 break;
1614         }
1615 }
1616
1617 int __init smp_mpic_probe(void)
1618 {
1619         int nr_cpus;
1620
1621         DBG("smp_mpic_probe()...\n");
1622
1623         nr_cpus = cpus_weight(cpu_possible_map);
1624
1625         DBG("nr_cpus: %d\n", nr_cpus);
1626
1627         if (nr_cpus > 1)
1628                 mpic_request_ipis();
1629
1630         return nr_cpus;
1631 }
1632
1633 void __devinit smp_mpic_setup_cpu(int cpu)
1634 {
1635         mpic_setup_this_cpu();
1636 }
1637 #endif /* CONFIG_SMP */
1638
1639 #ifdef CONFIG_PM
1640 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1641 {
1642         struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1643         int i;
1644
1645         for (i = 0; i < mpic->num_sources; i++) {
1646                 mpic->save_data[i].vecprio =
1647                         mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1648                 mpic->save_data[i].dest =
1649                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1650         }
1651
1652         return 0;
1653 }
1654
1655 static int mpic_resume(struct sys_device *dev)
1656 {
1657         struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1658         int i;
1659
1660         for (i = 0; i < mpic->num_sources; i++) {
1661                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1662                                mpic->save_data[i].vecprio);
1663                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1664                                mpic->save_data[i].dest);
1665
1666 #ifdef CONFIG_MPIC_U3_HT_IRQS
1667         {
1668                 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1669
1670                 if (fixup->base) {
1671                         /* we use the lowest bit in an inverted meaning */
1672                         if ((mpic->save_data[i].fixup_data & 1) == 0)
1673                                 continue;
1674
1675                         /* Enable and configure */
1676                         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1677
1678                         writel(mpic->save_data[i].fixup_data & ~1,
1679                                fixup->base + 4);
1680                 }
1681         }
1682 #endif
1683         } /* end for loop */
1684
1685         return 0;
1686 }
1687 #endif
1688
1689 static struct sysdev_class mpic_sysclass = {
1690 #ifdef CONFIG_PM
1691         .resume = mpic_resume,
1692         .suspend = mpic_suspend,
1693 #endif
1694         .name = "mpic",
1695 };
1696
1697 static int mpic_init_sys(void)
1698 {
1699         struct mpic *mpic = mpics;
1700         int error, id = 0;
1701
1702         error = sysdev_class_register(&mpic_sysclass);
1703
1704         while (mpic && !error) {
1705                 mpic->sysdev.cls = &mpic_sysclass;
1706                 mpic->sysdev.id = id++;
1707                 error = sysdev_register(&mpic->sysdev);
1708                 mpic = mpic->next;
1709         }
1710         return error;
1711 }
1712
1713 device_initcall(mpic_init_sys);